Design and Implementation of FPGA Based 32 Bit

Floating Point Processor for DSP Application.

1st Mr. Anand Burud 2nd Dr. Pradip Bhaskar
Department of technology, Department of technology,
Shivaji university, Shivaji university,
Kolhapur, India Kolhapur, India
[email protected] [email protected]

Abstract— The floating point arithmetic operations have is also used to store data to be processed by computer or data
discovered applications in the various different fields for the resulting from the processing.
necessities for requirments high precision operation because of
its incredible dynamic range, high accuracy and fast arithmetic CPU Section The central processing unit or CPU
operations. High accuracy is needed for the design and contains the control circuitry, an ALU, some registers andan
research of the floating point processing units. With the address program counter. To execute a program, the CPU
expanding necessities for the floating point operations for the sends out to memory the address of the location of the code
fast high speed data signal processing and the logical operation, for the first instruction to be executed. The CPU also sends
the requirements for the high-speed hardware floating point out a memory enable signal. The instruction code comes to
arithmetic units have turned out to be increasingly requesting. the CPU from memory and gets decoded and executed. After
This paper deals with the design and implementation of the each operation the program counter increments to the address
32-bit floating point Processor with MAC unit for signal the location of the next instruction or data stored in memory.
processing application. The Linear convolution and Circular
convolution of signals is verified. The necessary code is written Input-Output Ports The third part of the processor is the
in the language Verilog. Xilinx 14.7 suite is used for software interface of the processor with the outside world. This
development and then implementation on Spartan 6 board. interface is often called input-output ports. An input port
The designed DSP has instructions set and consists of 32-bit allows data from a keyboard or some other data to be taken
ALU, 32-bit X 32-bit parallel multiplier for single-cycle MAC into the processor under CPU control. An output port is used
operation, 2 addressing modes, 31 auxiliary register arithmetic to send a data to some output devices.
units.

Keywords—DSP, MAC, FPU, ALU, IEEE754, CPU, RAM,

ROM.

I. INTRODUCTION
The Digital Signal Processor (DSP) plays very
important role in day-to-day life. In today’s life the
importance of DSP processor goes increasing. The
intelligence of the word transmitting analog based system to
digital based system to fast handling and processing.
(a)
In this paper design, synthesis and implementation
of 32 bit IEEE 754 standard Floating Point DSP processor. It
has a complete instruction set, program memory and data
memory, general purpose registers and a simple Arithmetic
& Logical Unit with single precision floating point
arithmetic operations like addition, subtraction,
multiplication and division.
Figure 1 (a) shows a block diagram of simple
processor system. The three major parts of a processor are
the memory, the CPU and the I/O ports.
Memory Section The memory section usually consists of
ROM and RAM. Memory is used to store instruction
sequence or program which computer will execute. Memory

(b)
Fig.1 Basic block diagram of simple processor (ref 15)

978-1-5386-5257-2/18/$31.00 ©2018 IEEE

Authorized licensed use limited to: College of Engineering - THIRUVANANTHAPURAM. Downloaded on December 17,2022 at 16:05:40 UTC from IEEE Xplore. Restrictions apply.
 II. PROPOSED WORK multiplier–accumulator MAC unit below fig 2.shows the
basic MAC unit structure.
A. ALU
Arithmetic Logical Unit plays an important role indigital
signal processor. The Arithmetic Logic Unit is essentially the
heart of a CPU. ALU having generally two inputs one is
Operand and second is Opcode. Opcode is nothing but select
lines given to ALU.
The operations will be controlled by select lines.
Generally two types of operations are performed arithmetic
and logical operations. In this processor which operation will
be perform is selected by three select lines bit no 23-21
which will shown in table below table 1.

TABLE I. LOGICAL FUNCTIONS

Sr. Logical Functions

No. ALU Control Function
1. 000 Multiplication

2. 001 Addition

3. 010 Subtraction
Fig. 2. MAC Unit
4. 011 Division

5. 100 AND D. IEEE 754Standerd

6. 101 OR IEEE754 standard is a technical standard established by
7. 110 XOR
IEEE and the most widely used standard for floating-point
computation, followed by many hardware (CPU and FPU)
8. 111 NOT and software implementations [3]. IEEE 754 Standard for
Floating-Point calculations. This standard defines binary
representation for floating-point numbers of varying
B. Shifter precision, giving specific examples of the binary32 (or single
precision) format table no 2 below shows 32 bit floating
The shifter block in DSP processor plays an important point standard.
block in floating-point operations where it holds the block
exponent value. In this shifter the exponent part of the IEEE
754 Floating point number are normalized. The TABLE II. FLOATING POINT STANDARD
normalization is a processor nothing that the number IEEE 754 Standard single precision
represent one number after the decimal point. In this rotorby
Sign Exponent Mantissa Bias
the shifting of the number by left or right by that operation
we are normalizing the number for further calculations. The 1(31) 8(30-23) 23(22-00) 127
shifter provides a complete set of shifting functions for a 32-
bit input values and 32-bit output values. These include
arithmetic shift, logical shift and normalization. In this E. Instruction set
shifter the main role is normalization of a number is followed
All the instructions are 32 bits long and instruction is
by shifting.
represented in hex format. There are instructions that have
been implemented in the design. According to their purposes,
C. MAC the instructions can be divided into groups which are
MAC is one of the most important component of the illustrated in table 3.
digital signal processor. In this MAC unit the multiplication
and addition both operations are performs. In computing and
TABLE III. INSTRUCTION SET
especially digital signal processing, the multiply–accumulate
operation is a common step that computes the product of two Instruction set
numbers and adds that product to an accumulator. The Processing Unit Operation Instruction
hardware unit that performs the operation is known as a
CPU Arithmetic ADD SUB MUL DIV

Logical AND OR XOR NOT

Shifter
DSP Processing Unit MAC

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)

Authorized licensed use limited to: College of Engineering - THIRUVANANTHAPURAM. Downloaded on December 17,2022 at 16:05:40 UTC from IEEE Xplore. Restrictions apply.
 A 32-bit instruction is encoded as follows. The most The design is able to achieve best power consumption
significant 8 bits represents the opcode (bit 31–bit 24).The over the past work in the same field.
next 3 bits represent for select lines for which the ALU
operation (bit 23–bit 21), next 4-bit represents the second
source register (bit 19- 16 bit ) and the next 4-bit represents
first source register (bit 15–bit 12) respectively. Next bits are
not used. It is not necessary that all the bits will be used in
every instruction. When a new instruction is fetched from the
instruction memory, for example an arithmetic operation -
ADD R1, R2
This will be encoded in the instruction memory in
the following
format : h56212900

5 6 1 2 2 9 0 0 Fig. 3. Device utilization summary

0101 0110 0010 0001 0010 1001 0000 0000

When this instruction comes to the controller and register

file, the controller will interpret the opcode bits and will find
that this is an add operation. The controller will output the
corresponding control signals that set up the correct path for
this operation. The register file will output the stored value
for these corresponding registers. These data will be used as
the source for the specified operations.

F. Convolution
In this proposed system the application of digital signal
processor such as Linear convolution and Circular Fig. 4. Power consumption
convolution of signals are verified.
Convolution is a mathematical way of combining two
signal and form a third signal. It is a single most important
part in the digital signal processing. Convolution is
fundamental and important operation on signal processing
and the Multiply and accumulator (MAC) operation is
widely used in convolution. Convolution between of an input
signal x[n] with a system having impulse response h[n] is
given as,

III. PERFORMANCE ANALYSIS AND DISCUSSION

Fig. 5. Top level schematic view
In this system convolution of two signals are evaluated
on the terminal window tab, which as follows x[k]=251,302
and h[k]=4,-2 this two signals are stored in RAM.
The 32 bit DSP processor contain MAC unit and ALU,
based on 32-bit floating point IEEE 754 standard, which
was simulated and synthesized on Xilinx 14.7. , Where fig.
no. 3 shows the device utilization summary. Where is
obtained that Number of slice register utilization is 6% ,
number of slice LUT’s is 33% utilization ,number used as
logic 33% utilization , number of slice LUT’s utilization is
65% , fig. no. 4 shows the power consumption of this
system. The total power consumption is 0.016W. fig. no. 5
shows top level model , fig. no. 6 shows RTL schematic of
proposed system. By comparing with previous system this
system is power consumption and memory consumption Fig. 6. RTL Schematic
device because of that the hardware required is less.

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)

Authorized licensed use limited to: College of Engineering - THIRUVANANTHAPURAM. Downloaded on December 17,2022 at 16:05:40 UTC from IEEE Xplore. Restrictions apply.
 IV. CONCLUSION
Single precision floating point unit digital signal
processor MAC unit is designed and implemented using
Xilinx 14.7 in this paper. The designed MAC unit conforms
to IEEE 754 single precision floating point standard and
designed is verified using fpu test bench.
The design has been able to achieve low power over the
past work in the same field. The time and power required for
this system is low. Because of its processing fast speed and
hardware requirement is reduced, thereby reducing power
consumption and delay. This architecture has become
Fig. 7. Maximum Frequency indispensable and increasingly important in many
applications like signal processing, graphics and medical.
V. FUTURE SCOPE
Digital signal processor plays important role in Digital
communication and a day-to-day life the use of it and
importance is increases. For better operations and fast
handling processing are required for various applications. In
future by using this processor we can implement different a
various application of signal processing.

REFERENCES
[1] Sneha S.jumle and M. V. Vyawhare Development of an FPGA based
high speed single precision floating point multiplier (International
Journal of Electronic and Electrical Engineering.)
Fig. 8. Timing diagram of convolution [2] Sayali A. Bawankar1, Prof. G. D. Korde2 Review on 32 bit single
precision Floating point unit (FPU) Based on IEEE 754 Standard
using VHDL (IRJET)
[3] Tasnim Ferdous Design, Synthesis and FPGA-based Implementation
of a 32-bit Digital Signal Processor International Journal Of Scientific
& Engineering Research, Volume 3, Issue 7, July-2012
[4] Itagi Mahi P.a* and S. S. Kerurb Design and Simulation of Floating
Point Pipelined ALU Using HDL and IP Core Generator International
Journal of Current Engineering and Technology
[5] Prabhjot Kaur Rajiv Ranjan R a m inder Preet Pal Singh Onkar Singh
Double Precision Floating Point Arithmetic Unit Implementation- A
Review (IJERT)
[6] Amana Yadav Ila Chaudhary Design of 32-bit Floating Point Unit for
Advanced Processors. ijera
[7] Itagi Mahi P.a* and S. S. Kerurb Design and Simulation of Floating
Point Pipelined ALU Using HDL and IP Core Generator International
Journal of Current Engineering and Technology.
[8] Kahan, William. "IEEE standard 754 for binary floating-point
arithmetic."Lecture Notes on the Status of IEEE 754.94720-1776
(1996): 11.
Fig. 9. Setup [9] Ykuntam, Yamini Devi, MV Nageswara Rao, and G. R. Locharla.
"Design of 32-bit Carry Select Adder with Reduced Area."
International Journal of Computer Applications 75.2 (2013).
[10] Quinnell, Eric, Earl E. Swartzlander Jr, and Carl Lemonds. "Floating-
point fused multiply-add architectures." Signals, Systems and
Computers, 2007. ACSSC 2007. Conference Record of the Forty-First
Asilomar Conference on. IEEE, 2007
[11] F. Conti, D. Rossi, A. Pullini, I. Loi, and L. Benini, “Energy-efficient
vision on the PULP platform for ultra-low power parallel computing,”
in Signal Processing Systems (SiPS), 2014 IEEE Workshop on, Oct
2014.

[12] Naresh Grover, M.K.Soni Design of FPGA based 32-bit Floating

Point Arithmetic Unit and verification of its VHDL code using
MATLAB I.J. Information Engineering and Electronic Business,
Fig. 10. Output on terminal window 2014, 1, 1-14 Published Online February 2014 in MECS

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)

Authorized licensed use limited to: College of Engineering - THIRUVANANTHAPURAM. Downloaded on December 17,2022 at 16:05:40 UTC from IEEE Xplore. Restrictions apply.
 [13] Syed M. Qasim, Ahmed A. Telba and Abdulhameed Y. [17] https://en.wikipedia.org/wiki/Digital_signal_processor
AlMazrooFPGA Design and Implementation of Matrix Multiplier [18] https://en.wikipedia.org
Architectures for Image and Signal Processing Applications IJCSNS
International Journal of Computer Science and Network Security, [19] Shishir Kumar Das, Aniruddha Kanhe, R.H. Talwekar “ Design and
VOL.10 No.2, February 2010. Implementation of High- performance MAC Unit” International
Journal of Scientific & Engineering Research, Volume 4, Issue 6,
[14] Anuradha Savadi , Raju Yanamshetti , Jyoti Godihal Design and June-2013.
Synthesis of High Performance Vedic DSP Processor. International
Journal of Computer Applications (0975 – 8887) [20] Anuradha Savadi ,Raju Yanamshetti , Jyoti Godihal “Design and
Synthesis of High Performance Vedic DSP Processor” International
[15] Donghoon Lee, Chanwon Ryu, Jusung Park Kyunsoo Kwon, Wontae Journal of computer Application , Volume 168-No.6,June 2017.
ChoiDesign and implementation of 16-bit fixed point digital signal
[21] I.V.Vaibhavi , K.V.Saicharn, B.Sravanti, D.shrinivasvalu “VHDL
processor. 2008 International SoC Design Conference
Implementation Of Floating Point Multiplier Using Vedic
[16] Jinde Vijay Kumar1, Chintakunta Swapna2, Boya Nagaraju3 , Mathematics” International Conference on Electrical, Electronics and
Thogata Ramanjappa4 FPGA Based Implementation of Pipelined 32- Communications-ICEEC-21st June 2014.
bit RISC Processor with Floating Point Unit. Int. Journal of
[22] Tasnim Ferdous “Design and FPGA-based Implementation of a High
Engineering Research and Applications
Performance 32-bit DSP Processor” ,2012 IEEE.

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)

Authorized licensed use limited to: College of Engineering - THIRUVANANTHAPURAM. Downloaded on December 17,2022 at 16:05:40 UTC from IEEE Xplore. Restrictions apply.