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Experiment VI

Binary Adders

OBJECTIVES:
 Design a 1-bit full adder based on its truth table.
 Demonstrate modular design and hierarchy.
 Use Xilinx simulation tools to test combinational circuits

MATERIALS:
 Quartus II sofrware 13.1 or higher.
 IBM or compatible computer with Pentium III or higher, 128 M-byte RAM or more, and 8 G-
byte Or larger hard drive.
 XC FPGA Board with Altera FPGA (Cyclone IV EP4CE6E22C8)

DISCUSSION:
Addition and subtraction are two essential arithmetic functions performed by computers and other
digital systems. It is therefore important to understand how to design a circuit to perform such
functions. However, since subtraction is done by adding the 2s complement of a number, we will only
need to design one adder circuit to perform both operations. An adder can be 1 or more bits. A 4-bit
adder can add two 4-bit unsigned binary numbers. If larger binary numbers are to be added, an adder
with more bits is needed. Let’s observe what happens when adding two 4-bit binary numbers with
pencil and paper:

The symbols [A3 A2 Al A0] and [B3 B2 B1 B0] represent addend and minuend, respectively. C0 is
the carry bit generated by adding bits A0 and B0. C1 is the carry bit generated from the addition of
C0, Al, and B1. C2 and C3 are generated in the same manner, with C3 the carry-out. The column
containing A0 and B0 (the least significant bits of addend and minuend) allows for a carry-in from a
previous addition, for this example we set it to 0. Each column adds three bits. The implementation
of the above process in hardware called a full adder.
When we perform this addition, we will start from the least significant bit, and then push the process
left one bit at a time. This means that a 1-bit full adder is the basic element of a 4-bit adder and four
such elements are needed to construct a 4-bit adder.
The 1-Bit Full Adder
From the discussion above we know that a 1-bit full adder should have three inputs: carry input (Cin),
addend (A), and minuend (B). We can determine the number of output bits by looking at any column

1
in the addition process, say, the column containing C0, A1 and B1. Assume all three bits are 1. Then
the result is 3 which, in binary, are 11. The sum requires two bits but S1 can be only one bit, so there
must be a carry to the next column. Each column will produce a sum bit and a carry output to the next
more significant bit position. So the circuit for the 1-bit full adder should have two outputs: sum bit
(S) and carry output (Cout). Table 7.1 shows the truth table for the 1-bit full adder:

Using Boolean algebra, we can derive the following two equations for the sum bit and the carry output
bit:

The above two equations can be implemented using a 3-input XOR gate, two 2-input AND gates, and
two 2-input OR gates.
The 4-Bit Adder
Once we have the 1-bit full-adder (FA), we can use it as a building block in any design that needs to
do addition, such as the multi-bit adder in a CPU. In a multi-bit adder, the carry-in of the least
significant bit (LSB) must be connected to 0 since there is no previous stage. The carry output from
the LSB stage should feed into the second least significant bit. The carry output of second least
significant stage feeds into the next more significant stage as carry input, and so on. The last carry
output is the most significant bit of the sum. The 4-bit adder block diagram with interconnections
between the FA modules is shown in figure below:

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PROCEDURE:
Section I. The 1-Bit Full Adder
1. Open Quartus II and create a new project “fulladder”.
2. Create a “.vhd” file and write the gates equivalent VHDL code for 1-bit full adder

3. Test the program on your board by going through all the input combinations and observing the two
outputs. Fill the truth table.
Inputs Outputs
a b ci co s
0 0 0 o o

0 0 1 o 1
0 1 0 0 1
0 1 1 1 0

1 0 0 0 1
1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Section II. Building a 4-bit Adder Using Full-Adder (FA) Modules

3
 2. Fill the table accordingly by changing your initialization part of the code:

Switches(Input) LEDs(Output)
1 2 3 4 5 6 7 8 1 2 3 4 5

Decimal

Decimal

Decimal
a3 a2 a1 a0 b3 b2 b1 b0 co s3 s2 s1 s0
0 0 0 0 0 0 0 0 0 0 o o o o o o
0 0 0 1 1 0 0 0 0 0 o o o 0
1 1
0 0 1 0 2 0 0 0 1 1 0 0 0 1 1 3
0 0 1 1 3 0 0 1 0 2 0 0 1 0 1 5
0 1 0 0 4 0 0 1 1 3 0 0 1 1 1 7

0 1 0 1 5 0 0 1 1 3 1 1 0 0 0
8
0 1 1 0 6 0 0 1 0 2 0 1 0 0 0 8
1 0 0 0 8 0 0 1 0 2 0 1 0 1 0 10

1 0 1 0 10 1 0 0 1 8 0 0 0 1 1 1 8

1 1 0 0 12 1 0 0 1 9 0 0 1 0 1 21

0 1 1 1 7 1 1 0 0 12 0 0 0 1 1 1 9
1 0 0 1 9 1 0 1 1 11 1 0 1 0 0 zo

Question
1. Find the ADD4 symbol in the symbol library. Draw a schematic diagram in the space provided
below and show how to make an 8-bit adder using the ADD4s.
74283 74283
GND -
CN -
CN
t A1

AI7.biz/VP_u
1
ㄏ A1
T T 加 ⽔ 加
E A
3 su.nl → ⼥ A3 suml →
t Au * Au
swn_i-nst8.no]
sumz → sumz →
* B. surnx * B.
B [7 0] ⼥ 132 Snm4→ ⼥ 132
snm4-xc.co
-

2Mt 0133 叶 ⼥ 133 004 →

☐→ * 134 *134

24-bitfunadderC742831andonnecethminseries.ca
Wecanu.se

2. What is a carry look-ahead adder? Why is it preferred over a regular adder? (Refer to your textbook
and diagrams of Ripple Carry and Carry Lookahead in the following.)

glookaheadaddrisanimprouedadderwhichu.se
parallelconnectionmethodtoreducethe.de/ayoftheregu1ara
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