4935N DFN-8
4935N DFN-8
Power MOSFET
30 V, 93 A, Single N−Channel, SO−8 FL
Features
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses http://onsemi.com
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant V(BR)DSS RDS(ON) MAX ID MAX
Applications
3.2 mW @ 10 V
• CPU Power Delivery, DC−DC Converters 30 V 93 A
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) 4.2 mW @ 4.5 V
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NTMFS4935N
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NTMFS4935N
TYPICAL CHARACTERISTICS
180 160
10 V 4.2 V
160 VGS = 4.0 V TJ = 25°C
140 VDS = 10 V
7V
140 3.8 V
ID, DRAIN CURRENT (A)
1.5
1.4 1000 TJ = 125°C
1.3
1.2
1.1 TJ = 85°C
1.0 100
0.9
0.8
0.7
0.6
0.5 10
−50 −25 0 25 50 75 100 125 150 5 10 15 20 25 30
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current
Temperature vs. Voltage
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NTMFS4935N
TYPICAL CHARACTERISTICS
4500 11
8
3000 7
2500 6
2000 5
Qgd
Coss 4
1500 Qgs TJ = 25°C
3
1000 VDD = 15 V
2 VGS = 10 V
500 1 ID = 30 A
Crss
0 0
0 5 10 15 20 25 30 0 5 10 15 20 25 30 35 40 45 50
VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1000 30
VDD = 15 V
td(off)
ID = 15 A 25 VGS = 0 V
IS, SOURCE CURRENT (A)
VGS = 10 V
100 tf 20
t, TIME (ns)
TJ = 125°C
tr
15
td(on)
10 10
TJ = 25°C
5
1 0
1 10 100 0.4 0.5 0.6 0.7 0.8 0.9 1.0
RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage vs. Current
vs. Gate Resistance
1000 130
SOURCE AVALANCHE ENERGY (mJ)
120 ID = 29 A
EAS, SINGLE PULSE DRAIN−TO−
110
100
ID, DRAIN CURRENT (A)
10 ms 100
90
100 ms 80
10
1 ms 70
10 ms 60
1 0 ≤ VGS ≤ 20 V
50
Single Pulse
TC = 25°C 40
0.1 30
RDS(on) Limit
Thermal Limit 20
dc 10
Package Limit
0.01 0
0.01 0.1 1 10 100 25 50 75 100 125 150
VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy vs.
Safe Operating Area Starting Junction Temperature
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NTMFS4935N
TYPICAL CHARACTERISTICS
1000
10 5%
2%
1 1%
0.1
Single Pulse
0.01
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE TIME (sec)
Figure 13. Thermal Response
70
60
50
40
GFS (S)
30
20
10
0
0 10 20 30 40 50 60 70 80 90 100
ID (A)
Figure 14. GFS vs. ID
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NTMFS4935N
PACKAGE DIMENSIONS
0.10 C STYLE 1:
PIN 1. SOURCE
SIDE VIEW 2. SOURCE
DETAIL A SOLDERING FOOTPRINT* 3. SOURCE
4. GATE
3X 4X 5. DRAIN
8X b 1.270 0.750
4X
0.10 C A B
1.000
0.05 c L e/2
1 4
0.965
K
1.330 2X
0.905
E2 2X
PIN 5 M 0.495
(EXPOSED PAD) L1 4.530
3.200
0.475
G D2
2X
BOTTOM VIEW
1.530
4.560
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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