UNIT V

SEQUENTIAL CIRCUIT DESIGN AND PROGRAMMABLE LOGIC

Sequential circuits – Introduction

Combinational circuits have a set of outputs that are solely dependent on the
current input combination. The synchronous logic circuit's block diagram is
shown below.

A sequential circuit is a circuit with a set of inputs and outputs. The sequential
circuits' outputs are determined by the mix of current inputs and preceding
outputs. The prior output is used to determine the current state. As a result, the
sequential circuit includes the combinational circuit as well as the memory
storage parts. A combinational circuit does not have to be present in every
sequential circuit. As a result, just the memory element can be included in the
sequential circuit.
Types of Sequential Circuits
Asynchronous sequential circuits
The Asynchronous sequential circuits do not use the clock signals. The
asynchronous circuit is controlled by pulses. As a result, changes in the input
can affect the circuit's state. Clock pulses are not used in asynchronous
circuits. When the input variable is modified, the internal state is altered. The
memory elements of asynchronous sequential circuits are un-clocked flip-flops
or time-delayed flip-flops. Asynchronous sequential circuits are related to
feedback-based combinational circuits.
Synchronous sequential circuits
The clock signal synchronizes the state of the memory element in synchronous
sequential circuits. Flip-flops or latches (memory devices) are used to store the
output. The outputs are synchronized using either only the clock signal's
negative edges or only the clock signal's positive edges.
Clock Signal and Triggering
Clock signal
A clock signal is a periodic signal that does not have to have the identical ON
and OFF times. When the clock signal's ON and OFF times are the same, the
signal is represented by a square wave. The clock signal is depicted in the
diagram below:

The square wave is used to describe a clock signal. The signal can sometimes
stay at logic for an equal period of time, either at high 5V or low 0V. It repeats
for a specific amount of time, which is double the 'ON time' or 'OFF time.'
Types of Triggering
In sequential circuits, there are two forms of triggering:
Level triggering
The logic High and logic Low are the two levels in the clock signal. The
circuit is only activated when the clock pulse reaches a certain level in level
triggering. The following are the several forms of level triggering:
Positive level triggering
The signal with Logic High happens when a positive level is triggered. As a
result, the circuit is operated with this type of clock signal in this triggering.
The diagram of positive level triggering is shown below:
Negative level triggering
The signal with Logic Low happens when negative level triggering is used. As
a result, the circuit is operated with this type of clock signal in this triggering.
The negative level triggering diagram is shown below:

Edge triggering
Edge triggering clock signals have two types of transitions: either from Logic
Low to Logic High or from Logic High to Logic Low.
The following types of edge triggering are based on the clock signal's
transitions:
Positive edge triggering
The clock signal of positive edge triggering transitions from Logic Low to
Logic High. As a result, the circuit is operated with this form of clock signal in
positive edge triggering. Below is a diagram of positive edge triggering.
Negative edge triggering
The clock signal of negative edge triggering transitions from Logic High to
Logic Low. As a result, the circuit is operated with this form of clock signal in
negative edge triggering. Below is a diagram of negative edge triggering.

Latches
A latch is a form of logical circuit that is unique. The latches have two stable
states: low and high. Latches are also known as bistable-multivibrators
because of these states. A latch is a data storage device that uses the feedback
lane to store data. Until the device is set to 1, the latch saves 1 bit. When the
enable input is set to 1, the latch updates the stored data and continuously tests
the inputs. The circuit operates in two states based on the enable signal. Both
inputs are low when the enable input is high, and both inputs are high when
the enable input is low.
Types of Latches
There are various types of latches used in digital circuits which are as follows:
SR Latch
Gated S-R Latch
D latch
Gated D Latch
JK Latch
T Latch
SR Latch
The SR latch is a sort of asynchronous device that handles control signals
separately. It is dependent on the R-inputs and S-states. The SR latch is
created by using a cross loop connection to join two NOR gates. The NAND
gate can also be used to create the SR latch. The SR latch's circuit diagram and
truth table are shown below.
Truth Table

S R Q Q'

0 0 latch Latch

0 1 0 1

1 0 1 0

1 1 0 0

 
Circuit Diagram
Gated SR Latch
A Gated SR Latch is a form of SR Latch that has three inputs: Set, Reset, and
Enable. The SET and RESET inputs are only effective if the enable input is
engaged. The SET and RESET inputs of a gated SR Latch are enabled via the
ENABLE input. A switch is connected to this ENABLE input. When this
switch is turned on, the Set-Reset inputs are enabled. Otherwise, all changes in
the set and reset inputs are ignored. The Gated SR latch's circuit diagram and
truth table are shown below.
Truth Table

Circuit Diagram

D Latch
The D latch and the D flip flop are the same thing. The ENABLE input is the
sole difference between these two. When the ENABLE input is set to 1, the
latch's output is the same as the input given to the Data input. The latch is
open at that point, and the path from input to output is transparent. The D
latch's output is the last value of the latch, irrespective of the input D, when
the ENABLE input is set to 0, and the latch is closed. The D latch's circuit
diagram and truth table are shown below.

Truth Table
Circuit Diagram

Gated D Latch
Another sort of gated latch is the Gated D Latch, which has two inputs: DATA
and ENABLE. When the enable input is set to 1, the data input becomes the
enable input. Otherwise, the output remains unchanged.
Using a gated SR latch, we can create a gated D latch. An inverter is used to
connect the set and reset inputs together. The outputs will be in opposition to
each other as a result of this. The Gated D latch's circuit schematic is shown
below.
Circuit Diagram

JK Latch
The JK Latch and the SR Latch are identical. When the JK inputs are high, the
output is toggled, and the ambiguous states are deleted. The main difference
between an SR latch and a JK latch is that the SR latch lacks output feedback
to the inputs, but the JK latch does. The JK latch's circuit diagram and truth
table are as follows:
Truth Table

Circuit Diagram

T Latch
By shorting the JK latch inputs, the T latch is formed. When the input is set to
1 or high, the T latch's output toggles. The T latch's circuit schematic is shown
below.
Circuit Diagram
Truth table:

Basics of Flip Flop

The term "flip flop" refers to a circuit with two stable states. These stable
states are used to hold binary data that can be modified by changing the inputs.
The flip flops are the digital system's essential building pieces. Data storage
elements include flip flops and locks. The flip flop is the simplest storage
element of a sequential logical circuit. Latches and flip flops are both basic
storage pieces, yet they work in distinct ways. Flip flops come in a variety of
styles:
SR Flip Flop
In the digital system, the S-R flip flop is the most common flip flop. When the
set input "S" is true in an SR flip flop, the output Y is high and Y' is low.
When the outputs are established, it is necessary to maintain the circuit wiring.
We keep the wiring in place until the set or reset input gets high or the power
is turned off.
Circuit Diagram

The S-R flip flop is the simplest and easiest circuit to understand.
Truth Table

J-K Flip-flop
The JK flip flop is used to eliminate the S-R flip flop's problem of
indeterminate states. The JK flip flop is created by making changes to the SR
flip flop. In order to produce the J-K flip flop, the S-R flip flop is upgraded.
The SR flip flop produces an erroneous output when both S and R inputs are
set to true. In the instance of the JK flip flop, however, the output is right.
Circuit Diagram:
If both of the inputs to a J-K flip flop are different, the output Y takes the
value of J at the next clock edge. If both of its inputs are low, no change
occurs; if both are high at the clock edge, the output will toggle from one state
to the other. In the digital system, the JK Flip Flop is a Set or Reset Flip Flop.
Truth Table

D Flip Flop
In digital systems, the D flip flop is a commonly used flip flop. Shift registers,
counters, and input synchronization all require the D flip flop
Circuit Diagram
Truth Table

T Flip Flop
T flip flop is used in the same way that JK flip flop is. In contrast to JK flip
flops, T flip flops have only one input: the clock input. The T flip flop is made
by combining both of the JK flip flop's inputs into a single input.
Circuit Diagram

Toggle flip-flop is another name for the T flip-flop. These T flip-flops can find
the complement of their current condition.
Truth Table

SR Flip Flop
The SR flip flop is a bistable 1-bit memory device with two inputs, SET and
RESET. The RESET input 'R' resets the device or produces the output 0. The
SET input 'S' sets the device or produces the output 1. S and R are the labels
for the SET and RESET inputs, respectively.
The "Set-Reset" flip flop is known as the SR flip flop. From the present state
with an output 'Q,' the reset input is utilized to return the flip flop to its
original state. This output is determined by the set and reset conditions, which
are either "0" or "1" logic levels.
The NAND gate SR flip flop is a simple flip flop that delivers feedback to its
opposing input from both of its outputs. In the memory circuit, this circuit is
used to store a single data bit. The SR flip flop contains three inputs, namely
'S' and 'R,' as well as the current output 'Q.' This 'Q' output is relevant to the
current condition or history. The phrase "flip-flop" refers to the device's ability
to be "flipped" into a logic set state or "flopped" back into the opposing logic
reset state.
NAND Gate SR Flip-Flop
By putting two cross-coupled 2-input NAND gates together, we can make a
set-reset flip flop. Feedback is connected from each output to one of the other
NAND gate inputs in the SR flip flop circuit. As a result, the device has two
inputs, namely Set 'S' and Reset 'R,' with two outputs, Q and Q'. The S-R flip
flop's block diagram and circuit diagram are shown below.
Block Diagram

Circuit Diagram
Set State
When the input R is set to false or 0 and the input S is set to true or 1, the
NAND gate Y has an input 0, which produces the output Q' 1 in the diagram
above. The value of Q' is faded into the NAND gate 'X' as input 'A,' and both
of the NAND gate'X's inputs are now 1(S=A=1), resulting in the output 'Q' 0.
Now, if the input R is changed to 1 with 'S' remaining 1, the inputs of NAND
gate 'Y' is R=1 and B=0. Here, one of the inputs is also 0, so the output of Q' is
1. So, the flip flop circuit is set or latched with Q=0 and Q'=1.
Reset State
The output Q' is 0, and output Q is 1 in the second stable state. It is given by R
=1 and S = 0. One of the inputs of NAND gate 'X' is 0, and its output Q is 1.
Output Q is faded to NAND gate Y as input B. So, both the inputs to NAND
gate Y are set to 1, therefore, Q' = 0.
Now, if the input S is changed to 0 with 'R' remaining 1, the output Q' will be
0 and there is no change in state. So, the reset state of the flip flop circuit has
been latched, and the set/reset actions are defined in the following truth table:
From the above truth table, we can see that when set 'S' and reset 'R' inputs are
set to 1, the outputs Q and Q' will be either 1 or 0. These outputs depend on
the input state S or R before the input condition exist. As a result, when the
inputs are 1, the outputs' statuses remain unaltered.
When both input states are set to 0, the condition is considered invalid and
must be avoided.
JK Flip Flop
The SR Flip Flop, also known as the Set-Reset Flip Flop, offers numerous
advantages. However, it has the following issues when switching:
This circumstance is always avoided when the Set 'S' and Reset 'R' inputs are
both set to 0.
When the Set or Reset inputs are changed while the enable input is 1, the
latching action is wrong.
The JK Flip Flop eliminates the SR Flip Flop's two flaws.
In digital circuits, the JK flip flop is one of the most commonly used flip flops.
The JK flip flop is a universal flip flop that accepts two inputs: 'J' and 'K.' The
reduced truncated letters for Set and Reset in the SR flip flop are 'S' and 'R,'
however J and K are not.
The JK flip flop functions similarly to the SR flip flop. Instead of 'S' and 'R,'
the JK flip flop features 'J' and 'K'. The only difference between a JK flip flop
and an SR flip flop is that an SR flip flop produces invalid states as outputs
when both inputs are set to 1, whereas a JK flip flop produces no invalid states
even when both 'J' and 'K' flip flops are set to 1.
The JK Flip Flop is a gated SR flip-flop with a clock input circuitry added to
it. When both inputs are set to 1, an invalid or illegal output state occurs,
which can be avoided by using a clock input circuit. As a result, the JK flip-
flop has four input combinations: 1, 0, "no change," and "toggle." Except for
the inclusion of a clock input, the JK flip flop has the same symbol as the SR
Bistable Latch.
Block Diagram

Circuit Diagram

Both the inputs 'S' and 'R' are replaced by two inputs J and K in an SR flip
flop. It signifies that the J and K inputs are equivalent to S and R.
Two 3-input NAND gates are substituted for the two 2-input AND gates. Each
gate's third input is connected to the outputs at Q and Q'. Because the two
inputs of the SR flip-flop are now interlocked, the earlier faulty condition of (S
= "1", R = "1") can be employed to achieve the "toggle action."
The J input is interrupted from the "0" state of Q' through the lower NAND
gate if the circuit is "set." When the circuit is set to "RESET," the top NAND
gate interrupts the K input from the 0 positions of Q. We can utilize Q and Q'
to manipulate the input because they are always different. The JK toggles the
flip flop according to the truth table when both inputs 'J' and 'K' are set to 1.
Truth Table:

The circuit is toggled from the SET state to the RESET state when both inputs
of the JK flip flop are set to 1 and the clock input is likewise pulse "High."
When both of the JK flip flop's inputs are set to 1, it functions as a T-type
toggle flip flop.
The JK flip flop is a clocked type of the SR flip flop. However, it still has a
"race" problem. When the state of the output Q is altered before the clock
input's timing pulse has chance to go "Off," this problem occurs. To avoid this
period, we must maintain a short time plus period (T).
D Flip Flop
The undefined input conditions of SET = "0" and RESET = "0" are banned in
the SR NAND Gate Bistable circuit. The SR flip flop has this disadvantage.
This is the situation:
The feedback latching action can be overridden.
Make both outputs 1 if possible.
The first input, which goes to 1, loses control of the latch, while the other
input, which controls the latch's resulting state, remains "0."
To keep this from happening, we'll need an inverter. The inverter is connected
between the Set and Reset inputs to create a D flip flop, Delay flip flop, D-
type Bistable, and D-type flip flop circuit.
From all the timed varieties, the D flip flop is the most crucial. It ensures that
both inputs, S and R, are never equal to one at the same time. A gated SR flip-
flop with an inverter linked between the inputs allows for a single input D in
the Delay flip-flop.
This single data input, labelled "D," is utilized in place of the "Set" input, and
the inverter is used for the complementary "Reset" input. As a result, a level-
sensitive SR flip flop is used to create a level-sensitive D-type or D flip flop.
So, here S=D and R= ~D (complement of D)
Block Diagram

Circuit Diagram
The SR flip-flop requires two inputs, one to "SET" the output and the other to
"RESET" the output, as we know. We can set and reset the outputs with only
one input by using an inverter because the two input signals now complement
each other. When both inputs are zero in an SR flip flop, that condition is no
longer feasible. In the D-flip flop, the complement eliminates the uncertainty.
The single input "D" is referred to as the "Data" input in a D flip flop. When
the data input is set to 1, the flip flop is set, and when the data input is set to 0,
the flip flop changes and is reset. This, however, would be pointless because
the flip flop's output would change with each pulse delivered to this data input.
To circumvent this, the "CLOCK" or "ENABLE" input is utilized to isolate
the data input from the latching circuitry of the flip flop. The D input
condition is only replicated to the output Q when the clock input is set to true.
Another sequential device known as D Flip Flop is built on this foundation.
When the clock input is set to 1, the flip-"set" flop's and "reset" inputs are also
set to 1. As a result, it will not change its state and will store the data that was
present on its output prior to the clock shift. To put it another way, the output
is "latched" at 0 or 1.
Truth Table

Symbols ↓ and ↑ indicates the direction of the clock pulse. D-type flip flop
assumed these symbols as edge-triggers.
T Flip Flop
The term "Toggle" is defined by "T" in T flip flop. To avoid an intermediate
state in SR Flip Flop, we just supply a single input named "Toggle" or
"Trigger." This flip-flop now functions as a toggle switch. The complement of
the current state output is used to change the following output state.
"Toggling" is the term for this process.
We can make alterations to the "JK Flip Flop" to create the "T Flip Flop." The
"T Flip Flop" has only one input, which is made by joining the JK flip flop's
inputs. T is the name of this single input. To put it another way, we can make
the "T Flip Flop" by converting a "JK Flip Flop." Sometimes the "T Flip Flop"
is referred to as single input "JK Flip Flop".
Block diagram of the "T-Flip Flop" is given where T defines the "Toggle
input", and CLK defines the clock signal input.

T Flip Flop Circuit

There are the following two methods which are used to form the "T Flip
Flop":
By connecting the output feedback to the input in "SR Flips Flop".
We pass the output that we get after performing the XOR operation of T and
QPREV output as the D input in D Flip Flop.
Construction
The "T Flip Flop" is created by feeding the output of the AND gate into the
NOR gate of the "SR Flip Flop." Each AND gate receives the inputs of the
"AND" gates, as well as the current output state Q and its complement Q'. The
AND gates receive the toggling input as input. The Clock (CLK) signal is used
to connect these gates. A pulse train of narrow triggers is used as the toggle
input in the "T Flip Flop," changing the flip flop's output state. The "T Flip
Flop" circuit schematic employing the "SR Flip Flop" is shown below:
The "T Flip Flop" is formed using the "D Flip Flop". In D flip - flop, the
output after performing the XOR operation of the T input with the output
"QPREV" is passed as the D input. The logical circuit of the "T-Flip Flop" using
the "D Flip Flop" is given below:

The simplest construction of a D Flip Flop is with JK Flip Flop. Both the
inputs of the "JK Flip Flop" are connected as a single input T. Below is the
logical circuit of the T Flip Flop" which is formed from the "JK Flip Flop":
Truth Table

When the output Q is set to 0, the top NAND gate is enabled and the lower
NAND gate is deactivated. The trigger delivers the S input to the flip flop
when the flip flop is in "set state (Q=1)."
When the output Q is set to 1, the top NAND gate is disabled and the lower
NAND gate is enabled. The R input is passed to the flip flop by the trigger,
which puts the flip flop in the reset state (Q=0).
Operations of T-Flip Flop
When the T input is set to false or 0, the next state of the T flip flop is similar
to the present state.
The next state will be 0 if the toggle input is set to 0 and the current state is
also 0.
The next state will be 1 if the toggle input is set to 0 and the current state is 1.
When the toggle input is set to 1, the flip flop's next state is the polar opposite
of the present state.
The next state will be 1 if the toggle input is set to 1 and the current state is 0.
The next state will be 0 if the toggle input is set to 1 and the current state is 1.
When the set and reset inputs are alternately adjusted by the incoming trigger,
the "T Flip Flop" is toggled. To complete a full cycle of the output waveform,
the "T Flip Flop" requires two triggers. The output frequency of the "T Flip
Flop" is half that of the input frequency. The "Frequency Divider Circuit" is
the "T Flip Flop."
The state at an applied trigger pulse is determined only when the prior state is
defined in "T Flip Flop." It is the "T Flip Flop's" primary flaw.
The "T flip flop" can be designed from "JK Flip Flop", "SR Flip Flop", and "D
Flip Flop" because the "T Flip Flop" is not available as ICs. The block
diagram of "T Flip Flop" using "JK Flip Flop" is given below:

Master-Slave JK Flip Flop

When both the inputs and the CLK are set to 1 for a long time in "JK Flip
Flop," the Q output toggles until the CLK is 1. As a result, the output is
uncertain or unreliable. In JK flip-flop, this problem is known as a race-round
condition, and it can be avoided by setting the CLK to 1 for only a short time.
Explanation
Two JK flip flops are combined to make the master-slave flip flop. In a series
configuration, these flip flops are connected. The first flip flop, known as the
master flip flop, works as a "master," while the second, known as the slave flip
flop, works as a "slave." The master-slave flip flop is built so that the "master"
flip flop's output is sent to both of the "slave" flip flop's inputs. The "slave"
flip flop's output is fed into the master flip flop's inputs.
Aside from these two flip flops, an inverter or NOT gate is also utilized in a
"master-slave flip flop." The inverter is connected to the clock's pulse to
transfer the inverted clock pulse to the "slave" flip flop. Simply said, if CP is
set to false for "master," it is set to true for "slave," and if CP is set to true for
"master," it is set to false for "slave."
Working
The slave flip flop will be in the isolated state when the clock pulse is true,
and the J and K inputs may impact the system's state. Until the CP is 1, the
"slave" remains isolated. The master flip-flop transmits the information to the
slave flip-flop to acquire the output when the CP is set to 0.
Because the master flip flop is the positive level trigger and the slave flip flop
is the negative level trigger, the slave flip flop replies first.
When the input J is set to 0 and K is set to 1, the master flip flop's output Q'=1
is transmitted to the slave flip flop as an input K. The slave flip flop is forced
to work as a reset by the clock, and then the slave copies the master flip flop.
When J=1 and K=0, the slave's output Q=1 is sent to the J input. The slave is
set and the master is copied by the clock's negative transition.
When the inputs J and K are both set to 1, the master flip flop activates the
clock's positive transition. The slave flip flop then activates the clock's
negative transition.
The flip flop will be disabled, and Q remains unchanged when both the inputs
of the JK flip flop set to 0.
Timing Diagram of a Master Flip Flop

When the clock pulse is set to 1, the master flip flop's output is one until the
clock input is set to 0.
The master's output is 0 when the clock pulse becomes high again, and it will
be set to 1 when the clock becomes one again.
When the clock pulse is 1, the master flip flop is active. Because the slave flip
flop is not operational, the slave output remains 0 until the clock is not set to 0.
When the clock pulse is zero, the slave flip flop is active. The master's output
remains one until the clock is not reset to 0.
Because the output changes only once in the cycle, toggling occurs throughout
the procedure.
Analysis of clocked sequential circuit
Sequential Logic Circuits
Unlike Combinational Logic circuits, which change state based on the signals
applied to their inputs at the time, Sequential Logic circuits have some form of
inherent "Memory" built in because they can take into account their previous
input state as well as those currently present, resulting in a sort of "before" and
"after" effect.

In other words, a "sequential logic circuit's" output state is a function of the

three states of "present input," "past input," and/or "past output." Sequential
logic circuits "remember" these conditions and remain in their current state
until the next clock signal changes one of the states, giving them "memory."
Sequential logic circuits are two-state or bistable devices that can have their
outputs set in one of two basic states, a logic level "1" or a logic level "0," and
will remain "latched" (hence the name latch) in this current state or condition
indefinitely until another input trigger pulse or signal is applied, causing the
bistable to change its state.
The name "sequential" denotes that events occur in a "sequence," one after
the other, and in Sequential Logic circuits, the real clock signal dictates when
events occur next. Simple sequential logic circuits can be built using common
Bistable circuits like Flip-flops, Latches, and Counters, which can be formed
by simply joining universal NAND and/or NOR Gates in a specific
combinational fashion to produce the desired sequential circuit.

HDL for Sequential Circuits

STATE REDUCTION AND ASSIGNMENT
Two sequential circuits may have the same input-output behaviour, but their
state diagrams may have a different number of internal states.
Certain features of sequential circuits can reduce the number of gates and flip-
flops used in a design, making it easier to implement. A circuit's cost is
reduced by reducing the number of flip-flops.
The state reduction challenge refers to the reduction in the number of flip-
flops in a sequential circuit. Procedures for lowering the number of states in a
state table while maintaining the external input-output requirements same are
referred to as state-reduction algorithms.
Example of State Reduction

First we need the state table: it is more convenient to apply procedures for
state reduction with the use of a table rather than a diagram.

After that, we use the reduction methods. "Two states are said to be equal if
they offer exactly the same output for each member of the set of inputs and
send the circuit to the same state or to an equivalent state."
When two states are comparable, one can be eliminated without affecting the
input-output interactions.
We look for two current states that lead to the same future state and have the
same output for both input combinations as we progress through the state
table. State g and state e are two examples.
"The row with current state g is removed, and state g is replaced by state e
each time it occurs in the columns headed "Next State," says the technique for
deleting a state and replacing it with its counterpart. State f and state d are also
equivalent, and state f can be eliminated and substituted with d.

Reducing the number of states in a state table can result in a circuit with fewer
equipments in general. However, it does not ensure a reduction in the number
of flip-flops or gates.

Shift Register
Shift Register is a collection of flip flops used to store multiple bits of data and
move the data from one flip flop to the next. When the clock pulse is applied
within and outside the registers, the bits recorded in the registers shift. We
need to connect n flip flops to make an n-bit shift register. As a result, the
number of flip flops is directly proportional to the number of bits in the binary
integer. The flip flops are wired together so that the output of the first flip flop
becomes the input of the second flip flop.
A Shift Register can shift the bits either to the left or to the right. A Shift
Register, which shifts the bit to the left, is known as "Shift left register", and it
shifts the bit to the right, known as "Right left register".
The following are the several types of shift registers:
Serial in Serial Out
Serial in Parallel Out
Parallel In Serial Out
Parallel In Parallel Out
Bi-directional Shift Register
Universal Shift Register
Serial IN Serial OUT
The data is serially shifted "IN" or "OUT" in "Serial Input Serial Output."
Under clock control, a single bit is moved in either the right or left direction in
SISO.
At first, all of the flip-flops are in "reset" mode, with Y3 = Y2 = Y1 = Y0 = 0.
When we pass the binary number 1111 to the Din bit, the LSB bit of the
number is applied first. The serial data input D3 is directly connected to the
D3 input of the third flip flop, FF-3. The next flip flop's data input d2 receives
the output Y3. The method for the remaining flip flops is the same. The
"Serial IN Serial OUT" block diagram is shown below.

Block Diagram
Operation
When the clock signal application is disabled, the outputs Y3 Y2 Y1 Y0 = 0000.
The LSB bit of the number is passed to the data input Din, i.e., D3. We will
apply the clock, and this time the value of D3 is 1. The first flip flop, i.e., FF-3,
is set, and the word is stored in the register at the first falling edge of the
clock. Now, the stored word is 1000.

The next bit of the binary number, i.e., 1, is passed to the data input D2. The
second flip flop, i.e., FF-2, is set, and the word is stored when the next
negative edge of the clock hits. The stored word is changed to 1100.

The next bit of the binary number, i.e., 1, is passed to the data input D1, and
the clock is applied. The third flip flop, i.e., FF-1, is set, and the word is stored
when the negative edge of the clock hits again. The stored word is changed to
1110.

Similarly, the last bit of the binary number, i.e., 1, is passed to the data input
D0, and the clock is applied. The last flip flop, i.e., FF-0, is set, and the word is
stored when the clock's negative edge arrives. The stored word is changed to
1111.

Truth Table

Waveforms

Serial IN Parallel OUT

The data is sent serially to the flip flop in the "Serial IN Parallel OUT" shift
register, and the outputs are fetched in parallel. The data is passed in the
register bit by bit, with the output disabled until the data is not supplied to the
data input. The outputs are enabled and the flip flops contain the return value
when data is sent to the register.
The 4-bit serial in parallel-out shift register block diagram is shown below. A
clear and clock signal are used to reset the four D flip-flops in the circuit with
four D flip-flops. The output of the first flip flop is the input of the second flip
flop, and so on in SIPO. Because the flip flops are synchronized, the same
clock signal is applied to each one. For communication, the parallel outputs
are employed.

Block Diagram

Parallel IN Serial OUT

The data is input in parallel in the "Parallel IN Serial OUT" register, and the
output is serial. Below is a four-bit "Parallel IN Serial OUT" register. The
previous Flip Flop's output is the current flip flop's input. The combinational
circuit connects the input and output signals. The binary inputs B0, B1, B2,
and B3 are routed through this combinational circuit. The two modes in which
the "PISO" circuit operates are shift mode and load mode.
Load mode
When the second, fourth, and sixth "AND" gates are active, the bits B0, B1,
B2, and B3 are sent to the corresponding flip flops. When the shift or load bar
line is set to 0, these gates open. When the clock's edge is low, the binary
inputs B0, B1, B2, and B3 are loaded into the appropriate flip-flops. As a
result, parallel loading takes place.
Shift mode
When the load and shift lines are set to 0, the second, fourth, and sixth gates
remain inactive. As a result, we are unable to load data in parallel. The first,
third, and fifth gates will be turned on at this point, and the data will be shifted
to the right bit. The "Parallel IN Serial OUT" procedure is performed in this
manner.

Block Diagram

Parallel IN Parallel OUT

In "Parallel IN Parallel OUT," the register's inputs and outputs are connected
in a parallel fashion. The data inputs D0, D1, D2, and D3 of the respective flip
flop are directly connected to the inputs A0, A1, A2, and A3. When the
negative clock edge is applied, the bits of the binary input are loaded into the
flip flops. The clock pulse is required for all of the bits to be loaded. The
loaded bits appear on the output side.
Block Diagram

Bidirectional Shift Register

The binary number created by multiplying the original number by 2 is
equivalent to the binary number produced by shifting each bit of the number to
the left by one place. Similarly, the binary number created by dividing the
original number by 2 is similar to the binary number produced by shifting each
bit of the number to the right by one place.
In order to conduct multiplication and division operations using the shift
register, the data must be transferred in both directions, i.e. left and right in the
register. The "Bidirectional" shift register is the name for such a register.
Below is the diagram of 4-bit "bidirectional" shift register where DR is
the "serial right shift data input", DL is the "left shift data input", and M is
the "mode select input".
Block Diagram
Operations
1) Shift right operation (M=1)
The first, third, fifth, and seventh AND gates will be active, while the second,
fourth, sixth, and eighth AND gates will be inactive.
When the clock pulse is delivered, the data on the data input DR is shifted bit
by bit from the fourth flip flop to the first flip flop. The shift right procedure is
performed in this manner.
2) Shift left operation (M=0)
The AND gates number two, four, six, and eight will be enabled, but the AND
gates number one, three, five, and seven will be disabled.
When the clock pulse is delivered, the data on the data input DR is shifted bit
by bit from the first flip flop to the fourth flip flop. The shift right procedure is
performed in this manner.
Universal Shift Register
The "uni-directional" shift register is a register that only shifts data in one
way. The term "bi-directional" shift register refers to a register that shifts data
in both directions. A "Universal" shift register is a unique form of register that
can load data in parallel and shift it in both directions (right and left).
To accomplish the parallel loading process, the input M, i.e., the mode control
input, is set to 1. The serial shifting procedure is executed if this input is set to
0. When the mode control input is connected to ground, the circuit becomes a
"bi-directional" register. The universal shift register is seen in the diagram
below. The register performs the "serial left" operation when the input is
delivered to the serial input. The register executes the serial right operation
when the input is delivered to input D.
Block Diagram

Applications of shift registers 

Shift registers are used in a variety of applications. Here's a sample of a few.
To create a time lag
As a time delay device, the serial in-serial out shift register can be used. The
length of the delay can be adjusted by:
The register's total number of stages
The frequency of the clock
In order to transform serial data into parallel data,
To make combinational logic easier to understand.
Counters
A counter is a form of sequential circuit that counts the pulses, or a group of
flip flops to which the clock signal is applied.
One of the most common uses for the flip flop is as a counter. The counter's
output comprises a predetermined state based on the clock pulse. The counter's
output can be used to count the number of pulses.
Truth Table

There are the following types of counters:

Asynchronous Counters
Synchronous Counters
Asynchronous or ripple counters
The ripple counter is another name for the asynchronous counter. The 2-bit
Asynchronous counter, in which two T flip-flops were utilized, is shown
below. We can utilize the JK flip flop instead of the T flip flop by setting both
inputs to 1 permanently. The external clock pass to the clock input of the first
flip flop, i.e., FF-A and its output, i.e., is passed to clock input of the next flip
flop, i.e., FF-B.
Block Diagram
 Signal Diagram

Operation
Condition 1: When both the flip flops are in reset condition.
Operation: The outputs of both flip flops, i.e., QA QB, will be 0.
Condition 2: When the first negative clock edge passes.
Operation: The output of the first flip flop will vary from 0 to 1 as the first flip
flop toggles. The clock input of the next flip flop will take the output of this
flip flop. The second flip flop will use this output as a positive edge clock.
Because it is a negative edge triggered flip flop, this input will have no effect
on the output state of the second flip flop.
So, QA = 1 and QB = 0
Condition 3: When the second negative clock edge is applied.
Operation: The output of the first flip flop will change from 1 to 0, while the
output of the second flip flop will change from 1 to 0. The second flip flop
will use this output as a negative edge clock. Because it is a negative edge
triggered flip flop, this input will affect the output state of the second flip flop.
So, QA = 0 and QB = 1.
Condition 4: When the third negative clock edge is applied.
Operation: The output of the first flip flop will change from 0 to 1 as the first
flip flop toggles again. The second flip flop will use this output as a positive
edge clock. Because it is a negative edge triggered flip flop, this input will
have no effect on the output state of the second flip flop.
So, QA = 1 and QB = 1
Condition 5: When the fourth negative clock edge is applied.
Operation: The output of the first flip flop will change from 1 to 0, while the
output of the second flip flop will change from 1 to 0. The second flip flop
will use this output as a negative edge clock. The output state of the second
flip flop will be changed by this input.
So, QA = 0 and QB = 0
Synchronous counters
The output of the current counter is passed to the input of the next counter in
an asynchronous counter. As a result, the counters form a chain. The
disadvantage of this approach is that it introduces a counting delay, as well as
a propagation delay, during the counting stage. The synchronous counter was
created to address this flaw.
The clock input of all the flip flops in the synchronous counter receives the
same clock pulse. The clock signals generated by all of the flip flops are
identical. The inputs of the first flip flop, FF-A, are set to 1 in the schematic
below of a 2-bit synchronous counter. As a result, the first flip flop will
function as a toggle flip flop. The first flip flop's output is sent into both of the
JK flip flop's inputs.
Logical Diagram
 Signal Diagram

Operation
Condition 1: When both the flip flops are in reset condition.
Operation: The outputs of both flip flops, i.e., QA QB, will be 0.
So, QA = 0 and QB = 0
Condition 2: When the first negative clock edge passes.
Operation: The output of the first flip flop will be changed from 0 to 1, and
the first flip flop will be toggled. The first flip flop's output will be 0 when the
first negative clock edge is passed. The first flip flop's clock input, as well as
both of its inputs, will be set to 0. The state of the second flip flop will remain
unchanged in this manner.
So, QA = 1 and QB = 0
Condition 2: When the second negative clock edge is passed.
Operation: The output of the first flip flop will be changed from 1 to 0, and
the first flip flop will be toggled again. The first flip flop's output will be 1
when the second negative clock edge is passed. The first flip flop's clock
input, as well as both of its inputs, will be set to 1. The state of the second flip
flop will shift from 0 to 1 in this manner.
So, QA = 0 and QB = 1
Condition 2: When the third negative clock edge passes.
Operation: The first flip flop will switch from 0 to 1, but both inputs and the
clock input will be set to 0. As a result, the outputs will remain unchanged.

So, QA = 1 and QB = 1
Condition 2: When the fourth negative clock edge passes.
Operation: The first flip flop will toggle from 1 to 0. At this instance, the
inputs and the clock input of the second flip flop set to 1. Hence, the outputs
will change from 1 to 0.
So, QA = 0 and QB = 0
Ripple Counter
The clock pulse ripples through the circuit in a ripple counter, which is a sort
of Asynchronous counter. The n-MOD ripple counter is created by adding n
flip-flops together. The n-MOD ripple counter can count up to 2n states before
returning to its initial value.
Features of the Ripple Counter:
Particular varieties of flip flops are utilized, each having a different clock
pulse.
An asynchronous counter is an example of this.
Toggle mode is utilized with the flip flops.
Only one flip flop receives the external clock pulse. This flip flop's output is
used as a clock pulse for the next flip flop.
The flip flop through which the external clock pulse is transferred acts as the
LSB in the counting sequence.
Counters are categorized into the following types based on their circuitry
design:
Up Counter
The states are counted in ascending order by the up-counter.
Down Counter
In descending order, the states are counted by the down counter.
Up-Down Counter
The up and down counter is a form of bi-directional counter that counts states
either forward or backward. A reversible counter is often referred to as a
reversible counter.
Binary Ripple Counter
A Binary counter is a two-mode counter that counts up to two-bit state values,
or 22 = four values. The Ripple counter is made up of flip flops with identical
toggling circumstances, such as T and JK. A binary ripple counter's circuit
diagram is shown below.
Two JK flip flops are employed in the binary ripple counter's circuit design.
The high voltage signal is applied to both flip flops' inputs. The flip flops are
kept in state 1 by this high voltage input. The negative triggered clock pulse is
used in JK flip flips.
The LSB and MSB bits are outputs Q0 and Q1, respectively. The truth table of
the JK flip flop helps us understand how the counter works.

The fourth condition of the JK flip flop happens when high voltage is applied
to the inputs of the flip flops. When we supply high voltage to the flip-input,
flops the flip-flops will be in state 1. As a result, at the negative going end of
the clock pulse, the states of the flip flips passes are toggled. To put it another
way, the flip flop toggles when the clock pulse transitions from 1 to 0.
When the negative clock edge passes through the flip flop, the state of the
output Q0 changes. All of the flip flops are initially set to 0. When the passed
clock goes from 1 to 0, these flip flops change states. When the inputs of the
flip flops are all one, the JK flip flop toggles, changing its state from 0 to 1.
The procedure is the same for all clock pulses.

The clock pulse from the first flip flop is passed to the second flip flop. The
state of the second flip flop is changed when the output Q0 transitions from 1
to 0 as shown in the timing diagram above. Q0 and Q1 are treated as LSB and
MSB, respectively. The counter keeps track of the numbers 00, 01, 10, and 11.
The counter resets itself after counting these figures and begins counting anew
from 00, 01, 10, and 1. Count values until clock pulses are sent to the J0K0 flip
flop.
Ring Counter
A ring counter is a specific sort of Serial IN Serial OUT Shift register
application. The main difference between the shift register and the ring
counter is that the shift register uses the last flip flop result as the output.
However, in the ring counter, this result is supplied as an input to the first flip
flop. Everything else in the ring counter is identical to what's in the shift
register.
In the Ring counter
No. of states in Ring counter = No. of flip-flop used
The 4-bit ring counter's block diagram is shown below. We're using four D
flip flops here. As a synchronous counter, the same clock pulse is sent to the
clock input of all the flip flops. This circuit is designed using the Overriding
input (ORI).
The Overriding input is used as clear and pre-set.

When the pre-set is set to 0, the output is 1. When the clear parameter is set to
0, the output is 0. Because PR and CLR are active low signals, they always
work in the value 0 range.
PR = 0, Q = 1  
CLR = 0, Q = 0 
These two values (always fixed) are independent with the input D and the
Clock pulse (CLK).
Working
The ORI input is passed to the PR input of the first flip flop, i.e., FF-0, and it
is also passed to the clear input of the remaining three flip flops, i.e., FF-1, FF-
2, and FF-3. The pre-set input set to 0 for the first flip flop. So, the output of
the first flip flop is one, and the outputs of the remaining flip flops are 0. The
output of the first flip flop is used to form the ring in the ring counter and
referred to as Pre-set 1.
In the above table, the highlighted 1's are pre-set 1.
The Pre-set 1 is generated when
ORI input set to low, and that time the Clk doesn't care.
When the ORI input set to high, and the low clock pulse signal is passed as the
negative clock edge triggered.
A ring forms when the pre-set 1 is shifted to the next flip-flop at each clock
pulse.
So, 4-bit counter, 4 states are possible which are as follows:
1 0 0 0  
0 1 0 0  
0 0 1 0  
0 0 0 1  
Types of Ring Counter
The ring counter is classified into two parts which are as follows:
Straight Ring Counter
One hot counter is referred to by the Straight Ring Counter. The result of the
previous flip-flop is used as an input to the first flip-flop. The ORI input is
connected to the PR input of the first flip flop and the clear input of the other
flip flops in the ring counter.
Logic Diagram
Truth Table

Signal Diagram

Twisted Ring Counter

A switch-tail ring counter is what the Twisted Ring Counter is called. The
result of the last flip-flop is transmitted to the first flip-flop as an input, just
like the straight ring counter. The ORI input is given as clear input to all the
flip flops in the twisted ring counter.
Logic Diagram

Truth Table

Signal Diagram

Johnson Counter
The Ring counter and the Johnson counter are very similar. The main
difference between the Johnson counter and the ring counter is that the last flip
flop's result is supplied as an input to the first flip flop. The inverted outcome
Q' of the last flip flop, on the other hand, is provided as an input in the
Johnson counter. The Johnson counter's remaining tasks are similar to those of
a ring counter. The Creeping counter is another name for the Johnson counter.
In Johnson counter
No. of states in Johnson counter = No. of flip-flop used  
Number of used states=2n  
Number of unused states=2n - 2*n 
The 4-bit Johnson counter is depicted below. The 4-bit Johnson counter uses
four D flip flops, similar to the Ring counter, and the same clock pulse is
applied to all of the flip flops' inputs.

Truth Table

CP Q1 Q2 Q3 Q4

0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1
5 0 1 1 1

6 0 0 1 1

7 0 1 1 1

The above table state that

When there is no clock input, the counter produces the value 0000.
When the first clock pulse is sent to the flip flops, the counter outputs 1000.
When the second clock pulse is transmitted to the flip flops, the counter
produces the output 1100.
When the third clock pulse is delivered to the flip flops, the counter outputs
output 1110.
When the fourth clock pulse is transmitted to the flip flops, the counter
produces the result 1111.
When the fifth clock pulse is sent to the flip flops, the counter produces the
output 0111.
When the 6th clock pulse is transmitted to the flip flops, the counter produces
the output 0011.
The counter produces the output 0001 when the 7th clock pulse is passed to the
flip flops.
Timing diagram

Advantages
The number of flip flops in the Johnson counter is the same as in the ring
counter, and the Johnson counter can count twice as many states as the ring
counter can.
D or JK flip flops can also be used to create the Johnson counter.
The Johnson ring counter counts the data in a continuous loop.
The Johnson counter's circuit is self-decoding.
Disadvantages
In a binary sequence, the Johnson counter is unable to count the states.
The unutilized states are greater than the states that are used in the Johnson
counter.
One half of the amount of timing signals equals the number of flip flops.
The Johnson counter can be configured for any number of timing sequences.

HDL for Registers and Counters

In HDL, registers and counters can be described on a behavioral or structural
level.
The many components are instantiated to build a hierarchical design
description, comparable to a logic diagram representation.
Shift Register
Synchronous Counter
Ripple counter