Scribd
Upload
64 views11 pages

Assignment2 Solution

This document contains 16 questions regarding digital logic design concepts such as Boolean algebra, binary arithmetic, binary to decimal conversions, logic gates, adders, decoders, and Gray code. The questions cover simplifying Boolean functions, binary conversions, logic operations, combinational logic design, and decoder implementation.

Uploaded by

Syed Abdullah Hasan Chishti
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
Download as pdf or txt
64 views11 pages

Assignment2 Solution

This document contains 16 questions regarding digital logic design concepts such as Boolean algebra, binary arithmetic, binary to decimal conversions, logic gates, adders, decoders, and Gray code. The questions cover simplifying Boolean functions, binary conversions, logic operations, combinational logic design, and decoder implementation.

Uploaded by

Syed Abdullah Hasan Chishti
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
Download as pdf or txt
Download as pdf or txt
You are on page 1/ 11

Digital Logic Design - Fall 2022 – Assignment-2 - Solution

Q1. Simplify the following Boolean function F, together with the don’t-care conditions d, and then
express the simplified function in sum-of-minterms form.

𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∑(4,12,7,2,10)

𝑑(𝐴, 𝐵, 𝐶, 𝐷) = ∑(0,6,8)

Q2. Convert the following binary numbers into decimal


a) 100001 (33) d) 111001 (57) f) 1110001.0001
b) 100111 (39) e) 1011100.10101 (113.0625)
c) 11111101 (253) (92.65625) g) 110011.01 (51.25)
h) 1111000.101 (120.625)

Q3. Convert the following binary numbers into hexadecimal, octal, Gray codes and BCD codes:
a) 100001 (21)16 (41)8 (110001)GC (0011 0011)BCD
b) 100111 (27)16 (47)8 (110100)GC (0011 1001)BCD
c) 11111101 (FD)16 (375)8 (10000011)GC (0010 0101 0011)BCD
d) 111001 (39)16 (71)8 (100101)GC (0101 0111)BCD
Q4. Convert each decimal number to binary and BCD codes (a, b only):
a) 25 (11001)2 (0010 0101)BCD
b) 78 (1001110)2 (0111 1000)BCD
c) 0.456 (000.01110100101111000111)2
d) 12.8732 (1100.11011111100010100001)2

Q5. Perform the following binary arithmetic operations:


a) 111 + 110 (1101)2
b) 1101 – 101 (1000)2
c) 1100 × 101 (111100)2
d) 1010 ÷ 10 (0101)2

Q6. Determine the 1’s and 2’s complement of each binary number:
a) 1100 - 1’s complement (0011) 2’s complement (0100)
b) 101010 - 1’s complement (010101) 2’s complement (010110)
c) 10111011 - 1’s complement (01000100) 2’s complement (01000101)
d) 11001100 - 1’s complement (11001100) 2’s complement (11001101)

Q7. Convert the following into binary number:


a) 6358 (110 011 101)2
b) 788 (invalid)
c) A7B816 (1010 0111 1011 1000)2
d) 74CD16 (0111 0100 1100 1101)2
Q8. Add the following BCD numbers:
a) 1000 + 0110 (14)BCD
b) 0111 + 0101 (12)BCD

c) 1001 + 0111 (10)BCD

d) 00100101 + 00100111 (52)BCD

e) 10011000 + 10010111 (135)BCD


f) 010101100001 + 011100001000 (1269)BCD

Q9. Convert each Gray code to Binary:


a) 1010 (1100)2
b) 00010 (00011)2
c) 1100001000 (1000001111)2

Q10. Write the output expression for each circuit:


Q11. Implement the following Logic using NAND and NOR gates or a combination of both:
𝑋 = 𝐴̅𝐵 + 𝐶𝐷 + (𝐴
̅̅̅̅̅̅̅̅
+ 𝐵)(𝐴𝐶𝐷 + ̅̅̅̅
𝐵𝐸 )
𝑋 = 𝐴𝐵𝐶̅ 𝐷 ̅̅̅̅
̅ + 𝐷𝐸̅ 𝐹 + 𝐴𝐹

Q12. Show the decoding logic for each of the following codes if an active-HIGH (1) output is
required:
a) 1101
b) 1000

c) 101010

d) 111110

e) 1110110

Q13. Design a combinational circuit with three inputs and one output.
a) The output is 1 when the binary value of the inputs is less than 3. The output is 0
otherwise.

Truth Table
INPUT OUTPUT
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
b) The output is 1 when the binary value of the inputs is an even number.

Truth Table
INPUT OUTPUT
A B C Y
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Q14. Design a combinational circuit that converts a four-bit Gray code to a four-bit binary
number. Implement the circuit with exclusive-OR gates.

Truth Table
INPUT (Gray OUTPUT
Code) (Binary Code)
A B C D B4 B3 B2 B1

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 1 1 1 1 1
Q15. The adder–subtractor circuit of Fig. 4.13 (Morris Book) has the following values for mode
input M and data inputs A and B.

In each case, determine the values of the four SUM outputs, the carry C , and overflow V.
a) Sum-1101, C-0, V-1
b) Sum-0001, C-1, V-1
c) Sum-0101, C-1, V-1
d) Sum-0010, C-1, V-0
e) Sum-0010, C-0, V-0
Q16. Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-to-4-
line decoder. Use block diagrams for the components.

You might also like