3EEI 256: Multi-L.evel Inveters for igh Power Inuetion Motor Drives, Dr.

P, N, Tekwani

NIRMA UNIVERSITY OF SCIENCE AND TECHNOLOGY,INSTrrUTE OF TECHNOLOGY

Department of Electrlcal Engneering
M.Tech.
Electrienl Engg. (Power
Apparatus and Systems),
Semester I I
3FB1256: Multi L.evel Inverters for High-Powertnduction MotorDrives (Elective - I1)

HANDOUT-2 (15th January, 2008)

Theory of Multi-LevelInverter
Course Coordinator: Dr. P. N. Tekwani

Multi-level inverters generate output voltage with stepped waveforms by using an array of power
semiconductors and capacitor voltage sources. The commutation of switches permits the addition of the
capacitor voltages, which reach high voltuge at the output, while the power semiconductors must
withstand only reduced voltages. Fig. 1.3 shows the schematic of one phase leg (pole-A) of inverters
with different numbers of levels, for which the action of power semiconductors is represented by an
ideal switch with several positions. As shown in Fig. 1.3(a), for two-level inverter, the position of the
switch is represented by switching function sa, which can attain any of the two distinct values 0 or1
The point O in Fig. 1.3(a) is a fictitious neutral point (mid point of the dc-link) considered for the
representation of the pole voltage yao. Thus, vao = -Va/2 when sa = 0, and vao= Va/2 when sa = 1.
Similarly, the switching function for pole-B and pole-C are defined as sp and sc, respectively.
For a three-level inverter, as shown in Fig. 1.3(6), the pole voltage levels - Va/2, 0, and VacJ2 can

be attained with corresponding switching function values 0, 1, and 2, respectively. In a similar way, for

a five-level inverter, the pole voltage levels -Va/2, -Vas/4, 0, VaJ4 and Va/2 can be attained with
switching function values 0, 1, 2, 3, and 4, respectively (Fig. 1.3(c)). For a general n-level inverter, the
switching function has a range from 0 to n-1, as shown in Fig. 1.3(d).
Yae/2
Vae2

Va/4 CTVn-3/20m-19,
4 Co 1y2 n-2 -
Va/2 C3 n-1/2
Vad2 SA Vde T

C Vae A
Conm12
C2 T
Va Ot VaT O
-Vdo/4 -Vdc (n-3)/2(n-1)
CiT
V do 4 -Vd/2 -Vao/2 Vau/2
(a) (b) (c) (d)
Fig. 1.1: Representation of one leg (pole) of an inverter: (a) two-level, (b) three-level, (c) five-levet, and
(d) general n-level

The pole voltages of inverter are defined in terms of the switching functions as in (1.1), where n

represents the number of levels of inverter. When an induction motor with Wye (Y) connected stator is
connected at the output terminals of the inverter, the inverter pole voltage can be represented in terms of
 SEEI256: Multi-Level Invertersor High-Power Induction Motor Drives, Dr. P. N. TEkwani

PIase to motor neutral-point voltages and motor neutral to the inverter dc-link neutral (mid) poin

voltage, as given by (1.2). Considering balanced three-phase system (i.e., VAvtVaNtVCN=U), .2) can be
rewritten as (1.3). The voltage vno is known as common-mode voltage (CMV). Using (1.2) and (1.3),
phase to motor neutral-point voltages can be expressed in terms of the inverter pole voltages by (1.4)
a y the motor line-to-line voltages can be writet as in (1.5). The inverter pole voltages contain

narmonics of third order and its muitiples (triplen harmonics), which are absent (as they get cancelled)
the
1n phase-to-motor neutral voltage and line-to-line voltage.

"AO Vae
SA-((n-1)/2)1
VBO (n-1)°B{-)/2) (1.1)
Vco Lc-(n-1)/2)
AOAN +No
VBOVBN +VNO (1.2)
VcoJ LVcN +VNo

NoAot "Bo tVcol (1.3)

AN 2-1 -1VAO
VBN (1.4)
LCN -1 -1
2 jlvco.
AB -1 0Ao
VBC=0 1 -1VB0 (1.5)
VcA-1 0 1 lco
The inverter
voltage phasor is represented in terms of the three pole
space
is evident from voltages as in (1.6). It
(1.2) and (1.3) that the phase voltages vAN, VsN VCN also result
in the same
phasor Vs. Hence, the inverter
voltage space
voltage space phasor represents the combined information of all the three
phase voltages. The space phasor Vs can be resolved into two rectangular components (along a and B
axes) as shown in (1.7). The relationship between the components of Vs and the instantaneous
voltages of motor is phase
given by the conventional ABC-oß transformation as in (1.8).
inverse
Similarly, the
transformation in (1.9) provides oß-ABC conversion.
j240°
sVAO+VBoe" +Vcoe (1.6)
Vs-Vs(a)* s{p) (1.7)
s -y2 -/2 AN
Vs) o /2 -5/2 BN (1.8)

-2
 3EEI256: Multi-Level Inverters for High-Power Induction Motor Drives, Dr. P. N. Tekwani

NIRMA UNIVERSITY OF SCIENCE AND TECHNOLOGY, INSTITUTE OF TECHNOLOGY

Department of Electrical Engineering
M.Tech. Electrical Engg. (Power Apparatus and Systems), Semester - II
3EE1256: Multi-Level Inverters for High-Power Induction Motor Drives (Elective - I)

HANDOUT-3 (21t January, 2008)

Conventional Topologies of Multi-Level Inverter
Course Coordinator: Dr. P. N. Tekwani

Various topologies of multi-level inverters are reported in the literature. The most commonly used
multi-level inverter configurations are neutral-point-clamped (NPC) (diode-clamped), flying capacitors
(capacitor-clamped), cascaded H-bridge (cascaded multicell) and dual inverter fed open-end winding
IM structure. Comparative studies have been carried out for these inverter topologies to judge their

performance. The operating principles of these basic multi-level inverter configurations are discussed in
the following sub-sections.

1.1.1 Neutral-point-clamped (NPC) multi-level inverter topologies

In this class of inverter topologies, the dc-link is split into number of smaller voltage levels using
a bank of series-comnected bulk capacitors. The inverter structure allows the comnections of the inverter

poles to any one of these voltage levels, thus generating a multi-level voltage waveform at the output. In
the year 1981, Nabae et al. introduced a three-level inverter, which is shown in Fig. 1.5. Here, the

middle point O of the two de-link capacitors CI and C2 is defined as a neutral-point. This multi-level
inverter topology is popularly known as neutral-point-clamped NPC) PWM inverter, as the mid
voltage level is formed by clamping the switching devices to the neutral-point of the dc-bus. Each leg of
the inverter consists of four switches and two diodes
(clamping diodes).
Each pole of this inverter can attain one of the three voltage levels -Va/2 (-), zero (0') and

Vac 2 (+"), with respect to the neutral-point O. The output voltage at the pole-A of the inverter vao
reaches the level of Va/2. when the top switches Si1 and Si2 are turned ON. Level -Vas2 is realized
when the bottom switches S13 and S14 are ON. When the inner two switches, Si2 and S13, are ON, the
voltage vAo gets clamped to the neutral point (O' level) through the diode Dii or Di2 depending on the
direction of the load current. The inverter switches are switched in complementary fashion, for example,
in pole-A, Si is switched complementaryS13, and S12 is switched complementary to S14. The
to

relationship between the switch state and the pole voltage for any phase can be summarized as shown in
Table 1.1.

1-1
 Vae/2

C D21

Vae oO
B
Induction
D Motor

S
Fig. 1.1: Power schematic of a three-level neutral-point-clamped (NPC) inverter

Table 1.1: Generation of three different voltage levels based on state of the switches for pole-A (Fig. 1.5)*
Pole voltage Voltage State of the switch**
VAO level

Va/2

-Va/2
*IS1 and Si3, as well as Si2 and S14 are two different complementary pairs of the switches]
**
["1" indicates ON state and "0" indicates OFF state of the switch]
The key components that distinguish this circuit of a three-level inverter from a conventional two-
level inverter the
clamping diodes. The two diodes in each pole of the inverter clamp the switch
are

voltage to half the level of the dc-bus voltage. Therefore, the maximum voltage stress on each switch is
limited to the voltage across each capacitor, which is Vdo/2, when the
capacitor voltages are assumed to
be steady (balanced). Hence, the voltage stress of the inverter switches with this
three-level structure is
half to that of conventional two-level inverter that operates with the same dc-link
a
voltage Vdc. It can
be seen from Table 1.1, that two switches of a pole are always open for any voltage level and thus
share
the voltage stress equally. Thus the voltage rating of the switches is half the de-link voltage and the
blocking voltage rating of the clamping diodes is also half the dc-link voltage.
Extension of the three-level inverter configuration of Fig. 1.5 to the higher number of levels is
possible by subsequent splitting of dc-bus, A simple generalised structure of multi-level inverter is
presented in, which is a direct realisation of the multi-level concept using bi-directional switches. The
dc-link is spilt to several smaller voltage levels and the output terminal can be connected to any of these
levels by turning on the respective bi-directional switch. The
the different switches in this
stress on

topology wil depend on its position in the ladder structure and the top most and bottom most switches
have to block the full de-link voltages. A generalised structure of multi-level inverter proposed in,is a
direct extension of the NPC three-level inverter.
The configuration for a five-level NPC inverter is shown in Fig. 1.6, where four (ie., n-1) series

connected capacitors are used to realise the five voltage levels. Each capacitor of the dc-link has a
1-2
3EE1256: Multi-Level Inverters for High-Power Induction Motor Drives, Dr. P. N. Tekwaní

across one capacitor only, There are

voltage of Va/4 across it and each switch has to block the voltage
four pairs of switches in each leg (for example, Si and S15), which operate in complementary fashion
and thus the reverse blocking voltage rating of the power switched is equal to Va4. The poBe voltage
three-level
can be equal to Va/2, Vao/4, 0, -Vad4, or -Vao/2, with respect to neutral-point O. Unlike the
NPC inverter, the diodes in the five-level configuration has to be rated for different voltages, which can
The blocking voltage of each clamping
be higher than the blocking voltages of the switching devices.
on its position in the structure, and for an
n-level inverter, the two diodes per leg will see
diode depends
given by (1.12). For example, when lower three devices (S16, S17 and Sis) are on,
blocking voltage as
diode Di4 has to block three times capacitor voltage, i.e. 3Vdd4 (k = 1 in (1.12)), as evident from Fig.

1.6(a). Similarly, Di3 has to block 3Va/4 voltage, while, Di2 and Dis has to block Va/2 voltage (k =2
in (1.12)), whereas Di1 and Di6 has to block VaA voltage (k = 3 in (1.12)).

Vdiode Vae here k =1,2,..-2 (0.1)

n-1

Vdc/2 Vadc/2

C4 C4

Vac/4 Vae/4
S13

Vac
0 A Va
h4
C2T

4 -Vda/4

S18
Vdo/2 * * * * * * * * ° " " * * * * * * * a * * a * * a * * * * * * * * * " p *** a * * *

Vde/2
(a) (6)
Fig. 12: One leg of a five-le vel NPC (diode-clamped) inverter with: (a) clamping diodes of different voltage ratings, and (b)
clamping diodes of equal voltage ratings

An extended structure for an n-level inverter uses a total of n-l dc-link capacitors. In general, for
an NPC multi-level inverter topology, each capacitor has voltage across it equal to Vaon-1) and the
voltage stress on each switching device is equal to Va/(n-1), where n is the level ofinverter.An n-level
inverter structure requires 2(n-1) switches of equal voltage rating and 20n-2) neutral-point clamping
diodes of unequal voltage rating per leg (phase). For example, Fig. 1.6(a) shows a phase of a five-level

1-3
 3EET

complement
Multi-Level Inverters for High-Power
Induction Motor
Drives, Dr.
P. N.
1ekwatu

availabil
4
h e same
rating (eaCn naving
diodes of equal voltage un
nverter structure. On the other hand, if the number of
diodes has to be
used. then the more

voltage as the switching devices) are

total number of
In this case, the
D1Ocking
five-level inverter.
connected im series, as shown in Fig. 1.6(b) for a
increment in
shows a substantial
(n-1) (n-2), which
pole of the inverter is given by
x
per the
OCSrequired voltage, using
diodes with equal blocking
A pyramidal structure for the clamping
the diode count. eliminate the series assoclauon
number of diodes as the series connected structure is presented to
Same leads to the complex
of the diodes. The quadratic increase in the number of clamping diodes
clamping wnen

and make the NPC (diode-clamped) inverter system

impractical to implement
power-bus structure
the number of levels is sufficiently high. across the series
the neutral-point clamped strategy, voltage
In the multi-level inverters based on
of the dc-link voltages amon8
connected capacitors
is assumed to be constant to achieve equal sharing
on the
the switches. But, these capacitor voltages can fluctuate over a fundamental cycle (depending
load current drawn from the dc-link) and this means that devices are called upon to blck higher

than the ideal condition where each device has to block only Vd/n-1) for an n-level inverter.
voltages
This voltage unbalance problem can be addressed with special PWM control strategies or by replacing

the capacitors with separately controlled de-link voltages. The fluctuations in the neutral-point voltage
for a three-level inverter can be reduced by using an inner clamping capacitor across the clamping

diodes.

1.1.2 Flying capacitor multi-level inverter structures

In the year 1992, T. A. Meynard and H. Foch introduced the concept of a multi-level
commutation cell to be used as building blocks for multi-level inverters. Fig. 1.7(a) shows the structure
of one such multi-level commutation cell, which is equivalent to one leg of a three-level inverter. In this
configuration the capacitor C acts as a floating source chargedto Va/2. This circuit is called the fying
capacitor (or capacitor-clamped) inverter, as independent capacitors clamp the device voltage to one
capacitor voltage level. The four switches forming this cell are in two pairs, the inner two switches (S12
and S13) forming one pair and the outer two switches (S11 and Si4) forming the other pair. The switches
within each pair must always be in complementary states. The dc-link voltage Vae and the voltage on
the floating capacitor Va/2, ensure that the blocking voltage across any switch is Vao2 (i.e., Vae

(Vad2)).
The general concept here is that the capacitor can be kept charged to half thè de-link voltage and
the capacitor voltage can be added or subtracted from the dc-link voltage to generate more levels at the
output pole of the inverter. The pole voltage vAo can reach Vao2 when the upper two switches (S11 and
S12) are turned ON and vao can reach the level of -VdoJ2 when the bottom two switches (S13 and S14) are
ON. The "0' level can be attained in two ways, S1 and S13 are ON (i.e. Si2 and Si4 are OFF, as they are

1-4
SEBI256: Multi-Level Inverters for High-Power Induction Motor Drives, Dr. P. N. Tekwani

complementary to S1 and Si3 respectively) or Si2 and S14 are ON (e., Si1 and Si3 are OFF). The
availability of such redundancy of switching combinationsin realising the intermediate voltage levelsis
a unique feature of the multi-level inverter configurations based on these cells. Further, this unique
feature of switching redundancy associated with the phase can be used as an added advantage to
maintain the capacitor voltage balance. The relationship between the pole voltage'and switching states
of the inverter can be summarized as shown in Table 1.2.
The multiplicity, with which the middle voltage levels are obtained, increases for flying capacitor
structures of higher levels. For example, the five-level flying capacitor shown in Fig. 1.7(b), the

multiplicity for the pole voltage levels of Vas2, Vac/4, 0, -Val4, and -Vad2 are 1, 3, 6, 3, 1 respectively.

In this configuration also, by proper selection of

the switching combination, the capacitor voltages can be maintained at the balanced state.

Fig. 1.7(c) gives the general circuit of one leg of such a multi-level inverter. The voltage across

the floating sources (the flying capacitors) naturally evolves to the expected value in open-loop systems.

In other systems, these capacitor voltages have to be kept constant by ensuring equal charging and
discharging of these capacitors over a switching time period. This
is achieved by proper selection of the
switches. Hence the control
switching combinations to impose equal duty ratios for the respective
-

Vc/2

Vae/2
HS12
Vac/14
Si3

Vás 3Vae/4 Van/2Va/4 s

Vac O
A C C12 C13T
2

Vdc/4
C
C
Va/2 Vas/2
(a) (b)
Si(k+1) Si1
Si(n-1)
*********** **************

2s k+ A
Vde
*

444gsaraa*34944.
* s***************

S1(2n-2-) Si(2n-1-*) S(2n-2)

(c)
multi-level inverter configurations: ()
Fig. 1.3: Basic building blocks (one leg) of flying capacitor (capacitor-clamped) n-level
three-level scheme, (b) five-level scheme, and (c) general scheme

1-5
3EET256: Multt-Level Inverters 1or ign-row

1.7(a)*
on state of the switches for pole-A (Fig.
Table
1.2: Generation of three different voltage levels based Effect on flying
Pole voltage Voltage Stateof the switch**
VAO level S S13 S capacitor voltage (C1)
Va2 Noeffect
Charging
Discharging
V2 Noeffect
Sn and S14, as well as Si2 and Ss are two different complementary pairs of the switches]
**
["1" indicates ON state and "0" indicates OFF state of the switch)

strategies employed in flying capacitor based multi-level inverters, should be able to maintain the
capacitor voltages in addition to the required control action. A fault-tolerant design of four-level flying
capacitor inverter with the capacitor voltage balancing is described, which
provides the same number of
levels even in the condition of
single-switch fault per phase. An extended operation of a flying capacitor
multi-level inverter by altering the ratio of the
capacitor voltages is reported, however, redundant
switching states, vital to capacitor voltage balancing, are sacrificed to achieve a
higher number of output
voltage levels.
The flying capacitor multi-level inverters do not need the clamping diodes but need a
number of bulky capacitors as
large
floating sources to clamp the voltage. If capacitors with equal voltage
rating (Vd/(n-1)) as the main switches are used, an n-level inverter will need
(n-1) x (n-2/2) capacitors
per pole as floating sources in addition to (n-1) main dc-bus capacitors. In inverters. where
the number
of levels is high, the control also becomes complicated, as the
voltages across a large number of
capacitors have to be maintained by ensuring proper duty ratios in the switches. But
the amount large of
energy/voltage storage in the capacitors provides better ride-through capabilities to this class of
inverters against the input supply interruptions.
1.1.3 Cascaded H-bridge multi-level inverters
Multi-level inverter structures can be realised
by cascading (connecting in series) several
phase H-bridge structures with separate dc sources, and this single
technique has been adapted for high power
IM drive
applications. Fig. 1.8 shows a cascade multi-level inverter configuration which consists
cascade cells for each of two
phase and results into a five-level inverter structure. Each cascaded cell
of the full bridge inverter fed from an
consists
isolated rectifier.
The output from each cell is like a
three-level single-phase inverter and can attain
values Vd/2, 0 or any of the three
-Vd/2, depending upon the states of the switches (two switches
in each leg form a
complementary pair, e.g., S and S14, Fig. 1.8). For
example, in a cell, when switch Siu and Si2 are
switched ON, the output
voltage is equal to -VaJ2, when Si3 and Si4 are turned ON, the
is equal to Va/2, and when output voltage
S and S13 or Sja and Si2 are turned ON, the out
Thus depending on the states of
voltage of the cell is 0.
switches in the phase-A inverter cells, the
pole voltage of phase-A can
be either Vde, Vdo2, 0, -Vas2, or -Vdo. thus
forms a five-level inverter structure. n
general, the number
 Paga No:
Oata:

CaMea Vdc ue om
S w t e hes S12 t o S14

/4, posstble
Pararp- Cmbin
C2Veos 3Vac
Vue : Vde-VLe
2
V a 3Vie Si2, Sa3S1 S1s qre o

2 4
S4 S2 S1& S17 ON.

V Vi VieVde=3V4 4
2
SaiSa2, S44 S46 oNN

3)Vea= Vie/2_Si cmbinutians

VaVie- Us S14S42S& S oN
2

VeaVde/2 S43, S14,Si7, S1te ON

Vao Vae3e+ Ve- Vde<
S11, S13, Ss &S17 ON
VLs= Vac-e+Va S11 S44 S16 S4z 4N
-Nue= 3Vs-Ves + Saa Sat S1c1E aM
 Vaas 3 VA- V Sa254sSasSa an
29 J

C4Vaes Vde4 fan cera binutionas

VeLes Vie-3 Va S S47, Sse S4s V
VaeVte Sa Sa, S47S26idN
Yae Vd - VA Sa3, S4,S17,Sa N

Va 3 Va S42 S4s S46S15 oNV

SSSaSaSuSas|S4
V
Sar
Ves-
B. Vsc 1
3Vc 1
Vde/2 1 1 11
Vle/4 1|02|