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    Lab 3 Introduction To Verilog

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    pioneer boys
    This document appears to be a lab assignment document for an electrical engineering course on computer architecture and logic design. It provides instructions for a lab involving Verilog HDL, including familiarizing students with logic gates, modeling gates in Verilog, and implementing logic circuits using Verilog and on a breadboard. The lab consists of 4 tasks - modeling basic gates in Verilog, modeling 2 given logic circuits in Verilog and on a breadboard, determining the function of a full adder circuit, and answering pre-lab questions. Students are graded on various program learning outcomes for the lab report, demonstration, and viva.

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    Lab 3 Introduction To Verilog

    Uploaded by

    pioneer boys
    72 views6 pages
    This document appears to be a lab assignment document for an electrical engineering course on computer architecture and logic design. It provides instructions for a lab involving Verilog HDL, including familiarizing students with logic gates, modeling gates in Verilog, and implementing logic circuits using Verilog and on a breadboard. The lab consists of 4 tasks - modeling basic gates in Verilog, modeling 2 given logic circuits in Verilog and on a breadboard, determining the function of a full adder circuit, and answering pre-lab questions. Students are graded on various program learning outcomes for the lab report, demonstration, and viva.

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    Original Title

    Lab 3 Introduction to Verilog (1)

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    This document appears to be a lab assignment document for an electrical engineering course on computer architecture and logic design. It provides instructions for a lab involving Verilog HDL, including familiarizing students with logic gates, modeling gates in Verilog, and implementing logic circuits using Verilog and on a breadboard. The lab consists of 4 tasks - modeling basic gates in Verilog, modeling 2 given logic circuits in Verilog and on a breadboard, determining the function of a full adder circuit, and answering pre-lab questions. Students are graded on various program learning outcomes for the lab report, demonstration, and viva.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    72 views6 pages

    Lab 3 Introduction To Verilog

    Uploaded by

    pioneer boys
    This document appears to be a lab assignment document for an electrical engineering course on computer architecture and logic design. It provides instructions for a lab involving Verilog HDL, including familiarizing students with logic gates, modeling gates in Verilog, and implementing logic circuits using Verilog and on a breadboard. The lab consists of 4 tasks - modeling basic gates in Verilog, modeling 2 given logic circuits in Verilog and on a breadboard, determining the function of a full adder circuit, and answering pre-lab questions. Students are graded on various program learning outcomes for the lab report, demonstration, and viva.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 6

    Department of Electrical Engineering

    Faculty Member: ____________________ Dated: ________________

    Semester: __________________________ Section: ________________


    Group No.:

    EE122 Computer Architecture and Logic Design

    Lab 3: Introduction to Verilog HDL, Basic language constructs and Design Entry
    using Verilog HDL
    PLO4/CLO4 PLO4/ PLO5/ PLO8/ PLO9/
    CLO4 CLO5 CLO6 CLO7
    Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
    Performanc of data in Tool Safety and Team marks
    e Lab Usage Work Obtaine
    Report d

    5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25


    Marks

    EE122 Computer Architecture and Logic Design


    Introduction to Verilog HDL, Basic language constructs and design entry
    using Verilog HDL

    This Lab Activity has been designed to familiarize the beginning students with logic gates and IC
    chips, using breadboard and testing of gates and logic circuits. You will be introduced to Verilog and
    Gate-Level Modeling. I last part is the hardware implementation of a Boolean function given to you.
    Objectives:

    Familiarize the students with ICs, their categories, and different logic families.
    Identify ICs on the basis of series number as well as their functional behavior and pin
    numbers.
    Search data sheets of ICs from different sources and optimally use them in the design
    of digital circuits.
    Understand HDL and compare it with normal programming languages.
    Simulate Basic Gates using Verilog with ModelSim
    Write stimulus using Verilog
    Derive algebraic expression for a Boolean function from the given schematics.
    Hardware Implementation of Logic Circuit

    Lab Instructions:

    ✔ This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-lab viva session.
    ✔ The lab report will be uploaded on LMS before scheduled lab date. Complete the Pre-lab task
    before coming to the lab and show it to teacher/lab engineer for subsequent evaluation.
    Alternately each group to upload completed lab report on LMS for grading.
    ✔ The students failing to complete Pre-lab will not be allowed to attend lab session.
    ✔ The students will start lab task and demonstrate design steps separately for step-wise
    evaluation.
    ✔ Remember that a neat logic diagram with pins numbered and nicely patched circuit will
    simplify trouble-shooting/fault diagnostic process.
    ✔ After completion of lab, the students are expected to unwire the circuit and deposit back
    components to lab staff.
    ✔ The students will complete lab task within the prescribed time and submit complete report on
    LMS.
    ✔ There will be a viva/quiz session after demonstration for which students will be graded
    individually.

    EE122 Computer Architecture and Logic Design


    Introduction to Verilog, Gate-level/Behavioral Modeling and Hardware
    Implementation of Basic Logic Circuit
    Read the manual Getting Started with Verilog and answer the following questions:

    a) HDL stands for

    b) Two standard versions of HDL are

    c) Give the different levels of abstraction in Verilog HDL

    Lab Tasks:

    Lab Task 1:
    Model and simulate the basic gates i.e. NOT, AND & OR in Verilog (Gate level) using Modelsim. Provide the
    codes and the simulation waveforms.

    1.1. NOT Gate:

    1.2. AND Gate:

    1.3. OR Gate:

    Lab Task 2:
    Write the Verilog Code using Gate Level modeling for the following circuit. Provide the code for the design
    as well as the stimulus. You also have to provide screenshots of the waveform. Additionally, you need to fill
    in the truth table of the circuit, implement the circuit on hardware and provide the pictures of your work.

    EE122 Computer Architecture and Logic Design


    Truth Table:

    X Y Z F1

    Lab Task 3:
    Write the Verilog Code using Gate Level modeling for the following circuit. Provide the code for the design
    as well as the stimulus. You also have to provide screenshots of the waveform. Additionally, you need to fill
    in the truth table of the circuit, implement the circuit on hardware and provide the pictures of your work.

    EE122 Computer Architecture and Logic Design


    Truth Table:

    X Y Z F2

    Lab Task 4:
    Write the Verilog Code using Gate Level modeling for the following circuit. Provide the code for the design
    as well as the stimulus. You also have to provide screenshots of the waveform. Additionally, fill the truth
    table, perform the circuit on hardware and provide pictures of your work. Determine the function of the
    circuit.

    EE122 Computer Architecture and Logic Design


    Truth Table:

    X Y Carry Sum

    EE122 Computer Architecture and Logic Design

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