Computer Organization and Design: Lecture: 3 Tutorial: 1 Practical: 0 Credit: 4

CSE211
Computer Organization and

Design
Lecture : 3 Tutorial: 1 Practical: 0 Credit: 4
1
2
Overview
➢ Register Transfer Language
➢ Register Transfer
➢ Bus and Memory Transfers
➢ Logic Micro-operations
➢ Shift Micro-operations
➢ Arithmetic Logic Shift Unit
CSE 211
How much storage capacity does each stage in a shift register
represent?
 
a) One bit 
b) Two bits 
c) Four bits 
d) Eight bits
The bus used to connect the monitor to the CPU is
______
 
a) PCI bus 
b) SCSI bus 
c) Memory bus 
d) Rambus
Tri-state Buffer Switch Equivalent
When activated into its third state it disables or turns “OFF” its output producing
an open circuit condition that is neither at a logic “HIGH” or “LOW”, but instead
gives an output state of very high impedance, High-Z, or more commonly Hi-Z.
Then this type of device has two logic state inputs, “0” or a “1” but can produce
three different output states, “0”, “1” or ” Hi-Z ” which is why it is called a “Tri” or
“3-state” device.
Note that this third state is NOT equal to a logic level “0” or “1”, but is an high
impedance state in which the buffers output is electrically disconnected from
the rest of the circuit. As a result, no current is drawn from the supply.
7
Connecting Registers - Bus Transfer
CSE 211
8
Connecting Registers - Bus Transfer
CSE 211
9
Memory Transfer
Memory is usually accessed in computer systems by putting the desired
address in a special register, the Memory Address Register (MAR, or AR)
M
Memory Read
AR
unit Write
Data out Data in
CSE 211
10
Memory Read
➢ To read a value from a location in memory and load it into a

register, the register transfer language notation looks like this:
R1 ← M[MAR]
➢ This causes the following to occur

1. The contents of the MAR get sent to the memory address
lines
2. A Read (= 1) gets sent to the memory unit
3. The contents of the specified address are put on the
memory’s output data lines
4. These get sent over the bus to be loaded into register R1
CSE 211
11
Memory Write
➢ To write a value from a register to a location in memory looks like

this in register transfer language:
M[MAR] ← R1
➢ This causes the following to occur

1. The contents of the MAR get sent to the memory address
lines
2. A Write (= 1) gets sent to the memory unit
3. The values in register R1 get sent over the bus to the data
input lines of the memory
4. The values get loaded into the specified address in the
memory
CSE 211
12
SUMMARY OF R. TRANSFER MICROOPERATIONS
A← B 1.Transfer content of reg. B into reg. A
A ← constant 3.Transfer a binary constant into reg. A

ABUS ← R1, R2 ← ABUS 4.Transfer content of R1 into bus A and, at the same time,
transfer content of bus A into R2
AR 5.Address register
DR 6.Data register
M[R] 7.Memory word specified by reg. R
M 8.Equivalent to M[AR]
DR ← M 9.Memory read operation: transfers content of
memory word specified by AR into DR
M ← DR 10.Memory write operation: transfers content of
DR into memory word specified by AR
CSE 211
13
MICROOPERATIONS
Computer system microoperations are of four types:
➢ Register transfer microoperations

➢ Arithmetic microoperations
➢ Logic microoperations
➢ Shift microoperations
CSE 211
14
Arithmetic MICROOPERATIONS
• The basic arithmetic microoperations are

– Addition
– Subtraction
– Increment
– Decrement
• The additional arithmetic microoperations are

– Add with carry
– Subtract with borrow
– Transfer/Load
– etc. …
Summary of Typical Arithmetic Micro-Operations
R3 ← R1 + R2 Contents of R1 plus R2 transferred to R3

R3 ← R1 - R2 Contents of R1 minus R2 transferred to R3
R2 ← R2’ Complement the contents of R2
R2 ← R2’+ 1 2's complement the contents of R2 (negate)
R3 ← R1 + R2’+ 1 subtraction
R1 ← R1 + 1 Increment
R1 ← R1 - 1 Decrement
CSE 211
Full Adder is the adder which
adds three inputs and produces two
outputs. The first two inputs are A
and B and the third input is an input
carry as C-IN. The output carry is
designated as C-OUT and the
normal output is designated as S
which is SUM.
16
Binary Adder
CSE 211
17
Binary Adder-Subtractor
Binary Adder-Subtractor
B3 A3 B2 A2 B1 A1 B0 A0
FA C3 FA C2 FA C1 FA C0
C4 S3 S2 S1 S0
➢ Mode input M controls the operation

➢ M=0 ---- adder
➢ M=1 ---- subtractor
CSE 211
18
Binary Incrementer
Binary Incrementer
A3 A2 A1 A0 1
x y x y x y x y
HA HA HA HA
C S C S C S C S
C4 S3 S2 S1 S0
CSE 211
19
Arithmetic Circuits
Cin
S1
S0
A0 X0 C0
S1 D0
S0 FA
B0 0 Y0 C1
1 4x1
2 MUX
3
A1 X1 C1
S1 D1
S0 FA
B1 Y1 C2
0
1 4x1
2 MUX
3
A2 X2 C2
S1 D2
S0 FA
B2 0 Y2 C3
1 4x1
2 MUX
3
A3 X3 C3
S1 D3
S0 FA
B3 0 Y3 C4
1 4x1
2 MUX Cout
3
0 1
CSE 211

Computer Organization and Design: Lecture: 3 Tutorial: 1 Practical: 0 Credit: 4

Uploaded by

Copyright:

Available Formats

Computer Organization and Design: Lecture: 3 Tutorial: 1 Practical: 0 Credit: 4

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Computer Organization and Design: Lecture: 3 Tutorial: 1 Practical: 0 Credit: 4

Uploaded by

Copyright:

Available Formats

CSE211

Computer Organization and

Lecture : 3 Tutorial: 1 Practical: 0 Credit: 4

➢ Register Transfer Language

➢ Bus and Memory Transfers

➢ Arithmetic Logic Shift Unit

Connecting Registers - Bus Transfer

Connecting Registers - Bus Transfer

Data out Data in

➢ To read a value from a location in memory and load it into a

➢ This causes the following to occur

➢ To write a value from a register to a location in memory looks like

➢ This causes the following to occur

SUMMARY OF R. TRANSFER MICROOPERATIONS

A← B 1.Transfer content of reg. B into reg. A

A ← constant 3.Transfer a binary constant into reg. A

Computer system microoperations are of four types:

➢ Register transfer microoperations

• The basic arithmetic microoperations are

• The additional arithmetic microoperations are

R3 ← R1 + R2 Contents of R1 plus R2 transferred to R3

➢ Mode input M controls the operation

You might also like