Chapter5: Synchronous Sequential Logic

Lecture7- Design of Clocked Sequential Circuits

Engr. Arshad Nazir, Asst Prof
Dept of Electrical Engineering
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 Objectives
• Design of Clocked Sequential Circuits
• Conversion of Flip-Flops

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 Design Procedure
• Design starts from verbal specifications of design and results in a
logic diagram or a list of Boolean functions.
• The steps to be followed are:
➢ Derive a state diagram
➢ Reduce the number of states
➢ Assign binary values to the reduced states
➢ Obtain the binary coded state table
➢ Choose the type of flip flops to be used
➢ Derive the simplified flip flop input equations and output
equations
➢ Draw the logic diagram

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Design Steps

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 Design Example: A Sequence
Detector
• Design a sequence detector (Moore FSM) that detects three or more
consecutive 1’s from the serial binary data.
➢ From the verbal specifications of design, we derive state diagram
as shown below.

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 Synthesis Using D Flip Flops
➢ The next step is to create a state table and reduce states. No state
reduction is possible in our design example.
➢ Make binary assignment to the four states i.e 00, 01, 10, and 11 and
list Transition Table (Binary Coded State Table).
➢ Choose the type of flip-flops i.e two D flip flops to represent four
states, and label their outputs as A and B.
➢ There is one input, x, and one output, y, representing the input
sequence and the output value respectively.
➢ Remember that the characteristic equation of the D flip flop is
o Q(t + 1) = DQ
o This means that the next-state values in the state table specify
the D input condition for the flip flop.

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State Table for Sequence Detector

• Input equations can be obtained directly from the table using

minterms:
– A(t + 1) = DA(A, B, x) = ∑(3, 5, 7)
– B(t + 1) = DB(A, B, x) = ∑(1, 5, 7)
– y(A, B, x) = ∑(6, 7)
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 Boolean Minimization
• K-Maps can be used to minimize the input equations, resulting in
– DA = Ax + Bx; DB = Ax + B′x; Y = AB

• From Flip Flop Input Equations and Output Equation we can draw the
logic diagram of the circuit as shown in the next slide.
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Logic Diagram

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 Timing Diagram Moore
Example: Sequence detector to detect three or more consecutive 1’s

Clk

0 1 1 1 1 0
Input X

A 0 0 1 1 1 0
xxxx

B 0 1 0 1 1 0
xxxx

Output Y 0 0 0 1 1 0
xxxx

Y=ABSpring 2023 10
 Excitation Table
• The design of sequential circuits other than D type flip flops is
complicated by the fact that input equations must be derived
indirectly from the state table.
➢ It is necessary to derive a functional relationship between the
state table and the input equations.
• During the design, we usually know the transition from present to
next state but we need to find the flip flop input conditions that will
cause the required transition.
➢ We need a table that lists the required inputs for a given change
of state, called an excitation table.

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Excitation Tables for JK and T Flip-
Flops

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 Synthesis Using JK Flip Flops
• Synthesis of circuits with JK flip flops is the same as with D flip flops
except that the input equations must be evaluated from the present-
state to the next-state transition derived from the excitation table.
• Consider a sequential circuit described by the state table shown in
the next slide.
• Note that one extra section i.e Flip Flop Inputs has been added and
we are required to derive algebraic expressions for Flip Flop Inputs as
a function of present state and external inputs.

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Example JK Synthesis

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 JK Synthesis Logic Cont…
• By using K-maps we can minimize the flip flop input equations as under:-
JA = Bx′; KA = Bx JB = x; KB=(Ax)′

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JK Synthesis Logic Cont…

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 Synthesis using T flip-flops
Example: Three-bit binary counter Design. The state diagram is as shown

State Table
Present Next Flip-Flop
State State Inputs
A2 A1 A0 A2 A 1 A0 TA2 TA1 TA0

0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
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 Synthesis using T flip-flops Cont…
• By using K-maps we can minimize the flip flop input equations as under:-
TA2 = A1 A0 ; TA1 = A0 ; TA0 =1

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Synthesis using T flip-flops Cont…

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 Design Example: A Sequence
Detector
• Design a sequence detector (Mealy FSM) that detects three or more
consecutive 1’s from the serial binary data.
➢ From the verbal specifications of design, we derive state diagram
as shown below.

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Problem: Design a Sequence detector to detect an overlapping
sequence 1010

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Design a FSM that has one input w and one output z. The machine is a
sequence detector that produces z=1 when the previous two values of
w were 00 or 11; otherwise z=0.

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 Conversion of Flip-Flops
• We can covert one flip flop to another by the following procedure.
➢ List characteristic table of flip flop to be constructed.
➢ From this derive excitation table of the given flip flop.
➢ Derive flip flop input equations of given flip flop as a function of
present state and inputs of flip flop to be designed.
➢ From this we can draw the logic diagram of new flip-flop and perform
hardware implementation.

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Example-Conversion From D to T Flip-Flop
T Q(t) Q(t+1) D

0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0

D= TQ(t)
Q(t)

Conversion from D to T Flip Flop

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The End

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