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Electric Vehicle Charging Station With an Energy Storage Stage for Split-DC
Bus Voltage Balancing

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DOI: 10.1109/TPEL.2016.2568039

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2376 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017

Electric Vehicle Charging Station With an Energy

Storage Stage for Split-DC Bus Voltage Balancing
Sebastian Rivera, Member, IEEE, and Bin Wu, Fellow, IEEE

Abstract—This paper proposes a novel balancing approach for grid, as still the automotive industry is mainly sourced by the
an electric vehicle bipolar dc charging station at the megawatt gasoline supply chain, but this will gradually shift to a larger
level, enabled by a grid-tied neutral-point-clamped converter. The electricity consumption with transportation purposes, and if it is
study uses the presence of an energy storage stage with access to
both of the dc buses to perform the complementary balance. It not addressed properly, the actual electric system will be unable
proposes a generic balancing structure that can achieve balance to satisfy this demand [2], [7].
regardless the kind of energy storage system (ESS) employed. This In order to address the impacts of a large-scale adoption of
is aiming to reduce the hardware requirements of the system and these vehicles in the utility systems, several studies have been
maximize the usage of the ESS, whose main function is to per- carried out [8]–[12], mostly based on the conventional slow
form the energy management related tasks. To meet this purpose,
a three-level dc–dc interface is employed, allowing to compensate charging process of the batteries. This is mainly because con-
the dc currents with a single ESS. Furthermore, in order to pre- ventional charging is expected to remain as the preferred charg-
vent the appearance of even-order harmonics in the input current ing method [7], and also the fast charging process of the EV
during asymmetrical operation, an alternative switching sequence batteries is still not a widespread practice among the owners,
for the central converter is proposed. Results indicate that, without
due to the lack of facilities and misconceptions regarding the im-
altering dramatically the charging process of the ESS, it is possible
to cover the whole load scenario without the need of a balancing pact of this process to the battery pack. However, fast charging
circuit. This allows the use of off-the-shelf products both for the methods are still essential for a large-scale adoption of EVs, as
rectifier and the fast chargers. In this paper, simulation and exper- it will provide more flexibility to the drivers, occasional longer
imental results are presented to validate the proposed balancing trips addressing range anxiety [13]–[16]. Additionally, in or-
strategy. der to reduce power consumption from the utility grid during
Index Terms—Bipolar dc bus, electric vehicles (EVs), energy peak consumption hours, the presence of energy storage systems
storage stage, fast charger, power balance management, three-level (ESSs) in these stations is gaining attention [5].
dc–dc converter. An alternative to enable fast charging is in the form of fast
I. INTRODUCTION charging stations, which refers to the concept of having high-
power fast chargers installed off-board, similar to gas stations
LUG-IN electric vehicles (EVs), considering under this
P category to both plug-in hybrid electric and battery EVs,
have emerged as the most probable successor for conventional
located in public places. The structure of these charging stations
can either be with an ac bus, where each charging unit is fed by
its independent ac–dc stage, or each unit connected to a common
internal combustion engine vehicles. During these last years the dc bus enabled by a single ac–dc stage with higher power ratings
sales of these vehicles have been constantly increasing and it [5], [17]. Currently, fast charging is only enabled by standalone
is expected to remain in this trend for the upcoming years [1], units, each one with its independent rectifier stage [18]–[20]
[2]. Despite of the increasing EV fleet, these vehicles still have using the ac-bus concept.
to solve some shortcomings before becoming a real alternative However, considering the dc nature of the loads, the com-
to transportation. The long recharging process of the batter- mon dc-bus configuration appears as the viable solution, and
ies, limited mileage capacity (typically below 200 km) and the also presents advantages in terms of cost, efficiency, and size,
lack of public fast charging infrastructure are the main barriers as fewer power conversion stages are needed [5], [21], [22].
to its widespread usage [3]–[5]. However, to allow a large- Moreover, this structure facilitates the integration of distributed
scale penetration of this technology changes are required also generators or ESSs.
from the grid point of view, as the electricity demand will grow The central converter stage plays a fundamental role in this
accordingly [6]. Nowadays, there is no real threat to the utility charging architecture, and is desirable to provide several fea-
tures as low distortion operation, high power capability, fully
Manuscript received August 24, 2015; revised January 4, 2016 and April adjustable power factor, reduce the size of the input filters,
1, 2016; accepted May 3, 2016. Date of publication May 12, 2016; date of
current version December 9, 2016. This work was supported by Toronto Hydro
while featuring a reduced number in both active and passive
(THESL) through project TH1302 at the Centre for Urban Energy, Ryerson components. Among the alternatives, conventional two-level
University. Recommended for publication by associate editor R. Zane. voltage source converter might arise, however, it has a limited
S. Rivera is with the Department of Electrical & Computer Engineering,
University of Toronto, Toronto, ON M5S, Canada (e-mail: [email protected]).
capacity to fulfill power ratings, power quality and efficiency re-
B. Wu is with the Department of Electrical and Computer Engineering, Ryer- quirements due to semiconductors voltage/currents limits [23].
son University, Toronto, ON M5B 2K3, Canada (e-mail: [email protected]). Other works propose the use of a 12-pulse diode bridge rectifier,
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
improving its harmonic performance through the use of an active
Digital Object Identifier 10.1109/TPEL.2016.2568039 filter stage [5]. However, the lack of power factor control and

0885-8993 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
RIVERA AND WU: ELECTRIC VEHICLE CHARGING STATION WITH AN ENERGY STORAGE STAGE FOR SPLIT-DC BUS VOLTAGE BALANCING 2377

Fig. 2. Circuit diagram for the three-level dc–dc stage for the ESS.

TABLE I
Fig. 1. Proposed charging station architecture with balancing ESS. THREE-LEVEL DC–DC SWITCHING STATES

States Switching Output Neutral

its unidirectional power flow capability reduces the potential of Voltage Current
the charging station.
A different dc-bus concept is proposed and validated in [17]. v0 [OO] 0 iz k = 0
v1 P [PO] Vd 1 iz k < 0
The structure is based in the use of a central neutral-point- v1 N [ON] Vd 2 iz k > 0
clamped (NPC) converter enabling a bipolar dc bus. The use v2 [PN] 2V d iz k = 0
of this split dc bus provides flexibility to the connection of the
loads, has higher voltage and power handling capabilities and re-
duced step-down effort of the dc–dc stages. However, given the
and full balancing tasks. The overall performance of the system
adoption of the bipolar structure and the intended application,
will be validated both in simulation and experimentally.
the balance control becomes essential. In [17], this was done
by adding an additional circuit to the system, which enhances
the balancing capabilities of the grid-tied converter. The result II. THREE-LEVEL DC–DC STAGE FOR ESS
led to balanced dc voltages even under severe unbalanced load As stated earlier, in order to perform the balancing com-
conditions. Taking a different approach, this paper proposes a plement to the grid-tied converter, the ESS must have access to
novel balancing method that uses the presence of the existing both dc buses. Considering this requirement, a three-level dc–dc
ESS, regardless of its type, to perform the complementary bal- converter will be used as the dc–dc stage. This choice is further
ancing actions. The idea is to relocate the power consumption justified by the reduced voltage stress on the switching devices,
of the ESS in order to keep the central converter operating in its allowing the use of conventional low-voltage-rated switches,
balanced zone. This is achieved by the use of a three-level dc–dc improved output current waveform, and improved efficiency
interface. As it will be demonstrated, the only requirement of in comparison to conventional two-level-based topologies [25].
the approach is to meet the minimal balancing power. However, Finally, for this particular application, it will only require the
it is important to mention that the presence of this stage is for inclusion of a single energy storage stage, enabling the com-
managing the energy consumption of the charging station, and pensation of the currents in both of the dc buses, as it will be
its operation will be used toward the prevention of drifts in the demonstrated in the following sections.
dc voltages. It will be shown that the presence of this stationary The power circuit of the selected topology is presented in
load in the system can be used to complement the balancing Fig. 2, where it can be seen that it has three input terminals that
capabilities of the central converter. This will lead to the elim- can be directly connected to the bipolar charging station. The
ination of the additional NPC leg, thus reducing the cost of the converter is composed of four switching devices along with their
system. Moreover, the presence of this stage will allow the use corresponding freewheeling diodes, the input filter capacitors
of off-the-shelf products for both, the central converter, and the Cd1 and Cd2 , and an output inductor Lo and capacitor Co for
fast charging units. This use of standardized components leads filtering purposes.
to lower hardware costs, improved system robustness in addition Considering its structure, the basic requirement that Vd1 =
to cost-effective implementation and maintenances [24]. Vd2 = Vd , and the valid combinations of its switching signals,
In the following sections, the inclusion of an energy storage the converter generates four voltage states, which are resumed
stage in the system will be discussed. This additional stage in Table I. Each state results in a different equivalent circuit, as
will perform the tasks of energy buffer and also perform the presented in Fig. 3. These states are depicted as follows: when
complementary balancing of the dc voltages. In order to do so, a the switches Sk 1 and Sk 4 are turned ON, the output voltage vo
dc–dc stage with access to both of the dc buses must be included, is equal to the total input voltage 2Vd ; then when Sk 1 and Sk 3
to avoid having two batteries in the system, as shown in Fig. 1. To are ON, vo becomes Vd ; the same output voltage is generated
meet this purpose, a three-level dc–dc stage will be featured. A when the switches that are ON are Sk 2 and Sk 4 ; finally, when the
control scheme is developed and proposed, covering the partial inner switches Sk 2 and Sk 3 are turned ON, the output voltage is
2378 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017

Fig. 3. Four switching states and their equivalent circuits. (a) v 0 . (b) v 1 P .
(c) v 1 N . (d) v 2 .

equal to zero. Please note that the switching states v1P and v1N
generate opposite neutral-point currents, revealing the balancing
capabilities of the converter. For the remainder of the paper,
these states will be denominated mid states.

A. Operation Principle
From the circuit diagram in Fig. 2, the operation of the outer
switches Sk 1 and Sk 4 must be complementary to the inner
switches Sk 2 and Sk 3 , respectively, in order to avoid short cir-
cuiting the input voltage sources. This means that the operation
of the converter is regulated through two independent gating
signals g1 and g4 . The generation of these signals is usually
done by the use of pulse width modulation modulators with
phase-shifted carriers [25], [26]. However, taking into account
the generated switching sequence, it can also be synthesized by
a single-phase space vector modulation (SVM) approach. The
sequence will vary whether d ≤ 0.5 and d > 0.5. This will be
covered in detail in the following sections.
1) Small Duty Cycle: To start the analysis, the average value
of the output voltage is given by
 Ts
1
Vo = vo (τ )dτ (1)
Ts 0
this is the voltage that is being applied to the terminals of the
Fig. 4. Five segment switching sequence for SVM. (a) Small duty cycle
ESS. Then, by assuming that this voltage results in d ≤ 0.5, the d ≤ 0.5. (b) Large duty cycle d > 0.5.
required reference that synthesizes it is defined as:
1 The previous result reflects that during normal balanced op-
Vo = (tp v1P + tn v1N + to v0 ) (2)
Ts eration, the duty cycles for the outer switches are equal to d, as
where tp , tn , and to represent the dwell times of each state. the voltages Vd1 and Vd2 are balanced. Then, in the presence of
Whereas, the duty cycle d is defined as usual, by the ratio different dc voltages, the duty cycles dp and dn will be redis-
between the output and input voltages, according to tributed accordingly, in order to retrieve the balance condition.
This results in the five segment sequence for the SVM principle
Vo shown in Fig. 4(a).
d= . (3)
2Vd 2) Large duty cycle: Now, if the output voltage is larger
Now, considering the output voltages of Table I and replacing than Vd , the sequence varies as follows. In this case, the output
(2) into (3) leads to the following expression: voltage is synthesized by
dp Vd1 + dn Vd2 1
d= (4) Vo = (tp v1P + tn v1N + to v2 ) (6)
2Vd Ts
tk
dk = , where k = (p, o, n). (5) furthermore, regardless the relationship between Vd1 and Vd2 ,
Ts
the duty cycle for v2 is equal to
Please note that the duty cycles dp , do , and dn have been
introduced. do = 2d − 1. (7)
RIVERA AND WU: ELECTRIC VEHICLE CHARGING STATION WITH AN ENERGY STORAGE STAGE FOR SPLIT-DC BUS VOLTAGE BALANCING 2379

states. This will allow to select which bus is providing power

to the ESS. Given that the redistribution is done in such a way
that the positive bar current ipk must be equal to Id2 . From
Fig. 4(a), it can be deducted that this current is related with the
output current io according to
ipk = dp io . (10)
Additionally, assume that in order to meet the minimal load
condition, the output current is such as it requires to exclusively
use the positive redundancy of v1 . This leads to dp = 2d, and
bearing in mind the previous analysis, the minimal value for io
Fig. 5. Critical load ratio for the NPC using SVM. that allows to meet the balancing condition is defined as
Id2
io = . (11)
2d
Finally, replacing (7) into (6) and clearing the total duty cycle
This is an interesting result, as it demonstrates that in order to
leads to
guarantee a balanced operation of a system rated at Pb , it will
dp Vd1 + dn Vd2 only require an ESS with a power equivalent to Pb /(2 + ).
d=1− . (8)
2Vd Moreover, it is worth mentioning that despite the redistribution
The previous operation mode is illustrated in Fig. 4(b). An that the modulator is performing, for this duty cycle range the
important remark from the operating conditions displayed in power delivered to the ESS remains unaltered.
Fig. 4, is the confirmation that the redundancies of the state In the case the imbalance is located in the lower dc bus, the
v1 generates opposite currents circulating through the neutral procedure is analogous, as the ESS requires to drain at least a
point iz k . When the positive redundancy is employed, a negative current defined by
average current flows through the neutral point, while a positive Id1
average value for iz k is imposed when v1N is used. This concept io = (12)
2d
will be used to develop the balancing scheme employed in this while employing exclusively the mid-state v1N .
paper.
B. Large Duty Cycle
III. VOLTAGE BALANCING TECHNIQUE
Despite the balancing principle is the same for different
As established in [17], in order to achieve dc voltages bal- modulation index ranges, the generated compensation current
ance, the asymmetrical operation of the bipolar dc bus requires changes, as it will be demonstrated. Using the example provided
a minimal power ratio between the dc buses, which is deter- by Fig. 4(b), and again assuming the imbalance location is the
mined by the grid-side modulation stage. The motivation of this upper bus, the required value for ipk to achieve the dc voltage
paper is to use the ESS to perform the balancing tasks when the balance is still set by (9), hence must be equal to Id2 . The rela-
system is driven out of its balanced zone, which is displayed tionship between this current and io remains modeled by (10),
in Fig. 5. However, the fundamental difference with the afore- and since the positive redundancy is being exclusively used, the
mentioned approach is that the minimal load condition is no required output current is now defined as
longer emulated, as the ESS remains connected to the system
permanently. Instead, this approach allows to redistribute the Id2
io = . (13)
ESS power consumption in order to satisfy this minimal power 2(1 − d)
ratio , by concentrating it to the bus with lighter load. The It is demonstrated then, that for large duty cycles, the mini-
complete analysis is given in the following sections. mal ESS that is able to keep the system balanced under any load
scenario is given by dPb /(2 − 2d). In other words, in this duty
A. Small Duty Cycle cycle range, the ESS required to maintain the system balanced
For the first case, it is necessary to revisit the example pre- has higher power ratings. In case of having the imbalance lo-
sented in Fig. 4(a), and assume there is no load connected to the cated in the lower bus, the formulas must change accordingly,
upper bus, while the lower one is operating under rated condi- assuming that only v1N is being used.
tion. The work in [17] demonstrated that in order to keep the
dc voltages from drifting, the following condition must be met IV. PROPOSED CONTROL SCHEME
under any scenario Given that the ESS remains as a stationary load to the sys-
tem, it can drain power from any of the buses arbitrarily. This
min{Pd1 , Pd2 } ≥  max{Pd1 , Pd2 } (9)
means that its usage can be maximized, as its charging pro-
where, Pd1 and Pd2 are the power consumed at the upper and cess can be used to compensate the imbalances in the system.
lower dc bus, respectively. Now, as stated earlier, the imbalance Consequently, there is no need to modify the overall structure
will be compensated by redistributing the usage of the mid of the grid-side controller presented in Fig. 6, which performs
2380 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017

Fig. 6. VOC block diagram for the central NPC converter.

the regulation of the central NPC converter. However, in or-

der to overcome the generation of even-order harmonics during
unbalanced operation, a change is introduced in the switching
sequence employed.

A. Modified Sequence During Unbalanced Operation

Considering the results obtained in [17], the main drawback of
the control scheme was the presence of even-order harmonics in Fig. 7. SVM switching sequences during unbalanced operation. (a) Switching
the line current during asymmetrical load operation, because the sequence for region I-2a. (b) Switching sequence for region IV-2a. (c) Modified
sequence for region IV-2a.
half-wave symmetry was missed. This is not desirable for grid-
connected systems as the grid code sets stringent limits for these
particular components, thus it has to be solved. Therefore, the
SVM switching sequence for the central NPC will be modified In the studied case, the type B sequence is modified by swapping
during these instants in order to retrieve the half-wave symmetry v4P and v4N . It’s important to note that the condition of changing
and guarantee line currents without even-order harmonics. only two switches per segment is missed due the swapping of the
Is important to note that the dwell times for positive and small vectors. This leads to the switching sequence presented in
negative small vectors are redistributed according the dc voltage Fig. 7(c) for the region IV-2a. Fig. 7 shows that the symmetry
deviations, using a PI controller to maintain the balance. To do in the line-to-line voltages has been retrieved, however, this is
so, the controller actuation Δs is fed to the SVM modulator to done at the expenses of increasing the number of switchings per
adjust the dwell times according to sampling period.

ta ta B. ESS Controller
taP = (1 − Δs ), taN = (1 + Δs ). (14)
2 2
Now, for the regulation of the ESS, the following operation
Considering the voltage references of the scenario given by principle is proposed: the ESS controller will not be modified in
1 any way, generating the required duty cycle value d to regulate
vref = (ta v1 + tb v2 + tc v7 ) (15) its voltage following its prescribed charging profile; then, de-
Ts
pending on the location of the imbalance, the dc–dc stage will
1
vref = (ta v4 + tb v5 + tc v10 ) (16) redistribute the usage of the mid states, in such a way that it
Ts will drain the minimal current from the less congested bus. This
and in the presence of an imbalance at the dc side that results in redistribution is entirely related with the usage of the small vec-
Δs = −1/3. This will lead to ta P = 2ta N , and the resulting se- tors of the central stage controller, thus the same actuation Δs
quences are shown in Fig. 7. It becomes clear that the balancing can be used for this purpose. In addition, in order to minimize
mechanism has altered the switching sequence, causing a lack the required ESS power ratings, the ESS voltage is selected to
of half-wave symmetry in the line-to-line voltages. This yields be lower than Vd , leading to d ≤ 0.5.
to the appearance of even-order harmonics on the line currents. The required controller for the ESS is the one presented in
As the dwell-times redistribution is necessary to achieve bal- Fig. 8, and it confirms that the controller for the ESS is the
ance on the dc voltages, a modification on the switching se- conventional cascaded loop that depending on its SOC operates
quence is proposed to maintain the symmetry, and it will only be in constant current or constant voltage modes. This structure
used when the dc loads are different. This modification is simply generates the required d, and the modulator stage performs the
to swap the position of the negative and positive vectors in one redistribution of the states, using the information provided by
of the sequences, in order to retrieve the half-wave symmetry. the mid-point controller. This modification is applied to the duty
RIVERA AND WU: ELECTRIC VEHICLE CHARGING STATION WITH AN ENERGY STORAGE STAGE FOR SPLIT-DC BUS VOLTAGE BALANCING 2381

Fig. 8. Proposed controller for the balancing ESS.

TABLE II
SIMULATION AND EXPERIMENTAL PARAMETERS

Parameter Symbol Value

Grid Voltage Amplitude Vg 1 p.u.

Grid Frequency fg 1 p.u. Fig. 9. Dynamic performance of the dc currents. (a) Neutral-point current iz k
Input Filter Inductance Lg 0.1 p.u. and its average value Iz k . (b) Bus 1 current Id 1 . (c) Bus 2 current Id 2 .
Input Filter Resistance Rg 0.02 p.u.
dc Link Capacitance Cd 4.5 p.u.
dc Link Voltage 2V d 2.2117 p.u.
Output Filter Inductance Lo 0.18 p.u.
Output Filter Capacitance Co 1.8 p.u.
ESS Rated Power P ss 0.1402 p.u.
ESS Capacitance C ss 1.1 × 10 5 p.u.
Amplitude Modulation Index m 0.6433
Frequency Modulation Index mf 36
Critical Load Ratio ˆ 0.2823
Simulation Base Voltage VB 4160/960 V
Simulation Base Power PB 1.38 MW
Experimental Base Voltage VB 208 V
Experimental Base Power PB 3 kW
Base Frequency fB 60 Hz

cycles dp and dn according to

dp = d(1 + Δs ) (17) Fig. 10. Dynamic performance of the VOC signals. (a) DC bus voltages V d 1
and V d 2 . (b) Grid current ig a . (c) Grid voltage v g a .
dn = d(1 − Δs ). (18)

V. SIMULATION RESULTS load impact takes place, the current Id2 goes to zero, and in order
to keep the voltages from drifting, the system forces the power
Considering the proposed compensation technique to keep
demand to be exclusively from the lower bus. This is confirmed
the dc-link voltages balanced, the dynamic performance of the
by the positive average value of iz k . Furthermore, Id1 remains
system is validated under several load impacts, simulating the
unaltered, thus demonstrating the independent operation of the
random arrival of vehicles for recharge. In addition, the pro-
dc buses.
posed switching sequence correction is performed in order to
Later on, the asymmetrical operation is reversed at t =
keep the ac-side currents without even-order harmonics. The
0.13̄ s, by disconnecting the load in bus 1 and reconnecting
simulation parameters are presented in Table II. A 1.38-MW
the rated load to bus 2. It becomes clear how the polarity of the
charging station is simulated using MATLAB/Simulink.
current in the neutral point has changed, as only the positive
redundancy of the mid state is being used.
A. Dynamic Performance Finally, when the system returns to balanced operation at
The study of the dynamic performance in the presence of t = 0.216̄ s, there is no need for compensation actions from
severe load impacts is the first stage of validation. As men- the ESS, so the distribution of the mid states is done equally,
tioned earlier, this is to simulate the volatile loads that the EVs resulting in zero average current flowing through the midpoint.
represent in the system due to their random arrival, different A remarkable fact from the proposed method is the reduced
battery technologies, charging speeds, initial SOCs and so on. current stress in the output dc choke, as the ESS power rating is
Fig. 9 exhibits the dynamic evolution of the dc currents in the merely 14% of the rated power of the station.
system. It is possible to see that before t = 0.05 s, the system The proper regulation performed at the dc side, allows to keep
is operating with symmetrical dc loads, as Id1 = Id2 , hence, the voltages perfectly balanced throughout the entire simulation.
there is no need to generate any current compensation with the This situation is confirmed by Fig. 10(a) which shows how the
balancing ESS. As there is no need for redistributing the usage voltage of the dc capacitors remains tracking their reference.
of the mid states, the average value of iz k is zero, while the ESS It is possible to confirm that the proposed balancing technique
continues its charging process. Then, at the instant when the first allows to overcome the limitations of the conventional NPC.
2382 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017

Fig. 11. Steady-state analysis of the converter voltages. (i) Line-to-line voltage Fig. 12. Steady-state analysis of the input signals. (i) Grid voltage v g a .
v a b . (ii) Phase voltage v a z . (iii) FFT for v a z . (a) Case I, balanced operation. (ii) Grid current ig a . (iii) FFT for ig a . (a) Case I, balanced operation. (b)
(b) Case II, unbalanced operation in bus 2. Case II, unbalanced operation in bus 2.

As the balancing technique allows to keep the dc voltage

balance, the currents at the input side exhibit a sinusoidal wave-
form during any scenario, as shown in the waveform of ig a in
Fig. 10(b). Finally, the unity power factor operation remains
unaltered during the load impacts, as the currents are kept in
phase with the grid voltage vg a plotted in Fig. 10(c).

B. Steady-State Analysis
Continuing with the validation of the proposed balancing
scheme, the steady-state waveforms of the converter voltages
are discussed. Fig. 11 presents these waveforms for the balanced
and unbalanced cases.
The behavior of the system for symmetrical operation can be
seen in Fig. 11(a), where it is possible to see there are no cor-
rections being applied to either of the voltage signals, as there
is no difference between the dc loads. The generated voltages
presents half-wave symmetry, leading to a spectral distribution
that has no even-order harmonics as shown in the fast Fourier
transform (FFT) for vaz . Then, under the presence of an imbal-
Fig. 13. Experimental setup. (a) Photograph. (b) Block diagram.
ance, a dc drift is injected to the phase voltage with balancing
purposes, which results in a positive dc drift due the lack of
load in the lower bus, as presented in Fig. 11(b)ii. The modifica- cycles of the converter phase voltages, which is confirmed by
tion of the switching sequence for the asymmetrical operation the presence of even-order components in Fig. 11(b)iii.
can be also appreciated, as vaz exhibits six extra switchings per Just as in the previous method, the dc bias injected to vaz is
fundamental cycle. not reflected toward the line-to-line voltages, as the three phases
The presence of this dc drift is confirmed by the spectrum of are modified equally. This is confirmed by Fig. 11(a)i and (b)i.
vaz in Fig. 11(b)iii. In addition, the dc voltage injection has led To complete the analysis, the input signals are presented in
to a lack of symmetry between the positive and negative half Fig. 12 for steady-state regimen. The input current ig a exhibits
RIVERA AND WU: ELECTRIC VEHICLE CHARGING STATION WITH AN ENERGY STORAGE STAGE FOR SPLIT-DC BUS VOLTAGE BALANCING 2383

Fig. 14. Dynamic performance, Case I. (a) DC currents. ChM Neutral-point Fig. 15. Dynamic performance, Case II. (a) DC currents. ChM Neutral-point
current average value Iz k (4 A/div). Ch2 Neutral-point current iz k (5 A/div). current average value Iz k (4 A/div). Ch2 Neutral-point current iz k (5 A/div).
Ch3 Bus 1 load current Id 1 (5 A/div). Ch4 Bus 2 load current Id 2 (5 A/div). Ch3 Bus 1 load current Id 1 (5 A/div). Ch4 Bus 2 load current Id 2 (5 A/div).
(b) VOC signals. Ch1 dc bus 1 voltage V d 1 (100 V/div). Ch2 dc bus 2 voltage (b) VOC signals. Ch1 dc bus 1 voltage V d 1 (100 V/div). Ch2 dc bus 2 voltage
V d 2 (100 V/div). Ch3 Grid current ig a (14.8 A/div). Ch4 Grid voltage v g a V d 2 (100 V/div). Ch3 Grid current ig a (14.8 A/div). Ch4 Grid voltage v g a
(200 V/div). Time scale 30 ms/div. (200 V/div). Time scale 30 ms/div.

a sinusoidal nature for both balanced and unbalanced cases, to manage peripherals and protections. In this case, the SVM
with the corresponding increase in its ripple in the unbalanced algorithm is programmed to have an equivalent switching fre-
operation. However, the effectiveness of the modified switching quency of 1080 Hz per device. Using the parameters presented
frequency is confirmed, as the currents have maintained the in Table II, the control scheme is applied to the converter.
half-wave symmetry. This is further confirmed by its harmonic To validate the approach, the same dynamic test of the sim-
content, presented by Fig. 12(b)iii, as it does not contain energy ulations is performed. The ESS employed in the experimental
concentrated in even-order components. platform is a 845.64 Wh ultra capacitor stage Css , with a rated
voltage of 64.8 V. This stage is composed by the series connec-
VI. EXPERIMENTAL VALIDATION tion of four Maxwell ultra capacitor modules (BMOD0058 E016
B02), each one with a capacitance of 58 F and rated for 16.2 V.
The final step to demonstrate the effectiveness and validate The experimental setup diagram is presented in Fig. 13(b).
the proposed balancing approach is through experimental ver-
ification. In order to do so, the NPC prototype exhibited in
Fig. 13(a) is employed. A. Dynamic Performance
The experimental platform is composed by an isolation trans- The obtained results are displayed on Fig. 14. It is possible to
former, an inductive input filter, and the central NPC converter observe a close similarity with the simulation results obtained
in the ac side, while the dc side has the IGBT-based three-level earlier. Fig. 14(a) puts on display the behavior of the dc currents
dc–dc stage feeding an ultra capacitor ESS, and the resistive during the whole test. It’s important to remind that the ESS is
loads for each bus, both of them connected through a solid-state performing its charging tasks during the whole scenario. As the
relay in order to force the asymmetrical operation. The control system starts in balanced operation, there is no current com-
platform used is an eZdsp (TMS320F28335) from Spectrum pensation required from the ESS stage, therefore, it is draining
Digital, which is performing the main calculations and control power equally from both dc buses, as it can be seen by the
actions, along with an Altera Cyclone FPGA (EP1C6T144C8) average neutral-point current Iz k , which is zero. Later on, as
2384 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017

Fig. 16. Dynamic performance of the ESS. Ch1 ESS input current io (5 A/div). Ch2 ESS input voltage v o (200 V/div). Time scale 30 ms/div. (a) Case I.
(b) Case II.

soon as the load from the lower dc bus is disconnected (Id2 is

set to zero), it changes to a positive value in order to keep the
dc voltages from drifting. Consequently, when the imbalance is
reversed (Id1 is now zero), it will change its direction in order
to reach the minimal load condition. Finally, when the system
returns to balanced regiment, the current compensation is no
longer required and Iz k returns to zero.
As a continuation of the analysis, the evolution of the quan-
tities related with the grid-tied regulation are presented in
Fig. 14(b). Once again, it can be seen how the severe asymmetri-
cal operation is overcome by forcing the minimal load condition
at the dc side. The dc bus voltages show an improved dynamic
response, returning quickly to their reference. This leads to a
balanced operation during the whole test allowing to maintain Fig. 17. Dynamic performance of the ESS. Ch1 ESS input current io
a proper regulation of the input current ig a , which exhibits a (5 A/div). Ch2 ESS input voltage v o (200 V/div). (c) Ch3 Ultra Capacitor
highly sinusoidal waveform, and does not distort excessively Voltage V o (10 V/div). Time scale 6 s/div.
maintaining its phase disposition with the grid voltage, hence,
keeping the unity power factor operation.
In order to further validate this balancing approach a different assistance, as the dc voltages remain balanced regardless the
dynamic test is performed. This time, the system will be assumed load condition. It is important to recall that the ESS is charging
without any EV load connected to either bus, while the ESS is during the whole time, explaining why the ac currents are not
performing its charging process. Then, the maximum imbalance zero during the instants when no EVs are demanding power
is forced in the negative bus. This is followed by the system from the station. An important detail in this figure is the graph-
returning to the no EV state, and finally, the maximum imbalance ical confirmation of the reduced requirement on the ESS power
is forced toward the positive bus. This is done in order to have rating to achieve balance. It can be seen that is roughly one-sixth
a more realistic scenario, and at the same time force the worst of the total power.
case operation, which is when one of the buses is fully loaded Please note that despite the ESS interface is able to redis-
and the remaining one has no load connected. Any other power tribute its power consumption and provide the complementary
difference between the power consumptions on the buses is a balancing capability, its main function and raison d’être is still
less challenging balancing scenario. charge or discharge the energy buffer according to the energy
Fig. 15 presents the evolution of the relevant quantities during management strategy. To highlight this issue, Fig. 16 provides
the second test. The dc currents exhibited in Fig. 15(a) allows the evolution of the current injected to the ESS io and the volt-
to confirm the effectiveness of the method, and the converter age generated by the dc–dc stage vo during the aforementioned
redistributes the power consumption of the ESS toward the bus tests. It becomes clear that these outputs remain almost unaltered
that has the lighter load condition. Following this idea, the av- during the whole dynamic test, with the exception of a slight in-
erage value of iz k is positive to compensate imbalances in the crease in the current ripple during the unbalanced instants. The
upper dc bus, meanwhile a negative average value will do the reason for this increased ripple is the exclusive use of one of
same for imbalances located in the lower dc bus. the redundancies of the mid state, as it will lead to a reduction
The quantities related with the grid-connected converter, pre- of the apparent switching frequency (the switching sequence
sented in Fig. 15(b), confirms the validity of the balancing has only three segments in this case). This results demonstrate
RIVERA AND WU: ELECTRIC VEHICLE CHARGING STATION WITH AN ENERGY STORAGE STAGE FOR SPLIT-DC BUS VOLTAGE BALANCING 2385

Fig. 18. Steady-state analysis of the converter voltages. Ch1 phase voltage Fig. 19. Steady-state analysis of the input signals. Ch3 grid current ig a
v a z (200 V/div). Ch2 line-to-line voltage v a b (500 V/div). ChM FFT for v a z (10 A/div). Ch4 grid voltage v g a (200 V/div). ChM FFT for ig a (100 mA/div,
(20 V/div, Span 10 kHz, Center 4.8 kHz). (a) Balanced operation. (b) Unbalanced Span 10 kHz, Center 4.8 kHz). (a) Balanced operation. (b) Unbalanced operation
operation in bus 2. Time scale 3.4 ms/div. in bus 2. Time scale 3.4 ms/div.

half-wave symmetry as expected, leading to an input current

that is possible to integrate the operation of the ESS with the
with no energy concentrated in even-order harmonics.
complementary balancing required by the grid-tied converter.
The effectiveness of the modified switching sequence can be
Finally, aiming to display the charging process of the ultra
observed in Fig. 19(b), as even in the presence of asymmet-
capacitor, Fig. 17 presents its voltage Vo along with the output
rical dc loads, ig a has maintained its sinusoidal behavior and
signals of the dc–dc stage io and vo during a 60 s window. In the
retrieves its half-wave symmetry, which can be confirmed by
figure, it is possible to confirm the ESS is charging and it is not
the exclusive presence of odd-order harmonics in its spectrum.
disturbed dramatically by the forced imbalance of the different
It’s important to keep in account that the balancing actions
scenarios. Given the considerable difference between the time
performed by the central converter results in a reduction of
constants of the ESS charging and the electrical variables, this
the apparent switching frequency on the line-to-line voltages,
voltage is not shown during the dynamic scenarios as it virtually
as it can be appreciated in the cases of Fig. 18, which ex-
does not experience any noticeable changes during that time
plains the shifting of input current dominant harmonics to lower
window.
frequencies.

B. Steady-State Analysis VII. CONCLUSION

Finally the results in steady state are analyzed in order to A different complementary balancing approach has been de-
complete the validation of the balancing approach, which are veloped and successfully validated, which takes advantages
displayed on Figs. 18 and 19. As it could be expected, the con- from the optional stages that the distributed dc bus architec-
verter voltages during the symmetrical operation from Fig. 18(a) ture allows. In this case, the presence of an energy storage
do not present major differences with conventional operation of stage, interfaced with a three-level dc–dc converter, allows the
the NPC, as the modification of the switching sequence only elimination of the balancing leg and provide the supplementary
takes place during the unbalanced operation. This is confirmed balancing ability required. This leads to a reduction in the over-
by the waveforms in Fig. 18(b), as the effort to maintain the all cost of the charging architecture, as the requirements for the
symmetry of the line to line voltages is reflected in extra switch- rectifier stage has been reduced, allowing to use off-the-shelf
ings in the negative half cycle of vaz . Then, vab retrieves the equipment.
2386 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 3, MARCH 2017

Is important to highlight that despite the ESS converter is pro- [17] S. Rivera, B. Wu, S. Kouro, V. Yaramasu, and J. Wang, “Electric vehicle
viding the additional balancing ability, this does not alter dra- charging station using a neutral point clamped converter with bipolar DC
bus,” IEEE Trans. Ind. Electron., vol. 62, no. 4, pp. 1999–2009, Apr. 2015.
matically its operation, allowing to keep its main function which [18] ABB. (Mar. 2015). [Online]. Available: http://new.abb.com/ev-charging.
is the charging and discharging of the energy buffer according [19] Blink. (Mar. 2015). [Online]. Available: http://www.blinknetwork.com/
to the selected energy management strategy. Furthermore, given chargers-commercial-dc-fast.
[20] Schneider-Electric. (Mar. 2015). [Online]. Available: http://www.
the features of the three-level dc–dc converter, the minimal load schneider-electric.com/.
condition does not impose a heavy restriction on the ESS siz- [21] A. Sannino, G. Postiglione, and M. Bollen, “Feasibility of a DC net-
ing, which means that its ratings are still set by the selected work for commercial facilities,” IEEE Trans. Ind. Appl., vol. 39, no. 5,
pp. 1499–1507, Sep./Oct. 2003.
energy management approach. Experimental results using an [22] Y. Ito, Y. Zhongqing, and H. Akagi, “DC micro-grid based distribution
ultracapacitor stage have been carried out for the validation of power generation system,” in Proc. IEEE Int. Power Electron. Motion Con-
the method, but the concept can be extended to different kinds trol Conf., Xian, China, Aug. 2004, vol. 3, pp. 1740–1745.
[23] J. Rodriguez, S. Bernet, B. Wu, J. Pontt, and S. Kouro, “Multilevel voltage-
of ESSs. source-converter topologies for industrial medium-voltage drives,” IEEE
Similar to the balancing method presented in [17], the pro- Trans. Ind. Electron., vol. 54, no. 6, pp. 2930–2945, Dec. 2007.
posed solution allows to keep high-quality input signals, even [24] S. Bai and S. Lukic, “New method to achieve ac harmonic elimination and
energy storage integration for 12-pulse diode rectifiers,” IEEE Trans. Ind.
under the presence of severe imbalances at the dc side. In addi- Electron., vol. 60, no. 7, pp. 2547–2554, Jul. 2013.
tion, the alternate switching sequence allows to perform the [25] P. Grbović, P. Delarue, P. Le Moigne, and P. Bartholomeus, “A bidirec-
complementary balancing while keeping the current free of tional three-level dc-dc converter for the ultracapacitor applications,” IEEE
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even-order harmonics. [26] L. Tan, B. Wu, S. Rivera, and V. Yaramasu, “Comprehensive dc power
balance management in high-power three-level dc-dc converter for elec-
tric vehicle fast charging,” IEEE Trans. Power Electron., vol. 31, no. 1,
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Mar. 2012.

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