CM6803

8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO

GENERAL DESCRIPTION FEATURES
The CM6803 is a 8-pin Green PFC/PWM controller for ! Patent Filed #5,565,761, #5,747,977, #5,742,151,
power factor corrected, switched mode power supplies that #5,804,950, #5,798,635
offers very low start-up and operating currents. For the ! Both PFC and PWM have the Green Mode to meet blue
power supply less than 500Watt, its input current shaping angel and energy star spec.
PFC performance could be very close to CM6800 or ! 8-Pin SOIC package
ML4800 architecture. ! PWM pulse skipping for the green mode
! It can use the HV bipolar to start up the chip and it help
Power Factor Correction (PFC) offers the use of smaller, green mode.
lower cost bulk capacitors, reduces power line loading and ! Enable lowest BOM for power supply with PFC
stress on the switching FETs, and results in a power supply ! Internally synchronized PFC and PWM in one IC
fully compliant to IEC1000-3-2 specifications. The CM6803 ! Patented slew rate enhanced voltage error amplifier with
includes circuits for the implementation of a leading edge, advanced input current shaping technique
input current shaping technique “boost” type PFC and a ! Universal Line Input Voltage
trailing edge, PWM. ! CCM boost or DCM boost with leading edge modulation
PFC using Input Current Shaping Technique
The CM6803’s PFC and PWM operate at the same ! PFCOVP, VCCOVP, Precision -1V PFC ILIMIT, Tri-Fault
frequency, 67kHz. An PFC OVP comparator shuts down Detect comparator to meet UL1950
the PFC section in the event of a sudden decrease in load. ! No bleed resistor required
The PFC section also includes peak current limiting for ! Low supply currents; start-up: 100uA typical, operating
enhanced system reliability. current: 2mA typical.
! Synchronized leading PFC and trailing edge modulation
Both PFC and PWM have the Green Mode Functions. PWM to reduce ripple current in the storage capacitor
PFC Green Mode cannot be disabled by the design. between the PFC and PWM sections and to reduce
PWM Green Mode will happen when the PWMCMP (PWM switching noise in the system
Comparator) Duty Cycle is less than ~ 6%, in the next ! VINOK Comparator to guarantee to enable PWM when
cycle, the PWMOUT pulse will be removed until PWMCMP PFC reach steady state
Duty Cycle is greater than 6%, then the next cycle, ! High efficiency trailing-edge current mode PWM
PWMOUT pulse appears. ! UVLO, REFOK, and brownout protection
! Digital PWM softstart
! Precision PWM 1.5V current limit for current mode
operation
24 Hours Technical Support---WebSIM
Champion provides customers an online circuit simulation tool
called WebSIM. You could simply logon our website at
www.champion-micro.com for details.

2003/06/24 Preliminary Champion Microelectronic Corporation Page 1

 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO

APPLICATIONS PIN CONFIGURATION

! Desktop PC Power Supply PSOP-8 (PS08)
Top View
! AC Adaptor
! Internet Server Power Supply
1 G ND PW M O UT 8
! IPC Power Supply
2 ISENSE PFCO UT 7
! UPS
! Battery Charger 3 VEAO VCC 6
! DC Motor Power Supply
4 VFB DC ILIM IT 5
! Monitor Power Supply
! Telecom System Power Supply
! Distributed Power

PIN DESCRIPTION
Operating Voltage
Pin No. Symbol Description
Min. Typ. Max. Unit
1 GND Ground

2 ISENSE Current sense input to the PFC current limit comparator -5 0.7 V

PFC transconductance voltage error amplifier output

3 VEAO 0 6 V

4 VFB PFC transconductance voltage error amplifier input 0 2.5 3 V

5 DC ILIMIT PWM current limit comparator input 0 1.5 V

6 VCC Positive supply 10 15 20 V

7 PFC OUT PFC driver output 0 VCC V

8 PWM OUT PWM driver output 0 VCC V

ORDERING INFORMATION
Part Number Temperature Range Package
CM6803IS -40℃ to 125℃ 8-Pin PSOP (PS10)

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 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO

BLOCK DIAGRAM
6
VCC

R1B
ISENSE 400K ohm
R1A
2
-
-
100K ohm +
. S Q
ISENSEAMP
+ 7
PFCCMP R VREF OK

R Q
PFCOUT
VFB gmv
4 -
RAMP UVLO
. . .

2.5V +

VCC . . UVLO

3 FAULTB
VEA_O
VCC
VCC OVP
+
17.9V
.
-
16.4V -
OSC

PFCCLKB
Tri-Fault PFCCLKB
.
Detect PWMCLK
.
- PWMCLK
Green Mode
.

0.5V + VIN OK 8
VREF OK
VFB - S Q PWMOUT
. R
PFC OVP 2.45V + R
0.75V + R
+
R Q
2.75V .
-
2.5V -
1.5V -
-
.

- 10mS +
PWMCMP
. .

-1V +
PFC ILIMIT . .

PWM CLK
SS
1V

5 1
DCILIMIT GND

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum ratings are those values beyond which the device could be permanently damaged.

Parameter Min. Max. Units

VCC MAX 20 V
ISENSE Voltage -5 0.7 V
PFC OUT GND – 0.3 VCC + 0.3 V
PWM OUT GND – 0.3 VCC + 0.3 V
VEAO 0 6.3 V
Voltage on Any Other Pin GND – 0.3 VREF + 0.3 V
ICC Current (Average) 40 mA
Peak PFC OUT Current, Source or Sink 0.5 A
Peak PWM OUT Current, Source or Sink 0.5 A
PFC OUT, PWM OUT Energy Per Cycle 1.5 µJ
Junction Temperature 150 ℃
Storage Temperature Range -65 150 ℃
Operating Temperature Range -40 125 ℃
Lead Temperature (Soldering, 10 sec) 260 ℃
Thermal Resistance (θJA) 80 ℃/W

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 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO

ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply Vcc=+15V,

TA=Operating Temperature Range (Note 1)
CM6803
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
Voltage Error Amplifier (gmv)
Input Voltage Range 0 5 V
Transconductance VNONINV = VINV, VEAO = 3.75V 30 65 90 µmho
Feedback Reference Voltage 2.45 2.5 2.55 V
Input Bias Current Note 2 -0.5 -1.0 µA
Output High Voltage 5.8 6.0 V
Output Low Voltage 0.1 0.4 V
Sink Current VFB = 3V, VEAO = 6V -20 -35 µA
Source Current VFB = 1.5V, VEAO = 1.5V 30 40 µA
Open Loop Gain 50 60 dB
Power Supply Rejection Ratio 11V < VCC < 16.5V 50 60 dB
VCC OVP Comparator
Threshold Voltage 17.4 17.9 18.4 V
Hysteresis 1.4 1.5 1.65 V
PFC OVP Comparator
Threshold Voltage 2.70 2.77 2.85 V
Hysteresis 230 290 mV
PFC ILIMIT Comparator
Threshold Voltage -0.9 -1 -1.15 V
Delay to Output 150 300 ns
VIN OK Comparator
Threshold Voltage 2.35 2.45 2.55 V
Hysteresis 1.65 1.75 1.85 V
PWM Digital Soft Start
Digital Soft Start Timer (Note 2) Right After Start Up (CM6803) 10 ms
DC ILIMIT Comparator
Threshold Voltage 1.4 1.5 1.6 V
Delay to Output (Note 2) 150 300 ns
Tri-Fault Detect Comparator
Fault Detect HIGH 2.70 2.77 2.85 V
VFB=VFAULT DETECT LOW to VFB = OPEN,
Time to Fault Detect HIGH 2 4 ms
470pF from VFB to GND
Fault Detect LOW 0.4 0.5 0.6 V
Oscillator
Initial Accuracy TA = 25℃ 62 67 74 kHz
Voltage Stability 10V < VCC < 15V 1 %
Temperature Stability 2 %
Total Variation Line, Temp 60 67 74.5 kHz
PFC Dead Time (Note 2) 0.3 0.45 0.65 µs

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 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO

ELECTRICAL CHARACTERISTICS (Conti.) Unless otherwise stated, these specifications apply

Vcc=+15V, RT = 52.3kΩ, CT = 470pF, TA=Operating Temperature Range (Note 1)
CM6803
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
PFC
Minimum Duty Cycle VFB=2.55V, ISENSE = -100V 0 %
Maximum Duty Cycle VFB=2.0V, ISENSE = 0V 90 95 %
Output Low Rdson 15 22.5 ohm
IOUT = -100mA 0.8 1.5 V
Output Low Voltage
IOUT = -10mA, VCC = 8V 0.4 0.8 V
Output High Rdson 30 45 ohm
Output High Voltage IOUT = 100mA, VCC = 15V 13.5 14.2 V
Rise/Fall Time (Note 2) CL = 1000pF 50 ns
PWM
Duty Cycle Range CM6803 0-49.5 0-50 %
Output Low Rdson 15 22.5 ohm
IOUT = -100mA 0.8 1.5 V
Output Low Voltage
IOUT = -10mA, VCC = 8V 0.7 1.5 V
Output High Rdson 30 45 ohm
Output High Voltage IOUT = 100mA, VCC = 15V 13.5 14.2 V
Rise/Fall Time (Note 2) CL = 1000pF 50 ns
Supply
Start-Up Current VCC = 11V, CL = 0 100 150 uA
Operating Current VCC = 15V, CL = 0 2 4.0 mA
Undervoltage Lockout Threshold 14.7 15 15.3 V
Undervoltage Lockout Hysteresis 4.85 5 5.15 V
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Guaranteed by design, not 100% production test.

TYPICAL PERFORMANCE CHARACTERISTIC

127
120
Transconductance (umho)

113
106
99
92
85
78
71
64
57
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3
VFB (V)

Voltage Error Amplifier (gmv) Transconductance

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 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO
Functional Description Detailed Pin Descriptions
The CM6803 consists of an ICST (Input Current Shaping
DCILIMIT (Pin 5)
Technique), CCM (Continuous Conduction Mode) or DCM
This pin is tied to the primary side PWM current sense
(Discontinuous Conduction Mode) boost PFC (Power
resistor or transformer. It provides the internal pulse-by-pulse
Factor Correction) front end and a synchronized PWM
current limit for the PWM stage (which occurs at 1.5V) and
(Pulse Width Modulator) back end. The CM6803 is
the peak current mode feedback path for the current mode
designed to replace FAN4803 (8 pin SOP package), which
control of the PWM stage. Besides current information, the
is the second generation of the FAN4803 with 8 pin
optocouple also goes into DCILIMIT pin. Therefore, it is the
package. It is distinguished from earlier combo controllers
SUM Amplifier input.
by its low count, innovative input current shaping technique,
and very low start-up and operating currents. The PWM VCC (Pin 6)
section is dedicated to peak current mode operation. It uses
VCC is the power input connection to the IC. The VCC
conventional trailing-edge modulation, while the PFC uses
start-up current is 100uA. The no-load ICC current is 2mA.
leading-edge modulation. This patented Leading
VCC quiescent current will include both the IC biasing
Edge/Trailing Edge (LETE) modulation technique helps to
currents and the PFC and PWM output currents. Given the
minimize ripple current in the PFC DC buss capacitor.
operating frequency and the MOSFET gate charge (Qg),
average PFC and PWM output currents can be calculated as
The main improvements from FAN4803 are:
1. Add Green Mode Functions for both PFC and PWM IOUT = Qg x F. The average magnetizing current required for
2. Remove the one pin error amplifier and add back the any gate drive transformers must also be included. The VCC
slew rate enhancement gmv, which is using voltage pin is also assumed to be proportional to the PFC output
input instead of current input. This transconductance voltage. Internally it is tied to the VCC OVP comparator
amplifier will increase the transient response 5 to 10 (17.9V) providing redundant high-speed over-voltage
times from the conventional OP protection (OVP) of the PFC stage. VCC also ties internally
3. VFB PFC OVP comparator to the UVLO circuitry and VREFOK comparator, enabling the
4. Tri-fault Detect for UL1950 compliance and enhanced IC at 15V and disabling it at 10V. VCC must be bypassed
safety with a high quality ceramic bypass capacitor placed as close
5. VINOK comparator is added to guaranteed PWM as possible to the IC. Good bypassing is critical to the proper
cannot turn on until VFB reaches 2.5V in which PFC operation of the CM6803.
boost output is about steady state, typical 380V.
6. A 10mS digital PWM soft start circuit is added VCC is typically produced by an additional winding off the
7. 8 pin SOP package boost inductor or PFC Choke, providing a voltage that is
8. No internal Zener but with VCCOVP comparator
proportional to the PFC output voltage. Since the VCC OVP
max voltage is 17.9V, an internal shunt limits VCC
The CM6803 operates both PFC and PWM sections at
overvoltage to an acceptable value. An external clamp, such
67kHz. This allows the use of smaller PWM magnetic and
as shown in Figure 1, is desirable but not necessary.
output filter components, while minimizing switching losses
in the PFC stage.
VCC

Several protection features have been built into the

CM6803. These include soft-start, redundant PFC
overvoltage protection, Tri-Fault Detect, VINOK, peak
current limiting, duty cycle limiting, under-voltage lockout,
reference ok comparator and VCCOVP. 1N 5250B

GND

Fig ure 1. O ptional V C C C lam p

This limits the maximum VCC that can be applied to the IC

while allowing a VCC which is high enough to trip the VCC
OVP. An RC filter at VCC is required between boost trap
winding and VCC.

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 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO
PFCOUT (Pin 7) and PWM OUT (Pin 8)
PFC OUT and PWM OUT are the high-current power driver To hold the input current draw of a device drawing power
capable of directly driving the gate of a power MOSFET from the AC line in phase with and proportional to the input
with peak currents up to -1A and +0.5A. Both outputs are voltage, a way must be found to prevent that device from
actively held low when VCC is below the UVLO threshold loading the line except in proportion to the instantaneous line
level which is 15V or VREFOK comparator is low. voltage. The PFC section of the CM6803 uses a boost-mode
DC-DC converter to accomplish this. The input to the
ISENSE (Pin 2) converter is the full wave rectified AC line voltage. No bulk
This pin ties to a resistor which senses the PFC input filtering is applied following the bridge rectifier, so the input
current. This signal should be negative with respect to the voltage to the boost converter ranges (at twice line
IC ground. It internally feeds the pulse-by-pulse current limit frequency) from zero volts to the peak value of the AC input
comparator and the current sense feedback signal. The and back to zero.
ILIMIT trip level is –1V. The ISENSE feedback is internally
multiplied by a gain of four and compared against the By forcing the boost converter to meet two simultaneous
internal programmed ramp to set the PFC duty cycle. The conditions, it is possible to ensure that the current draws
intersection of the boost inductor current downslope with from the power line matches the instantaneous line voltage.
the internal programming ramp determines the boost One of these conditions is that the output voltage of the
off-time. boost converter must be set higher than the peak value of
the line voltage. A commonly used value is 385VFB, to allow
It requires a RC filter between ISENSE and PFC boost for a high line of 270VACrms. The other condition is that the
sensing resistor. current that the converter is allowed to draw from the line at
any given instant must be proportional to the line voltage.
VEAO (Pin 3)
This is the PFC slew rate enhanced transconductance PFC Control: Leading Edge Modulation with Input
amplifier output which needs to connected with a Current Shaping Technique
compensation network Ground. (I.C.S.T.)

VFB (Pin 4) The only differences between the conventional PFC control
Besides this is the PFC slew rate enhanced topology and I.C.S.T. is:
transconductance input, it also tie to a couple of protection the current loop of the conventional control method is a close
comparators, PFCOVP, and Tri-Fault Detect loop method and it requires a detail understanding about the
system loop gain to design. With I.C.S.T., since the current
loop is an open loop, it is very straightforward to implement it.
Power Factor Correction
Power factor correction makes a nonlinear load look like a The end result of the any PFC system, the power supply is
resistive load to the AC line. For a resistor, the current like a pure resistor at low frequency. Therefore, current is in
drawn from the line is in phase with and proportional to the phase with voltage.
line voltage, so the power factor is unity (one). A common In the conventional control, it forces the input current to
class of nonlinear load is the input of most power supplies, follow the input voltage. In CM6803, the chip thinks if a boost
which use a bridge rectifier and capacitive input filter fed converter needs to behave like a low frequency resistor, what
from the line. The peak-charging effect, which occurs on the duty cycle should be.
the input filter capacitor in these supplies, causes brief
high-amplitude pulses of current to flow from the power line, The following equations is CM6803 try to achieve:
rather than a sinusoidal current in phase with the line
voltage. Such supplies present a power factor to the line of
less than one (i.e. they cause significant current harmonics Re = Vin (1)
of the power line frequency to appear at their input). If the
I in
input current drawn by such a supply (or any other
nonlinear load) can be made to follow the input voltage in I l = I in (2)
instantaneous amplitude, it will appear resistive to the AC
line and a unity power factor will be achieved.

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 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO

Equation 2 means: average boost inductor current equals

to input current. ( d ' ) 2 × Vout
∴Vin × I l ≈ Vout × I d (3)
Id × d ' =
Re
Therefore, input instantaneous power is about to equal to '
× Vout
the output instantaneous power. ∴ Id = d (8)
Re
For steady state and for the each phase angle, boost
Vout toff
converter DC equation at continuous conduction mode is: ∴ Id = ×
Vout Re Tsw
= 1 (4)
Vin (1 − d )
From this simple equation (8), we implement the PFC control
section of the CM6803.
Rearrange above equations, (1), (2),(3), and (4) in term of
Vout and d, boost converter duty cycle and we can get
Leading/Trailing Modulation
average boost diode current equation (5):
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will turn
I d = (1 − d ) × Vout
2
(5) ON right after the trailing edge of the system clock. The error
Re amplifier output is then compared with the modulating ramp.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned OFF. When
Also, the average diode current can be expressed as: the switch is ON, the inductor current will ramp up. The
effective duty cycle of the trailing edge modulation is
1 Toff
Id =
Tsw ∫0
I d (t ) ⋅ dt (6) determined during the ON time of the switch. Figure 2 shows
a typical trailing edge control scheme.
If the value of the boost inductor is large enough, we can
In case of leading edge modulation, the switch is turned OFF
assume I d (t ) ~ I d . It means during each cycle or we right at the leading edge of the system clock. When the
can say during the sampling, the diode current is a modulating ramp reaches the level of the error amplifier
constant. output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
Therefore, equation (6) becomes: during OFF time of the switch. Figure 3 shows a leading
I d × toff edge control scheme.
Id = = I d × d ' = I d × (1 − d ) (7)
Tsw
Combine equation (7) and equation (5), and we get:

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 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO

One of the advantages of this control technique is that it ZCV: Compensation Net Work for the Voltage Loop
required only one system clock. Switch 1(SW1) turns OFF GMv: Transconductance of VEAO
and switch 2 (SW2) turns ON at the same instant to PIN: Average PFC Input Power
minimize the momentary “no-load” period, thus lowering VOUTDC: PFC Boost Output Voltage; typical designed value is
ripple voltage generated by the switching action. With such 380V.
synchronized switching, the ripple voltage of the first stage CDC: PFC Boost Output Capacitor
is reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be ∆VEAO: This is the necessary change of the VEAO to deliver
reduced by as much as 30% using this method, the designed average input power. The average value is
substantially reducing dissipation in the high-voltage PFC 6V-3V=3V since when the input line voltage increases, the
capacitor. delta VEAO will be reduced to deliver the same to the output.
To over compensate, we choose the delta VEAO is 3V.
Typical Applications
PFC Section: Internal Voltage Ramp
PFC Voltage Loop Error Amp, VEAO The internal ramp current source is programmed by way of
The ML4803 utilizes an one pin voltage error amplifier in VEAO pin voltage. When VEAO increases the ramp current
the PFC section (VEAO). In the CM6803, it is using the source is also increase. This current source is used to
slew rate enhanced transconductance amplifier, which is develop the internal ramp by charging the internal 30pF +12/
the same as error amplifier in the CM6800. The unique -10% capacitor. The frequency of the internal programming
transconductance profile can speed up the conventional ramp is set internally to 67kHz.
transient response by 10 times. The internal reference of
the VEAO is 2.5V. The input of the VEAO is VFB pin. Design PFC ISENSE Filtering
ISENSE Filter, the RC filter between Rs and ISENSE:
PFC Voltage Loop Compensation
The voltage-loop bandwidth must be set to less than 120Hz There are 2 purposes to add a filter at ISENSE pin:
to limit the amount of line current harmonic distortion. A 1.) Protection: During start up or inrush current
typical crossover frequency is 30Hz. conditions, it will have a large voltage cross Rs,
which is the sensing resistor of the PFC boost
The Voltage Loop Gain (S) converter. It requires the ISENSE Filter to attenuate
the energy.
2.) Reduce L, the Boost Inductor: The ISENSE Filter
∆VOUT ∆VFB ∆VEAO
= * * also can reduce the Boost Inductor value since the
∆VEAO ∆VOUT ∆VFB ISENSE Filter behaves like an integrator before
PIN * 2.5V going ISENSE which is the input of the current error
≈ * GMV * ZCV amplifier, IEAO.
VOUTDC * ∆VEAO * S * CDC
2

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 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO

The ISENSE Filter is a RC filter. The resistor value of the PWM section wakes up after PFC reaches steady state
ISENSE Filter is between 100 ohm and 50 ohm. By selecting PWM section is off all the time before PFC VFB reaches
RFILTER equal to 50 ohm will keep the offset of the IEAO less 2.45V. Then internal 10mS digital PWM soft start circuit
than 5mV. Usually, we design the pole of ISENSE Filter at slowly ramps up the soft-start voltage.
fpfc/6, one sixth of the PFC switching frequency. Therefore,
the boost inductor can be reduced 6 times without PFC OVP Comparator
disturbing the stability. Therefore, the capacitor of the ISENSE PFC OVP Comparator sense VFB pin which is the same the
Filter, CFILTER, will be around 283nF. voltage loop input. The good thing is the compensation
network is connected to VEAO. The PFC OVP function is a
IAC, RAC, Automatic Slope Compensation, DCM at high line relative fast OVP. It is not like the conventional error amplifier
and light load, and Startup current which is an operational amplifier and it requires a local
feedback and it make the OVP action becomes very slow.
PFC Current Sense Filtering The threshold of the PFC OVP is 2.5V+10% =2.75V with
250mV hysteresis.
In DCM, the input current wave shaping technique used by
the FAN4803 could cause the input current to run away. In Tri-Fault Detect Comparator
order for this technique to be able to operate properly under
DCM, the programming ramp must meet the boost inductor To improve power supply reliability, reduce system
current down-slope at zero amps. Assuming the component count, and simplify compliance to UL1950 safety
programming ramp is zero under light load, the OFF-time standards, the CM6803 includes Tri-Fault Detect. This
will be terminated once the inductor current reaches zero. feature monitors VFB (Pin 4) for certain PFC fault conditions.
Subsequently the PFC gate drive is initiated, eliminating the
necessary dead time needed for the DCM mode. This In case of a feedback path failure, the output of the PFC
forces the output to run away until the VCCOVP shuts could go out of safe operating limits. With such a failure, VFB
down the PFC. This situation is corrected by adding an will go outside of its normal operating area. Should VFB go
offset voltage to the current sense signal, which forces the too low, too high, or open, Tri-Fault Detect senses the error
duty cycle to zero at light loads. This offset prevents the and terminates the PFC output drive.
PFC from operating in the DCM and forces pulse-keeping
from the CCM to no-duty, avoiding DCM operation. External Tri-Fault detect is an entirely internal circuit. It requires no
filtering to the current sense signal helps to smooth out the external components to serve its protective function.
sense signal, expanding the operating range slightly into
the DCM range, but this should be done carefully, as this VCC OVP and generate VCC
filtering also reduces the bandwidth of the signal feeding For the CM6803 system, if VCC is generated from a source
the pulse-by-pulse current limit signal. The typical circuit for that is proportional to the PFC output voltage and once that
adding offset to ISENSE at light load as below. source reaches 17.9V, PFCOUT, PFC driver will be off.

R59 R62 R63 C56 The VCC OVP resets once the VCC discharges below
2 1 1 2 1 2 2 1
PFC GATE 16.4V, PFC output driver is enabled. It serves as redundant
1 1k
20k
2
2 20k
C57
103 PFC OVP function.
ISENSE R64
D1 Typically, there is a bootstrap winding off the boost inductor.
R18 2 105
0.15
C46
10k 1 1N4148 The VCC OVP comparator senses when this voltage
2
102
1 exceeds 17.9V, and terminates the PFC output drive. Once
1
the VCC rail has decreased to below 16.4V the PFC output
VCC RTN drive be enabled. Given that 16V on VCC corresponds to
380V on the PFC output, 17.9V on VCC corresponds to an
OVP level of 460V.
It is a necessary to put RC filter between bootstrap winding
and VCC. For VCC=15V, it is sufficient to drive either a
PFC section wakes up after Start up period power MOSFET or a IGBT.
After Start up period, PFC section will softly start since
VEAO is zero before the start-up period. Since VEAO is a
slew rate enhanced transconductance amplifier (see figure
3), VEAO has a high impedance output like a current
source and it will slowly charge the compensation net work
which needs to be designed by using the voltage loop gain
equation.
Before PFC boost output reaches its design voltage, it is
around 380V and VFB reaches 2.5V, PWM section is off.

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 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO

UVLO Therefore, DCILIMIT actually is a summing node from

The UVLO threshold is 15V providing 5V hysteresis. voltage information which is from photo couple and CM431
and current information which is from one end of PWM
PFCOUT and PWMOUT sensing resistor and the signal goes through a single pole,
RC filter then enter the DCILIMIT pin.
Both PFCOUT and PWMOUT are CMOS drivers. They both
have adaptive anti-shoot through to reduce the switching This RC filter at DCILMIT also serves several functions:
loss. Its pull-up is a 30ohm PMOS driver and its pull-down 1.) It protects IC.
is a 15ohm NMOS driver. It can source 0.5A and sink 1A if 2.) It provides level shift for voltage information.
the VCC is above 15V. 3.) It filters the switching noise from current information.

PWM Section The pole location of the RC filter should be greater than one
sixth of the PWM switching frequency which is 67Khz for
Green Mode CM6803. Since the typical photo couple should be biased
CM6803 has the green mode function to improve the light around 1mA, the resistor of the RC filter should be around
load efficiency. PWM Green Mode will happen when the 1.5V/1mA~1.5K ohm and we suggest R is 1K ohm.
PWMCMP (PWM Comparator) Duty Cycle is less than ~ Therefore, for CM6803, C should be around 14nF.
6%, in the next cycle, the PWMOUT pulse will be removed
until PWMCMP Duty Cycle is greater than 6%, then the The maximum input voltage of the DCILIMIT pin is 1.5V.
next cycle, PWMOUT pulse appears.
Component Reduction
In other words, during the green mode, PWM switching Components associated with the VRMS and IEAO pins of a
frequency will reduce to improve the efficiency. With the typical PFC controller such as the CM6800 have been
proper external components, CM6803 can easily meet eliminated. The PFC power limit and bandwidth does vary
energy star and blue angel specification. with line voltage.

After 10mS digital soft start, CM6803’s PWM is operating

as a typical current mode. It requires a secondary
feedback, typically, it is configured with CM431, and photo
couple.

Since PWM Section is different from CM6800 family, it

needs the emitter of the photo couple to connected with
DCILIMIT instead of the collector. The PWM current
information also goes into DCILIMIT. Usually, the PWM
current information requires a RC filter before goes into the
DCILIMIT.

2003/06/24 Preliminary Champion Microelectronic Corporation Page 11

 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO
MAIN BOARD CIRCUIT

CM6800 DEMO BOARD (1 OUTPUT)

INPUT POWER: AC 90V-->5.8A
INPUT POWER: AC 260V-->1.9A
OUTPUT POWER: DC 250W
DATE:09-20-2002 3:00 PM

C2 Primary Section
224P/250V L1 D5 Secondary Section
850UH CTD80U60
ANODE CATHODE
2

D4 C7
RT1 6A/600V(CTD08B60G) R14 + 103/1KV
10/5A 4 - + 1 27K/1W C10 R16A
220UF/400V 412K 1% D8
t MUR1100
R15 R27 C20
R18 27K/1W 1 102/1KV
3

0.08/2W R102 Q12 R17A 100K/2W

CMT08N50 82/3W 412K 1% 2
2 1 1 R6 T1
2
R5 ER39/PC40
0
3

0 1
8 9
Q1 D13 R34 10uH
2

CMT08N50 3T 4.7/0.5W 5 6
45T
2

MUR1100 4 7
1 Q2 7 12 C14 3 8
2 1 CMT08N50 103/50V 2 9 10T +5V/20A
6 10 1 2 1 10
3

10T
R22 R3 2 D10 L2 L5
3

22 0 MUR1100 900V/7A 45T HS4

1.1uH
1
R2 R26 Q3 HS5 D9 + +
2

D11 0 18K/2W 5 11 SBL6040PT R35 2

2 JW1
4001 1 2
2 4.7/0.5W C17 C17A SNW
D12 R24 22 1 4 14 3300UF/10V 3300UF/10V

3
1
JP2 4148 R23 C22
R1 D14 JUMP 75 R25 C23 103/50V JW2
3

2T
560K 4001 10K 47OPF/1KV R28 R29 1
1 SNW
2 22 10K 1
1 3 15
1
3

SR34
R7 2 13 4.7/0.5W HS JW3
CML2 0 HS 1 L6 10 SNW
9.4mH 1
ZD1 2T SC14 2 9
1
VCC R31 6.8V 103/50V 3 8
0.33/2W 1 16 6T 4 10T 7 10T JW4
5 6 SNW

2
C30 L7
2

+ 10uH 1
47UF/25V JP3 3 + + 1.1uH + R52
C36 JUMP-WIRE SC22 C24 C25 C26 C27 20/2W JW5
222/3KV D15 3300UF/10V 3300UF/10V 3300UF/10V 104/50V SNW
C33 103/50V 1
C32 104/50V C34 C31 D16 SBL6040PT JW28 JW21
+
224/250VC9 104/50V 47UF/25V 4148 SNW SNW JW6

1
C8
3

SNW
1 1
2 Q8 2 Q6 SR35 1
KN2222A KN2222A R4 R32 4.7/0.5W JW29 JW22
0 120/0.5W SNW SNW JW7
11

11

F1 222/3KV 222/3KV 1 1
SNW
2 Q9 2
1
7A/250V KN2907A Q7 JW30 JW23
KN2907A SNW SNW JW8
SNW
3

1 1
J1 1
AC INLET SOCKET JW31 JW24
SNW SNW JW9
ip-ctl SNW
1 1
PFC-CT JW32 JW25 1
VP PFC-DRV PWM-DRV VCC VFB PWM-IL SNW SNW JW10
SNW
1 1
PGND 5V 1

JUMP
JP1

JP4
JUMP-WIRE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

20-PIN
J4

H1 H2 H3 H4
HOLE HOLE HOLE HOLE
1

2003/06/24 Preliminary Champion Microelectronic Corporation Page 12

 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO
CONTROL BOARD CIRCUIT

J1
20-PIN
PFC-CT

10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
2 +5V
2 R62 R63 C56
R59 1 2 1 2 2 1 R61
VFB
1k 20k 20k 103 510
2 2
C57 1
1 R64 D1 PWMDRV
10k 105 PWM-IL R44
1 1N4148
1K
1 VCC 2 1

ISO1
U1 817c
2
1 8
GND PWM OUT
C41 R45
2 1 104 51K 1% C38
2 7 821/50V
Isense PFC OUT C54 1
R43 R46 C40
1 102
390 100 104
3 6 2 1
VEAO VCC 2

4 5
VFB DC ILimit
3 1 1
2 1 CM6803-PP 2 2 U2
2 2 C52 C53 CM-431 R48
C46 C55 R57 R58 1 51K 1%
5.6k 390k 105 104

2
102 104 C41A 1 1 2
1 1 1 2
1 154
C43 2
104
2

2003/06/24 Preliminary Champion Microelectronic Corporation Page 13

 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO
PACKAGE DIMENSION
8-PIN SOP (S08)

PIN 1 ID

2003/06/24 Preliminary Champion Microelectronic Corporation Page 14

 CM6803
8-PIN GREEN MODE PFC/PWM CONTROLLER COMBO

IMPORTANT NOTICE

Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to discontinue any integrated
circuit product or service without notice, and advises its customers to obtain the latest version of relevant information to verify,
before placing orders, that the information being relied on is current.

A few applications using integrated circuit products may involve potential risks of death, personal injury, or severe property or
environmental damage. CMC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for
use in life-support applications, devices or systems or other critical applications. Use of CMC products in such applications is
understood to be fully at the risk of the customer. In order to minimize risks associated with the customer’s applications, the
customer should provide adequate design and operating safeguards.

HsinChu Headquarter Sales & Marketing

5F, No. 11, Park Avenue II, 11F, No. 306-3, Sec. 1, Ta Tung Rd.,
Science-Based Industrial Park, Hsichih, Taipei Hsien 221
HsinChu City, Taiwan Taiwan, R.O.C.

T E L : +886-3-567 9979 T E L : +886-2-8692 1591

F A X : +886-3-567 9909 F A X : +886-2-8692 1596
http://www.champion-micro.com

2003/06/24 Preliminary Champion Microelectronic Corporation Page 15