MP28167GQ A

MP28167-A
2.8V to 22V VIN, 3A IOUT, 4-Switch,

Integrated Buck-Boost Converter
with FB Pin
DESCRIPTION FEATURES
The MP28167-A is a synchronous, four-switch,  Configurable Output Voltage via FB Pin
integrated buck-boost converter capable of  Wide 2.8V to 22V Operating Input Voltage
regulating the output voltage across a wide 2.8V Range
to 22V input voltage range with high efficiency.  0.08V to 1.637V Reference Voltage Range
The integrated output voltage scaling and with 0.8mV Resolution through I2C (1)
adjustable output current limit functions meet (Default 1V Reference Voltage)
USB power delivery (PD) requirements.  3A Output Current or 4A Input Current
The MP28167-A uses constant-on-time (COT)  Four Low RDS(ON) Internal Buck Power
control in buck mode and constant-off-time MOSFETs
control in boost mode, providing fast load  Adjustable Accurate CC Output Current
transient response and smooth buck-boost Limit with Internal Sensing MOSFET via I2C
mode transient. The MP28167-A provides auto-  500kHz/750kHz Selectable Switching
PFM/PWM or forced PWM switching modes. It Frequency
also provides configurable output constant  Output Over-Voltage Protection (OVP) with
current (CC) current limit, which supports flexible Hiccup
design for different applications.  Output Short-Circuit Protection (SCP) with
Full protection features include over-current Hiccup
protection (OCP), over-voltage protection  Over-Temperature Warning and Shutdown
(OVP), under-voltage protection (UVP),  I2C Interface with ALT Pin
configurable soft start, and thermal shutdown.  One-Time Programmable (OTP) Non-
Volatile Memory
The MP28167-A is available in a QFN-16  I2C-Configurable Line Drop Compensation,
(3mmx3mm) package. PFM/PWM Mode, Soft Start, OCP, and
OVP
 Configurable EN Shutdown Discharge
 Available in a QFN-16 (3mmx3mm)
Package
 The MPL-AL Inductor Series Matches the
Best Performance
APPLICATIONS
 USB PD Sourcing Ports
 Buck-Boost Bus Supplies
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance. “MPS”,
the MPS logo, and “Simple, Easy Solutions” are registered trademarks of
Monolithic Power Systems, Inc. or its subsidiaries.
Note:
1) For applications where VOUT is below 3V, the switching
frequency decreases.
MP28167-A Rev. 1.0 www.MonolithicPower.com 1

4/15/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
TYPICAL APPLICATION
Efficiency vs. Output Current
VIN = 12V, VOUT = 5V to 20V, L = 4.7µH,
fSW = 500kHz, RDC = 16.5mΩ,
C4 100nF forced PWM mode
VIN L1 4.7µH 100
12V BST1 SW1
IN C5 100nF
95
+ BST2
C1 C1A
22µF 90
EFFICIENCY (%)
100µF SW2
R3 VOUT
499kΩ 5V
EN
OUT
85
C7 MP28167-A Cout
22µFx5
Vout=12V
22nF R1 80
Rt 430kΩ Vout=5V
ALT 806kΩ
SCL I2C slave FB
75
R2 Vout=9V
SDA
107kΩ 70
VCC Vout=15V
C3 AGND GND OC
1µF 65
Vout=20V
C6
R5
21.5kΩ 22nF
60
0.01 0.1 1 10
OUTPUT CURRENT (A)

ORDERING INFORMATION
Part Number* Package Top Marking MSL Rating
MP28167GQ-A QFN-16 (3mmx3mm)
See below 1
EVKT-MP28167-A Evaluation kit
* For Tape & Reel, add suffix –Z (e.g. MP28167GQ-A–Z).
TOP MARKING
BKN: Product code of MP28167GQ-A

Y: Year code
LLL: Lot number
EVALUATION KIT EVKT-MP28167-A

EVKT-MP28167-A kit contents (items below can be ordered separately, and the GUI installation file and
supplemental documents can be downloaded from the MPS website):
# Part Number Item Quantity
1 EV28167-A-Q-00A MP28167-A evaluation board 1
Includes one USB to I2C communication interface, one
2 EVKT-USBI2C-02 1
USB cable, and one ribbon cable
Order directly from MonolithicPower.com or our distributors.
Input Power
Supply
Input
USB Ribbon
Cable Cable
GUI Evaluation Board
USB to I2C Communication
Interface (EVKT-USBI2C-02)
Output
Load
Load
Figure 1: EVKT-MP28167-A Evaluation Kit Set-Up

PACKAGE REFERENCE
TOP VIEW
QFN-16 (3mmx3mm)

PIN FUNCTIONS
Pin # Name Description
Supply voltage. IN is the drain of the internal power device, and provides power to the entire
chip. The MP28167-A operates from a 2.8V to 22V input voltage. A capacitor (CIN) is required
1 IN
to prevent large voltage spikes from appearing at the input. Place CIN as close to the IC as
possible.
Power ground. GND is the reference ground of the regulated output voltage. GND requires
2, 11 GND
extra consideration during PCB layout. Connect GND with copper traces and vias.
On/off control for entire chip. Drive EN high to turn the device on. Drive EN low or float EN
3 EN
to turn it off. EN has an internal 2MΩ pull-down resistor to ground.
4 ALT Alert output. If ALT pulls to logic low, a fault or warning has occurred.
Clock pin of the I2C interface. SCL can support an I2C clock up to 3.4MHz. If not used, SCL
5 SCL
should be pulled up to VCC.
6 SDA Data pin of the I2C interface. If not used, SDA should be pulled up to VCC.
7 OC Output constant current limit set pin.
Feedback. Sets the output voltage when connected to the tap of an external resistor divider
8 FB
that is connected between output and GND.
9 VCC Internal 3.65V LDO regulator output. Decouple VCC with a 1µF capacitor.
10 AGND Analog ground. Connect AGND to GND.
12 OUT Output power pin. Place the output capacitor close to OUT and GND.
Bootstrap. Connect a 0.1µF capacitor between SW2 and BST2 to form a floating supply
13 BST2
across the high-side switch driver.
Switching node of the second half bridge. Connect one end of the inductor to SW2 for the
14 SW2
current to run through the bridge.
Switching node of the first half bridge. Connect one end of the inductor to SW1 for the
15 SW1
current to run through the bridge.
Bootstrap. Connect a 0.1µF capacitor between SW1 and BST1 to form a floating supply
16 BST1
across the high-side switch driver.

ABSOLUTE MAXIMUM RATINGS (2) Thermal Resistance θJA θJC

Supply voltage (VIN) ..................................... 26V QFN-16 (3mmx3mm)
VOUT .............................................................. 24V EV28167-A-Q-00A (6) ............. 26 ........ 3.... °C/W
VSW1, SW2 (DC) ................................-0.3V to +24.3V JESD51-7 (7) .......................... 50 ....... 12 ... °C/W
VSW1, SW2 (10ns) ....................................-7V to +26V
VBST1, BST2 ............................................. VSWx + 4V Notes:
2) Exceeding these ratings may damage the device.
VEN ................................................-0.3V to +26V 3) The maximum allowable power dissipation is a function of the
VALT ..............................................-0.3V to +5.5V maximum junction temperature, TJ (MAX), the junction-to-
All other pins ...................................-0.3V to +4V ambient thermal resistance, θJA, and the ambient
temperature, TA. The maximum allowable continuous power
Continuous power dissipation (TA = 25°C) (3) (6) dissipation at any ambient temperature is calculated by PD
................................................................... 4.8W (MAX) = (TJ (MAX) - TA) / θJA. Exceeding the maximum
Junction temperature ................................150°C allowable power dissipation produces an excessive die
temperature, and the regulator goes into thermal shutdown.
Lead temperature .....................................260°C Internal thermal shutdown circuitry protects the device from
Storage temperature ................ -65°C to +150°C permanent damage.
4) HBM, per JEDEC specification JESD22-A114; CDM, per
ESD Rating (4) JEDEC specification JESD22-C101. JEDEC document
JEP155 states that 500V HBM allows safe manufacturing with
All pins (HBM) ........................................... ±2kV a standard ESD control process. JEDEC document JEP157
All pins (CDM).............................................±2kV states that 250V CDM allows safe manufacturing with a
standard ESD control process.
5) The device is not guaranteed to function outside of its
Recommended Operating Conditions (5) operating conditions.
Operation input voltage range ......... 2.8V to 22V 6) Measured on EV28167-A-Q-00A, 4-layer PCB, 64mmx64mm.
7) Measured on JESD51-7, 4-layer PCB. The value of θJA given
Output voltage range ..................... 1V to 20.47V in this table is only valid for comparison with other packages
Output current .................. 3A continuous current and cannot be used for design purposes. These values were
or 4A input current calculated in accordance with JESD51-7 and simulated on a
specified JEDEC board. They do not represent the
Operating junction temp (TJ) .... -40°C to +125°C performance obtained in an actual application.

ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 5V, TJ = -40°C to +125°C (8), typical value is tested at TJ = 25°C, unless otherwise
noted.
Parameter Symbol Condition Min Typ Max Units
Shutdown supply current IIN VEN = 0V 0 3 μA
Quiescent supply current IQ Non-switching, I2C sets PFM mode 1 mA
EN rising threshold VEN_RISING 1.00 1.10 1.20 V
EN hysteresis VEN_HYS 110 mV
EN to ground resistance REN VEN = 2V 2 MΩ
EN on to VOUT > 90% delay tDELAY See Figure 7 on page 19 3.6 ms
VCC regulator VCC 3.3 3.65 4 V
VCC load regulation VCC_LOG ICC = 10mA 1 %
VIN under-voltage lockout
VIN_UVLO 2.50 2.65 2.8 V
rising threshold
VIN under-voltage lockout
VUVLO_HYS 160 mV
threshold hysteresis
Power Converter
HS switch on resistance RDSON_HS Switch A, D 25 40 mΩ
LS switch on resistance RDSON_LSB Switch B, C 21 35 mΩ
TJ = 25°C -1% 1000 +1% mV
Feedback voltage VFB
TJ = -40°C to +125°C -1.5% 1000 +1.5% mV
Feedback current IFB VFB = 1.05V 10 nA
Output discharge
RDIS 60 100 Ω
resistance
VEN = 0V, VSW1, SW2 = 22V, TJ = 25°C 1
Switch leakage SWLKG VEN = 0V, VSW1, SW2 = 22V, μA
5
TJ = -40°C to +125°C
fS1 Set FREQ = 500kHz by I2C, TJ = 25°C -20% 520 +20% kHz
Oscillator frequency
2
fS2 Set FREQ = 750kHz by I C, TJ = 25°C 750 kHz
Minimum on time (9) tON_MIN1 Switch A, B, C, D 160 ns
Maximum duty cycle DMAX Buck mode, FREQ = 500kHz 85 %
Minimum duty cycle (9) DMIN Boost mode, FREQ = 500kHz 15 %
Can be changed by I2C, VREF from 0V
Soft-start time tSS 3.5 ms
to 1V, default SS time
Protection
Output over-voltage
VOVP_R 150% 160% 170% VREF
protection
Output OVP recovery VOVP_F 130% 140% 150% VREF
Low-side B valley limit ILIMIT2 Switch B 6 8 10 A
Low-side C peak current
ILIMIT3 Switch C 10 A
limit

ELECTRICAL CHARACTERISTICS (continued)

VIN = 12V, VEN = 5V, TJ = -40°C to +125°C (8), typical value is tested at TJ = 25°C, unless otherwise
noted.
Parameter Symbol Condition Min Typ Max Units
VOUT = 5V,
IOUT_LIM1 0.85 1 1.15 A
across 0°C to 125°C temp range
(9)
Output average current
VOUT = 5V,
IOUT_LIM2 -5% 3.5 +5% A
across 0°C to 125°C temp range
Output UV threshold VUVP 20µs deglitch, UV falling 45% 50% 55% VREF
ALT sink current capability ALT_LOW Sink 4mA 0.2 0.4 V
ALT leakage ALT_LKG VPULL = 5V 1 μA
Thermal shutdown rising
TSTD 150 °C
threshold (9)
Thermal hysteresis (9) TSTD_HYS 20 °C
I2C Specification (9)
Input logic high VIH I2C pull-up VDD can be 1.8V to 5V 1.4 V
Input logic low VIL 0.4 V
Output voltage logic low VOUT_L 0.4 V
SCL clock frequency fSCL 400 3400 kHz
SCL high time tHIGH 60 ns
SCL low time tLOW 160 ns
Data set-up time tSU_DAT 10 ns
Data hold time tHD_DAT 0 60 ns
Set-up time for (repeated)
tSU_STA 160 ns
start condition
Hold time for (repeated)
tHD_STA 160 ns
start condition
Bus free time between a
tBUF 160 ns
start and a stop condition
Set-up time for stop
tSU_STO 160 ns
condition
SCL and SDA rising time tR 10 300 ns
SCL and SDA falling time tF 10 300 ns
Pulse width of suppressed
tSP 0 50 ns
spike
Capacitance for each bus
CB 400 pF
line
Notes:
8) All min/max parameters are tested at TJ = 25°C. Over-temperature limits are guaranteed by design, characterization, and correlation.
9) Guaranteed by engineering sample characterization.

TYPICAL CHARACTERISTICS
VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 500kHz, TA = 25°C, unless otherwise noted.
Load Regulation
VIN = 12V, VOUT = 5V/9V/12V/20V, Line Regulation vs. Input Voltage
IOUT = 0A to 3A, no line drop compensation VOUT = 5V
0.3 0.3
LOAD REGULATION (%)
0.2 0.2
LINE REGULATION (%)

0.1 0.1
0 0
-0.1 -0.1
Vo=5V Io=0A
-0.2 Vo=9V
Vo=12V -0.2 Io=1.5A
Vo=20V Io=3A
-0.3 -0.3
0 1 2 3 2 4 6 8 10 12 14 16 18 20 22 24
OUTPUT CURRENT (A) INPUT VOLTAGE (V)
Line Regulation vs. Input Voltage Line Regulation vs. Input Voltage
VOUT = 9V VOUT = 12V
0.3 0.3
0.2 0.2
LINE REGULATION (%)
LINE REGULATION (%)
0.1 0.1
0 0
-0.1 -0.1
Io=0A
Io=0A
-0.2 Io=1.5A -0.2 Io=1.5A
Io=3A Io=3A
-0.3 -0.3
2 4 6 8 10 12 14 16 18 20 22 24 2 4 6 8 10 12 14 16 18 20 22 24
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
Line Regulation vs. Input Voltage Thermal Rise vs. Output Current
VOUT = 20V VIN = 12V, VOUT = 5V to 20V, IOUT = 0A to 3A
0.3 40
0.2 35
LINE REGULATION (%)
THERMAL RISE (℃）
0.1 30
25
0
20
-0.1
15
-0.2
Io=0A 10 Vo=5V
-0.3 Io=1A Vo=9V
Io=2A 5 Vo=12V
Vo=20V
-0.4 0
2 4 6 8 10 12 14 16 18 20 22 24 0 1 2 3
INPUT VOLTAGE (V) OUTPUT CURRENT (A)

TYPICAL CHARACTERISTICS (continued)

Efficiency vs. Output Current
VOUT = 5V to 20V, RDC = 16.5mΩ, Efficiency vs. Output Current
forced PWM mode VOUT = 5V to 20V, RDC = 16.5mΩ, PFM mode
100 100
95 95
90 90
EFFICIENCY (%)
EFFICIENCY (%)
85 85
Vout=12V Vout=5V
80 80
Vout=5V Vout=9V
75 75
Vout=9V Vout=12V
70 70
Vout=15V Vout=20V
65 65
Vout=20V
60 60
0.01 0.1 1 10 0.01 0.1 1 10
OUTPUT CURRENT (A) OUTPUT CURRENT (A)
Recommended VIN, VOUT, IOUT

Operation Range
22μF x 5 ceramic COUT capacitor Output Voltage vs. Temperature
3.5 6
5.8
3
OUTPUT VOLTAGE (V)
5.6
2.5 5.4
IO_MAX(A)
2 Vo=5V 5.2
Vo=9V 5
1.5
4.8
Vo=12V
1 4.6
Vo=15V
0.5 4.4
Vo=20V 4.2
0 4
0 2 4 6 8 10 12 14 16 18 20 22 24 -60 -40 -20 0 20 40 60 80 100
INPUT VOLTAGE (V) TEMPERATURE (°C)
VIN UVLO Rising and Falling EN Rising and Falling Threshold vs.
Threshold vs. Temperature Temperature
3 2
EN RISING AND FALLING
FALLING THRESHOLD (V)
2.5
VIN UVLO RISING AND
1.5
THRESHOLD (V)
1.5 1
1
0.5
0.5 Rising Rising
Falling Falling
0 0
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)

TYPICAL CHARACTERISTICS (continued)

Output Voltage UVP Threshold vs.
Buck Current Limit vs. Temperature Temperature
10 100
90
BUCK CURRENT LIMIT (A)
OUTPUT VOLTAGE UVP

8 80
THRESHOLD (%)
70
6 60
50
4 40
30
2 20
Falling
10 Rising
0 0
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 500kHz, TA = 25°C, test waveform is based on Figure 17,
unless otherwise noted.
EN Bit Enabled through I2C EN Bit Enabled through I2C
Command Command
Load = 0A Load = 3A
CH1: VOUT CH1: VOUT

5V/div. 5V/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2 CH3: VSW2
5V/div. 5V/div.
CH4: IL CH4: IL
2A/div. 2A/div.
2ms/div. 2ms/div.
EN Bit Shutdown through I2C EN Bit Shutdown through I2C

Command Command
Load = 0A Load = 3A
CH1: VOUT CH1: VOUT

5V/div. 5V/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2 CH3: VSW2
10V/div. 5V/div.
CH4: IL CH4: IL
2A/div. 2A/div.
2ms/div. 100μs/div.
EN Pin Enabled EN Pin Enabled

Load = 0A Load = 3A
CH1: VOUT CH1: VOUT

5V/div. 5V/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2 CH3: VSW2
5V/div. 5V/div.
CH4: IL CH4: IL
2A/div. 2A/div.
2ms/div. 1ms/div.

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

EN Pin Disabled EN Pin Disabled
Load = 0A Load = 3A
CH1: VOUT CH1: VOUT

5V/div. 5V/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2 CH3: VSW2
5V/div. 10V/div.
CH4: IL CH4: IL
2A/div. 2A/div.
VIN Start-Up VIN Start-Up

Load = 0A Load = 3A
CH1: VOUT CH1: VOUT

5V/div. 5V/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2 CH3: VSW2
5V/div. 10V/div.
CH4: IL CH4: IL
2A/div. 2A/div.
2ms/div. 2ms/div.
VIN Shutdown VIN Shutdown

Load = 0A Load = 3A
CH1: VOUT CH1: VOUT

5V/div. 5V/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2 CH3: VSW2
5V/div. 5V/div.
CH4: IL CH4: IL
2A/div. 5A/div.


Steady State Steady State
VOUT = 5V, load = 0A, fSW = 500kHz VOUT = 5V, load = 3A, fSW = 500kHz
CH1: VOUT CH1: VOUT

20mV/div. 20mV/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2 CH3: VSW2
5V/div. 5V/div.
CH4: IL CH4: IL
2A/div. 5A/div.
2μs/div. 2μs/div.
Steady State Steady State

VOUT = 5V, load = 0A, fSW = 750kHz VOUT = 5V, load = 3A, fSW = 750kHz
CH1: CH1:
VOUT/AC VOUT/AC
10mV/div. 10mV/div.
CH2: VSW1 CH2: VSW1
5V/div. 5V/div.
CH3: VSW2 CH3: VSW2
5V/div. 5V/div.
CH4: IL CH4: IL
2A/div. 2A/div.
1μs/div. 1μs/div.
I2C VID I2C VID

VOUT = 5V to 12V, IOUT = 0A, R1 = 430kΩ, VOUT = 12V to 5V, IOUT = 0A, R1 = 430kΩ,
R2 = 53.6kΩ R2 = 53.6kΩ
CH1: VOUT CH1: VOUT

5V/div. 5V/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2 CH3: VSW2
10V/div. 10V/div.
CH4: IL CH4: IL
2A/div. 2A/div.
2ms/div. 2ms/div.


I2C VID I2C VID
VOUT = 5V to 12V, IOUT = 3A, R1 = 430kΩ, VOUT = 12V to 5V, IOUT = 3A, R1 = 430kΩ,
R2 = 53.6kΩ R2 = 53.6kΩ
CH1: VOUT CH1: VOUT

5V/div. 5V/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2 CH3: VSW2
10V/div. 10V/div.
CH4: IL CH4: IL
5A/div. 5A/div.
2ms/div. 2ms/div.
Load Transient Load Transient

VIN = 12V, VOUT = 5V, no line drop compensation, VIN = 12V, VOUT = 5V, no line drop compensation,
0A to 1.5A, 150mA/μs 1.5A to 3A, 150mA/μs
CH2: CH2:
VOUT/AC VOUT/AC
500mV/div. 500mV/div.
CH4: IOUT CH4: IOUT

1A/div. 1A/div.
500μs/div. 500μs/div.
Short-Circuit Protection Entry with Short-Circuit Protection Entry with

Latch-Off Mode Hiccup Mode
CH1: VOUT CH1: VOUT

5V/div. 5V/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2 CH3: VSW2
10V/div. 10V/div.
CH4: IL CH4: IL
10A/div. 10A/div.
5ms/div. 20ms/div.


Short-Circuit Protection Recovery CC Current Limit Entry
with Hiccup Mode (Test with CV mode of electronic load)
CH1: VOUT CH1: VOUT

5V/div. 2V/div.
CH2: VSW1 CH2: VSW1
10V/div. 10V/div.
CH3: VSW2 CH3: VSW2
10V/div. 5V/div.
CH4: IL CH4: IL
10A/div. 5A/div.
20ms/div. 100ms/div.
CC Current Limit Steady State VOUT OVP with Hiccup Mode
CH1: VOUT
CH1: VOUT 5V/div.
5V/div.
CH2: VSW1
CH2: VSW1 10V/div.
10V/div. CH3: VSW2
CH3: VSW2 5V/div.
5V/div.
CH4: IL
CH4: IL 5A/div.
2A/div.
1μs/div. 500ms/div.
VOUT OVP with Latch-Off Mode
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH4: IL
5A/div.
500ms/div.

FUNCTIONAL BLOCK DIAGRAM

IN
VCC
OUT Bootstrap
Regulator BST1
VCC Regulator
HS
On Timer Driver A
SCL DAC
I2C/OTP
SW1
VCC
IF and
SDA A, B, C, D
Register LS
FET Sensing Driver
B
ALT
GND
Current Limit
Buck-Boost Bootstrap IN
Comparator
EN Reference Control Logic Regulator OUT
2MΩ
COMP BST2
FB Error HS
Amplifier Driver D
VCC SW2
SS VCC
PG and
LS C
OVP OV Driver
GND
OC AGND
Figure 1: Functional Block Diagram

OPERATION SWA works with COT control logic, and SWB

turns on as a complement of SWA. In each cycle,
The MP28167-A is a four-switch, integrated
SWB turns on to conduct the inductor current.
buck-boost converter that can work in constant-
on-time (COT) control mode with a fixed When the inductor current drops to the COMP
frequency. This provides fast transient response voltage (VCOMP), SWB turns off and SWA turns
for the buck, boost, and buck-boost modes. A
special buck-boost control strategy provides
high efficiency over the full input range, and on. SWA turns on for a fixed on time before
smooth transient between different modes. turning off. Then SWB turns on again, and the
operation repeats. The COMP signal is the error
Buck-Boost Operation
amplifier (EA) output from the VOUT feedback and
The MP28167-A can regulate the output voltage internal FB reference voltage (see Figure 4).
(VOUT) to be above, equal to, or below the input
voltage (VIN). Figure 2 shows a power structure SW1
with one inductor and the four switches. SW2
IL
tON COMP
Control by COMP
Figure 4: Buck Waveform
Boost Mode
When VIN is significantly lower than VOUT, the
MP28167-A works in boost mode. In boost
mode, SWC and SWD switch for the boost
regulation. SWB is off, and SWA remains on to
conduct the inductor current.
During each period, SWC remains off with COT
Figure 2: Buck-Boost Topology control, while SWD turns on as a complement of
The MP28167-A can operate in buck mode, SWC to boost the inductor current to the output.
boost mode, or buck-boost mode with different In each cycle, SWC turns on to conduct the
VIN inputs (see Figure 3). inductor current. When the inductor current rises
and reaches VCOMP, SWC turns off and SWD
Boost Buck-Boost Buck turns on. SWC turns off with a fixed off time
SWA On, SWB Off, All FETs D On, C Off, before turning on again. During this period, SWD
SWC and SWD Switching A and B Switching
Switching
turns on for the current freewheel (see Figure 5).
VO-SET
VIN Voltage SW1
Boost Boost Buck Buck
DMAX DMIN DMAX DMIN
SW2
Figure 3: Buck-Boost Operation Range
COMP
Buck Mode IL
When VIN is significantly higher than VOUT, the
MP28167-A works in buck mode. In buck mode, Control by COMP
SWA and SWB switch for buck regulation. SWC tOFF
is off, and SWD remains on to conduct the Figure 5: Boost Waveform
inductor current.

Buck-Boost Mode If VIN exceeds 130% of VOUT in buck-boost mode,

When VIN is almost equal to VOUT, the MP28167- the MP28167-A switches from buck-boost mode
A cannot provide enough energy to operate in to buck mode. If VIN drops below 20% of VOUT,
buck mode due to SWA’s minimum off time, or it the MP28167-A switches from buck-boost mode
supplies too much power to VOUT in boost mode to boost mode.
due to SWC’s minimum on time. The IC uses
buck-boost control to regulate VOUT in these
conditions. SW1 tBUCK-MIN
If VIN drops and the SWA off period is close to

the minimum buck off time in buck mode, buck- SW2
boost mode is engaged. When the next cycle
Boost Min On Time
starts after the SWA and SWD on time (the buck COMP
high-side MOSFET [HS-FET] on period), the IL
boost starts with SWA and SWC on (boost low-
side MOSFET [LS-FET] on). Boost Buck-Boost
tBUCK-BOOST
SWA and SWD turn on again for the resting Figure 7: Buck-Boost Waveform
period of boost mode (boost HS-FET on). After
Working Mode Selection
the boost period elapses, the buck period starts,
and SWB and SWD remain on until the inductor The MP28167-A works with a fixed frequency
current drops to VCOMP. Then SWA and SWD turn under heavy-load conditions. When the load
on until the next boost period begins. Buck and current decreases, the MP28167-A can work in
boost switching work with a one-interval period. forced continuous conduction mode (FCCM) or
This is called buck-boost mode. pulse-skip mode (PSM) based on the MODE
register setting.
If VIN rises, and the SWC on period is close to
the boost minimum on time in boost mode, buck- FCCM (or Forced PWM)
boost mode is enabled. After the boost constant- In forced continuous conduction mode (FCCM),
off-time period (SWA and SWD on), SWB and the buck on time and boost off time are
SWD remain on until the inductor current signal determined by the internal circuit. This achieves
drops to VCOMP, just like a buck off-time period a fixed frequency based on the VIN / VOUT ratio.
control. When the load decreases, the average input
current drops, and the inductor current may go
After the inductor current signal triggers VCOMP,
negative from VOUT to VIN during the off time
SWA and SWD turn on for the buck on time,
(SWD on). This forces the inductor current to
which is followed by boost switching (SWA and
work in continuous mode with a fixed frequency,
SWC on). Buck and boost switching work with a
producing a lower VOUT ripple than in PSM mode.
one-interval period. Figure 6 shows the buck-
boost waveform when VIN exceeds VOUT. PSM (Auto-PFM/PWM Mode)
If the inductor current drops to 0A in PSM, SWD
SW1
turns off to prevent the current from flowing from
VOUT to VIN, forcing the inductor current to work
tBOOST-MIN
in discontinuous conduction mode (DCM).
SW2
Meanwhile, the internal off time clock stretches
Buck Min Off Time once the MP28167-A enters DCM mode. The
frequency drops when the inductor current
IL
conduction period decreases, which helps save
COMP
power loss and reduce the VOUT ripple.
Buck Buck-Boost
tBUCK-BOOST
If VCOMP drops to the PSM threshold (even if the
Figure 6: Buck to Buck-Boost Transient IC stretches the frequency), the MP28167-A
Figure 7 shows the buck-boost waveform when stops switching to further decrease the switching
VOUT exceeds VIN. power loss.

The MP28167-A recovers switching once VCOMP the SS voltage (VSS) is below VREF, the error
exceeds the PSM threshold. The switching pulse amplifier uses VSS as the reference. If VSS
skips based on VCOMP in very light-load exceeds VREF, the error amplifier uses VREF as
conditions. PSM has a much higher efficiency the reference.
than FCCM mode in light load, but the VOUT ripple
If the output of the MP28167-A is pre-biased to a
may be higher due to the group switching pulse.
certain voltage during start-up, the IC disables
Internal VCC Regulator the switching of both the HS-FET and LS-FET
The 3.65V internal regulator powers most of the until the voltage on the internal SS capacitor
internal circuitries. This regulator takes VIN and exceeds the internal feedback voltage (see
operates in the full VIN range. When VIN exceeds Figure 8).
3.65V, the output of the regulator is in full
regulation. If VIN drops below 3.65V, the output EN
decreases with VIN. VCC requires an external
1µF ceramic capacitor for decoupling. VOUT
90%
Enable (EN) Control
tDELAY
The MP28167-A has an enable (EN) control pin.
Pull EN high to enable the IC. Pull EN low or float Figure 9: EN On to VOUT > 90% Delay
EN to disable the IC. Over-Current Protection (OCP)
If EN is pulled down when the output discharge The MP28167-A has a constant-current limit
function is enabled, the MP28167-A shuts down control loop to limit the output average current.
after 55ms. The MP28167-A’s I2C register value The current information is sensed from switches
is reset to default only after the MP28167-A A, B, C, and D. Then an average algorithm
experiences this type of shutdown. If EN is pulled calculates the output current.
high within 55ms, the I2C register is not reset,
When the output current exceeds the current-
and the MP28167-A enables the output with the
limit threshold, the output voltage starts to drop.
previous register setting.
There are two conditions that activate this
If the output discharge function is disabled, the
condition:
MP28167-A shuts down once EN is pulled down
for more than 100µs, and the MP28167-A I2C 1. The first is if VOUT exceeds 3V, VFB drops
register is reset after a 100µs delay. below 50% of VREF, and VOUT drops below 3V.
The MP28167-A then enters hiccup mode or
VOUT = 12V (I2C Setting) VOUT = 12V (I2C Setting)
latch off mode according to the I2C setting.
VOUT = 5V (I2C Reset)
2. The second is if VOUT is set below or equal to
3V, and VOUT drops below the under-voltage
EN EN Off
< 55ms
(UV) threshold (typically 50% below VREF).
EN Off > 55ms The MP28167-A then enters hiccup mode or
latch-off mode according to the I2C setting.
Figure 8: EN On/Off Logic for I2C Register Reset
In hiccup mode, the MP28167-A stops switching
Under-Voltage Lockout (UVLO) and recovers automatically with 12.5% duty
Under-voltage lockout (UVLO) protects the chip cycles. In latch-off mode, the MP28167-A stops
from operating at an insufficient supply voltage. switching until the IC restarts (power cycling on
The UVLO comparator monitors the input VIN or EN, or EN bit toggling).
voltage and enables or disables the entire IC.
Over-Voltage Protection (OVP)
Internal Soft Start (SS) The MP28167-A monitors a resistor-divided
Soft start (SS) prevents the converter output feedback voltage to detect output over-voltage
voltage from overshooting during start-up. When (OV) conditions. When the feedback voltage
the chip starts up, the internal circuitry generates exceeds 160% of the target voltage, the over-
an SS voltage that ramps up from 0V to 3.65V. If voltage protection (OVP) comparator output

goes high. The output-to-ground discharge connecting to the line, a master device
resistor turns on. generates the SCL signal and device address,
The OUT pin has an absolute OVP function. and arranges the communication sequence.
Once VOUT exceeds the absolute OVP threshold The MP28167-A interface is an I2C slave that
(23V), the MP28167-A stops switching and turns supports fast mode (400kHz) and high-speed
on the OUT-to-ground discharge resistor. mode (3.4MHz). The I2C interface adds flexibility
Start-Up and Shutdown to the power supply solution. The output voltage,
transition slew rate, and other parameters can be
If both VIN and EN exceed their respective
controlled instantaneously via the I2C interface.
thresholds, the chip is enabled. The reference
block starts first, generating a stable reference When the master sends the address as an 8-bit
voltage and current, and then the internal value, the 7-bit address should be followed by a
regulator is enabled. The regulator provides a 0 to indicate a write operation, or 1 to indicate a
stable supply for the remaining circuitries. read operation.
Three events can shut down the chip: EN going Start and Stop Conditions
low, VIN going low, and thermal shutdown. During The start and stop conditions are signaled by the
shutdown, the signaling path is blocked to avoid master device, which signifies the beginning and
fault triggers. Then VCOMP and the internal supply end of an I2C transfer. The start (S) condition is
rail are pulled down. The floating driver is not defined as the SDA signal transitioning from high
subject to this shutdown command. to low while the SCL is high. The stop (P)
Output Discharge condition is defined as the SDA signal
transitioning from low to high while the SCL is
The MP28167-A has an output discharge
high (see Figure 9).
function that provides a resistive discharge path
for the external output capacitor. The function is The master then generates the SCL clocks and
active when the part is disabled (input voltage is transmits the device address and the read/write
under UVLO or enable off), the discharge path is direction bit (R/W) on the SDA line.
turned off when VOUT < 50mV or waits for the
Transfer Data
50ms maximum timer to pass. This function can
also be disabled via the I2C. Data is transferred in 8-bit bytes by an SDA line.
Each byte of data should be followed by an
Thermal Warning (TSW) and Shutdown (TSD) acknowledge (ACK) bit.
Thermal warning and thermal shutdown prevent
I2C Update Sequence
the part from operating at exceedingly high
temperatures. When the silicon die temperature The MP28167-A requires a start condition, a
exceeds 120°C, the MP28167-A sets the OTW valid I2C address, a register address byte, and a
bit [D5] to 1. When the temperature falls below data byte for a single data update. The
its lower threshold (typically 100°C), the OTW bit MP28167-A acknowledges that it has received
[D5] is set to 0. each byte by pulling the SDA line low during the
high period of a single clock pulse. A valid I2C
When the silicon die temperature exceeds address selects the MP28167-A. The MP28167-
150°C, the entire chip shuts down. When the A performs an update on the falling edge of the
temperature falls below its lower threshold LSB byte. See Figure 11, Figure 12, and Figure
(typically 130°C), the chip is enabled. This is a 13 for examples I2C write and read sequences.
non-latch protection.
I2C Start-Up Timing
2
I C INTERFACE I2C functionality is enabled once EN is active and
I2C Serial Interface Description VIN exceeds the under-voltage lockout (UVLO)
The I2C is a two-wire, bidirectional, serial threshold. The I2C works during over-current
interface consisting of a data line (SDA) and a protection (OCP), over-voltage protection (OVP),
clock line (SCL). The lines are pulled to a bus and thermal shutdown.
voltage externally when they are idle. When

SDA
SCL
S P
Start Condition Stop Condition
Figure 10: Start and Stop Conditions
8 Bits 8 Bits 8 Bits
S Slave Address WR A Register Address K A Write Data A P
Master to Slave A = Acknowledge (SDA = Low) S = Start Condition WR Write = 0
Slave to Master NA = Not Acknowledge (SDA = High) P = Stop Condition RD Read = 1
Figure 11: I2C Write Example (Write Single Register)
8 Bits 8 Bits 8 Bits
S Slave Address WR A Register Address K A Write Data K A Write Data K + 1 A Write Data K + N A P
Multi-byte write executed from current register location (the

read-only register is skipped)
Master to Slave A = Acknowledge (SDA = Low) S = Start Condition WR Write = 0
Figure 12: I2C Write Example (Write Multi-Register)
8 Bits 8 Bits 8 Bits 8 Bits
S Slave Address WR A Register Address K A Sr Slave Address RD A Read Data K NA P
Register address to read specified Read register data from current register location
Master to Slave A = Acknowledge (SDA = Low) S = Start Condition Sr = Repeat WR Write = 0

Start Condition
Figure 13: I2C Read Example (Read Single Register)

I2C REGISTER MAP

Add
Name R/W D7 D6 D5 D4 D3 D2 D1 D0
(Hex)
00 VREF_L R/W RESERVED VREF DATA BIT LOW [2:0] (10)
01 VREF_H R/W VREF DATA BIT HIGH [10:3] (10)

PG_
GO_
02 VREF_GO R/W RESERVED DELAY_
BIT
EN (10)
03 IOUT_LIM R/W RESERVED Output current limit threshold (0A to 6.35A/50mA step for 21.5kΩ OC resistor) (10)
HICCUP DISCHG
04 CTL1 R/W EN (10) MODE (10) FREQ (10) RESERVED
OCP_OVP (10) _EN (10)
05 CTL2 R/W LINE DROP COMP (10) SS (10)
RESERVED
06 RESERVED R RESERVED, ALL “0” RESERVED
07 RESERVED R RESERVED
08 RESERVED R RESERVED
09 Status R PG OTP OTW CC_CV RESERVED
OT OT
OTEMPP_ OC_ OC_ UVP_ OTEMPP PG_
0A INTERRUPT W1C WARNING_ WARNING
ENTER ENTER RECOVER FALLING _EXIT RISING
ENTER _EXIT
OTPMSK OTWMSK OC_ UVP_ PG_
0B MASK R/W RESERVED (10) (10)
MSK (10) MSK (10) MSK (10)
0C ID1 R OTP Configure Code. “0x00” means the standard MP28167-A
27 MFR_ID R Manufacturer ID: b ‘0000 1001’
28 DEV_ID R Device ID: b ‘0101 1000’
29 IC_REV R IC revision: b ‘0000 0001’
Note:
10) These items have one-time programmable (OTP) non-volatile memory. The OTP is reloaded to the I2C register when VIN exceeds the
under-voltage lockout (UVLO) threshold, or during EN shutdown.

REGISTER DESCRIPTION
I2C Bus Slave Address
The MP28167-A I2C slave address is fixed as 60H.
Output Reference Voltage Setting
The registers VREF_L and VREF_H set the reference voltage and follow 11-bit direct format.
Name VREF
Format Direct, unsigned binary integer
Register
N/A VREF_H D[7:0] VREF_L D[2:0]
Name
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Function N/A Data bit high Data bit low
Default
Value N/A 1250 integer
(1000mV)
The reference voltage can be calculated with Equation (1):

VREF (mV) = V x 0.8 (1)
Where V is an 11-bit unsigned binary integer of VREF[10:0] that ranges from 0 to 2047. The VREF
resolution is 0.8mV/LSB. The reference voltage changing slew rate is fixed at 1mV/µs. See the GO_BIT
section below to change the reference voltage.
VREF_GO Register
GO_BIT D[0]
The MP28167-A can be controlled when VREF begins to change. Set GO_BIT to 1 to start the output
reference change based on the VREF register. When the VREF change is complete (internal VREF reaches
its target value), GO_BIT auto-resets to 0. This prevents a false operation of VREF scaling.
Write the reference voltage (0x00 and 0x01 registers) first, and then write GO_BIT = 1. VREF changes
based on the new register setting. GO_BIT resets to 0 when VREF reaches a new value. The host can
read GO_BIT to determine whether VREF scaling has completed.
The VOUT-to-ground discharge function is enabled when GO_BIT = 1. This can ramp VOUT from high to
low under light-load conditions.
When GO_BIT = 0, VREF does not change. When GO_BIT = 1, VREF changes based on the VREF register
setting. After VREF scaling finishes, GO_BIT is automatically reset to 0.
PG_DELAY_EN D[1]
When PG_DELAY_EN D[1] = 0, there is no delay on PG. When PG_DELAY_EN D[1] = 1, PG
experiences a 100µs rising delay. The default value is 0.
IOUT_LIM Register
Sets the output current limit threshold.
Name IOUT_LIM
Format Direct, unsigned binary integer
Bit 7 6 5 4 3 2 1 0
Access N/A R/W R/W R/W R/W R/W R/W R/W
Default Value
N/A 70 integer
(3.5A)

IOUT_OC can be calculated with Equation (2):

IOUT_OC (A) = IOUT_LIM x 0.05 (2)
Where IOUT_LIM is a 7-bit unsigned binary integer of IOUT_LIM D[6:0], and the IOUT_OC resolution is
50mA/LSB (maximum value is 6.35A).
The resistor connected from the OC pin to ground should be 21.5kΩ when using the IOUT_LIM register.
Add a 22nF (C6) filter capacitor on OC to keep the CC loop stable. The MP28167-A allows IOUT_LIM to
be directly changed using the I2C. If the CC threshold must be changed after the MP28167-A has already
entered the CC limit operation state, it is recommended to change the CC threshold step by step (e.g.
50mA per step) instead of changing the current value to the final value.
CTL1 Register
Bits Bit Name Default Description
I2C-controlled bit to turn the part on and off. When the external EN pin is low, the
converter is off, and the I2C shuts down. When EN is high, the EN bit takes over.
D[7] EN 1
1: Enable the part
0: Disable the part
Over-current (OC) and over-voltage protection (OVP) mode selection.
HICCUP
D[6] 1 1: Hiccup mode
OCP_OVP
0: Latch-off mode
Output discharge enable bit.
D[5] DISCHG_EN 1 1: Output discharge occurs during EN or VIN shutdown
0: No output discharge occurs during shutdown
Enable PFM/PWM mode bit. The default is PWM mode under light-load conditions.
D[4] MODE 1 0: Enables auto-PFM/PWM mode
1: Sets forced PWM mode
Sets the switching frequency.
00: 500kHz
D[3:2] FREQ 00 01: 750kHz
10: Reserved
11: Reserved
CTL2 Register
Bits Bit Name Default Description
Sets the output voltage compensation (VLINE vs. the load feature).
00: No compensation
01: VOUT compensates 60mV when IOUT = 3A
LINE DROP 10: VOUT compensates 120mV when IOUT = 3A
D[7:6] 00 11: VOUT compensates 200mV when IOUT = 3A
COMP
VOUT compensation is based on R1 and R2. VLINE = (1 + R1 / R2) x VREFLINE. Where
VREFLINE is 0mV/12mV/24mV/40mV when the D[7:6] bits are 00/01/10/11,
respectively. VLINE is the compensated voltage.
Sets the output start-up soft-start timer (from 0% to 100%). If the reference voltage
is 1V:
00: 1.1ms
01: 2.2ms
D[5:4] SS 10
10: 3.5ms
11: 4.4ms
The SS slew rate is constant, but SS time changes with different VREF values. For
example, the SS time = 3.5ms for 1V VREF, and the SS time = 5.25ms for 1.5V VREF.

Status Register
Bit Bit Name Default Description Notes
Output power good indication.
D[7] PG N/A 0: Output power is not good
1: Output power is good
Over temperature protection (OTP) indication.
D[6] OTP N/A 0: OTP has not occurred
These status
1: OTP has occurred
bits indicate
Over-temperature warning (OTW) indication. instantaneous
D[5] OTW N/A 0: OTW has not occurred values.
1: OTW has occurred
Enable bit for constant-current (CC) output mode or constant-voltage
(CV) output mode.
D[4] CC_CV N/A
0: CV mode
1: CC mode
Interrupt Register
Bits Bit Name Description Notes
Over-temperature protection entry indication. When this bit is high, the IC
OTEMPP_
D[7] enters thermal shutdown. This bit is not masked, even if OTPMSK = 1.
ENTER
Setting OTPMSK to 1 only masks the interrupt pin’s output (ALT).
OTWARNING_ Die temperature early warning enter bit. When this bit is high, the die
D[6] temperature exceeds 120°C. This bit is not masked, even if OTWMSK = 1.
ENTER Setting OTWMSK to 1 only masks the interrupt pin’s output (ALT).
Entry of over-current (OC) or constant-current (CC) current-limit mode. THE This bit is
D[5] OC_ENTER OC_MSK bit can enable or disable the OC_ENTER and OC_RECOVER latched once
ALERT outputs. triggered.
Recovery from constant-current (CC) current-limit mode. If the device Write 0xFF to
D[4] OC_RECOVER this register to
recovers from a hiccup, it does not trigger this interrupt signal.
reset the
D[3] UVP_FALLING Reference voltage is in under-voltage protection (UVP) threshold. interrupt and
ALT pin’s state.
Over-temperature protection (OTP) ends. OTPMSK can mask off the ALT
D[2] OTEMPP_EXIT
signals of this bit.
Die temperature early warning exit bit. When the die temperature is below
OTWARNING_
D[1] 100°C, this bit is set to 1. This bit is not masked, even if OTWMSK = 1.
EXIT
Setting OTWMSK to 1 only masks the interrupt pin’s output (ALT).
D[0] PG_RISING Output power good rising edge.

MSK Register
Bit Bit Name Default Description
Set OTPMSK to 1 to mask off the over-temperature protection (OTP) alert. Setting
D[4] OTPMSK 0 OTPMSK to 1 only masks the interrupt pin’s output (ALT). This is not the interrupt
register, but it is similar for other mask bits.
D[3] OTWMSK 0 Masks off the over-temperature warning.
D[2] OC_MSK 0 Masks off both over-current (OC) and constant current (CC) entry and recovery.
D[1] UVP_MSK 0 Masks off the output under-voltage protection (UVP) interrupt.
Masks off the PG indication function on ALT.
D[0] PG_MSK 0 1: The ALT pin does not indicate a PG event
0: The ALT indicates a PG rising event
OTEMPP_ENTER,
OTWARNING_ENTER,
or OC_ENTER
Event
ALT Pin
Active
Low
Write 0xFF to 0A Reg to OTEMPP_EXIT,

ALT pin OTWARNING_EXIT,
or OC_RECOVER
Event
Figure 14: ALT Behavior of OTP, OT Warning, and OC Recovery

APPLICATION INFORMATION
Setting the Output Voltage The target inductance for boost mode can be
The external resistor divider sets the output estimated with Equation (3):
voltage. R1 can be calculated with Equation (1): VIN  ( VOUT  VIN )
L BOOST  (3)
V  VREF VOUT  f SW  IL
R1  OUT  R2 (1)
VREF Choosing a larger-value inductor reduces the
ripple current but increases the physical size of
Figure 11 shows the feedback circuit.
the inductor. A larger-value inductor also
VOUT reduces the converter’s bandwidth by moving
the right half-plane zero to lower frequencies.
MP28167-A This tradeoff should be determined based on the
R1 application requirements.
RT
FB In addition to the inductance value, the inductor
R2 must support the peak current to avoid saturation.
The peak current can be calculated with
Equation (4) and Equation (5) for buck and boost
Figure 15: Feedback Network mode, respectively:
Table 1 lists the recommended resistors and VOUT  (VIN(MAX)  VOUT )
inductor values for common output voltages. If IPEAK BUCK  IOUT  (4)
2  VIN(MAX)  fREQ  L
the I2C is not used to set the output voltage, it
can be set using the resistors below. VOUT  IOUT VIN(MIN)  (VOUT  VIN(MIN) )
IPEAK BOOST   (5)
Table 1: Resistor Selection for Common Output  VIN(MIN) 2  VOUT  fREQ  L
Voltages
VOUT (V) R1 (kΩ) R2 (kΩ) RT (kΩ) L (μH) Where η is the estimated efficiency of the
5 430 107 806 4.7 MP28167-A.
9 430 53.6 787 4.7 For most applications, a 4.7µH inductor is
12 430 39.2 787 4.7 recommended for 500kHz switching frequency
15 402 28.7 402 4.7 applications, and a 3.3µH inductor is
20 390 20.5 200 3.3 recommended for 750kHz switching frequency
applications.
Selecting the Inductor
The inductor selection is based on which mode MPS inductors are optimized and tested for use
the device operates in. The inductance for buck with our complete line of integrated circuits.
mode (LBUCK) can be estimated with Equation (2): Table 2 lists recommended power inductors.
VOUT V Table 2: Power Inductor Selection
L B UCK   (1  OUT ) (2)
f SW  IL VIN Part Number
Inductor
Manufacturer
Value
Where ∆IL is the peak-to-peak inductor ripple Select family 2.2µH to
current, and is 30% to 50% of the maximum load MPS
series (MPL-AL) 4.7µH
current.
MPL-AL6050-4R7 4.7μH MPS
In boost mode, the inductor selection is based on MPL-AL6050-3R3 3.3μH MPS
limiting the peak-to-peak current ripple (∆IL) MPL-AL5030-2R2 2.2μH MPS
between 30% and 50% of the maximum input
current. Visit MonolithicPower.com for more information.

Input and Output Capacitor Selection

It is recommended to use ceramic capacitors
with an electrolytic capacitor at the input to filter
the input ripple current and achieve stable
operation.
Since the input capacitor absorbs the input
switching current, it requires sufficient
capacitance. For most applications, a 100µF
electrolytic capacitor and a 22µF ceramic
capacitor are sufficient.
The output capacitor stabilizes the DC output
voltage. A sufficient capacitor value is
recommended to limit the output voltage ripple.
The minimum ceramic COUT should be 22µF x 5.
The input and output ceramic capacitors must be
placed as close as possible to the device.
PCB Layout Guidelines (11) Top Layer
Efficient PCB layout is critical for stable
operation and thermal dissipation. For the best
results, refer to Figure 16 and follow the
guidelines below:
1. Place the ceramic CIN and COUT capacitors
close to the IC’s VIN-to-GND and OUT-to-
GND pins, respectively.
2. Use a large copper plane for PGND.
3. Add multiple vias to improve thermal
dissipation.
4. Connect AGND to PGND.
5. Use short, direct, and wide traces to connect
OUT.
6. Add vias under the IC and route the OUT
trace on both PCB layers (highly
recommended). Close-Up of Layout
Figure 16: Recommended PCB Layout
7. Use a large copper plane for SW1 and SW2.
8. Place the VCC decoupling capacitor as close
to VCC as possible.
9. The FB trace requires special consideration.
Use a GND copper to cover this trace, and
route other signal traces far from FB, such as
SWx/BSTx.
Note:
11) The recommended layout is based on the Typical Application
Circuit (see Figure 17).

TYPICAL APPLICATION CIRCUITS

R6, 0Ω C4, 100nF
16
L1 4.7µH
15
VIN = 2.8V to 22V BST1 SW1
1
IN R7, 0Ω C5 100nF
13
+ BST2
C1 C1B C1A
0.1µF 14
100µF 22µF SW2
12 VOU T = 5V
R3
OUT
499kΩ 3
EN C2A C2B C2C C2D C2E C2F
VCC C7
22nF
MP28167-A R1
0.1µF 22µF 22µF 22µF 22µF 22µF
R4
RT 430kΩ
10kΩ
4 8 806kΩ
ALT FB
2
5 I C Slave
SCL R2
6 SDA 107kΩ
9 VCC AGND GND OC

C3
10 2, 11 7
1µF
R5 C6
21.5kΩ 22nF
Figure 17: Typical Application Circuit for 5V VOUT

MP28167-A-22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
PACKAGE INFORMATION
QFN-16 (3mmx3mm)

MP28167-A-22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
CARRIER INFORMATION
Pin1 1 1 1 1
ABCD ABCD ABCD ABCD
Feed Direction
Package Quantity/ Quantity/ Quantity/ Reel Carrier Carrier

Part Number
Description Reel Tube Tray Diameter Tape Width Tape Pitch
QFN-16
MP28167GQ-A–Z 5000 N/A N/A 13in 12mm 8mm
(3mmx3mm)
Notice: The information in this document is subject to change without notice. Users should warrant and guarantee that third-
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume
any legal responsibility for any said applications.
MP28167-A Rev 1.0 www.MonolithicPower.com 32

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MP28167-A

2.8V to 22V VIN, 3A IOUT, 4-Switch,

MP28167-A Rev. 1.0 www.MonolithicPower.com 1

MP28167-A Rev. 1.0 www.MonolithicPower.com 2

BKN: Product code of MP28167GQ-A

EVALUATION KIT EVKT-MP28167-A

Order directly from MonolithicPower.com or our distributors.

Figure 1: EVKT-MP28167-A Evaluation Kit Set-Up

MP28167-A Rev. 1.0 www.MonolithicPower.com 3

MP28167-A Rev. 1.0 www.MonolithicPower.com 4

MP28167-A Rev. 1.0 www.MonolithicPower.com 5

ABSOLUTE MAXIMUM RATINGS (2) Thermal Resistance θJA θJC

MP28167-A Rev. 1.0 www.MonolithicPower.com 6

MP28167-A Rev. 1.0 www.MonolithicPower.com 7

ELECTRICAL CHARACTERISTICS (continued)

MP28167-A Rev. 1.0 www.MonolithicPower.com 8

LINE REGULATION (%)

LINE REGULATION (%)

THERMAL RISE (℃）

MP28167-A Rev. 1.0 www.MonolithicPower.com 9

TYPICAL CHARACTERISTICS (continued)

Recommended VIN, VOUT, IOUT

MP28167-A Rev. 1.0 www.MonolithicPower.com 10

TYPICAL CHARACTERISTICS (continued)

OUTPUT VOLTAGE UVP

MP28167-A Rev. 1.0 www.MonolithicPower.com 11

TYPICAL PERFORMANCE CHARACTERISTICS

CH1: VOUT CH1: VOUT

EN Bit Shutdown through I2C EN Bit Shutdown through I2C

CH1: VOUT CH1: VOUT

EN Pin Enabled EN Pin Enabled

CH1: VOUT CH1: VOUT

MP28167-A Rev. 1.0 www.MonolithicPower.com 12

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

CH1: VOUT CH1: VOUT

VIN Start-Up VIN Start-Up

CH1: VOUT CH1: VOUT

VIN Shutdown VIN Shutdown

CH1: VOUT CH1: VOUT

MP28167-A Rev. 1.0 www.MonolithicPower.com 13

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

CH1: VOUT CH1: VOUT

Steady State Steady State

I2C VID I2C VID

CH1: VOUT CH1: VOUT

MP28167-A Rev. 1.0 www.MonolithicPower.com 14

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

CH1: VOUT CH1: VOUT

Load Transient Load Transient

CH4: IOUT CH4: IOUT

Short-Circuit Protection Entry with Short-Circuit Protection Entry with

CH1: VOUT CH1: VOUT

MP28167-A Rev. 1.0 www.MonolithicPower.com 15

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

CH1: VOUT CH1: VOUT

CC Current Limit Steady State VOUT OVP with Hiccup Mode

VOUT OVP with Latch-Off Mode

MP28167-A Rev. 1.0 www.MonolithicPower.com 16