Rockchip RK3399-T Datasheet V1.0-20210818
Rockchip RK3399-T Datasheet V1.0-20210818
Rockchip RK3399-T Datasheet V1.0-20210818
Rockchip
RK3399-T
Datasheet
Revision 1.0
Aug. 2021
Revision History
Date Revision Description
2021-8-24 1.0 Initial Release
Table of Content
Table of Content .................................................................................................. 3
Figure Index ....................................................................................................... 5
Table Index 6
Chapter 1 Introduction ....................................................................................... 8
1.1 Overview ................................................................................................ 8
Figure Index
Fig. 1-1 Block Diagram .................................................................................... 25
Fig. 2-1 Top Marking ....................................................................................... 26
Fig. 2-2 Package Top and SideView ................................................................... 26
Fig. 2-3 Package Bottom View .......................................................................... 27
Fig. 2-4 Package Dimension ............................................................................. 27
Fig. 2-5 Ball Mapping Diagram .......................................................................... 28
Table Index
Table 2-1Ball Pin Number Order Information ........................................................... 35
Table 2-2 Power/Ground IO information ................................................................. 45
Table 2-3 Function IO description .......................................................................... 50
Table 2-4eMMC pin description ............................................................................. 55
Table 2-6USB2 pin description .............................................................................. 55
Table 2-7eDP pin description ................................................................................ 56
Table 2-8HDMI pin description .............................................................................. 56
Table 2-9MIPI pin description ............................................................................... 56
Table 2-10ISP pin description ............................................................................... 57
Table 2-11EFUSE pin description ........................................................................... 57
Table 2-12SAR-ADC pin description ....................................................................... 57
Table 2-13TSADC pin description .......................................................................... 57
Table 2-14GMAC pin description ............................................................................ 58
Table 2-15UART pin description ............................................................................ 58
Table 2-16I2C pin description ............................................................................... 58
Table 2-17PWM pin description ............................................................................. 58
Table 2-18CIF pin description ............................................................................... 59
Table 2-19SPI pin description ............................................................................... 59
Table 2-20SPDIF pin description............................................................................ 59
Table 2-21I2S pin description ............................................................................... 59
Table 2-22DDRC pin description ............................................................................ 60
Table 2-23SDIO pin description............................................................................. 60
Table 2-24SDMMC pin description ......................................................................... 61
Table 2-25JTAG pin description ............................................................................. 61
Table 2-26MISC pin description ............................................................................. 61
Table 3-1 Absolute maximum ratings ..................................................................... 62
Table 3-2 Recommended operating conditions ......................................................... 62
Table 3-3DC Characteristics.................................................................................. 64
Table 3-4Electrical Characteristics for Digital General IO ........................................... 65
Table 3-5Electrical Characteristics for PLL ............................................................... 66
Table 3-6 Electrical Characteristics for SAR-ADC ...................................................... 66
Table 3-7 Electrical Characteristics for TSADC ......................................................... 66
Table 3-8 Electrical Characteristics for Type-C PHY ................................................... 67
Table 3-9 Electrical Characteristics for USB2.0 PHY .................................................. 67
Table 3-10 Electrical Characteristics for DDR IO ...................................................... 68
Table 3-11 Electrical Characteristics for eFuse ......................................................... 68
Table 3-12 Electrical Characteristics for HDMI ......................................................... 68
Table 3-13 Electrical Characteristics for MIPI PHY .................................................... 69
Table 3-14 Electrical Characteristics for eMMC PHY .................................................. 69
Table 4-1Thermal Resistance Characteristics ........................................................... 70
NOTICE
1. By using this document, you hereby unequivocally acknowledge that you have read and
agreed to be bound by the contents of this notice.
2. Rockchip Electronics Co., Ltd. (“Rockchip”) may make changes to any information in this
document at any time without any prior notice. The information herein is subject to change
without notice. Do not finalize a design with this information.
3. Information in this document is provided in connection with Rockchip products.
4. THIS DOCUMENT IS PROVIDED “AS IS” WITHOUT ANY WARRANTY OR CONDITION OF ANY
KIND, EITHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, ANY
WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY, FITNESS FOR ANY
PARTICULAR PURPOSE, OR NON-INFRINGEMENT.ROCKCHIP DOES NOT ASSUME ANY
RESPONSIBILITY AND LIABILITY FOR ITS USE NOR FOR ANY INFRINGEMENT OF PATENTS OR
OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM ITS USE.
5. Rockchip products described in this document are not designed, intended for use in medical,
lifesaving, life sustaining, critical control or safety systems, or in nuclear facility application.
6. Rockchip and Rockchip logo are trademarks or registered trademarks of Rockchip in China
and other countries. All referenced brands, product names, service names and trademarks in this
document are the property by their respective owners.
Chapter 1 Introduction
1.1 Overview
RK3399-T is a low power, high performance processor for computing, personal mobile
internet devices and other smart device applications. Based on Big.Little architecture, it
integrates dual-coreCortex-A72and quad-core Cortex-A53 with separate NEON coprocessor.
Many embedded powerful hardware engines provide optimized performance for high-end
application. RK3399-T supports multi-format video decoders including H.264/H.265/VP9up
to4Kx2K@60fps, especially, H.264/H.265 decoders support 10bits coding, and also
supports H.264/MVC/VP8 encoders by 1080p@30fps, high-quality JPEG encoder/decoder,
and special image preprocessor and postprocessor.
Embedded 3D GPU makes RK3399-T completely compatible with OpenGL
ES1.1/2.0/3.0/3.1/3.2, OpenCL 1.2 and DirectX 11.1. Special 2D hardware engine with
MMU will maximize display performance and provide very smooth operation.
RK3399-T has high-performance dual channel external memory interface
(DDR3/DDR3L/LPDDR3/LPDDR4) capable of sustaining demanding memory bandwidths,
also provides a complete set of peripheral interface to support very flexible applications.
1.2 Features
The features listed below which may or may not be present in actual product, may
be subject to the third party licensing requirements. Please contact Rockchip for
actual product feature configurations and licensing requirements.
1.2.1 Microprocessor
Dual-core ARM Cortex-A72 MPCore processor and Quad-core ARM Cortex-A53MPCore
processor, both are high-performance, low-power and cached application processor
Two CPU clusters big cluster with dual-coreCortex-A72 is optimized for high-
performance and little cluster with quad-core Cortex-A53 is optimized for low power.
Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced
SIMD (single instruction, multiple data) support for accelerating media and signal
processing
ARMv8 Cryptography Extensions
SCU ensures memory coherency between the MPCore for each cluster
CCI500 ensures the memory coherency between the two clusters
Each Cortex-A72 integrates48KB L1 instruction cache and 32KB L1 data cache with 4-
way set associative. Each Cortex A53 integrates 32KB L1 instruction cache and 32kB L1
data cache separately with 4-way set associative
1MB unified L2 Cache for Big cluster, 512KB unified L2 Cache for Little cluster
Trust zone technology support
Full Core sight debug solution
Debug and trace visibility of whole systems
ETM trace support
Invasive and non-invasive debug
Eight separate power domains for CPU core system to support internal power switch
and externally turn on/off based on different application scenario
PD_A72_B0: 1st Cortex-A72 + Neon + FPU + L1 I/D cache of big cluster
PD_A72_B1: 2nd Cortex-A72+ Neon + FPU + L1 I/D cache of big cluster
PD_SCU_B: SCU + L2 Cache controller, and including PD_A72_B0, PD_A72_B1,
debug logic of big cluster
PD_A53_L0: 1st Cortex-A53 + Neon + FPU + L1 I/D Cache of little cluster
PD_A53_L1: 2nd Cortex-A53 + Neon + FPU + L1 I/D Cache of little cluster
PD_A53_L2: 3rd Cortex-A53 + Neon + FPU + L1 I/D Cache of little cluster
eMMC Interface
Fully compliant with JEDEC eMMC 5.1and eMMC 5.0 specification
There is only one eMMC interface
It is backward compliant with eMMC 4.51 and earlier versions specification.
SD/MMC Interface
Compatible with SD3.0, MMC ver4.51
There are 2 MMC interfaces which can be configured as SD/MMC or SDIO
Support FIFO over-run and under-run prevention by stopping card clock
automatically
Support CRC generation and error detection
Embedded clock frequency division control to provide programmable baud rate
Support block size from 1 to 65535Bytes
Data bus width is 4bits
Timer
14 on-chip 64bits Timers in SoC with interrupt-based operation for non-secure
application
12 on-chip 64bits Timers in SoC with interrupt-based operation for secure
application
Provide two operation modes: free-running and user-defined count
Support timer work state checkable
Fixed 24MHz clock input
PWM
Four on-chip PWMs with interrupt-based operation
Programmable pre-scaled operation to bus clock and then further scaled
Watchdog
Three Watchdogs in SoC with 32 bits counter width
Counter clock is from APB bus clock
Counter counts down from a preset value to 0 to indicate the occurrence of a
timeout
WDT can perform two types of operations when timeout occurs:
Generate a system reset
First generate an interrupt and if this is not cleared by the service routine by
the time a second timeout occurs then generate a system reset
Programmable reset pulse length
Totally 16 defined-ranges of main timeout period
Mailbox
Two Mailboxes in SoC to service multi-core communication
Support four mailbox elements per mailbox, each element includes one data word,
one command word register and one flag bit that can represent one interrupt
Provide 32 lock registers for software to use to indicate whether mailbox is occupied
Bus Architecture
128bit/64-bit/32-bit multi-layer AXI/AHB/APB composite bus architecture
CCI500 embedded to support two clusters cache coherency
5 embedded AXI interconnect
PERI low performance interconnect with one 128-bits AXI master, seven 64-bits
AXI masters, one 32-bits AXI master, two 64-bits AXI slaves, five 32-bits AHB
masters and lots of 32-bits AHB/APB slaves
PERI high performance interconnect with one 128-bits AXI master, one 128-bits
AXI slave, four 32-bits AHB masters and lots of 32-bits AHB/APB slaves
DISPLAY interconnect with two 128-bits AXI masters, two 64-bits AXI masters,
one 32-bits AXI master and lots of 32-bits AHB/APB slaves
GPU interconnect with one 128-bits AXI master and 32-bits APB slave
VIDEO interconnect with two 128-bits AXI masters, two 64-bits AXI masters
and four 32-bits AHB slaves
Flexible different QoS solution to improve the utility of bus bandwidth
Interrupt Controller
Support 8 PPI interrupt source and 148 SPI interrupt sources input from different
components inside RK3399-T
Support 16 software-triggered interrupts
Input interrupt level is fixed, high-level sensitive for SPI and low-level sensitive for
PPI
Support Locality-specific Peripheral Interrupts (LPIs). These interrupts are
generated by a peripheral writing to a memory-mapped register in the controller
Two AXI stream interrupt interfaces separately for each cluster
Support different interrupt priority for each interrupt source, and they are always
software-programmable
DMAC
Micro-code programming based DMA
The specific instruction set provides flexibility for programming DMA transfers
Linked list DMA function is supported to complete scatter-gather transfer
Support internal instruction cache
Embedded DMA manager thread
Security system
Support Trustzone technology for the following components inside RK3399-T
Cortex-A72, support security and non-security mode, switch by software
Cortex-A53, support security and non-security mode, switch by software
Except Cortex-A72 and Cortex-A53, the other masters in the SoC can also
support security and non-security mode by software-programmable
Some slave components in SoC can only be addressed by security master and
the other slave components can be addressed by security master or non-
security master by software-programmable
Internal memory, part of space is addressed only in security mode, detailed
size is software-programmable together with TZMA(Trustzone memory adapter)
External DDR space can be divided into eight parts; each part can be software-
programmable to be addressed in security mode or non-security mode
Video Encoder
Support video encoder for H.264 UP to [email protected], MVC and VP8
MMU Embedded
Only support I and P slices, not B slices
Support error resilience based on constrained intra prediction and slices
Input data format:
YCbCr 4:2:0 planar
YCbCr 4:2:0 semi-planar
YCbYCr 4:2:2
CbYCrY 4:2:2 interleaved
RGB444 and BGR444
RGB555 and BGR555
RGB565 and BGR565
RGB888 and BRG888
RGB101010 and BRG101010
Image size is from 96x96 to 1920x1080(Full HD)
Maximum frame rate is up to 1920x1080@30FPS
②
JPEG encoder
Input raw image:
YCbCr 4:2:0 planar
YCbCr 4:2:0 semi-planar
YCbYCr 4:2:2
CbYCrY 4:2:2 interleaved
RGB444 and BGR444
RGB555 and BGR555
RGB565 and BGR565
RGB888 and BRG888
2D Graphics Engine:
Source format:
ARGB/RGB888/RGB565/RGB4444/RGB5551/YUV420/YUV422(SupportYUV422S
P10bit/YUV420SP10bit)
Destination formats:
ARGB/RGB888/RGB565/RGB4444/RGB5551/YUV420/YUV422(Support
YVYU422/420 output)
Max resolution: 8192x8192 source, 4096x4096 destination
Block transfer and Transparency mode
Color fill with gradient fill, and pattern fill
Alpha blending modes including global alpha, per pixel alpha (color/alpha channel
separately) and fading
Arbitrary non-integer scaling ratio, from 1/16 to 16
0, 90, 180, 270-degree rotation, x-mirror, y-mirror & rotation operation
ROP2, ROP3, ROP4
Support 4k/64k page size MMU
Display Interface
Embedded two VOP, output from the following display interface.
One or Two MIPI-DSI port
One eDP port
One DP port
One HDMI port
Support AFBC function co-operation with GPU
decompress FB generated by GPU FBC
support 2560x1600 UI
support ARGB888, RGB888, RGB565
output for one layer among WIN0/1/2/3
only support one IFDBC block which can be used for WIN0/1/2/3 by
configuration
1.2.11 HDMI
Single Physical Layer PHY with support for HDMI 1.4 and 2.0 operation
For HDMI operation, support for the following:
HPD input analog comparator
13.5–600MHz input reference clock
Up to 10-bit Deep Color modes
Up to 18Gbps aggregate bandwidth
Up to 1080p at 120Hz and 4kx2k at 60Hz HDTV display resolutions and up to QXGA
graphic display resolutions
3-D video formats
Link controller flexible interface with 30-, 60- or 120-bit SDR data access
Support HDCP 1.4/2.2
1.2.14 DisplayPort
Compliant with DisplayPort Specification, version 1.2
Compliant with HDCP2.2 (and back compatible with HDCP1.3)
There is only one DisplayPort controller built-in RK3399-T which is shared by 2 Type-C
interface
25-600Mhz pixel clock
Supports 8/10 bpp RGB, YCbCr422, YCbCr420formats
Supports up to 4kx2k at 60Hz resolution
Variety of audio formats–PCM and compressed, over I2S or SPDIF interfaces
1Mbps AUX channel
lanes and two PMA half-duplex TX/RX lanes (can be configured as TX-only or RX-only)
Up to 5Gbps data rate for USB3.0
Up to 5.4Gbps(HBR2) data rate for DP1.2, can support 1/2/4 lane mode
Support DisplayPort AUX channel
SPDIF
Support two 16-bit audio data store together in one 32-bit wide location
Support biphase format stereo audio data output
Support 16 to 31-bit audio data left or right justified in 32-bit wide sample data
buffer
Support 16, 20, 24 bits audio data transfer in linear PCM mode
Support non-linear PCM transfer
1.2.17 Connectivity
SDIO interface
Compatible with SDIO 3.0 protocol
4bits data bus width
There are 2 total MMC interfaces which may be configured as SD/MMC or SDIO
underrun conditions
SPI Controller
6 on-chip SPI controllers are inside
Support serial-master and serial-slave mode, software-configurable
DMA-based or interrupt-based operation
Embedded two 32x16bits FIFO for TX and RX operation respectively
UART Controller
5 on-chip UART controllers inside RK3399-T
DMA-based or interrupt-based operation
Embedded two 64Bytes FIFO for TX and RX operation respectively
Support 5bit,6bit,7bit,8bit serial data transmit or receive
Standard asynchronous communication bits such as start,stop and parity
Support different input clock for UART operation to get up to 4Mbps or other special
baud rate
Support non-integer clock divides for baud clock generation
Support auto flow control mode for UART0 and UART3
I2C controller
9 on-chip I2C controllers
Multi-master I2C operation
Support 7bits and 10bits address mode
Serial 8bits oriented and bidirectional data transfers can be made
Software programmable clock frequency
Data on the I2C-bus can be transferred at rates of up to 100 kbit/s in the Standard-
mode, up to 400 kbit/s in the Fast-mode or up to 1 Mbit/s in Fast-mode Plus.
GPIO
5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs
All of GPIOs can be used to generate interrupt to CPU
GPIO0 and GPIO1 can be used to wakeup system from low-power mode
The pull direction (pull-up or pull-down) for all of GPIOs are software-
programmable
All of GPIOs are always in input direction in default after power-on-reset
The drive strength for all of GPIOs is software-programmable
USB OTG3.0
Embedded 2 USB OTG3.0 interfaces
Compatible Specification
Universal Serial Bus 3.0 Specification, Revision 1.0
Universal Serial Bus Specification, Revision 2.0
eXtensible Host Controller Interface for Universal Serial Bus (xHCI), Revision
1.1
Support Control/Bulk (including stream)/Interrupt/Isochronous Transfer
Simultaneous IN and OUT transfer for USB3.0, up to 8Gbps bandwidth
Descriptor Caching and Data Pre-fetching
USB3.0 Device Features
Up to 7 IN endpoints, including control endpoint 0
Up to 6 OUT endpoints, including control endpoint 0
Up to 13 endpoint transfer resources, each one for each endpoint
Flexible endpoint configuration for multiple applications/USB set-configuration
modes
Hardware handles ERDY and burst
Stream-based bulk endpoints with controller automatically initiating data
movement
Isochronous endpoints with isochronous data in data buffers
1.2.18 Others
Temperature Sensor(TS-ADC)
Embedded 2 channel TS-ADC in RK3399-T
TS-ADC clock must be less than 800KHZ
10-bits TS-ADC up to 50KS/s sampling rate
-40~125C temperature range and 5℃ temperature resolution
eFuse
Two 1024bits(32x32) high-density electrical Fuse are integrated in RK3399-T
Support standby mode and power down mode
Embedded power-switch
Embedded four redundancy bits
Package Type
FCBGA828(body: 21mmx21mm; ball size: 0.35mm; ball pitch: 0.65mm)
① :
Notes : DDR3/DDR3L/LPDDR3/LPDDR4could not be used simultaneously
②:
Actual maximum frame rate will depend on the clock frequency and system bus performance
③:
Actual maximum data rate will depend on the clock frequency and JPEG compression rate
System Peripheral
Clock & Reset
RK3399-T Connectivity
USB OTG0 3.0/2.0
PMU Cortex-A72 Dual-Core Cortex-A53 Quad-Core
(48K/32K L1 I/D Cache)
USB OTG1 3.0/2.0
(32K/32K L1 I/D Cache)
PLL x 8
Type-C x 2
System register 1MB L2 Cache 512KB L2 Cache
Dual Display Controller Hardware-based DDR frequency scaling Non secure eFuse
2.3 Dimension
Fig.2-4Package Dimension
Notes :
1) Controlling dimension: millimeter
2) Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
3) Dimension b is measured at the maximum solder ball diameter, parallel to primary datum C.
4) Special characteristics C class: A, ddd
5) The pattern of pin 1 fiducial is for reference only.
6) The tilt of heat sink should be within 10mil(0.254mm) (vertical position)
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
DDR0_CLK0 DDR0_CLK1
J DDR0_A6 DDR0_A7 VSS_68 VSS_69 VSS_70 VSS_71
N N
DDR0_DQ DDR0_DQ2
N NP NP NP NP NP VSS_105
26 8
1 2 3 4 5 6 7 8
DDR0_D DDR0_D
T NP NP NP NP NP VSS_134
Q20 Q21
DDR0_D DDR0_D
W NP NP NP NP NP VSS_161
Q6 Q7
GPIO4_C7/HDMI GPIO2_C4/S
A DDR0_DQ DDR0_DQ GPIO4_A6/I2
DDR0_DQ11 VSS_17 VSS_18 _CECINOUT/EDP DIO0_D0/SP
D 13 S1N S1_SDI0
_HOTPLUG I5_RXD
GPIO2_C7/S
A DDR0_DQ GPIO3_D4/I2S0
DDR0_DQ9 NP NP GPIO4_D0 NP DIO0_D3/SP
E 12 _SDI1SDO3
I5_CSN0
GPIO3_D GPIO3_D6/I
A GPIO4_ GPIO2_D0/S GPIO2_C1/U
7/I2S0_S 2S0_SDI3SD NP GPIO4_D4 NP
H D2 DIO0_CMD ART0_TX
DO0 O1
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
DDR1_CL DDR1_DQS
D NP DDR1_ODT0 DDR1_BA2 NP DDR1_DQS1N NP
K0P 1P
DDR1_CL
E NP DDR1_ODT1 VSS_42 NP DDR1_DM1 VSS_43 NP
K1P
DDR1_CA DDR1_PLL_TESTOU
F NP DDR1_CSN2 DDR1_CSN0 NP VSS_49 NP
SN T_P
0 9 10 11 12 13 14 15 16
DDR1PLL_AVD
H VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64
D_0V9
DDR1_V
J VSS_72 VSS_73 DDR1_VDD_1 DDR1_VDD_2 DDR1_VDD_3 DDR1_VDD_4 DDR1_VDD_5
DD_6
DDR1_VDD_1
K VSS_75 VSS_76 DDR1_VDD_9 VSS_77 VSS_78 DDR1_VDD_11 VSS_79
0
DDR0_V DDR0_V
L VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93
DD_1 DD_2
0 9 10 11 12 13 14 15 16
DDR0_VD GPU_VD
U DDR0_VDD_11 VSS_126 VSS_127 VSS_137 VSS_143 VSS_144
D_10 D_7
GPU_VD GPU_VDD
W VSS_162 GPU_VDD_20 GPU_VDD_2 VSS_128 GPU_VDD_3 GPU_VDD_18
D_1 _19
A HDMI_AVDD
VSS_6 VSS_179 AVSS_13 AVSS_17 VSS_177 AVSS_26 AVSS_53
A _0V9_1
A MIPI_TX0_AV MIPI_RX0_AV
VSS_9 AVSS_12 AVSS_8 AVSS_9 AVSS_42 AVSS_41
B DD_1V8 DD_1V8
A APIO4_V MIPI_TX1/RX1_A
AVSS_44 NC_7 AVSS_45 NC_4 AVSS_10 AVSS_18
C DD VDD_1V8
A GPIO2_D3/SDIO0 HDMI_AVD
VSS_19 NC_2 NC_3 AVSS_11 NC_5 NC_6
D _PWREN D_1V8
A GPIO2_C0/UART0 HDMI_HP
NP AVSS_21 AVSS_22 NP AVSS_23 NP
E _RX D
A
AVSS_33 NP AVSS_34 AVSS_35 NP AVSS_36 AVSS_37 NP
J
9 10 11 12 13 14 15 16
0 17 18 19 20 21 22 23 24
DDR1_D DDR1_D
E VSS_44 NP VSS_45 NP DDR1_DM3 VSS_46
M0 M2
828 17 18 19 20 21 22 23 24
BIGCPU_
BIGCPU_VD BIGCPU_VDD_ PMUIO2_VDDP GPIO0_A2/WIFI_2
N VSS_94 VDD_CO VSS_83 VSS_98
D_10 9 ST 6MHZ
M
GPIO0_B5/TCPD_
PLL_AVD LITCPU_VD
P PLL_AVSS VSS_119 VSS_121 LITCPU_VDD_4 PMUIO2_VDD VBUS_FDIS/TCPD
D_1V8 D_1
_VBUS_SOURCE3
0 17 18 19 20 21 22 23 24
LOGIC_V USB_AVD
V VSS_148 LOGIC_VDD_5 LOGIC_VDD_4 LOGIC_VDD_2 LOGIC_VDD_1 AVSS_50
DD_3 D_0V9
LOGIC_V
W VSS_159 VSS_169 VSS_167 VSS_81 VSS_158 AVSS_46 DNU
DD_6
A TYPEC1_U3VB ADC_AVD
AVSS_43 VSS_145 VSS_13 VSS_132 VSS_12 AVSS_19
C USDET D
A TYPEC1_CC
AVSS_27 VSS_7 NP VSS_10 NP AVSS_2 AVSS_3
F 2
A
AVSS_38 AVSS_39 NP VSS_180 VSS_172 NP VSS_173 VSS_174
J
17 18 19 20 21 22 23 24
25 26 27 28 29 30 31 0
GPIO3_B7/MAC_C
_CLKOUTB
GPIO3_B1/MAC_R
NP VSS_37 EDP_AVSS_2 EDP_AVSS_3 EDP_TX2P EDP_TX2N C
XDV
GPIO3_A4/M GPIO3_C0/MAC_C
I0_RXD SPDIF_TX
25 26 27 28 29 30 31 0
GPIO2_B3/S
GPIO2_B0/VOP GPIO2_A4/V GPIO2_A
GPIO2_A1/VOP_D1 GPIO2_A6/VO PI2_CLK/VOP
VSS_67 _CLK/CIF_VSY OP_D4/CIF_ 2/VOP_D H
/CIF_D1/I2C2_SCL P_D6/CIF_D6 _DEN/CIF_C
NC/I2C7_SCL D4 2/CIF_D2
LKOUTA
EMMC_D
EMMC_D3 EMMC_D4 EMMC_D5 EMMC_D0 EMMC_D1 EMMC_CMD J
2
EMMC_D
NP NP NP NP NP EMMC_STRB K
7
GPIO1_C GPIO1_C7/T
GPIO1_B6/PWM3B GPIO1_B7/SPI3_RX GPIO1_C1/SPI GPIO1_C3/PW GPIO1_C4/I
5/I2C8_S CPD_VBUS_ M
_IR D/I2C0_SDA 3_CLK M2 2C8_SDA
CL SOURCE1
GPIO1_C
0/SPI3_T GPIO1_C2/S
NP NP NP NP NP N
XD/I2C0 PI3_CSN0
_SCL
GPIO1_B2/S
GPIO1_A7/SPI GPIO1_B1/SPI GPIO1_B
GPIO0_A6/PWM3A GPIO1_A6/TSADC_ PI1_CSN0/P GPIO1_B3/I2
1_RXD/UART4 1_CLK/PMCU_J 4/I2C4_S P
_IR INT MCU_JTAG_ C4_SDA
_RX TAG_TCK CL
TMS
25 26 27 28 29 30 31 0
GPIO1_A1/ISP0_SH
UTTER_TRIG/ISP1_
NP NP NP NP NP NPOR T
SHUTTER_TRIG/TCP
D_CC0_VCONN_EN
GPIO4_B3/S GPIO0_B0/SDM
PMU_VDD_1 SDMMC0_VD GPIO0_A0/TEST_CL
DMMC0_D3/ MC0_WRPT/TES VSS_150 GPIO0_B3 U
V8 DPST KOUT0/CLK32K_IN
APJTAG_TMS T_CLKOUT2
GPIO4_B5/S GPIO4_B4/SD
GPIO0_B4/T GPIO0_B1/
DMMC0_CM GPIO0_A5/E GPIO0_A7/SDM MMC0_CLKOUT GPIO0_A3/SDIO0_
CPD_VBUS_ PMUIO2_V V
D/MCUJTAG MMC_PWRON MC0_DET /MUCJTAG_TC WRPT
BDIS OLSEL
_TMS K
NP NP NP NP NP VSS_160 GPIO0_B2 W
GPIO0_A4/S
AVSS_6 DNU DNU AVSS_7 USB1_DP USB1_DN AA
DIO0_INTN
NP NP NP NP NP USB0_DP USB0_DN AB
USB1_RBI
AVSS_51 AVSS_14 DNU DNU AVSS_15 USB0_RBIAS AC
AS
A
USIC_AVDD_0V9 AVSS_40 DNU DNU AVSS_20 DNU DNU
D
A
NP TYPEC1_ID AVSS_25 NP NP DNU DNU
E
TYPEC1_AUXM_PU A
NP DNU DNU AVSS_28 DNU DNU
_PD F
A
ADC_IN2 ADC_IN0 NP ADC_IN3 AVSS_29 DNU DNU
G
A
NP ADC_IN1 ADC_IN4 NP AVSS_30 DNU DNU
H
25 26 27 28 29 30 31
A1,A27,A31,AA3,AA5,AA9,AA10,AA13,AB9,AB19,AC3,AC18,AC2
0,AC21,AC22,AD3,AD5,AD10,AD21,AD22,AE23,AF9,AF18,AF20,
AG2,AJ5,AJ20,AJ21,AJ23,AJ24,AJ26,AJ27,AJ28,AL1,AL31,B5,C8
,C9,C11,C12,C14,C15,C17,C18,C20,C21,C23,C24,C26,D5,E2,E4
Internal Logic Ground
VSS ,E7,E12,E15,E18,E21,E24,E31,F8,F15,F18,F20,F21,G5,G9,G18,
and Digital IO Ground
G27,H3,H9,H10,H11,H12,H13,H15,H16,H17,H18,H26,J3,J6,J7,J
8,J9,J10,K8,K9,K10,K12,K14,K16,K18,K20,K22,L3,L6,L8,L11,L1
2,L13,L14,L15,L16,L20,L22,L27,M3,M8,M10,M16,M23,N8,N13,N
14,N15,N16,N17,N19,N21,P3,P6,P7,P8,P10,P11,P12,P16,P19,P2
1,R3,R5,R6,R14,R15,R16,R18,R21,R23,T8,T10,T16,T18,T19,T2
1,U3,U8,U11,U12,U14,U15,U16,U19,U21,U22,U29,V3,V5,V8,V1
0,V17,W8,W9,W13,W17,W18,W19,W21,W22,W30,Y3,Y9,Y10,Y1
1,Y12,Y13,Y14,Y15,Y16,Y17,Y20
K19,K21,L18,L19,L21,L23,M18,M19,M20,M21,M22,N18,N20,N2
BIGCPU_VDD Internal BIG CPU A72 Power
2
Internal LITTLE CPU A53
LITCPU_VDD P20,P22,R19,R20,R22,T20,T22
Power
R11,R12,R13,T11,T12,T13,T14,T15,U13,V11,V12,V13,V14,V15,
GPU_VDD Internal GPU power
V16,W10,W11,W12,W14,W15,W16
PMU_VDD_0V9 T24
Internal PMU Domain Power
PMU_VDD_1V8 U25
AA11,AA12,AA14,AA15,AA23,AA26,AA29,AB10,AB11,AB13,AB1
5,AB16,AB17,AB23,AC11,AC13,AC15,AC16,AC17,AC23,AC25,A
C26,AC29,AD13,AD17,AD26,AD29,AE11,AE12,AE14,AE17,AE27
AVSS Analog Ground
,AF17,AF23,AF24,AF29,AG29,AH29,AJ6,AJ8,AJ9,AJ11,AJ12,AJ1
4,AJ15,AJ17,AJ18,AJ29,B31,C28,C29,D29,H19,J21,U23,V23,W2
3,Y23,Y29
PMUIO2 IO domain
Support 1.8v and 3.0v mode, controlled by PMUGRF_SOC_CON0[9:8], please refer
to GRF TRM chapter for detail control information description.
With PMUIO2_VDDPST and PMUIO2_VDD two power supply.
1.8v mode: Both PMUIO2_VDDPST and PMUIO2_VDD power supply with
1.8v(typical).
3.0v mode: PMUIO2_VDDPST power supply with 1.5v(typical) and
PMUIO2_VDD power supply with 3.0v(typical).
PMUIO2_VDDPST and PMUIO2_VDD power up rise time need to >100us and power
down fall time also need to >100us.
Change from 3.0v mode to 1.8v mode sequence: change external power supply
firstly, then wait >1ms, last configure GFR register to change IO working mode.
Change from 1.8v mode to 3.0v mode sequence: configure GFR register to change
IO working mode firstly, then wait >1ms, last change external power supply.
Power up sequence for 3.0v mode: power up PMUIO2_VDDPST firstly, then
wait >20us, last power up PMUIO2_VDD.
Power down sequence for 3.0v mode: power down PMUIO2_VDD firstly, then
wait >20us, last power down PMUIO2_VDDPST.
Not support fail-safe condition (PMUIO2 power off, but signal PAD still with high
level input drive), otherwise IO reliability will be uncontrollable.
APIO1 IO domain
Only support 3.3v mode, with APIO1_VDDPST(1.8v typical) and APIO1_VDD(3.3v
typical) two power supply.
APIO1_VDDPST and APIO1_VDD power up rise time need to >100us and power
down fall time also need to >100us.
Power up sequence: power up APIO1_VDDPST firstly, then wait >20us, last power
up APIO1_VDD.
Power down sequence: power down APIO1_VDD firstly, then wait >20us, last
power down APIO1_VDDPST.
Not support fail-safe condition (APIO1 power off, but signal PAD still with high level
input drive), otherwise IO reliability will be uncontrollable.
APIO2/4/5 IO domain
Support 1.8v and 3.0v mode, controlled by GRF_IO_VSEL, please refer to GRF TRM
chapter for detail control information description.
With APIO2/4/5_VDDPST and APIO2/4/5_VDD two power supply.
1.8v mode: Both APIO2/4/5_VDDPST and APIO2/4/5_VDD power supply with
1.8v(typical).
3.0v mode: APIO2/4/5_VDDPST power supply with 1.5v(typical) and
APIO2/4/5_VDD power supply with 3.0v(typical).
APIO2/4/5_VDDPST and APIO2/4/5_VDD power up rise time need to >100us and
power down fall time also need to >100us.
Change from 3.0v mode to 1.8v mode sequence: change external power supply
firstly, then wait >1ms, last configure GFR register to change IO working mode.
Change from 1.8v mode to 3.0v mode sequence: configure GFR register to change
IO working mode firstly, then wait >1ms, last change external power supply.
Power up sequence for 3.0v mode: power up APIO2/4/5_VDDPST firstly, then
wait >20us, last power up APIO2/4/5_VDD.
Power down sequence for 3.0v mode: power down APIO2/4/5_VDD firstly, then
wait >20us, last power down APIO2/4/5_VDDPST.
Not support fail-safe condition (APIO2/4/5 power off, but signal PAD still with high
level input drive), otherwise IO reliability will be uncontrollable.
APIO3 IO domain
Only support 1.8v mode, with APIO3_VDD_1V8(1.8v typical) power supply.
SDMMC IO domain
Support 1.8v and 3.0v mode, controlled by GRF_IO_VSEL, please refer to GRF TRM
chapter for detail control information description.
With only SDMMC0_VDD one power supply.
1.8v mode: SDMMC0_VDD power supply with 1.8v(typical).
3.0v mode: SDMMC0_VDD power supply with 3.0v(typical).
SDMMC0_VDD power up rise time need to >100us and power down fall time also
need to >100us.
Change from 3.0v mode to 1.8v mode sequence: change external power supply
firstly, then wait >1ms, last configure GRF register to change IO working mode.
Change from 1.8v mode to 3.0v mode sequence: configure GFR register to change
IO working mode firstly, then wait >1ms, last change external power supply.
Not support fail-safe condition (SDMMC power off, but signal PAD still with high
level input drive), otherwise IO reliability will be uncontrollable.
Pin Name Func 1 Func 2 Func 3 Func 4 Type Def PD/PU Default INT
Pin Name Func 1 Func 2 Func 3 Func 4 Type Def PD/PU Default INT
GPIO2_B2/SPI2_TXD/CIF_CLKIN/I2C6_SCL gpio2_b[2] spi2_txd i2c6_scl io_cif_clkin I/O I up 3mA √
GPIO2_B3/SPI2_CLK/VOP_DEN/CIF_CLKOUT gpio2_b[3] spi2_clk vop_den io_cif_clkout I/O I up 3mA √
GPIO2_B4/SPI2_CSN0 gpio2_b[4] spi2_csn0 I/O I up 3mA √
GPIO2_C0/UART0_RX gpio2_c[0] uart0_rx I/O I up 5mA √
GPIO2_C1/UART0_TX gpio2_c[1] uart0_tx I/O I up 5mA √
GPIO2_C2/UART0_CTSN gpio2_c[2] uart0_ctsn I/O I up 5mA √
GPIO2_C3/UART0_RTSN gpio2_c[3] uart0_rtsn I/O I up 5mA √
GPIO2_C4/SDIO0_D0/SPI5_RXD gpio2_c[4] sdio0_data0 spi5_rxd I/O I up 5mA √
GPIO2_C5/SDIO0_D1/SPI5_TXD gpio2_c[5] sdio0_data1 spi5_txd I/O I up 5mA √
GPIO2_C6/SDIO0_D2/SPI5_CLK gpio2_c[6] sdio0_data2 spi5_clk I/O I up 5mA √
GPIO2_C7/SDIO0_D3/SPI5_CSN0 gpio2_c[7] sdio0_data3 spi5_csn0 I/O I up 5mA √
GPIO2_D0/SDIO0_CMD gpio2_d[0] sdio0_cmd I/O I up 5mA √
GPIO2_D1/SDIO0_CLKOUT/TEST_CLKOUT1 gpio2_d[1] sdio0_clkout test_clkout1 I/O I up 5mA √
GPIO2_D2/SDIO0_DETN gpio2_d[2] sdio0_detect_n I/O I up 5mA √
GPIO2_D3/SDIO0_PWREN gpio2_d[3] sdio0_pwren I/O I down 5mA √
GPIO2_D4/SDIO0_BKPWR gpio2_d[4] sdio0_bkpwr I/O I down 5mA √
GPIO3_A0/MAC_TXD2/SPI4_RXD gpio3_a[0] mac_txd2 spi4_rxd trace_data12 I/O I down 4mA √
GPIO3_A1/MAC_TXD3/SPI4_TXD gpio3_a[1] mac_txd3 spi4_txd trace_data13 I/O I down 4mA √
GPIO3_A2/MAC_RXD2/SPI4_CLK gpio3_a[2] mac_rxd2 spi4_clk trace_data14 I/O I up 4mA √
GPIO3_A3/MAC_RXD3/SPI4_CSN0 gpio3_a[3] mac_rxd3 spi4_csn0 trace_data15 I/O I up 4mA √
GPIO3_A4/MAC_TXD0/SPI0_RXD gpio3_a[4] mac_txd0 spi0_rxd I/O I down 4mA √
GPIO3_A5/MAC_TXD1/SPI0_TXD gpio3_a[5] mac_txd1 spi0_txd I/O I down 4mA √
GPIO3_A6/MAC_RXD0/SPI0_CLK gpio3_a[6] mac_rxd0 spi0_clk I/O I up 4mA √
GPIO3_A7/MAC_RXD1/SPI0_CSN0 gpio3_a[7] mac_rxd1 spi0_csn0 I/O I up 4mA √
GPIO3_B0/MAC_MDC/SPI0_CSN1 gpio3_b[0] mac_mdc spi0_csn1 I/O I up 4mA √
GPIO3_B1/MAC_RXDV gpio3_b[1] mac_rxdv I/O I down 4mA √
Pin Name Func 1 Func 2 Func 3 Func 4 Type Def PD/PU Default INT
GPIO3_B2/MAC_RXER/I2C5_SDA gpio3_b[2] mac_rxer i2c5_sda I/O I up 4mA √
GPIO3_B3/MAC_CLK/I2C5_SCL gpio3_b[3] mac_clk i2c5_scl I/O I up 4mA √
GPIO3_B4/MAC_TXEN/UART1_RX gpio3_b[4] mac_txen uart1_rx I/O I up 4mA √
GPIO3_B5/MAC_MDIO/UART1_TX gpio3_b[5] mac_mdio uart1_tx I/O I up 4mA √
GPIO3_B6/MAC_RXCLK/UART3_RX gpio3_b[6] mac_rxclk uart3_rx I/O I up 4mA √
GPIO3_B7/MAC_CRS/UART3_TX/CIF_CLKOUTB gpio3_b[7] mac_crs uart3_tx cif_clkoutb I/O I up 4mA √
GPIO3_C0/MAC_COL/UART3_CTSN/SPDIF_TX gpio3_c[0] mac_col uart3_ctsn spdif_tx I/O I up 4mA √
GPIO3_C1/MAC_TXCLK/UART3_RTSN gpio3_c[1] mac_txclk uart3_rtsn I/O I up 4mA √
GPIO3_D0/I2S0_SCLK gpio3_d[0] i2s0_sclk trace_data0 I/O I down 3mA √
GPIO3_D1/I2S0_LRCK_RX gpio3_d[1] i2s0_lrck_rx trace_data1 I/O I down 3mA √
GPIO3_D2/I2S0_LRCK_TX gpio3_d[2] i2s0_lrck_tx trace_data2 I/O I down 3mA √
GPIO3_D3/I2S0_SDI0 gpio3_d[3] i2s0_sdi0 trace_data3 I/O I down 3mA √
GPIO3_D4/I2S0_SDI1SDO3 gpio3_d[4] i2s0_sdi1sdo3 trace_data4 I/O I down 3mA √
GPIO3_D5/I2S0_SDI2SDO2 gpio3_d[5] i2s0_sdi2sdo2 trace_data5 I/O I down 3mA √
GPIO3_D6/I2S0_SDI3SDO1 gpio3_d[6] i2s0_sdi3sdo1 trace_data6 I/O I down 3mA √
GPIO3_D7/I2S0_SDO0 gpio3_d[7] i2s0_sdo0 trace_data7 I/O I down 3mA √
GPIO4_A0/I2S_CLK gpio4_a[0] i2s_clk trace_ctl I/O I down 3mA √
GPIO4_A1/I2C1_SDA gpio4_a[1] i2c1_sda trace_clk I/O I up 3mA √
GPIO4_A2/I2C1_SCL gpio4_a[2] i2c1_scl trace_data8 I/O I up 3mA √
GPIO4_A3/I2S1_SCLK gpio4_a[3] i2s1_sclk trace_data9 I/O I down 3mA √
GPIO4_A4/I2S1_LRCK_RX gpio4_a[4] i2s1_lrck_rx trace_data10 I/O I down 3mA √
GPIO4_A5/I2S1_LRCK_TX gpio4_a[5] i2s1_lrck_tx trace_data11 I/O I down 3mA √
GPIO4_A6/I2S1_SDI0 gpio4_a[6] i2s1_sdi0 I/O I down 3mA √
GPIO4_A7/I2S1_SDO0 gpio4_a[7] i2s1_sdo0 I/O I down 3mA √
GPIO4_B0/SDMMC0_D0/UART2DBG_RX gpio4_b[0] sdmmc0_data0 uart2dbg_rx I/O I up 6mA √
GPIO4_B1/SDMMC0_D1/UART2DBG_TX gpio4_b[1] sdmmc0_data1 uart2dbg_tx hdcpjtag_trstn I/O I up 6mA √
Pin Name Func 1 Func 2 Func 3 Func 4 Type Def PD/PU Default INT
GPIO4_B2/SDMMC0_D2/APJTAG_TCK gpio4_b[2] sdmmc0_data2 ap_jtag_tck hdcpjtag_tdi I/O I up 6mA √
GPIO4_B3/SDMMC0_D3/APJTAG_TMS gpio4_b[3] sdmmc0_data3 ap_jtag_tms hdcpjtag_tdo I/O I up 6mA √
GPIO4_B4/SDMMC0_CLKOUT/MUCJTAG_TCK gpio4_b[4] sdmmc0_clkout mcujtag_tck hdcpjtag_tck I/O I down 6mA √
GPIO4_B5/SDMMC0_CMD/MCUJTAG_TMS gpio4_b[5] sdmmc0_cmd mcujtag_tms hdcpjtag_tms I/O I up 6mA √
GPIO4_C0/I2C3_SDA_HDMI/UART2DBG_RX gpio4_c[0] i2c3_sda_hdmi uart2dbg_rx I/O I up 3mA √
GPIO4_C1/I2C3_SCL_HDMI/UART2DBG_TX gpio4_c[1] i2c3_scl_hdmi uart2dbg_tx I/O I up 3mA √
GPIO4_C2/PWM0/VOP0_PWM/VOP1_PWM gpio4_c[2] pwm0 vop0_pwm vop1_pwm I/O I down 3mA √
GPIO4_C3/UART2DBG_RX/UARTHDCP_RX gpio4_c[3] uart2dbg_rx uarthdcp_rx I/O I up 3mA √
GPIO4_C4/UART2DBG_TX/UARTHDCP_TX gpio4_c[4] uart2dbg_tx uarthdcp_tx I/O I up 3mA √
GPIO4_C5/SPDIF_TX gpio4_c[5] spdif_tx I/O I down 3mA √
GPIO4_C6/PWM1 gpio4_c[6] pwm1 I/O I down 3mA √
GPIO4_C7/HDMI_CECINOUT/EDP_HOTPLUG gpio4_c[7] hdmi_cecinout edp_hotplug I/O I up 3mA √
GPIO4_D0 gpio4_d[0] I/O I up 3mA √
GPIO4_D1/DP_HOTPLUG gpio4_d[1] dp_hotplug I/O I down 3mA √
GPIO4_D2 gpio4_d[2] I/O I down 3mA √
GPIO4_D3 gpio4_d[3] I/O I down 3mA √
GPIO4_D4 gpio4_d[4] I/O I down 3mA √
GPIO4_D5 gpio4_d[5] I/O I down 3mA √
GPIO4_D6 gpio4_d[6] I/O I down 3mA √
Notes :
①:Pad types : I = input , O = output , I/O = input/output (bidirectional) ,
AP = Analog Power , AG = Analog Ground
DP = Digital Power , DG = Digital Ground
A = Analog
②: Output Drive strength is configurable, it’s the suggested value in this table. Unit is mA , only Digital IO have drive value
③:Reset state: I = input without any pull resistor O = output
④:It is die location. For examples, “Left side” means that all the related IOs are always in left side of die
⑤:Power supply means that all the related IOs are in this IO power domain. If multiple powers are included, they are connected together in one IO power ring
⑥:The pull up/pull down is configurable.
2.9.1 eMMC
Table 2-4eMMC pin description
Interface Pin Name Dir. Description
2.9.3 USB
Table 2-5USB2 pin description
Interface Pin Name Dir. Description
2.9.4 eDP
Table 2-6eDP pin description
Interface Pin Name Dir. Description
EDP_TXiP(i=0~3) O eDP data lane positive output
EDP_TXiN(i=0~3) O eDP data lane negative output
2.9.5 HDMI
Table 2-7HDMI pin description
Interface Pin Name Dir. Description
2.9.6 MIPI
Table 2-8MIPI pin description
Interface Pin Name Dir. Description
MIPI_DSI MIPI_TX0_DiN(i=0~3) I/O MIPI DSI negative differential data line transceiver output
MIPI_TX0_DiP(i=0~3) I/O MIPI DSI positive differential data line transceiver output
MIPI_TX0_CLKP I/O MIPI DSI positive differential clock line transceiver output
MIPI_TX0_CLKN I/O MIPI DSI negative differential clock line transceiver output
MIPI_RX0_DiN(i=0~3) I/O MIPI CSI negative differential data line transceiver output
MIPI_RX0_DiP(i=0~3) I/O MIPI CSI positive differential data line transceiver output
MIPI_RX0_CLKP I/O MIPI CSI positive differential clock line transceiver output
MIPI_CSI
MIPI_RX0_CLKN I/O MIPI CSI negative differential clock line transceiver output
MIPI_TX1/RX1_DiN(i=0~3) I/O MIPI CSI negative differential data line transceiver output
MIPI_ TX1/RX1_DiP(i=0~3) I/O MIPI CSI positive differential data line transceiver output
MIPI_ TX1/RX1_CLKP I/O MIPI CSI positive differential clock line transceiver output
MIPI_CSI/DSI MIPI CSI negative differential clock line transceiver
MIPI_ TX1/RX1_CLKN I/O
output
2.9.7 ISP
Table 2-9ISP pin description
Interface Pin Name Dir. Description
2.9.8 EFUSE
Table 2-10EFUSE pin description
Interface Pin Name Dir. Description
2.9.9 SAR-ADC
Table 2-11SAR-ADC pin description
Interface Pin Name Dir. Description
2.9.10 TSADC
Table 2-12TSADC pin description
Interface Pin Name Dir. Description
2.9.11 GMAC
Table 2-13GMAC pin description
Interface Pin Name Dir. Description
2.9.12 UART
Table 2-14UART pin description
Interface Pin Name Dir. Description
UART[i]_RX I UART serial data input
2.9.13 I2C
Table 2-15I2C pin description
2.9.14 PWM
Table 2-16PWM pin description
Interface Pin Name Dir. Description
2.9.15 CIF
Table 2-17CIF pin description
Interface Pin Name Dir. Description
CIF_CLKIN I Camera interface input pixel clock
2.9.16 SPI
Table 2-18SPI pin description
Interface Pin Name Dir. Description
SPI0 SPI0_CNS1 I/O SPI second chip select signal, low active
SPI[i] SPI[i]_CSN0 I/O SPI first chip select signal, low active
2.9.17 SPDIF
Table 2-19SPDIF pin description
Interface Pin Name Dir. Description
2.9.18 I2S
Table 2-20I2S pin description
Interface Pin Name Dir. Description
I2S I2S_CLK O I2S/PCM clock source, shared by I2S0 and I2S1
DDR[i]_DQS[j]N[j=0~3] I/O Differential data strobes to/from the memories. For writes,
the pad drives these signals. For reads, the memory drives
DDR[i]_DQS[j]P[j=0~3] I/O
these signals.
2.9.20 SDIO
Table 2-22SDIO pin description
Interface Pin Name Dir. Description
SDIO Host SDIO0_CMD I/O SDIO card command output and response input.
2.9.21 SDMMC
Table 2-23SDMMC pin description
Interface Pin Name Dir. Description
2.9.22 JTAG
Table 2-24JTAG pin description
Interface Pin Name Dir. Description
JTAG APJTAG_TMS I/O APJTAG interface TMS input/SWD interface data out
Note: AP means CPU core in RK3399-T including Cortex A72 and Cortex A53.
JTAG MCUJTAG_TMS I/O MCUJTAG interface TMS input/SWD interface data out
Note: MCU means built-in micro-controller in RK3399-T core domain.
PMCU PMCU_JTAG_TCK I PMU MCU JTAG interface clock input/SWD interface clock input
JTAG PMCU_JTAG_TMS I/O PMU MCU JTAG interface TMS input/SWD interface data out
Note: PMCU means built-in micro-controller in RK3399-T PMU domain.
2.9.23 MISC
Table 2-25MISC pin description
Interface Pin Name Dir. Description
BIGCPU_VDD,
LITCPU_VDD,
DC supply voltage for Internal digital logic 1.3 V
LOGIC_VDD,
CENTERLOGIC_VDD
Absolute maximum ratings specify the values beyond which the device may be damaged
permanently. Long-term exposure to absolute maximum ratings conditions may affect
device reliability.
The below table describes the recommended operating condition for every clock domain.
Table 3-2 Recommended operating conditions
Supply voltage for Cortex A72 CPU BIGCPU_VDD 0.875 0.925 1.15 V
Supply voltage for Cortex A53 CPU LITCPU_VDD 0.875 0.925 0.975 V
CENTERLOGIC_VDD
Internal digital logic Power 0.8 0.9 1.0 V
LOGIC_VDD
PMU digital logic power (0.9V) PMU_VDD_0V9 0.81 0.9 0.99 V
MIPI_TX0_AVDD_1V8
Supply voltage for MIPI MIPI_TX1/RX1_AVDD_1V8 1.62 1.8 1.98 V
MIPI_RX0_AVDD_1V8
TYPEC0_AVDD_0V9 0.81 0.9 0.99
TYPEC0_AVDD_1V8 1.62 1.8 1.98
TYPEC0_AVDD_3V3 2.97 3.3 3.63
Supply voltage for TYPEC V
TYPEC1_AVDD_0V9 0.81 0.9 0.99
TYPEC1_AVDD_1V8 1.62 1.8 1.98
TYPEC1_AVDD_3V3 2.97 3.3 3.63
USIC_AVDD_0V9 0.81 0.9 0.99
Supply voltage for USIC V
USIC_AVDD_1V2 1.08 1.2 1.32
USB_AVDD_0V9 0.81 0.9 0.99
Supply voltage for USB USB_AVDD_1V8 1.62 1.8 1.98 V
USB_AVDD_3V3 2.97 3.3 3.63
3.3 DC Characteristics
Table 3-3DC Characteristics
Parameters Symbol Min Type Max Units
Input Low Voltage Vil -0.3 N/A 0.8 V
LPDDR4 0
HS TX static Common-
VCMTX 150 200 250 mV
mode voltage
HS transmit differential
|VOD| 140 200 270 mV
voltage
Single-ended standby
Voff avddtmds±10 mV
voltage
avddtmds±10 mV
Vh avddtmds-
N/A avddtmds+10 mV
200
Single-ended output high
avddtmds-
voltage Vh_data N/A avddtmds+10 mV
HDMI 400
avddtmds-
Vh_clock N/A avddtmds+10 mV
400
avddtmds-
N/A avddtmds-400 mV
600
Vl
avddtmds-
Single-ended output low N/A avddtmds-400 mV
700
voltage avddtmds-
Vl_data N/A avddtmds-400 mV
1000
avddtmds-
Vl_clock N/A avddtmds-200 mV
1000
Differential source
Rterm 50 N/A 200 Ω
termination load
@1.8V High level output current Oih 25℃ 3.7 N/A 24.6 mA
Power consumption
N/A FVCO=1GHz N/A 3 N/A mW
(normal mode)
Transmitter
Classic mode
40.5 45 49.5 ohms
(Vout = 0 or 3.3V)
Output resistance ROUT
HS mode (Vout = ohms
40.5 45 49.5
0 to 800mV)
seen from D+ or
Output Capacitance COUT 3 pF
D-
Classic (LS/FS)
Output Common Mode 1.45 1.65 1.85 V
VM mode
Voltage
HS mode 0.175 0.2 0.225 V
Classic (LS/FS);
2.97 3.3 3.63 V
Io=0mA
Differential output
VOH Classic (LS/FS);
signal high 2.2 0.3 NA V
Io=6mA
HS mode
(differential and
0.1 0.2 0.3 V
squelch
Receiver common mode RCM
comparator)
HS mode
(disconnect 0.5 0.6 0.7 V
comparator)
Input capacitance (seen
NA NA 3 pF
at D+ or D-)
DDR IO
Input leakage current @ 1.5V -2 N/A 2 uA
@DDR3 mode
DDR IO
Input leakage current @ 1.35V -2 N/A 2 uA
@DDR3L mode
DDR IO
Input leakage current @ 1.2V -2 N/A 2 uA
@LPDDR3 mode
DDR IO
Input leakage current @ 1.1V -2 N/A 2 uA
@LPDDR4 mode
Active mode VDD current in PGM mode Ipgm_vdd STROBE high N/A 17 N/A mA
VQPS current in PGM mode Ipgm_vqps STROBE high N/A 0.2 N/A uA
20~80%
tR_CLOCK 75 N/A N/A ps
RL=50Ω
20~80%
tF 75 N/A N/A ps
RL=50Ω
Common-mode variations
ΔVCMTX(HF) N/A N/A 15 mVRMS
above 450 MHz
Common-mode variations
ΔVCMTX(LF) N/A N/A 25 mVPEAK
between 50MHz – 450MHz
20%-80% rise time and fall
TR and TF 100 N/A N/A ps
time
4.1 Overview
For reliability and operability concerns, the absolute maximum junction temperature
has to be below 125℃.
Note: The testing JEDEC PCB is based on 6 layers, 114.3x101.6 mm, 1.6 mm Thickness,
ambient temperature is 25℃.