A3941 Datasheet

A3941
Automotive Full Bridge MOSFET Driver
FEATURES AND BENEFITS DESCRIPTION

▪ High current gate drive for N-channel MOSFET full bridge The A3941 is a full-bridge controller for use with external
▪ High-side or low-side PWM switching N‑channel power MOSFETs and is specifically designed for
▪ Charge pump for low supply voltage operation automotive applications with high-power inductive loads, such
▪ Top-off charge pump for 100% PWM as brush DC motors.
▪ Cross-conduction protection with adjustable dead time
▪ 5.5 to 50 V supply voltage range A unique charge pump regulator provides full (>10 V) gate
▪ Integrated 5 V regulator drive for battery voltages down to 7 V and allows the A3941
▪ Diagnostics output to operate with a reduced gate drive, down to 5.5 V.
▪ Low current sleep mode A bootstrap capacitor is used to provide the above-battery
supply voltage required for N-channel MOSFETs. An internal
charge pump for the high-side drive allows DC (100% duty
cycle) operation.
PACKAGE: 28-pin TSSOP with exposed The full bridge can be driven in fast or slow decay modes using
thermal pad (suffix LP) diode or synchronous rectification. In the slow decay mode,
current recirculation can be through the high-side or the low-
side FETs. The power FETs are protected from shoot-through
by resistor adjustable dead time.
Integrated diagnostics provide indication of undervoltage,
overtemperature, and power bridge faults, and can be configured
to protect the power MOSFETs under most short circuit
conditions.
Not to scale The A3941 is supplied in a 28-pin TSSOP power package with
an exposed thermal pad (suffix LP). This package is lead (Pb)
free, with 100% matte-tin leadframe plating.
Typical Application
VBAT
PWM
A3941
Direction
Fault Flags
3941-DS, Rev. 8 May 11, 2022

MCO-0000662
A3941 Automotive Full Bridge MOSFET Driver
SELECTION GUIDE
Part Number Packing
A3941KLPTR-T 4000 pieces per reel
ABSOLUTE MAXIMUM RATINGS*

Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB –0.3 to 50 V
Logic Inputs and Outputs –0.3 to 6.5 V
V5 Pin –0.3 to 7 V
LSS Pin –4 to 6.5 V
VDSTH Pin –0.3 to 6.5 V
SA and SB Pins –5 to 55 V
VDRAIN Pin –5 to 55 V
GHA and GHB Pins Sx to Sx+15 V
GLA and GLB Pins –5 to 16 V
CA and CB Pins –0.3 to Sx+15 V
Operating Temperature Range TA Range K –40 to 150 °C
Junction Temperature TJ(max) 150 °C
Overtemperature event not exceeding 1 second,
Transient Junction Temperature TtJ lifetime duration not exceeding 10 hours; 175 °C
guaranteed by design characterization
Storage Temperature Range Tstg –55 to 150 °C
ESD Rating, Human Body Model AEC-Q100-002, all pins 2000 V
ESD Rating, Charged Device Model AEC-Q100-011, all pins 1050 V
*With respect to GND.
THERMAL CHARACTERISTICS: May require derating at maximum conditions

Characteristic Symbol Test Conditions* Value Units
4-layer PCB based on JEDEC standard 28 °C/W
RθJA
Package Thermal Resistance 2-layer PCB with 3.8 in.2 of copper area each side 32 °C/W
RθJP 2 °C/W
*Additional thermal information available on Allegro website.
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Functional Block Diagram

Battery +
CP
VBB CP2 CP1

VBAT
Charge
V5 VREG
+5V Reg Pump
Regulator CREG
FF1 VDRAIN
FF2 Diagnostics
VDSTH and Protection Charge Bootstrap
Pump Monitor
CA
CBOOTA
High GHA
Side RGHA RGHB
SA
PWMH Low GLA

Side
RGLA RGLB
PWML LSS
Control
Logic Charge Bootstrap
Pump Monitor
CB
PHASE
CBOOTB
High GHB
SR Side
SB
RESET
Low GLB
Side
LSS
PAD
RDEAD GND
3
955 Perimeter Road
ELECTRICAL CHARACTERISTICS: Valid at TJ = –40°C to 150°C, VBB = 7 to 50 V, unless noted otherwise

Characteristics Symbol Test Conditions Min. Typ. Max. Units
SUPPLY AND REFERENCE
Load Supply Voltage Functional Operating Range [1] VBB 5.5 – 50 V
IBBQ RESET = high, outputs = low, VBB = 12 V – 10 14 mA
Load Supply Quiescent Current
IBBS RESET = low, Sleep mode, VBB = 12 V – – 10 µA
VBB > 9 V, IREG = 0 to 10 mA 12.5 13 13.75 V
7.5 V < VBB ≤ 9 V, IREG = 0 to 7 mA 12.5 13 13.75 V
VREG Output Voltage VREG
6 V < VBB ≤ 7.5 V, IREG = 0 to 7 mA 2×VBB – 2.5 – – V
5.5 V < VBB ≤ 6 V, IREG < 5.5 mA 8.5 9.5 – V
V5 Output Voltage V5(out) No load 4.5 5 5.5 V
V5 Line Regulation V5(line) I5 = –2 mA – 15 40 mV
V5 Load Regulation V5(load) I5 = 0 to –2 mA – 50 100 mV
V5 Short-Circuit Current I5M VBB = 40 V, V5 = 0 V – 28 35 mA
ID = 10 mA 0.4 0.7 1.0 V
Bootstrap Diode Forward Voltage VfBOOT
ID = 100 mA 1.5 2.2 2.8 V
rD(100mA) =
Bootstrap Diode Resistance rD 6 10 20 Ω
(VfBOOT(150mA) – VfBOOT(50mA)) / 100 mA
Bootstrap Diode Current Limit IDBOOT 250 500 750 mA
Top-off Charge Pump Current Limit ITOCPM – 400 – µA
High-Side Gate Drive Static Load Resistance RGSH 250 – – kΩ
GATE OUTPUT DRIVE
Turn-On Time tr CLOAD = 1 nF, 20% to 80% – 35 – ns
Turn-Off Time tf CLOAD = 1 nF, 80% to 20% – 20 – ns
TJ = 25°C, IGHx = –150 mA 6 8 12 Ω
Pullup On Resistance RDS(on)UP
TJ = 150°C, IGHx = –150 mA 10 13 16 Ω
TJ = 25°C, IGLx = 150 mA 2 3 4 Ω
Pulldown On Resistance RDS(on)DN
TJ = 150°C, IGLx = 150 mA 3 4.5 6 Ω
GHx Output Voltage VGHX Bootstrap capacitor fully charged VCx – 0.2 – – V
GLx Output Voltage VGLX VREG – 0.2 – – V
Input change to unloaded gate output
Turn-Off Propagation Delay [2] tP(off) 60 90 150 ns
change
Input change to unloaded gate output
Turn-On Propagation Delay [2] tP(on) 60 90 150 ns
change
Measured between corresponding
Propagation Delay Matching, Phase-to-Phase ∆tPP – 10 – ns
transition points on both phases
Propagation Delay Matching, On-to-Off ∆tOO Measured across one phase – 10 – ns
RDEAD = 3 kΩ – 180 – ns
RDEAD = 30 kΩ 815 960 1110 ns
Dead Time [2] tDEAD
RDEAD = 240 kΩ – 3.5 – µs
RDEAD tied to V5 – 6 – µs
Continued on the next page…
4
955 Perimeter Road
ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VBB = 7 to 50 V, unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Units
LOGIC INPUTS AND OUTPUTS
FF1 and FF2 Fault Output (Open Drain) VFF(L) IFF = 1 mA, fault not present – – 0.4 V
FF1 and FF2 Fault Output Leakage Current [3] IFF(H) VFF = 5 V, fault present –1 – 1 µA
RDEAD Current [3] IDEAD RDEAD = GND –200 – –70 µA
Input Low Voltage VIN(L) – – 1 V
Input High Voltage VIN(H) 3.5 – – V
Input Hysteresis (Except RESET Pin) VINhys 300 500 – mV
Input Hysteresis (RESET Pin) VINRSThys 200 – – mV
Input Current (Except RESET Pin) [3] IIN 0 V < VIN < V5 –1 – 1 µA
Input Pulldown Resistor (RESET Pin) RPD – 50 – kΩ
RESET Pulse Time tRES 0.1 – 3.5 µs
PROTECTION
VREGUVon VREG rising 7.5 8 8.5 V
VREG Undervoltage Lockout Threshold
VREGUVoff VREG falling 6.75 7.25 7.75 V
Bootstrap Undervoltage Threshold VBOOTUV Cx with respect to Sx 59 – 69 %VREG
Bootstrap Undervoltage Hysteresis VBOOTUVhys – 13 – %VREG
V5 Undervoltage Turn-Off Threshold V5UVoff V5 falling 3.4 3.6 3.8 V
V5 Undervoltage Hysteresis V5UVhys 300 400 500 mV
VDSTH Input Range VDSTH 0.1 – 2 V
VDSTH Input Current IDSTH 0 V < VDSTH < 2 V –2 – 2 µA
VDSTH Disable Voltage VDSDIS When not connected directly to V5 4.95 – – V
VDRAIN Input Voltage VDRAIN VDSTH = 2 V, VBB = 12 V, 7 VBB 50 V
VDSTH = 2 V, VBB = 12 V,
VDRAIN Input Current IDRAIN – – 250 µA
0 V < VDRAIN < VBB
High-side on, VDSTH ≥ 1 V – ±100 – mV
Short-to-Ground Threshold Offset [4] VSTGO
High-side on, VDSTH < 1 V –150 ±50 150 mV
Low-side on, VDSTH ≥ 1 V – ±100 – mV
Short-to-Battery Threshold Offset [5] VSTBO
Low-side on, VDSTH < 1 V –150 ±50 150 mV
Overtemperature Fault Flag Threshold TJF Temperature increasing 150 170 – °C
Overtemperature Fault Hysteresis TJFhys Recovery = TJF – TJFhys – 15 – °C
[1] Functions correctly, but parameters are not guaranteed, below the general limits (7 V).
[2] See Gate Drive Timing diagrams.
[3] For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
[4] As V
Sx decreases, fault occurs if VBAT –VSx > VSTG. STG threshold, VSTG = VDSTH + VSTGO .
[5] As V
Sx increases, fault occurs if VSx – VLSS > VSTB . STB threshold, VSTB = VDSTH+VSTBO .
5
955 Perimeter Road
TIMING DIAGRAMS
Gate Drive Timing – PWM inputs, Slow Decay, Synchronous Rectification
PWMH PWML
tP(off) tP(off) tP(off) tP(off)

GHx GHx
GLx tDEAD tDEAD GLx tDEAD tDEAD
SR=1, PWML=1 SR=1, PWMH=1
Gate Drive Timing – PWM inputs, Slow Decay, Diode Rectification
PWMH PWML
tP(off) tP(on) tP(off) tP(on)

GHx GHx
GLx GLx
SR=0, PWML=1 SR=0, PWMH=1
Gate Drive Timing – Phase Input, Fast Decay, Gate Drive Timing – PWM Input, Fast Decay,
Synchronous Rectification Diode Rectification
PHASE PWMH
tP(off) tP(off) PWML
tDEAD tDEAD tP(off) tP(on)

GHA GHA
GLA GLA
GHB GHB
GLB GLB
PWML=1, PWMH=1 PHASE=1
6
955 Perimeter Road
FUNCTIONAL DESCRIPTION
The A3941 is a full-bridge MOSFET driver (pre-driver) requiring provided by an integrated 5 V regulator. This regulator is also
a single unregulated supply of 7 to 50 V. It includes an integrated used by the internal logic circuits and must always be decoupled
5 V logic supply regulator. by at least a 100 nF capacitor between the V5 pin and GND. The
5 V regulator is disabled when RESET is held low.
The four high current gate drives are capable of driving a wide
range of N-channel power MOSFETs, and are configured as two
high-side drives and two low-side drives. The A3941 provides
GATE DRIVES
all the necessary circuits to ensure that the gate-source voltage
of both high-side and low-side external FETs are above 10 V, at The A3941 is designed to drive external, low on-resistance,
supply voltages down to 7 V. For extreme battery voltage drop power N-channel MOSFETs. It supplies the large transient cur-
conditions, correct functional operation is guaranteed at supply rents necessary to quickly charge and discharge the external FET
voltages down to 5.5 V, but with a reduced gate drive voltage. gate capacitance in order to reduce dissipation in the external
FET during switching. The charge and discharge rate can be
The A3941 can be driven with a single PWM input from a
controlled using an external resistor in series with the connection
microcontroller and can be configured for fast or slow decay.
to the gate of the FET.
Fast decay can provide four-quadrant motor control, while slow
decay is suitable for two-quadrant motor control or simple induc- Gate Drive Voltage Regulation. The gate drives are powered
tive loads. In slow decay, current recirculation can be through by an internal regulator which limits the supply to the drives and
the high-side or the low-side MOSFETs. In either case, bridge therefore the maximum gate voltage. When the VBB supply is
efficiency can be enhanced by synchronous rectification. Cross- greater than about 16 V, the regulator is a simple linear regulator.
conduction (shoot through) in the external bridge is avoided by Below 16 V, the regulated supply is maintained by a charge pump
an adjustable dead time. boost converter, which requires a pump capacitor connected
between the CP1 and CP2 pins. This capacitor must have a mini-
A low power sleep mode allows the A3941, the power bridge, and
mum value of 220 nF, and is typically 470 nF.
the load to remain connected to a vehicle battery supply without
the need for an additional supply switch. The regulated voltage, nominally 13 V, is available on the VREG
pin. A sufficiently large storage capacitor must be connected to
The A3941 includes a number of protection features against
this pin to provide the transient charging current to the low-side
undervoltage, overtemperature, and power bridge faults. Fault
drives and the bootstrap capacitors.
states enable responses by the device or by the external control-
ler, depending on the fault condition and logic settings. Two fault Top-off Charge Pump. An additional top-off charge pump is
flag outputs, FF1 and FF2, are provided to signal detected faults provided for each phase. The charge pumps allow the high-side
to an external controller. drives to maintain the gate voltage on the external FETs indefi-
nitely, ensuring so-called 100% PWM if required. This is a low
current trickle charge pump, and is operated only after a high-side
POWER SUPPLIES FET has been signaled to turn on. The floating high-side gate
drive requires a small bias current (<20 µA) to maintain the high-
A single power supply connection is required to the VBB pin
level output. Without the top-off charge pump, this bias current
through a reverse voltage protection circuit. The supply should be
would be drawn from the bootstrap capacitor through the Cx pin.
decoupled with a ceramic capacitor connected close to the VBB
The charge pump provides sufficient current to ensure that the
and ground pins.
bootstrap voltage and thereby the gate-source voltage is main-
The A3941 operates within specified parameters with a VBB tained at the necessary level.
supply from 7 to 50 V and functions correctly with a supply down
Note that the charge required for initial turn-on of the high-side
to 5.5 V. This provides a very rugged solution for use in the harsh
gate is always supplied by the bootstrap capacitor. If the bootstrap
automotive environment.
capacitor becomes discharged, the top-off charge pump will not
V5 Pin. A 5 V low current supply for external pullup resistors is provide sufficient current to allow the FET to turn on.
7
955 Perimeter Road
In some applications a safety resistor is added between the gate LSS Pin. This is the low-side return path for discharge of the
and source of each FET in the bridge. When a high-side FET is capacitance on the FET gates. It should be tied directly to the
held in the on-state, the current through the associated high-side common sources of the low-side external FETs through an inde-
gate-source resistor (RGSH) is provided by the high-side drive and pendent low impedance connection.
therefore appears as a static resistive load on the top-off charge
RDEAD Pin. This pin controls internal generation of dead time
pump. The minimum value of RGSH for which the top-off charge
during FET switching.
pump can provide current is shown in the Electrical Characteris-
tics table. • When a resistor greater than 3 kΩ is connected between
RDEAD and AGND, cross-conduction is prevented by the gate
GLA and GLB Pins. These are the low-side gate drive outputs for
drive circuits, which introduce a dead time, tDEAD , between
the external N-channel MOSFETs. External resistors between the
switching one FET off and the complementary FET on. The
gate drive output and the gate connection to the FET (as close as
dead time is derived from the resistor value connected between
possible to the FET) can be used to control the slew rate seen at
the RDEAD and AGND pins.
the gate, thereby providing some control of the di/dt and dv/dt of
• When RDEAD is connected directly to V5, cross-conduction is
the SA and SB outputs. GLx going high turns on the upper half of
prevented by the gate drive circuits. In this case, tDEAD defaults
the drive, sourcing current to the gate of the low-side FET in the
to a value of 6 µs typical.
external power bridge, turning it on. GLx going low turns on the
lower half of the drive, sinking current from the external FET gate
circuit to the LSS pin, turning off the FET. LOGIC CONTROL INPUTS
SA and SB Pins. Directly connected to the motor, these terminals Four low-voltage level digital inputs provide control for the
sense the voltages switched across the load. These terminals are gate drives. These logic inputs all have a nominal hysteresis of
also connected to the negative side of the bootstrap capacitors 500 mV to improve noise performance. They are used together
and are the negative supply connections for the floating high-side to provide fast decay or slow decay with high-side or low-side
drives. The discharge current from the high-side FET gate capaci- recirculation. They also provide brake, coast, and sleep modes as
tance flows through these connections, which should have low defined in tables 1 and 2.
impedance circuit connections to the FET bridge.
PWMH and PWML Pins. These inputs can be used to control
GHA and GHB Pins. These terminals are the high-side gate current in the power bridge. PWMH provides high-side chopping
drive outputs for the external N-channel FETs. External resistors and PWML provides low-side chopping. When used together
between the gate drive output and the gate connection to the FET they control the power bridge in fast decay mode. The PWM
(as close as possible to the FET) can be used to control the slew options are provided in table 2.
rate seen at the gate, thereby controlling the di/dt and dv/dt of the
• Setting PWMH low turns off active high-side drives. This
SA and SB outputs. GHx going high turns on the upper half of
provides high-side–chopped slow-decay PWM.
the drive, sourcing current to the gate of the high-side FET in the
external motor-driving bridge, turning it on. GHx going low turns • Setting PWML low turns off active low-side drives. This
on the lower half of the drive, sinking current from the external provides low-side–chopped slow-decay PWM.
FET gate circuit to the corresponding Sx pin, turning off the FET. • PWMH and PWML may also be connected together and driven
with a single PWM signal. This provides fast-decay PWM.
CA and CB Pins. These are the high-side connections for the
PHASE Pin. The state of the PHASE pin determines the positive
bootstrap capacitors and are the positive supply for the high-side
direction of load current (see table 1). The PHASE pin can also
gate drives. The bootstrap capacitors are charged to approxi-
be used as a PWM input when full four-quadrant control (fast
mately VREG when the associated output Sx terminal is low.
decay synchronous rectification) is required (see table 2).
When the Sx output swings high, the charge on the bootstrap
capacitor causes the voltage at the corresponding Cx terminal to SR Pin. This enables or disables synchronous rectification. When
rise with the output to provide the boosted gate voltage needed SR is high, synchronous rectification is enabled. When a PWM-
for the high-side FETs. off phase occurs (low on either or both of the PWMH and PWML
8
955 Perimeter Road
Table 1. Phase Control Truth Table

Inputs Outputs Bridge
Mode of Operation
PWMH PWML PHASE SR GHA GLA GHB GLB SA SB
1 1 1 X H L L H HS LS Bridge driven with A high and B low
1 1 0 X L H H L LS HS Bridge driven with B high and A low
0 1 X 1 L H L H LS LS Slow decay, both low-side on or low-side brake
1 0 X 1 H L H L HS HS Slow decay, both high-side on or high-side brake
0 1 1 0 L L L H Z LS Slow decay, current flow A to B, low-side diode rectification
0 1 0 0 L H L L LS Z Slow decay, current flow B to A, low-side diode rectification
1 0 1 0 H L L L HS Z Slow decay, current flow A to B, high-side diode rectification
1 0 0 0 L L H L Z HS Slow decay, current flow B to A, high-side diode rectification
0 0 X X L L L L Z Z Fast decay, diode rectification/coast
X = don’t care (same for input 1 or input 0), HS = high-side FET active, LS = low-side FET active, Z = high impedance, both FETs off
Table 2. PWM Options

Inputs [a] PWM Effect [b]
Decay Mode of Operation
SR PWMH PWML PHASE 100% 0%
X 1 1 PWM A to B B to A Fast Full four-quadrant control, zero average load current at 50% PWM
1 A to B
0 PWM PWM Coast Fast Fast decay, diode recirculation or coast
0 B to A
1 A to B
1 PWM 1 Brake Slow High-side PWM, low-side MOSFET recirculation
0 B to A
1 A to B
1 1 PWM Brake Slow Low-side PWM, high-side MOSFET recirculation
0 B to A
1 A to B
0 PWM 1 Brake [c] Slow High-side PWM, low-side diode recirculation
0 B to A
1 A to B
0 1 PWM Brake [c] Slow Low-side PWM, high-side diode recirculation
0 B to A
X 0 0 X Coast Coast Fast Coast, all MOSFETs off
[a] Xindicates don’t care condition. The action is the same for input 1 or input 0.
[b] PWM Effect indicates the effect on the load current direction or the equivalent action.
[c] With SR disabled, braking is only effective in one direction when sufficient forward voltage is available to allow the diode to conduct.
9
955 Perimeter Road
pins), synchronous rectification turns on the MOSFET that is Several brake states are possible using combinations of inputs
complementary to the one that is turned off. This ensures that the on PWMH, PWML, and SR. For example, holding PWML and
current passes through the lower resistance MOSFET rather than SR high, while PWMH is low, turns on both low-side FETs to
the diode. short the load. The shorting path is always present and provides
braking in both directions of motor rotation. Another example is
When SR is low, synchronous rectification is disabled. In this holding SR low, when PWML is high and PWMH is low, mak-
case, fewer MOSFET switching cycles occur, reducing dissipa- ing only one low-side FET active, and the braking current flow
tion in the A3941. However, load current recirculates through the through the body diode of the opposite low-side FET. This pro-
higher resistance body diode of the power MOSFETs, causing vides braking in only one direction, because the diode does not
greater power dissipation in the power bridge. permit the braking current to flow if the motor is reversed. Also,
RESET Pin. This is an active-low input, and when active it the braking current can be made to circulate around the high-side
allows the A3941 to enter sleep mode. When RESET is held low, switches by swapping PWMH and PWML.
the regulator and all internal circuitry are disabled and the A3941
enters sleep mode. Before fully entering sleep mode, there is a
DIAGNOSTICS
short delay while the regulator decoupling and storage capacitors
discharge. This typically takes a few milliseconds, depending on Several diagnostic features are integrated into the A3941 to
the application conditions and component values. provide indication of fault conditions and, if required, take action
to prevent permanent damage. In addition to system-wide faults
During sleep mode, current consumption from the VBB supply such as undervoltage and overtemperature, the A3941 integrates
is reduced to a minimal level. In addition, latched faults and the individual drain-source monitors for each external FET, to pro-
corresponding fault flags are cleared. When the A3941 is coming vide short circuit detection.
out of sleep mode, the protection logic ensures that the gate drive
outputs are off until the charge pump reaches its correct operat-
ing condition. The charge pump stabilizes in approximately 3 ms DIAGNOSTIC MANAGEMENT PINS
under nominal conditions.
VDSTH Pin. Faults on the external FETs are determined by
RESET can be used also to clear latched fault flags without measuring the drain-source voltage, VDS , of each active FET
entering sleep mode. To do so, hold RESET low for less than the and comparing it to the threshold voltage applied to the VDSTH
reset pulse time, tRES. This clears any latched fault that disables input, VDSTH. To avoid false fault detection during switching
the outputs, such as short circuit detection or bootstrap capacitor transients, the comparison is delayed by an internal blanking
undervoltage. timer. If the voltage applied to the VDSTH pin is greater than the
disable threshold voltage, VDSDIS , then FET short circuit detec-
Note that the A3941 can be configured to start without any exter-
tion is disabled.
nal logic input. To do so, pull up the RESET pin to VBB by means
of an external resistor. The resistor value should be between VDRAIN Pin. This is a low current sense input from the top of the
20 and 33 kΩ. external FET bridge. This input allows accurate measurement of
the voltage at the drain of the high-side FETs. It should be con-
nected directly to the common connection point for the drains of
COAST AND BRAKE STATES the power bridge FETs at the positive supply connection point.
The input current to the VDRAIN pin is proportional to the volt-
To put the power bridge into a coast state, that is all power bridge age on the VDSTH pin and can be approximated by:
MOSFETs switched off, the two PWM inputs, PWMH and
PWML, must be held low and at the same time SR must be held IVDRAIN = 72 × VDSTH + 52 ,
low. This forces all gate drive outputs low. where IVDRAIN is the current into the VDRAIN pin, in µA, and
VDSTH is the voltage on the VDSTH pin, in V.
Braking is achieved by forcing the power bridge to apply a short
across the load, allowing the back EMF of the load to generate a FF1 and FF2 Pins. These are open drain output fault flags, which
braking torque. indicate fault conditions by their state, as shown in table 3. In
10
955 Perimeter Road
the event that two or more faults are detected simultaneously, the Bootstrap Capacitor Undervoltage. The A3941 monitors the
state of the fault flags will be determined by a logical OR of the voltage across the individual bootstrap capacitors to ensure they
flag states for all detected faults. have sufficient charge to supply the current pulse for the high-
side drive. Before a high-side drive can be turned on, the voltage
Table 3. Fault Definitions
across the associated bootstrap capacitor must be higher than the
Flag State Disable Fault turn-on voltage limit. If this is not the case, then the A3941 will
Fault Description
FF1 FF2 Outputs* Latched
start a bootstrap charge cycle by activating the complementary
Low Low No fault No – low-side drive. Under normal circumstances, this will charge the
Low High Short-to-ground Yes Yes bootstrap capacitor above the turn-on voltage in a few microsec-
Low High Short-to-supply Yes Yes onds and the high-side drive will then be enabled.
Low High Shorted load Yes Yes The bootstrap voltage monitor remains active while the high-side
High Low Overtemperature No No drive is active and, if the voltage drops below the turn-off volt-
High High V5 undervoltage Yes No age, a charge cycle is initiated.
High High VREG undervoltage Yes No In either case, if there is a fault that prevents the bootstrap capaci-
High High Bootstrap undervoltage Yes Yes tor charging, then the charge cycle will timeout, the fault flags
*Yes indicates all gate drives low, and all FETs off. (indicating an undervoltage) will be set, and the outputs will be
disabled. The bootstrap undervoltage fault state remains latched
until RESET is set low.
FAULT STATES
V5 Undervoltage. The output of the logic supply regulator
Overtemperature. If the junction temperature exceeds the over- voltage at V5 is monitored to ensure correct logical operation.
temperature threshold, typically 165°C, the A3941 will enter the If the voltage at V5, V5 , drops below the falling V5 undervolt-
overtemperature fault state and FF1 will go high. The overtem- age lockout threshold, V5UVoff , then the A3941 will enter the V5
perature fault state, and FF1, will only be cleared when the tem- undervoltage fault state. In this fault state, both FF1 and FF2 will
perature drops below the recovery level defined by TJF – TJFhys . be high, and the outputs will be disabled. In addition, because
No circuitry will be disabled. External control circuits must take the state of other reported faults cannot be guaranteed, all fault
action to limit the power dissipation in some way so as to prevent states and fault flags are reset and replaced by the fault flags cor-
overtemperature damage to the A3941 chip and unpredictable responding to a V5 undervoltage fault state. For example, a V5
device operation. undervoltage will reset an existing short circuit fault condition
and replace it with a V5 undervoltage fault. The V5 undervoltage
VREG Undervoltage. VREG supplies the low-side gate driver fault state and the fault flags will be cleared when V5 rises above
and the bootstrap charge current. It is critical to ensure that the the rising V5 undervoltage lockout threshold defined by V5UVoff
voltages are sufficiently high before enabling any of the outputs. + V5UVhys.
If the voltage at VREG, VREG , drops below the falling VREG
undervoltage lockout threshold, VREGUVoff , then the A3941 will The V5 undervoltage monitor circuit is active during power-up,
enter the VREG undervoltage fault state. In this fault state, both and the A3941 remains in the V5 undervoltage fault state until V5
FF1 and FF2 will be high, and the outputs will be disabled. The is greater than the rising VREG undervoltage lockout threshold,
VREG undervoltage fault state and the fault flags will be cleared V5UVoff +V5UVhys.
when VREG rises above the rising VREG undervoltage lockout Short Fault Operation. Shorts in the power bridge are deter-
threshold, VREGUVon.
mined by monitoring the drain-source voltage, VDS , of each
The VREG undervoltage monitor circuit is active during active FET and comparing it to the fault threshold voltage at the
power‑up, and the A3941 remains in the VREG undervoltage VDSTH pin. Because power MOSFETs take a finite time to reach
fault state until VREG is greater than the rising VREG undervolt- the rated on‑resistance, the measured drain-source voltages will
age lockout threshold, VREGUVon. show a fault as the phase switches. To avoid such false short fault
11
955 Perimeter Road
detections, the output from the comparators are ignored under The result of this comparison is ignored if the FET is not active.
two conditions: It also is ignored for one fault blank time interval after the FET is
turned on. If, when the comparator is not being ignored, its output
▪ while the external FET is off, and
▪ until the end of the period, referred to as the fault blank time, indicates that VDS exceeds the voltage at the VDSTH pin, then
after the FET is turned on. FF2 will be high.
When the FET is turned on, if the drain-source voltage exceeds Short to Ground. When VDSTH is less than the disable thresh-
the voltage at the VDSTH pin at any time after the fault blank old voltage, VDSDIS , a short from any of the motor phase con-
time, then a short fault will be detected. This fault will be latched nections to ground is detected by monitoring the voltage across
and the FET disabled until reset. the high-side FETs in each phase, using the appropriate Sx pin
and the voltage at VDRAIN. This drain-source voltage, VDS , is
In applications where short detection is not required, this feature
continuously compared to the voltage on the VDSTH pin. The
may be disabled by connecting VDSTH to V5 or by applying a
voltage greater than the disable threshold voltage, VDSDIS . This result of this comparison is ignored if the FET is not active. It
completely disables the VDS monitor circuits, preventing detec- also is ignored for one fault blank time interval after the FET is
tion of short faults and any indication of short faults by the fault turned on. If, when the comparator is not being ignored, its output
flags. In this condition the external FETs will not be protected by indicates that VDS exceeds the voltage at the VDSTH pin, FF2
the A3941. will be high.
Short to Supply. When VDSTH is less than the disable threshold Shorted Load. The short-to-ground and short-to-supply monitor
voltage, VDSDIS, a short from any of the motor phase connec- circuits will also detect a short across a motor phase winding. In
tions to the battery or VBB connection is detected by monitoring most cases, a shorted winding will be indicated by a high-side
the voltage across the low-side FETs in each phase, using the and low-side fault being detected at the same time. In some cases,
appropriate Sx pin and the LSS pin. This drain-source voltage, the relative impedances may permit only one of the shorts to be
VDS, is continuously compared to the voltage on the VDSTH pin. detected.
12
955 Perimeter Road
APPLICATIONS INFORMATION
POWER BRIDGE MANAGEMENT USING PWM
CONTROL GHA GHB GHA GHB
The A3941 provides two PWM control signals, a phase control LOAD LOAD
for current direction, and the ability to enable or disable syn- GLA GLB GLA GLB
chronous rectification. This allows a wide variety of full bridge
control schemes to be implemented. The six basic schemes are Driving Recirculating
shown in table 2 and described further below. Inputs Outputs Inputs Outputs
PWMH 1 Phase A B PWMH 0 Phase A B
Slow Decay. Slow decay is the simplest and most common PWML 1 PWML 1
GHx H L GHx H L
control configuration. Figure 1A shows the path of the bridge PHASE 1 PHASE 1
SR 0 GLx L H SR 0 GLx L H
and load current when a PWM signal is applied to PWMH, with
PWML and PHASE tied high, and SR low. (A) Slow decay, diode recirculation, high-side PWM
In this case the high-side MOSFETs are switched off during the
current decay time (PWM off-time) and load current recirculates
through the low-side MOSFETs. This is commonly referred to as
high-side chopping or high-side PWM. The recirculating current
flows through the body diode of the low-side MOSFET, which GHA GHB GHA GHB
is complementary to the high-side MOSFET being switched off. LOAD LOAD
Improved efficiency can be achieved by turning on the comple-
GLA GLB GLA GLB
mentary MOSFETs during the PWM off-time to short the reverse
diode and provide synchronous rectification. This can be easily
Driving Recirculating
achieved by taking SR high as shown in figure 1B.
Inputs Outputs Inputs Outputs
By applying the PWM signal to the PWML pin instead of the PWMH 1 Phase A B PWMH 0 Phase A B
PWML 1 PWML 1
PWMH pin, the low-side MOSFET is turned off during the PWM PHASE 1 GHx H L PHASE 1 GHx L L
off-time and the load current recirculates through the high-side SR 1 GLx L H SR 1 GLx H H
MOSFETs as in figure 1C.
(B) Slow decay, SR active, high-side PWM
In the three slow decay configurations shown, the direction of the
average current in the load can be reversed by simply applying a
low level to the PHASE pin. Referring to the slow decay entries
in table 2, when PHASE is high the average current flows from
the phase A connection (SA) to the phase B connection (SB).
When PHASE is low the direction is from B to A.
GHA GHB GHA GHB
Fast Decay. While slow decay usually provides sufficient control LOAD LOAD
over the load current for most simple control systems, it is pos- GLA GLB GLA GLB
sible that current control stability can be affected by, for example,
the back EMF of the load. In these cases, typically actuator posi- Driving Recirculating
tioning or servo control systems, it may be necessary to use fast Inputs Outputs Inputs Outputs
decay to provide continuous control over the load current. The PWMH 1 Phase A B PWMH 1 Phase A B
A3941 can be configured to provide fast decay using either diode PWML 1
GHx H L
PWML 0
GHx H H
PHASE 1 PHASE 1
recirculation or synchronous rectification. SR 1 GLx L H SR 1 GLx L L
Fast decay with diode recirculation is achieved by applying a

PWM signal at the same time to both PWM inputs, PWMH and (C) Slow decay, SR active, low-side PWM
PWML, with SR disabled (figure 2A). Because current recircu-
lation is through the body diodes of the MOSFETs, the aver- Figure 1. Slow decay power bridge current paths
13
955 Perimeter Road
age load current cannot be negative so, as for the slow decay
schemes, the PHASE input is still required to reverse the load
GHA GHB GHA GHB
current.
LOAD LOAD
Although fast decay with diode rectification provides a higher GLA GLB GLA GLB
degree of current control than slow decay schemes, it still may
not provide sufficient control for servo systems where full four- Driving Recirculating
quadrant control is required. This is only possible using fast Inputs Outputs Inputs Outputs
decay with synchronous rectification. By applying the PWM sig- PWML 1 PWML 0
GHx H L GHx L L
nal to the PHASE input, and holding PWMH and PWML and SR PHASE
SR
1
0 GLx
PHASE
SR
1
0 GLx
L H L L
high (figure 2B), the load current can be controlled in both direc-
(A) Fast decay, diode recirculation
tions with a single PWM signal. Because all four MOSFETs in
the bridge change state, the supply can be directly applied to the
load in either direction. The effect is: when the PWM duty cycle
is less than 50%, the average current flows from B to A; when
GHA GHB GHA GHB
greater than 50%, the average current flows from A to B; and
LOAD LOAD
when at 50%, the average current is zero. This allows the load
GLA GLB GLA GLB
current to be independent of any back EMF voltage generated, for
example by a rotating motor, and effectively allowing the applied Driving Recirculating
torque to work with or against a motor in either direction. Inputs Outputs Inputs Outputs
Synchronous Rectification. Synchronous rectification is used to PWML 1 PWML 1
PHASE 1 GHx H L PHASE 0 GHx L H
reduce power dissipation in the external MOSFETs. As described SR 1 GLx L H SR 1 GLx H L
above, the A3941 can be instructed to turn on the appropriate
(B) Fast decay, SR active, full four-quadrant control
low-side and high-side driver during the load current recirculation
Figure 2. Fast decay power bridge current paths
PWM off-cycle. During the decay time, synchronous rectifica-
tion allows current to flow through the selected MOSFET, rather
than through the source-drain body diode. The body diodes of the 4.5
recirculating power MOSFETs will conduct only during the dead
4.0
time that occurs at each PWM transition.
3.5
3.0
DEAD TIME
t DEAD (µs)
2.5
To prevent cross-conduction (shoot through) in any phase of
the power FET bridge, it is necessary to have a dead time delay, 2.0
tDEAD , between a high-side or low-side turn-off and the next 1.5
complementary turn-on event. The potential for cross-conduction
1.0
occurs when any complementary high-side and low-side pair of
FETs are switched at the same time; for example, when using 0.5
synchronous rectification or after a bootstrap capacitor charg- 0
ing cycle. In the A3941, the dead time for both phases is set by 0 50 100 150 200 250 300 350 400 450
RDEAD (kΩ)
a single dead-time resistor, RDEAD , between the RDEAD and
AGND pins. Figure 3. Dead time versus RDEAD , (full range)
14
955 Perimeter Road
For RDEAD values between 3 kΩ and 240 kΩ, at 25°C the nomi- PWML=0). This effectively short-circuits the back EMF of the
nal value of tDEAD in ns can be approximated by: motor, creating a breaking torque.
7200 During braking, the load current can be approximated by:
tDEAD(nom) = 50 + , (1)
1.2 + (200 / RDEAD) VBEMF
IBRAKE = , (3)
where RDEAD is in kΩ. Greatest accuracy is obtained for values RL

of RDEAD between 6 and 60 kΩ, which are shown in figure 3.
where VBEMF is the voltage generated by the motor and RL is the
The IDEAD current can be estimated by: resistance of the phase winding.
1.2
IDEAD = . (2) Care must be taken during braking to ensure that maximum rat-
RDEAD ings of the power FETs are not exceeded. Dynamic braking is
The maximum dead time, 6 µs typical, can be set by connecting equivalent to slow decay with synchronous rectification.
the RDEAD pin directly to the V5 pin.
The choice of power FET and external series gate resistance BOOTSTRAP CAPACITOR SELECTION
determine the selection of the dead-time resistor, RDEAD. The
dead time should be long enough to ensure that one FET in a The bootstrap capacitors, CBOOTx, must be correctly selected to
phase has stopped conducting before the complementary FET ensure proper operation of the A3941. If the capacitances are too
starts conducting. This should also take into account the tolerance high, time will be wasted charging the capacitor, resulting in a
and variation of the FET gate capacitance, the series gate resis- limit on the maximum duty cycle and the PWM frequency. If the
tance, and the on-resistance of the A3941 internal drives. capacitances are too low, there can be a large voltage drop at the
time the charge is transferred from CBOOTx to the FET gate, due
Dead time will be present only if the on-command for one FET
to charge sharing.
occurs within tDEAD after the off-command for its complementary
FET. In the case where one side of a phase drive is permanently To keep this voltage drop small, the charge in the bootstrap
off, for example when using diode rectification with slow decay, capacitor, QBOOT, should be much larger than the charge required
then the dead time will not occur. In this case the gate drive will by the gate of the FET, QGATE. A factor of 20 is a reasonable
turn on within the specified propagation delay after the corre- value, and the following formula can be used to calculate the
sponding phase input goes high. (Refer to the Gate Drive Timing value for CBOOT :
diagrams.)
QBOOT = CBOOT × VBOOT = QGATE × 20 ,

FAULT BLANK TIME therefore:
QGATE × 20
To avoid false short fault detection, the output from the VDS CBOOT = ,
monitor for any FET is ignored when that FET is off and for a VBOOT (4)

period of time after it is turned on. This period of time is the fault where VBOOT is the voltage across the bootstrap capacitor.
blank time. Its length is the dead time, tDEAD , plus an additional
period of time that compensates for the delay in the VDS moni- The voltage drop across the bootstrap capacitor as the FET is
tors. This additional delay is typically 300 to 600 ns. being turned on, ∆V , can be approximated by:
QGATE
∆V ≈ . (5)
CBOOT
BRAKING
So, for a factor of 20, ∆V would be approximately 5% of VBOOT .
The A3941 can be used to perform dynamic braking either by
forcing all low-side FETs on and all high-side FETs off (SR=1, The maximum voltage across the bootstrap capacitor under
PWMH=0, and PWML=1) or conversely by forcing all low- normal operating conditions is VREG(max). However, in some
side FETs off and all high-side FETs on (SR=1, PWMH=1, and circumstances the voltage may transiently reach 18 V, the clamp
15
955 Perimeter Road
voltage of the Zener diodes between the Cx and Sx pins. In most capacitors. When a low-side FET is turned on, the gate-drive
applications, with a good ceramic capacitor the working voltage circuit will provide the high transient current to the gate that is
can be limited to 16 V. necessary to turn on the FET quickly. This current, which can be
several hundred milliamperes, cannot be provided directly by the
limited output of the VREG regulator, and must be supplied by an
BOOTSTRAP CHARGING external capacitor connected to VREG.
It is good practice to ensure the high-side bootstrap capacitor is
The turn-on current for the high-side FET is similar in value to
completely charged before a high-side PWM cycle is requested.
that for the low-side FET, but is mainly supplied by the boot-
The time required to charge the capacitor, tCHARGE (µs), is
approximated by: strap capacitor. However, the bootstrap capacitor must then be
recharged from the VREG regulator output. Unfortunately, the
CBOOT × ∆V
tCHARGE = , (6) bootstrap recharge can occur a very short time after the low-
100 side turn-on occurs. This requires that the value of the capacitor
where CBOOT is the value of the bootstrap capacitor, in nF, and connected between VREG and AGND should be high enough to
∆V is the required voltage of the bootstrap capacitor. minimize the transient voltage drop on VREG for the combina-
At power-up and when the drives have been disabled for a long tion of a low-side FET turn-on and a bootstrap capacitor recharge.
time, the bootstrap capacitor can be completely discharged. In A value of 20 × CBOOT is a reasonable value. The maximum
this case ∆V can be considered to be the full high-side drive working voltage will never exceed VREG , so the capacitor can be
voltage, 12 V. Otherwise, ∆V is the amount of voltage dropped rated as low as 15 V. This capacitor should be placed as close as
during the charge transfer, which should be 400 mV or less. possible to the VREG pin.
The capacitor is charged whenever the Sx pin is pulled low and
current flows from VREG through the internal bootstrap diode
circuit to CBOOT. SUPPLY DECOUPLING
Because this is a switching circuit, there are current spikes from all
BOOTSTRAP CHARGE MANAGEMENT supplies at the switching points. As with all such circuits, the power
supply connections should be decoupled with a ceramic capacitor,
The A3941 provides automatic bootstrap capacitor charge typically 100 nF, between the supply pin and ground. These capaci-
management. The bootstrap capacitor voltage for each phase tors should be connected as close as possible to the device supply
is continuously checked to ensure that it is above the bootstrap
pins VBB and V5, and the ground pin, GND.
under-voltage threshold, VBOOTUV. If the bootstrap capacitor volt-
age drops below this threshold, the A3941 will turn on the neces-
sary low-side FET, and continue charging until the bootstrap
POWER DISSIPATION
capacitor exceeds the undervoltage threshold plus the hysteresis,
VBOOTUV + VBOOTUVhys. The minimum charge time is typically In applications where a high ambient temperature is expected, the
7 µs, but may be longer for very large values of bootstrap capaci- on-chip power dissipation may become a critical factor. Careful
tor (>1000 nF). If the bootstrap capacitor voltage does not reach attention should be paid to ensure the operating conditions allow
the threshold within approximately 200 µs, an undervoltage fault the A3941 to remain in a safe range of junction temperature.
will be flagged.
The power consumed by the A3941, PD, can be estimated by:
PD = PBIAS + PCPUMP + PSWITCHING ,
VREG CAPACITOR SELECTION (7)
given:
The internal reference, VREG, supplies current for the low-side
gate drive circuits and the charging current for the bootstrap PBIAS = VBB × IBB ; (8)
16
955 Perimeter Road
PCPUMP = [( 2 VBB) – VREG] IAV , for VBB < 15 V, • Sensitive connections such as RDEAD and VDSTH, which
or have very little ground current, should be connected to the Quiet
= [VBB – VREG] IAV , for VBB ≥ 15 V, ground (refer to figure 4), which is connected independently,
(9) closest to the GND pin. These sensitive components should
PSWITCHING = QGATE × VREG × N × fPWM × Ratio ; (10) never be connected directly to the supply common or to a
where: common ground plane. They must be referenced directly to the
IAV = QGATE × N × fPWM , GND pin.

N is the number of FETs switching during a PWM cycle, and • The supply decoupling for VBB, VREG, and V5 should
10 be connected to the Controller Supply ground, which is
Ratio = .
RGATE + 10 independently connected close to the GND pin. The decoupling
N = 1 for slow decay with diode recirculation, N = 2 for slow decay capacitors should also be connected as close as practicable to
with synchronous rectification or for fast decay with diode recir- the relevant supply pin.
culation, and N = 4 for fast decay with synchronous rectification. • If layout space is limited, then the Quiet and Controller Supply
grounds may be combined. In this case, ensure that the ground
return of the dead time resistor is close to the GND pin.
LAYOUT RECOMMENDATIONS • Check the peak voltage excursion of the transients on the LSS
Careful consideration must be given to PCB layout when design- pin with reference to the GND pin, using a close grounded (tip
ing high frequency, fast switching, high current circuits. The and barrel) probe. If the voltage at LSS exceeds the absolute
following are recommendations regarding some of these consid- maximum shown in this datasheet, add either or both of
erations: additional clamping and capacitance between the LSS pin and
• The A3941 ground, GND, and the high-current return of the the GND pin, as shown in figure 4.
external FETs should return separately to the negative side • Gate charge drive paths and gate discharge return paths may
of the motor supply filtering capacitor. This will minimize carry a large transient current pulse. Therefore, the traces from
the effect of switching noise on the device logic and analog GHx, GLx, Sx, and LSS should be as short as possible to reduce
reference. the circuit trace inductance.
• The exposed thermal pad should be connected to the GND • Provide an independent connection from LSS to the common
pin and may form part of the Controller Supply ground (see point of the power bridge. It is not recommended to connect
figure 4). LSS directly to the GND pin, as this may inject noise into
• Minimize stray inductance by using short, wide copper traces at
sensitive functions such as the timer for dead time.
the drain and source terminals of all power FETs. This includes
• A low-cost diode can be placed in the connection to VBB to
motor lead connections, the input power bus, and the common
source of the low-side power FETs. This will minimize voltages provide reverse battery protection. In reverse battery conditions,
induced by fast switching of large load currents. it is possible to use the body diodes of the power FETs to clamp
• Consider the use of small (100 nF) ceramic decoupling the reverse voltage to approximately 4 V. In this case, the
capacitors across the sources and drains of the power FETs to additional diode in the VBB connection will prevent damage
limit fast transient voltage spikes caused by the inductance of to the A3941 and the VDRAIN input will survive the
the circuit trace. reverse voltage.
• Keep the gate discharge return connections Sx and LSS as short
as possible. Any inductance on these traces will cause negative Note that the above are only recommendations. Each application
transitions on the corresponding A3941 pins, which may exceed is different and may encounter different sensitivities. A driver
the absolute maximum ratings. If this is likely, consider the use running a few amps will be less susceptible than one running with
of clamping diodes to limit the negative excursion on these pins 150 A, and each design should be tested at the maximum current
with respect to GND. to ensure any parasitic effects are eliminated.
17
955 Perimeter Road
Optional reverse
battery protection
VBB VDRAIN
+ Supply
GHB
VREG
GHA
A3941
VS SA
SB
Motor
GLA
VDSTH
GLB
RDEAD
LSS
GND
RS
Optional components
Quiet Ground
to limit LSS transients Supply
Power Ground
Common
Controller Supply Ground
Figure 4. Supply routing suggestions
Input and Output Structures

CP1 CP2 VDRAIN VBB VS
VBB Cx
20 V
18 V
19 V ESD
18 V
GHx 18 V
19 V
18 V 18 V 6V
20 V
Sx (B) Supply protection structures
VREG
ESD
18 V 18 V
GLx 10 Ω 3 kΩ
FFx RESET
LSS 50 kΩ
6V 6V
(A) Gate drive outputs (C) Fault output (D) RESET input
ESD ESD ESD
1.2 V
PWMx 3 kΩ 1 kΩ 100 Ω
SR VDSTH RDEAD
PHASE
8.5 V 8.5 V 8.5 V
(E) Logic inputs, no pulldown (F) VDS monitor threshold input (G) RDEAD
18
955 Perimeter Road
Pinout Diagram
VDRAIN 1 28 VDSTH
LSS 2 tDEAD 27 RDEAD
GLB 3 26 FF2
SB 4 25 FF1
GHB 5 24 RESET
CB 6 23 PWMH
Control Logic
VREG 7 22 PWML
Reg
VREG 8 21 SR
CA 9 Reg 20 V5
GHA 10 19 PHASE
SA 11 18 GND
GLA 12 17 GND
VBB 13 Charge 16 CP1
Pump
VBB 14 15 CP2
Terminal List
Number Name Description Number Name Description
1 VDRAIN High-side common drain 16 CP1 Pump capacitor
2 LSS Low-side common source 17 GND Ground
3 GLB Low-side gate drive B 18 GND Ground
4 SB Load connection B 19 PHASE Phase control input
5 GHB High-side gate drive B 20 V5 5 V regulator
6 CB Bootstrap capacitor B 21 SR SR control input
7 VREG Regulated 13 V 22 PWML Low-side PWM control input
8 VREG Regulated 13 V 23 PWMH High-side PWM control input
9 CA Bootstrap capacitor A 24 RESET Reset input
10 GHA High-side gate drive A 25 FF1 Fault Flag 1 output
11 SA Load connection A 26 FF2 Fault Flag 2 output
12 GLA Low-side gate drive A 27 RDEAD Dead time setting input
13 VBB Main supply 28 VDSTH VDS threshold level Input
14 VBB Main supply Exposed pad for enhanced thermal
– PAD
15 CP2 Pump capacitor dissipation (underside)
19
955 Perimeter Road
Package LP 28-Pin TSSOP with Exposed Thermal Pad

For Reference Only – Not for Tooling Use
(Reference Allegro DWG-0000379, Rev. 3 and JEDEC MO-153AET)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
9.70 ±0.10
5.08 NOM 8º
0º
28
0.20
0.09
B
3 NOM 4.40±0.10 6.40±0.20
0.60 ±0.15 1.00 REF

1 2
Branded Face
0.25 BSC
28X C
1.20 MAX
0.10 C SEATING SEATING PLANE
PLANE GAUGE PLANE
0.30 0.65 BSC 0.15
0.19 0.025
0.45 0.65
28 XXXXXXX
Date Code
1.65 Lot Number
D Standard Branding Reference View
3.00 6.10 Lines 1, 2, 3 = 10 characters
Line 1: Part Number

Line 2: Logo A, 4-digit Date Code
Line 3: Characters 5, 6, 7, 8 of
Assembly Lot Number
1 2 A Terminal #1 mark area

5.00 B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
C PCB Layout Reference View All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Branding scale and appearance at supplier discretion.
20
955 Perimeter Road
REVISION HISTORY
Number Date Description
6 December 23, 2013 Update IDSTH
7 May 8, 2019 Minor editorial updates
8 May 11, 2022 Updated package drawing (page 20) and minor editorial updates
Copyright 2022, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:

21
955 Perimeter Road

A3941 Datasheet

Uploaded by

Copyright:

Available Formats

A3941 Datasheet

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

A3941 Datasheet

Uploaded by

Copyright:

Available Formats

A3941

Automotive Full Bridge MOSFET Driver

FEATURES AND BENEFITS DESCRIPTION

3941-DS, Rev. 8 May 11, 2022

ABSOLUTE MAXIMUM RATINGS*

*With respect to GND.

THERMAL CHARACTERISTICS: May require derating at maximum conditions

*Additional thermal information available on Allegro website.

Functional Block Diagram

VBB CP2 CP1

PWMH Low GLA

ELECTRICAL CHARACTERISTICS: Valid at TJ = –40°C to 150°C, VBB = 7 to 50 V, unless noted otherwise

Continued on the next page…

Gate Drive Timing – PWM inputs, Slow Decay, Synchronous Rectification

tP(off) tP(off) tP(off) tP(off)

GLx tDEAD tDEAD GLx tDEAD tDEAD

SR=1, PWML=1 SR=1, PWMH=1

Gate Drive Timing – PWM inputs, Slow Decay, Diode Rectification

tP(off) tP(on) tP(off) tP(on)

SR=0, PWML=1 SR=0, PWMH=1

tP(off) tP(off) PWML

tDEAD tDEAD tP(off) tP(on)

PWML=1, PWMH=1 PHASE=1

Table 1. Phase Control Truth Table

Table 2. PWM Options

Fast decay with diode recirculation is achieved by applying a

Figure 4. Supply routing suggestions

Input and Output Structures

ESD ESD ESD

8.5 V 8.5 V 8.5 V

Package LP 28-Pin TSSOP with Exposed Thermal Pad

0.60 ±0.15 1.00 REF

D Standard Branding Reference View

3.00 6.10 Lines 1, 2, 3 = 10 characters

Line 1: Part Number

1 2 A Terminal #1 mark area

Copyright 2022, Allegro MicroSystems.

For the latest version of this document, visit our website:

You might also like