A6862

Automotive 3-Phase Isolator MOSFET Driver

FEATURES AND BENEFITS DESCRIPTION

• Three floating N-channel MOSFET drives The A6862 is an N-channel power MOSFET driver capable
• Maintains VGS with 100 kΩ gate-source resistors of controlling MOSFETs connected as a 3-phase solid-state
• Integrated charge pump controller relay in phase-isolation applications. It has three independent
• 4.5 to 50 V supply voltage operating range floating gate drive outputs to maintain the power MOSFETs in
• Two independent activation inputs the on-state over the full supply range with high phase-voltage
• Single phase-enable input slew rates. An integrated charge pump regulator provides the
• VCP and VGS undervoltage protection above battery supply voltage necessary to maintain the power
• 150°C ambient (165°C junction) continuous MOSFETs in the on-state continuously when the phase voltage
is equal to the battery voltage. The charge pump will maintain
APPLICATIONS sufficient gate drive (>7.5 V) for battery voltages down to 4.5 V
• 3-phase disconnect for up to ASIL D level systems with 100 kΩ gate source resistors.
• Electric power steering (EPS) The three gate drives can be controlled by a single logic-level
• Electric braking input. In typical applications, the MOSFETs will be switched
• 3-phase solid-state relay driver on within 8 µs and will switch off within 1 µs.
Two independent activation inputs can be used to put the A6862
PACKAGE: into a low-power sleep mode with the charge pump disabled.
16-lead TSSOP with exposed thermal pad (suffix LP) Undervoltage monitors check that the pumped supply voltage
and the gate drive outputs are high enough to ensure that the
MOSFETs are maintained in a safe conducting state.
The A6862 is supplied in a 16-lead TSSOP (LP) with exposed
pad for enhanced thermal dissipation. They are lead (Pb) free,
Not to scale with 100% matte-tin leadframe plating.

VBAT
A4405
Regulator

A4910
3-Phase
A4935
BLDC
Micro- A4937 Motor
Controller A4939

A6862

Figure 1: Typical Application Diagram

A6862-DS, Rev. 4 April 13, 2022

MCO-0000285
A6862 Automotive 3-Phase Isolator MOSFET Driver

SELECTION GUIDE
Part Number Packing Package
A6862KLPTR-T 4000 pieces per 13-inch reel 16-lead TSSOP with exposed thermal pad, 4.4 mm × 5 mm case

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS [1]

Characteristic Symbol Notes Rating Units
Load Voltage Supply VBB –0.3 to 50 V
VBB – 0.3 to
Terminal VCP VCP V
VBB + 12
VBB – 12 to
Terminal CP1 VCP1 V
VBB + 0.3
VBB – 0.3 to
Terminal CP2 VCP2 V
VCP4 + 0.3
VBB – 12 to
Terminal CP3 VCP3 V
VBB + 0.3
VCP2 – 0.3 to
Terminal CP4 VCP4 V
VCP + 0.3
Terminal IG, POK, ENA VI –0.3 to 50 V
VSX – 0.3 to
Terminal GU, GV, GW VGX V
VSX + 12
Terminal SU, SV, SW VSX –6 to 55 V
Operating Ambient Temperature TA Limited by power dissipation –40 to 150 °C
Maximum Continuous Junction Temperature TJ(max) 165 °C
Overtemperature event not exceeding 10 seconds;
Transient Junction Temperature TJt lifetime duration not exceeding 10 hours; 175 °C
guaranteed by design characterization.
Storage Temperature Tstg –55 to 150 °C

[1] With respect to GND. Ratings apply when no other circuit operating constraints are present.

THERMAL CHARACTERISTICS: May require derating at maximum conditions

Characteristic Symbol Test Conditions [2] Value Units

Package Thermal Resistance 4-layer PCB based on JEDEC standard 34 °C/W

RθJA
(Junction to Ambient) 1-layer PCB with copper limited to solder pads 43 °C/W
Package Thermal Resistance
RθJP 2 °C/W
(Junction to Pad)

[2] Additional thermal data available on the Allegro Web site.

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A6862 Automotive 3-Phase Isolator MOSFET Driver

PINOUT DIAGRAM AND TERMINAL LIST TABLE

VBB 1 16 VCP
CP4 2 15 GU
CP3 3 14 SU
CP2 4 13 GV
PAD
CP1 5 12 SV
IG 6 11 GW
POK 7 10 SW
ENA 8 9 GND

Package LP, 16-Pin TSSOP Pinout Diagram

Terminal List Table

Name Number Description
CP1 5 Pump capacitor connection
CP2 4 Pump capacitor connection
CP3 3 Pump capacitor connection
CP4 2 Pump capacitor connection
ENA 8 Phase enable input
GND 9 Ground
GU 15 U-phase MOSFET gate drive
GV 13 V-phase MOSFET gate drive
GW 11 W-phase MOSFET gate drive
IG 6 Ignition input
POK 7 Power OK input
SU 14 U-phase MOSFET source reference
SV 12 V-phase MOSFET source reference
SW 10 W-phase MOSFET source reference
VBB 1 Main power supply
VCP 16 Pumped supply
PAD – Exposed pad; connect to GND

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A6862 Automotive 3-Phase Isolator MOSFET Driver

FUNCTIONAL BLOCK DIAGRAM

Battery

VCP
VCP Bridge
Mon VCP
C VCP
Floating GU
VBB Gate-Drive
Mon
Reverse CP4
SU
Protected Motor
CCP2
Supply
CP3 Charge Pump
CP2 VCP Bridge
CCP1
CP1 Floating GV
Gate-Drive
GND
IG Mon
To Ignition Switch
SV
Motor

POK
To Logic Power Monitor VCP Bridge

Level Floating GW
ENA Shift Gate-Drive
Mon
Voltage SW
Motor
Monitors
VOLF

GND

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A6862 Automotive 3-Phase Isolator MOSFET Driver

ELECTRICAL CHARACTERISTICS: Valid at TJ = –40 to 150°C, VBB = 4.5 to 50 V, unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Units
SUPPLY
Operating; outputs active 4.5 – 50 V
VBB Functional Operating Range [1] VBB Operating; outputs disabled 4 – 50 V
No undefined states 0 – 50 V
IBB Gate drive active, VBB = 12 V – 11 15 mA
VBB Supply Current IBBQ Gate drive inactive, VBB = 12 V – 6 9 mA
IBBS IG or POK < 0.8 V, VBB = 12 V – – 10 µA
VBB > 9 V, IVCP > –1 mA [2] 9 10 11 V
VCP Output Voltage w.r.t. VBB VCP 6 V < VBB ≤ 9 V, IVCP > –1 mA  [2] 8 10 11 V
4.5 V < VBB ≤ 6 V, IVCP > –800 µA [2] 7.5 9.5 – V
VCP Static Load Resistor RCP Between VCP and VBB (using ±1% tolerance resistor) 100 – – kΩ
GATE DRIVE
Turn-On Time tr CLOAD = 10 nF, 20% to 80% – 5 – µs
Turn-Off Time tf CLOAD = 10 nF, 80% to 20% – 0.5 – µs
Propagation Delay – Turn On [3] tPON CLOAD = 10 nF, ENx high to Gx 20% – – 3 µs
Propagation Delay – Turn Off [3] tPOFF CLOAD = 10 nF, ENx low to Gx 80% – – 2.25 µs
Turn-On Pulse Current IGXP 8.5 10 12 mA
Turn-On Pulse Time tGXP 16 – 36 µs
On Hold Current IGXH – 400 – μA
TJ = 25°C, IGx= 10 mA – 5 – Ω
Pull-Down On Resistance RDS(on)DN
TJ = 150°C, IGx = 10 mA – 10 – Ω
VBB > 9 V 9 10 12 V
Gx Output High Voltage w.r.t. SX,
VGH 6 V < VBB ≤ 9 V 8 10 12 V
when SX ≤ VBB
4.5 V < VBB ≤ 6 V 7.5 9.5 – V
Gate Drive Static Load Resistor RGS Between Gx and Sx (using ±1% tolerance resistor) 100 – – kΩ
Gx Output Voltage Low VGL –10 µA < IGx < 10 µA – – VSX + 0.3 V
Gx Passive Pull-Down RGPD VGx – VSx < 0.3 V – 950 – kΩ

Continued on next page...

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A6862 Automotive 3-Phase Isolator MOSFET Driver

ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40 to 150°C, VBB = 4.5 to 50 V, unless noted otherwise
Characteristics Symbol Test Conditions Min. Typ. Max. Units
LOGIC INPUTS AND OUTPUTS
ENA Input Low Voltage VIL – – 0.4 V
ENA Input High Voltage VIH 0.7 – – V
ENA Input Hysteresis VIhys 120 200 – mV
ENA Input Pull-Down Resistor RPD – 100 – kΩ
ENA Output Low Voltage VOLF Any VGS or VCP undervoltage, IOL = –0.5 mA [2] 1.1 1.0 0.9 V
POK, IG Input High Voltage VIH 2.0 – – V
POK, IG Input Low Voltage VIL – – 0.8 V
POK, IG Input Pull-Down Resistor RPD – 100 – kΩ
DIAGNOSTICS AND PROTECTION
VGS Undervoltage Threshold Rising VGSUV 6.0 – 7.0 V
VGS Undervoltage Threshold
VGShys – 200 – mV
Hysteresis
VGS Undervoltage Filter Time tGSUV 3.7 – 18 µs
VCP Undervoltage Filter Time tCPUV – 12.5 – µs
VCP Startup Blank Timer tCPON – 100 – µs
VCPON VCP w.r.t. VBB, VCP rising 6.5 7.0 7.5 V
VCP Undervoltage Lockout
VCPOFF VCP w.r.t. VBB, VCP falling 6.25 6.75 7.25 V

[1] Function is correct but parameters are not guaranteed below the general limits (4.5 to 50 V).
[2] Forinput and output current specifications, negative current is defined as coming out of (sourcing) the specified device terminal.
[3] Refer to Figure 2.

ENA

tPON tPOFF

80% 80%

VGSx

20% 20%

tr tf

Figure 2: Enable Input to VGS Timing

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A6862 Automotive 3-Phase Isolator MOSFET Driver

FUNCTIONAL DESCRIPTION
The A6862 is an N-channel power MOSFET driver capable of Input and Output Terminal Functions
controlling MOSFETs connected as a 3-phase solid-state relay
VBB: Main power supply. The main power supply should be
in phase-isolation applications. It has three independent floating
connected to VBB through a reverse voltage protection circuit.
gate drive outputs to maintain the power MOSFETs in the
on-state or the off-state over the full supply range when the phase GND: Main power supply return. Connect to supply ground.
outputs are PWM switched with high phase-voltage slew rates. VCP: Pumped gate drive voltage. Can be used to turn on a
The three gate drives can be controlled by a single logic-level MOSFET connected to the main supply, to provide reverse
battery protection. Connect a 1 µF ceramic capacitor between
signal on the enable input. In typical applications, the MOSFETs
VCP and VBB.
will be switched on within 8 µs and will switch off within 1 µs.
The enable input can also be used as an open-drain output to CP1, CP2: Pump capacitor connections. Connect a 330 nF
indicate that the charge pump regulator is undervoltage. ceramic capacitor between CP1 and CP2.

A charge pump regulator provides the above-battery supply CP3, CP4: Pump capacitor connections. Connect a 330 nF
voltage necessary to maintain the power MOSFETs in the ceramic capacitor between CP3 and CP4.
on-state continuously when the phase voltage is equal to the ENA: Logic-level input to control all three gate drive outputs.
battery voltage. Voltage regulation is based on the difference Pulled to VOLF by open-drain output if VCP or any VGSx is
between VBB and VCP . undervoltage. Battery voltage compliant terminal.

The charge pump will maintain sufficient gate drive (>7.5 V) POK: Logic-level input to control the pump regulator activity.
for battery voltages down to 4.5 V. It is also able to provide the Both POK and IG must be high to enable the charge pump.
Battery voltage compliant terminal.
current taken by gate source resistors as low as 100 kΩ, should
they be required, between the source and gate of the power IG: Logic-level input to control the pump regulator activity. Both
MOSFETs. POK and IG must be high to enable the charge pump. Battery
voltage compliant terminal.
The voltage generated by the charge pump can also be used
to power circuitry to control the gate source voltage for a GU, GV, GW: Floating gate drive outputs for external N-channel
MOSFET connected to the main supply to provide reverse battery MOSFETs.
protection. SU, SV, SW: Load phase connections. These terminals are the
reference connections for the floating gate drive outputs.
Two independent activation inputs can be used to disable
the charge pump and put the A6862 into a low-power sleep Power Supplies
mode. These two inputs can be driven by logic-level signals or
A single reverse polarity protected power supply voltage is
connected directly to other systems supplies including the main required. It is recommended to decouple the supply with ceramic
battery supply through an external reverse protection diode. capacitors connected close to the supply and ground terminals.
Undervoltage monitors check that the pumped supply voltage The A6862 will operate within specified parameters with
and the gate drive outputs are high enough to ensure that the VBB from 4.5 to 50 V and can maintain the external isolator
MOSFETs are maintained in a safe conducting state. If the MOSFETs in the off condition down to 4.0 V. The A6862 will
pumped supply voltage or any gate drive output voltage is less operate without any undefined states down to 0 V to ensure
than the undervoltage threshold, the enable input ENA will be deterministic operation during power-up and power-down events.
pulled low by an open-drain output. As the supply voltage rises from 0 V, the gate drive outputs are
maintained in the off-state until the gate voltage is sufficiently
All logic inputs can be shorted to the main positive battery supply high to ensure conduction and the outputs are enabled.
voltage without damage, even during a load dump up to 50 V.
This provides a very rugged solution for use in the harsh
automotive environment and permits use in start-stop systems.

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A6862 Automotive 3-Phase Isolator MOSFET Driver

Pump Regulator voltage of the MOSFET is held close to 0 V even with the power
disconnected. This can remove the need for additional gate source
The gate drivers are powered by a regulated charge pump, which resistors on the isolation MOSFETs. If gate source resistors
provides the voltage above VBB to ensure that the MOSFETs are are mandatory for the application, then the pump regulator
fully enhanced with low on-resistance when the source of the can provide sufficient current to maintain the MOSFET in the
MOSFET is at the same voltage as VBB. on-state with a gate source resistor of as low as 100 kΩ using 1%
Voltage regulation is based on the difference between the VBB tolerance resistors.
and VCP pins. The floating gate drive outputs for external N-channel MOSFETs
The pumped voltage, VCP, is available at the VCP terminal and is are provided on pins GU, GV, and GW. The reference points
limited to 12 V maximum with respect to VBB. This removes the for the floating drives are the load phase connections: SU, SV,
need for external clamp diodes on the power MOSFETs to limit and SW. The discharge current from the floating MOSFET gate
the gate source voltage. capacitance flows through these connections.
It also allows the VCP terminal to be used to power circuitry When ENA goes high, the upper-half of all of the drivers are turned
to control MOSFETs connected to the main supply to provide on (low sides are turned off) and a current (IGXP) will be sourced
reverse battery protection and supply isolation. to the gate, for a period of time defined between tGXP . After this
period, an “on hold current” (IGXH) will be sourced to the gates of
To provide the continuous low-level current required when gate the MOSFETs to keep them switched on. See Figure 3.
source resistors are connected to the external MOSFETs, a pump
storage capacitor, typically 1 µF, must be connected between the When ENA goes low, the lower half of the drivers are turned on
VCP and VBB terminals. Pump capacitors, typically 330 nF, must (high side is turned off) and will sink current from the external
be connected between the CP1 and CP2 terminals and between MOSFET’s gates to the respective Sx terminal, turning them off.
the CP3 and CP4 terminals to provide sufficient charge transfer, See Figure 3.
especially at low supply voltage. If driving MOSFETs with a
total charge above 400 nC, larger value capacitors (charge pump VCP
capacitors and CVCP) may be necessary. 10 mA
Typ

Positive-edge
The charge pump can be disabled by pulling either the POK or one shot 0.40 mA
the IG terminal low. This will cause VCP to reduce to zero, the 16-36 µs Typ

outputs to switch off, and the A6862 to enter a low-power sleep

mode with minimum supply current. GU
GV
Gate Drives GW

The A6862 is designed to drive external, low on-resistance, ENA

11V
power N-channel MOSFETs when used in a phase isolation SU
SV
application. The gate drive outputs and the VCP supply will
SW
turn the MOSFETs on in typically 8 µs and will maintain the
on-state during transients on the source of the MOSFETs. The
Figure 3: Operational Output Drive
gate drive outputs will turn the MOSFETs off in typically 1 µs
and will hold them in the off-state during transients on the source.
An integrated hold-off circuit will ensure that the gate source

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A6862 Automotive 3-Phase Isolator MOSFET Driver

Recirculation Current Path the Schottky diode. This will turn on the external MOSFET enough
to draw current through the MOSFET. If the bridge is still on,
In most applications, it will be necessary to provide a current current will come from the positive supply, or if it is off, the current
recirculation path when the motor load is isolated. This will be will come from the bridge low-side body diode. If the current is
necessary when the motor driver does not reduce the load current flowing from the motor to the bridge and the MOSFET is switched
to zero before the isolation MOSFETs are turned off. off, the motor inductance will force the voltage on the source pin
There are two ways of connecting the external MOSFETs to the up and the body diode will conduct. If the bridge is still on, the
motor: with the source connected to the bridge or supply (see current will come from the ground, or if it is off, the current will
Figure 4), and conversely with the source connected to the motor come from the bridge high-side body diode.
or load (see Figure 5 and Figure 6). All methods require one diode
Bridge Supply
per phase.
High Power
In the case when the Bridge or supply is connected to the source Diode
(see Figure 4). When the current is flowing from bridge to the Motor
motor and the MOSFET is switch off, the motor inductance will try
to force the voltage on the drain pin down. This will draw current G
through the body diode from the bridge. If the bridge is still on, the M

current will come from the positive supply, or if it is off, the current
will come from the bridge low-side body diode. If the current is S
Bridge
flowing from the motor to the bridge and the MOSFET is switched
off, the motor inductance will force the voltage on the drain pin up Figure 4: Source to Bridge, Drain Diode
and the high-power diode is required to clamp the voltage to the
Bridge
bridge VBB. The high-power diodes must handle the pulse current
capacity to survive all of the drive current flowing through it until
it decreases to zero. G
M

In the second case, the motor is connected to the source (see Figure
5). When the current is flowing from the bridge to the motor and S
Motor
the MOSFET is switch off, the motor inductance will try to force
High Power
the voltage on the source pin down. This will draw current through Diode
the high-power diode from the ground. If the current is flowing
from the motor to the bridge and the MOSFET is switched off, the GND
motor inductance will force the voltage on the source pin up and
the body diode will conduct. If the bridge is still on, the current will Figure 5: Source to Motor, Source Diode
come from the ground, or if it is off, the current will come from the
bridge high-side body diode. The high-power diodes must handle Bridge
the pulse current capacity to survive all of the drive current flowing
through it until it decreases to zero. G
M
The third case—and the recommended method (see Figure 6)—
allows the recirculation current to be dissipated in the external S
MOSFETs. This also has the advantage that there is no direct Motor
connection to the supply other than through the external MOSFETs Low Power
Schottky Diode
and the bridge. When the current is flowing from the bridge to the
motor and the MOSFET is switched off, the motor inductance will GND
try to force the voltage on the source pin down. This will drop the
voltage on the source to –4 V and the gate will be held at –1 V by Figure 6: Source to Motor, Gate Diode

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A6862 Automotive 3-Phase Isolator MOSFET Driver

Logic Control Inputs Gate Drive Output Monitor

A single digital terminal, ENA, controls all three gate drives. The gate-source voltage between the Gx terminal and the Sx
When ENA is high, all gate drive outputs will be on. When ENA terminal, for each phase, is monitored for an undervoltage
is driven low, all gate drive outputs will be off. An internal open- condition. If the voltage between the gate and source of
drain output is connected to the ENA terminal. This will pull the any active gate drive output, VGSx, drops below the VGS
ENA terminal to a regulated low voltage to indicate the status of undervoltage threshold, VGSUV, then a timer is started. If VGSx
the internal charge pump regulator. This terminal can be shorted remains below VGSUV for the duration of the VGS undervoltage
to VBB without damage. filter time, tGSUV, then the ENA input will be pulled to VOLF , but
all gate drive outputs will remain in the on-state. The ENA will
Table 1: Logic Truth Table remain at VOLF until VGSx rises above the undervoltage threshold
ENA IG POK Pump Gate Drive VGSUV .
0 1 1 Active Off
The status of the charge pump output voltage monitor and the
1 1 1 Active On VGS undervoltage monitors can be checked using the ENA
X 0 1 Disabled Off terminal. To use this feature, the ENA terminal should be driven
X 1 0 Disabled Off with an active open-drain pull-down and a passive pull-up
X 0 0 Disabled Off resistor. When no undervoltage states are present, the voltage at
ENA is determined by the digital voltage on the pull-up resistor
The two activation inputs, POK and IG, must both be high before and the control signal (DIS) applied to the ENA terminal.
the A6862 is activated with the charge pump operating. These
two inputs can be driven by logic-level signals or connected When any VGS undervoltage condition (VGSUx) is present, then
directly to other systems supplies including the main battery sup- ENA will be pulled to VOLF and can be recognized as a logic low
ply through an external reverse protection diode. Typically, these by the controller. The controller can then decide whether to hold
would be connected to the logic supply or logic supply monitor the outputs in this state or to switch off the outputs by asserting
and to the switched battery supply (ignition signal). the control signal (DIS).

When either POK or IG is low, the charge pump will be disabled, A typical connection arrangement to use this feature is shown in
and the outputs will be off. This provides additional security in Figure 7 and Figure 8 and a representative sequence shown in
the case of a supply failure. When the charge pump is disabled, Figure 9.
the supply current drawn by the A6862 will reduce to a very low The arrangement permits three specific states (see Figure 7):
level and it will be in a low-power sleep mode.
ON Gate drive commanded on.
Charge Pump Output Monitor No fault indicated.
Gate drive on.
The A6862 includes undervoltage detection on the charge pump FAULT Gate drive commanded on.
output. If the voltage at the charge pump output, VCP, drops Fault indicated.
below the undervoltage threshold, VCPON, then a timer is started. Gate drive on.
If VCP , remains below VCPON for the duration of the VCP under- OFF Gate drive commanded off.
voltage filter time, tCPUV , then a VCP undervoltage condition No fault indication.
(VCPU) will be asserted. The ENA input will be pulled to VOLF, Gate drive off.
but the device stays in the on-state.
This feature also allows the controller to actively determine
the delay between power-on and the time the outputs should be
activated.

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A6862 Automotive 3-Phase Isolator MOSFET Driver

ENA Terminal
Input Output VDIGITAL

High 1.1 V R = (VDIGITAL – 1) / (10-500 µA) in Ω

High Fault On
0.9 V MCU A6862

0.7 V ENA
ENH ACTIVE

0.4 V DIS UV = VCPU + VGSUx

Low Off VOLF (+1 V @ 10-500 µA)

Figure 7: ENA Terminal Input and Output Levels Figure 8: ENA Connection

VBB

VCPON
VCP

UV*

ACTIVE*

ENA* VOLF

DIS*

ENH*

Power on Active when Disabled Enabled VCPUV Recover when Power Disabled by MCU Enabled
VCP > VCPON, by MCU by MCU after VCP > VCPON, off and Power on by MCU
after tCPON tCPUV after tCPON

Figure 9: ENA Signal Sequence

* For signals, see Figure 8

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A6862 Automotive 3-Phase Isolator MOSFET Driver

INPUT AND OUTPUT STRUCTURES

VESD

100 kΩ
ENA

80 kΩ

4V

6V
20 kΩ UV = VCPU + CGSUx

0.2 V
10 µA to 500 µA

Figure 10: ENA Terminal

VCP

VESD
GU
GV
200 kΩ GW
IG
POK VESD 11 V
SU
100 kΩ SV
4V 6V SW

Figure 11: IG, POK Inputs Figure 12: Drive Outputs

VBB

12 V
VCP

VESD
12 V 12 V

16 V

16 V

20 V CP1 CP3 CP2 CP4

Figure 13: Supplies

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A6862 Automotive 3-Phase Isolator MOSFET Driver

PACKAGE OUTLINE DRAWING

For Reference Only – Not for Tooling Use

(Reference JEDEC MO-153 ABT; Allegro DWG-0000379, Rev. 3)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

0.45
5.00 ±0.10 8° 0.65
0° 16
16
0.22 1.70
0.09

3.00 4.40 ±0.10 6.40 ±0.20 3.00 6.10

0.60 ±0.15
A 1.00 REF

1 2
3.00
0.25 BSC 1 2

16× C SEATING PLANE 3.00

0.10 C SEATING GAUGE PLANE C PCB Layout Reference View
PLANE
0.30 0.65 BSC 1.20 MAX
0.19
0.15
0.025

A Terminal #1 mark area XXXXXXX

Date Code
B Exposed thermal pad (bottom surface) Lot Number
C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Standard Branding Reference View
Line 1, 2 = 7 characters
D Branding scale and appearance at supplier discretion Line 3 = 5 characters

Line 1: Part Number

Line 2: Logo A, 4 digit Date Code
Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number

Figure 14: LP Package, 16-Lead TSSOP with Exposed Pad

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A6862 Automotive 3-Phase Isolator MOSFET Driver

Revision History
Number Date Description
– September 23, 2016 Initial release
1 August 25, 2017 Corrected Turn-Off Time symbol (page 5), Figure 1 (page 6), and Figure 3 (page 8)
2 March 15, 2019 Updated VSX rating (page 2)
3 April 3, 2020 Minor editorial updates
4 April 13, 2022 Updated package drawing (page 13)

Copyright 2022, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
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