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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1

A 12 bit 100 MS/s SAR-Assisted

Digital-Slope ADC
Chun-Cheng Liu, Member, IEEE, Mu-Chen Huang, and Yu-Hsuan Tu

Abstract— This paper presents an energy-efficient successive consumption. However, the additional bit cycles degrade the
approximation register (SAR)-assisted digital-slope analog-to- maximum operation speed of the ADCs.
digital converter (ADC) architecture for high-resolution appli- SAR-assisted pipelined ADCs [7]–[12] achieve high SNR
cations. The proposed hybrid ADC combines a low-noise fine
digital-slope ADC with a low-power coarse SAR ADC. The coarse by pipelining two or more low-resolution SAR sub-ADC
SAR ADC rapidly approximates the input signal and produces stages. The residue signal amplification between the sub-ADC
a small residue signal for the succeeding fine ADC. The fine stages relaxes the requirement for a low-noise comparator.
digital-slope ADC linearly approaches the small residue signal. In addition, splitting the ADC conversion into two or more
A prototype was fabricated in 1P8M 28 nm CMOS technology. low-resolution sub-ADCs increases conversion speed. How-
At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion
ratio of 64.43 dB and a spurious free dynamic range of 75.42 dB ever, a high-gain high-bandwidth amplifier is needed to avoid
at the Nyquist input frequency while consuming 0.35 mW from the gain error problem between stages, and design restrictions
a 0.9 V supply. The resultant Walden and Schreier figures of for advanced CMOS processes make high-performance ampli-
merit are 2.6 fJ/conversion-step and 176.0 dB, respectively. The fier design challenging. Using a dynamic [8]–[10] or low-gain
ADC occupies an active area of 66 µm × 71 µm. amplifier [11] induces gain errors between stages and hence
Index Terms— Analog-to-digital converter (ADC), digital-slope complicated background calibration is needed to overcome the
ADC, hybrid ADC, SAR ADC, SAR-assisted digital-slope ADC, process, supply voltage, and temperature (PVT) variations. The
successive approximation register (SAR).
fully differential ring amplifier [12] achieves high gain and
high bandwidth with high power efficiency, but the cascading
I. I NTRODUCTION
first stage is not suited for operating with the low supply

T HE successive approximation register (SAR) analog-to-

digital converter (ADC) is a popular architecture for
achieving high energy efficiency. The operation speed of SAR
voltage in advanced CMOS processes. Moreover, the amplifier
and the sampling capacitor in the back-end stages contribute
extra noise and area to the ADC.
ADCs has improved with the scaling of CMOS technology. A dual-slope integrating ADC [13] transforms a voltage-
With growing transistor bandwidth, a single-channel SAR domain signal into a time-domain signal using an integrator
ADC can achieve a sampling speed of up to a few hun- and a continuous-time comparator (CT-CMP). Then, the ADC
dred MS/s with a resolution of 8 to 12 bits [1], [2]. Energy- quantizes the time-domain signal by a digital counter, which
efficient high-speed SAR ADCs are attractive for wireless is triggered by a synchronous clock. The dual-slope ADC
communication systems, such as Wi-Fi and LTE. However, inherently has high linearity and low noise but its speed is
the signal-to-noise ratio (SNR) of high-speed SAR ADCs low. The digital-slope ADC [14] replaces the integrator in the
is mainly constrained by comparator noise and usually lim- dual-slope ADC by an asynchronous switched capacitor (SC)
ited to below 60 dB. The tradeoff between the noise and operation while retaining the latter’s low noise. It quantizes the
power consumption of a comparator is not linear. The power time-domain signal using memory cells and an encoder instead
consumption increases quadratically to suppress comparator of a digital counter. Hence, the digital-slope ADC achieves a
noise in a limited comparison time [3]. Noise-tolerant SAR much higher operation speed. However, the hardware grows
ADCs [4] reduce comparator power in the first few bit cycles exponentially with ADC resolution and the maximum conver-
by using a coarse comparator. However, the fine comparator sion rate is halved with each extra bit of resolution. Therefore,
in the remaining bit cycles still consumes significant power to the digital-slope ADC is unattractive for resolutions higher
achieve an SNR of greater than 60 dB. The data-driven noise- than 8 bits. To ameliorate this limitation, the present study
reduction technique [5] and the adaptive-tracking-averaging proposes a hybrid ADC that combines a low-noise digital-
technique [6] enhance SNR by taking extra bit cycles to slope ADC with a low-power SAR ADC to achieve high
convert the least significant bits (LSBs). These techniques resolution without complicated hardware.
reduce comparator noise without a quadratic increase in power This work presents a 12-bit SAR-assisted digital-slope
ADC [15] that combines a 6 bit fine digital-slope ADC
Manuscript received April 18, 2016; revised June 10, 2016; accepted with a 7 bit coarse SAR ADC. With a 0.9 V supply, the
July 3, 2016. This paper was approved by Associate Editor Jan Mulder.
The authors are with MediaTek Inc., Hsinchu 30078, Taiwan (e-mail: prototype achieves a 100 MS/s sampling rate and consumes
[email protected]). only 0.35 mW. The ADC achieves a signal-to-noise-and-
Color versions of one or more of the figures in this paper are available distortion ratio (SNDR) of 64.43 dB and a spurious free
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2016.2591822 dynamic range (SFDR) of 75.42 dB at the Nyquist input

0018-9200 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE JOURNAL OF SOLID-STATE CIRCUITS

proportional to the input signal. Finally, the encoder converts

the thermometer code into binary to complete the conversion.
Similar to the SAR ADC architecture, the digital-slope
ADC architecture is a simple and highly digital architec-
ture. Both architectures achieve good power efficiency in
advanced CMOS processes. However, there are some differ-
ences between them. The SAR ADC uses a binary search
algorithm, whereas the digital-slope ADC uses a linear search
algorithm. The SAR ADC needs at least N comparisons for
an N-bit conversion, whereas the digital-slope ADC needs just
one comparison [14]. For a SAR ADC conversion, the residue
Fig. 1. Block diagram of an ansychronous digital-slope ADC. signal gets smaller with the SAR bit-cycling. A regenerative
comparator makes comparison by sensing a very small static
residue voltage in the LSB bit cycle. The input-output relation
of a regenerative comparator is given by
Vout = Vin · e Tc /τ . (1)
The sense amplification of a smaller residue signal leads to
a longer decision time to determine logical level “1” or “0”.
A metastable state occurs when the decision delay is longer
than a limited comparison time, which is very critical in high-
speed SAR ADCs.
Fig. 2. Timing diagram of a digital-slope ADC. For digital-slope ADC conversion, the CT-CMP measures
signals by detecting a dynamic zero-crossing. The continuous
frequency. The resultant Walden and Schreier figures of ramping of the reference level prevents the CT-CMP from
merit (FoMs) are 2.6 fJ/conversion-step and 176.0 dB, respec- entering a metastable state and the output always flips with
tively. These FoM values are the best reported to date for approximately a constant delay after the zero-crossing. The
sampling rates higher than 10 MS/s. The ADC core fabricated comparison time is given by
in 1P8M 28 nm CMOS technology occupies an active area of Vin
only 66 μm × 71 μm. Tc = · τu + Tlatency (2)
VLSB
The remainder of this paper is organized as follows.
Section II introduces the architecture of the proposed ADC. where τu is the latency of a delay cell and Tlatency is the
Section III describes the detailed implementation of the pro- latency from the input zero-crossing to the output flipping.
posed ADC and its key building blocks. Section IV shows the The comparison time Tc is linearly proportional to the input
measurement results of the prototype ADC and a comparison signal Vin . Hence, the digital-slope ADC is free of metasta-
to the state-of-the-art works. Finally, conclusions are given bility regardless of the size of the input signal.
in Section V.
B. Proposed SAR-Assisted Digital-Slope ADC
II. P ROPOSED ADC A RCHITECTURE
The SAR ADC has good power efficiency for large-signal
A. Review of Asynchronous Digital-Slope ADC conversion, but suffers from comparator noise and metastabil-
Fig. 1 shows a block diagram of an asynchronous digital- ity for small residue signals. The digital-slope ADC transforms
slope ADC [14]. The corresponding time diagram is sketched a voltage-domain signal into a time-domain signal using digital
in Fig. 2. The asynchronous digital-slope ADC is composed ramping and a CT-CMP, and then performs quantization in
of a sample-and-hold (S/H) circuit, a CT-CMP, delay cells, the time domain. It inherits the low noise from the dual-
unit capacitors, D flip-flops (DFFs) and an encoder. The S/H slope ADC [13], so it achieves good noise suppression, but
circuit samples the input signal at the falling edge of sampling has limited resolution due to hardware complexity [14]. The
clock ϕs and holds the sampled signal Vs when the sampling present study proposes a hybrid ADC architecture that adopts
clock signal is low. The voltage Vd is reset to ground during a power-efficient SAR ADC for most significant bits (MSBs)
the sampling phase. After the input signal is sampled, Vd is conversion and a low-noise digital-slope ADC for LSBs
switched up 1 LSB step by 1 LSB step at a constant interval conversion. The combination of a SAR ADC and a digital-
controlled by the delay line. When the voltage Vd is higher slope ADC preserves their respective advantages and mitigates
than the sampled signal Vs , the output of the CT-CMP will their limitations. Fig. 3 shows the block diagram of the pro-
change the output polarity and stop the delay propagation. posed SAR-assisted digital-slope ADC. The coarse dynamic
To avoid some unnecessary switching in the encoder when comparator (D-CMP) and SAR logic are used for the SAR
delay propagating, the outputs of all delay cells are sampled coarse conversion. The fine CT-CMP, delay line, D-flip-flops,
by D flip-flops, which are all clocked with the latch signal. and encoder are used for the digital-slope fine conversion.
The sampled outputs represent a thermometer code that is The digital correction logic converts the output of the coarse
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LIU et al.: 12 BIT 100 MS/s SAR-ASSISTED DIGITAL-SLOPE ADC 3

the digital-slope operation in the proposed hybrid ADC. The

digital-slope operation replaces the current source in the zero-
crossing MDAC by digital ramping and directly quantizes the
residue signal in the time domain, where the conversion time
of the zero-crossing MDAC is proportional to the residue
signal. With the digital-slope operation, the proposed ADC
does not need the back-end stages required in a zero-crossing
pipelined ADC, and hence has smaller power consumption
Fig. 3. Block diagram of the proposed SAR-assisted digital-slope ADC. and area.
III. I MPLEMENTATION OF P ROPOSED SAR ADC AND
B UILDING B LOCKS
A. Proposed 12 bit SAR-Assisted Digital-Slope ADC
Fig. 5 depicts the building blocks of the proposed 12 bit
SAR-assisted digital-slope ADC. The ADC samples the input
signals at the top plates of capacitor arrays to reduce the
number of unit capacitors by half. The sampling time is
around 2.5 ns, which is 25% of a clock cycle. The coarse
SAR ADC takes 8 bit cycles to convert 7 bits. Based on
the redundant weighting method [17], the capacitor sizes
from the first to the eighth MSB bits are 480, 256, 128,
64, 40, 24, 16, and 8 units, respectively. The capacitor DAC
adopts a monotonic switching procedure [18] to reduce the
switching power and simplify the control logic. The SAR ADC
Fig. 4. A 6 bit operation example of the proposed SAR-assisted digital- conversion takes about 2.4 ns. When the SAR ADC conversion
slope ADC. finishes, capacitors CD15 to CD0 at the negative input terminal
of the comparator are switched from Vref to ground. The
and fine ADCs into binary codes. The coarse SAR ADC level-shift operation ensures that the residue voltage is within
and fine digital-slope ADC share a capacitor digital-to-analog 25% to 75% of the input range of the digital-slope ADC.
converter (DAC). Therefore, there is no gain error between At the same time, the CT-CMP is enabled and its output is
the coarse and fine ADCs. This hybrid architecture consists of initially low. It takes about 0.8 ns for the capacitor DAC and
only elementary analog circuits and digital blocks, making it CT-CMP to settle. Next, the delay line is enabled to start the
attractive for advanced CMOS processes. conversion of the digital-slope ADC. Capacitors CD31 to CD0
at the positive terminal of the comparator are switched from
C. Operation Example of Proposed Hybrid ADC Vref to ground in sequence with an interval of 100 ps. When
the voltage at the positive terminal is lower than that at the
Fig. 4 shows a 6 bit example to explain the operation of
negative terminal, the output of the CT-CMP rises from low
the proposed hybrid ADC. The 6 bit ADC consists of a 3 bit
to high to stop the propagation in the delay line and disable
coarse SAR ADC and a 4 bit fine digital-slope ADC; there is a
the CT-CMP. At the same time, the time-domain information
1 bit redundancy overlap between the ADCs. After 3 bit SAR
in delay cells is sampled by D-flip-flops, and the encoder
ADC conversion, the residue signal converges to the range of
converts the thermometer code into binary codes. The digital
[−Vmax /8, +Vmax /8]. Next, the residue signal is level-shifted to
error correction (DEC) circuit converts the 14 bit redundant
the middle of the range [0, +Vmax /2] for the 4 bit digital-slope
codes (8 bit codes from the SAR ADC and 6 bit binary codes
ADC conversion. After the residue signal has well-settled, the
from the digital-slope ADC) into 12 bit binary codes. This
residue signal is continuously switched down with a 1 LSB
hybrid ADC does not need gain calibration because the coarse
step. When the residue signal is less than zero, the output of
SAR ADC and the fine digital-slope ADC share a capacitor
the CT-CMP changes polarity and stops the conversion of the
array.
fine digital-slope ADC. To obtain a correct output code, the
The digital-slope ADC conversion in this work is single-
offset induced by the redundant range is subtracted from the
ended, so it employs a unit capacitor that is twice as large as
raw codes by the correction logic. The offset is four LSBs in
that for a differential ADC to perform 1 LSB switching [14].
this example.
The single-ended operation reduces the overall capacitor count
by 2. After the 7 bit coarse SAR ADC conversion, the
D. Comparison With SAR-Assisted Zero-Crossing residue signal swing is around 12.5 mVp-p for a 1.6 Vp-p
Pipelined ADC ADC input signal swing. The single-ended operation induces
To a certain extent, the proposed hybrid ADC is similar to a 6.25 mV input common-mode (CM) voltage (Vcm ) variation
a SAR-assisted zero-crossing pipelined ADC [16]. In fact, the in the CT-CMP. According to simulation, a 6.25 mV input
operation of a multiplying DAC (MDAC) and back-end stages variation of Vcm only causes a 2.7 ps delay uncertainty in
in a SAR-assisted zero-crossing pipeline ADC is replaced by the output signal generation of the CT-CMP. The difference
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4 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 5. Block diagram of the proposed 12 bit SAR-assisted digital-slope ADC.

TABLE I
ADC N OISE B UDGET

Fig. 6. Schematic of a low-noise low-power CT-CMP.

digital-slope ADC conversion. When the CT-CMP turns on,

is equivalent to 0.054 LSB and has a minor influence on the the first and second stages consume only 120 and 40 μA,
ADC conversion. respectively. Before the digital-slope ADC conversion, the
The kT/C noise of the sampling capacitor, quantization CT-CMP takes about 0.8 ns to settle, which prevents the
noise, CT-CMP noise, and on-chip reference buffer noise digital-slope ADC conversion from experiencing startup tran-
totally yielded a 67.2 dB SNR. Table I summarizes the detailed sients. The CT-CMP is designed to have a very low bandwidth
noise breakdown of the prototype hybrid ADC. The CT-CMP (the -3 dB bandwidth is designed to be around 100 MHz) that
noise was obtained by calculating the jitter of the CT-CMP is much lower than the 10 GHz step frequency (an interval of
output with a transient noise simulation. The on-chip reference 100 ps) of capacitor switching. The low-bandwidth CT-CMP
buffer noise was obtained by integrating the output noise with filters out high-frequency harmonics and noise of the stair
a noise simulation. The overall noise is signal-independent. curve, and uses the low-frequency components and noise
to generate the output signal. Fig. 7 shows a mathematical
B. Continuous-Time Comparator concept to explain the effectiveness of the low-bandwidth
Fig. 6 depicts a schematic of the CT-CMP, which uses a CT-CMP. Fig. 7(a) plots a stair step curve with an interval of
two-stage structure to increase the open-loop gain. The inverter T, which is the input signal of the CT-CMP. Fig. 7(b) shows
guarantees that the output signal will produce logic levels for a fast Fourier transform (FFT) spectrum of the stair step curve.
the succeeding digital circuit. For proper function with an input The step frequency is the inverse of T. The low-bandwidth
CM voltage of around 100 mV, the CT-CMP uses a p-type CT-CMP acts as a low-pass filter (LPF), attenuating the high-
input pair for the first stage, and an n-type input pair for the frequency components. Fig. 7(c) shows the effective spectrum
second stage. Some MOS capacitors are added to decouple the after filtering by the low-bandwidth CT-CMP. Taking the
gate bias of the current sources. The decoupling capacitors are inverse FFT of the effective spectrum, we can get the
designed to be 8 times the size of the current sources. equivalent input signal curve of the low-bandwidth CT-CMP,
The CT-CMP turns off to save power during the sampling as shown in Fig. 7(d). With the low-bandwidth CT-CMP, the
phase, SAR ADC conversion, and idle time after the switching capacitor curve is similar to discharging with a
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LIU et al.: 12 BIT 100 MS/s SAR-ASSISTED DIGITAL-SLOPE ADC 5

layout size. Each delay cell consists of an AND gate and

five buffers. The six logic gates have a total delay time of
around 100 ps. With the help of the low-bandwidth CT-CMP,
an additional bit is generated by time-domain interpolation.
With interpolation, the LSB time step in this design is
equivalent to 50 ps. According to simulation results, random
mismatch results in a standard deviation of 2.0 ps for the delay
of each delay cell. The standard deviation of the maximum
integral nonlinearity (INL) in a thermometer DAC can be
expressed as [19]
√
σmax INL, (LSB) = 0.5 n ∗ σ (3)

Fig. 7. (a) Stair step curve with an interval of T. (b) FFT spectrum of the where n is the total number of unit cells. With 32 delay
stair step curve. (c) Effective spectrum after fitlering by the low-bandwidth cells, the standard deviation of the maximum INL is 5.66 ps.
CT-CMP. (d) Equivalent input signal curve of the low-bandwidth CT-CMP.
In addition, according to transient noise simulation, the circuit
noise results in a standard deviation of only 193 fs in different
cycles. These variations are much smaller than a 1-LSB time
step. Therefore, the random mismatch and noise of the delay
cells have a minor influence on the SNR.
During the digital-slope approaching (switching at most 32
times), the fine ADC obtains 63 samples using D flip-flops
when the Valid signal goes high. The encoder converts the
63 bit thermometer codes into 6 bit Gray codes, and then
converts the 6 bit Gray codes into binary codes. For a 6 bit
digital-slope ADC, 1 bit time-domain interpolation helps to
reduce the total number of unit capacitors from 64 to 32, which
reduces the hardware complexity by a factor of 2. The parasitic
capacitance of the routing line is much greater than the unit
capacitance. Reducing the total number of routing lines thus
Fig. 8. Implementation of the 6 bit digital-slope fine ADC. reduces the circuit area and switching power consumption
caused by parasitic capacitance. The ADC can achieve a
current source in a dual-slope ADC. The low bandwidth higher SNR with more aggressive time-domain interpolation
alleviates the signal-dependent effect and makes the (e.g., 2 or 3 interpolated samples between two switching
comparison time more linearly proportional to the input nodes) at the cost of increasing the number of D-flip-flops
voltage. Therefore, the digital-slope ADC can achieve a and the complexity of the encoder.
higher resolution using time-domain interpolation without
extra unit capacitors. D. Latency Compensation
Using the CT-CMP for the LSBs conversion has some
Fig. 9 plots a diagram of the latency from the crossing-
benefits compared to using a dynamic comparator. First, it
point generation of the Valid signal in the low-bandwidth
only needs one comparison for N-bit conversions and is free of
CT-CMP. The latency problem here is similar to that of a
the metastability problem. Second, it works like an integrator
zero-crossing pipelined ADC. However, the latency is harmful
and takes a much longer comparison time to generate the
to zero-crossing pipelined ADCs because the current source
output. Therefore, it has better suppression of high-frequency
in a zero-crossing-based circuit (ZCBC) MDAC has limited
noise. In this work, the input-referred noise of the CT-CMP
linearity, resulting in a signal-dependent offset for the conver-
is designed to be 150 μV. If we designed a dynamic com-
sion even if the latency is well-compensated. Owing to the
parator [17] with roughly 1/N the energy consumption of this
intrinsic high linearity of digital ramping, the latency in this
CT-CMP, its input-referred noise would be up to 360 μV
work results in only a constant systematic offset. The latency
according to simulation. The CT-CMP thus achieves better
can be compensated by additional delay cells and removed
efficiency in suppressing noise.
in the digital domain by estimating the offset according to
post-layout simulation. Fig. 10 shows the implementation of
C. Fine Digital-Slope ADC With Time-Domain Interpolation latency compensation. The additional delay cells are designed
Fig. 8 shows the implementation of the 6 bit fine digital- with a delay of 100 ps, which is the same as that of the
slope ADC, which consists of delay cells, switches, unit first 32 delay cells. The number of additional delay cells
capacitors, D-flip-flops, and an encoder. Except for the unit depends on the latency. To remove the latency in the digital
capacitors, all components are constructed using digital stan- domain, the sampling positions of the D-flip-flops are shifted
dard library logic cells, which are provided by a foundry and according to the number of additional delay cells. In this
have verified device properties and a regular and compact way, the latency is easily removed from the ADC conversion.
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6 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 11. Schematic of reference buffer.

dealt with to ensure that the ADC works properly without

performance degradation.
Fig. 9. The latency from the input crossing point to the valid signal Although the redundancy between the coarse SAR ADC and
generation.
fine digital-slope ADC can tolerate their offset mismatch, it is
insufficient when a small comparator size is used. To make
the design more robust, the input offsets of the D-CMP and
the CT-CMP are calibrated in the foreground by shorting the
inputs to Vcm . Dynamic offset caused by temperature and
supply voltage variations can be tolerated by the 16-LSB
redundant range in this design. If the redundant range is
insufficient for a critical case, the 6-bit output of the digital-
slope ADC will contain the boundary codes (0 or 63). The
offset of the CT-CMP can be adjusted in the background to
ensure that the 6 bit output code is within the range of 0 to 63
Fig. 10. Implementation of latency compensation. by utilizing boundary code detection logic.
The first 3 MSB capacitors in the capacitor array at the
positive terminal are also calibrated in the foreground with a
The mismatch between the latency of the CT-CMP and the
step size of 0.5 LSB and a range of 4 LSB. The calibration
total delay of the additional delay cells in PVT corners can
mechanism is similar to a previously reported one [20]. Instead
be compensated with CT-CMP offset calibration, which is
of adjusting the bit weights and generating the digital output
mentioned in Section III-F.
in the digital domain, we adjust the capacitances to match
the ideal bit weights in the analog domain to avoid extra
E. On-Chip Reference Voltage Buffer digital power consumption. However, the accuracy is limited
For a SAR ADC with a 100 MS/s sampling rate, the by the finite step size, and the error will propagate with the
capacitor DAC network must settle in a few hundred picosec- calibration of each capacitance. Therefore, we only calibrate
onds or less, which requires a high-speed reference buffer, the first 3 MSB capacitances, and enhance the LSB capacitors
especially for the MSB cycle. With the help of the redundant matching by placing them together in the center of the DAC
algorithm [17], the bandwidth requirement of the reference network to achieve 9 bit linearity.
buffer can be relaxed greatly. An open-loop source-follower The static PVT variation leads to a static offset for the ADC
architecture is adopted for the proposed ADC, as shown that can be compensated with CT-CMP offset compensation.
in Fig. 11. The VBG is equal to 0.9 V, which tracks the bandgap However, the dynamic variations at the input CM and supply
voltage and is insensitive to temperature and process variation. voltage will degrade ADC performance. According to the
In order to generate an output voltage Vref of 0.9 V, the simulation, the CM rejection ratio of the ADC is 49.5 dB
resistance ratio of R1/R2 is designed to be equal to the NMOS (a 100 V input CM variation results in an input-referred
size ratio of M2/M1. R0 and C0 act as a low-pass filter to offset of 0.336 mV). The power supply rejection ratio of
isolate the kick-back noise from the ADC. The open-loop the ADC is 36.0 dB (a 100 mV supply variation results
topology has the benefits of small output impedance (which is in an input-referred offset of 1.857 mV). The CM rejection
equal to (1/gm2)//R2), wide bandwidth, and small area. It is ratio can be improved by enlarging or cascading the current
very suitable for high-speed operation. source of first stage in the CT-CMP, which would lead to a
more constant current for different input CM voltages. The
power supply rejection ratio can be improved by reducing the
F. Non-ideal Effect of Proposed ADC latency of the CT-CMP, while it consumes more power to
The performance of the proposed ADC may degrade due improve the bandwidth of CT-CMP. In this work, a 0.9 V
to a lot of nonideal effects, such as device mismatch and low-dropout regulator is used to supply the proposed ADC to
power supply noise. These nonideal effects must be carefully avoid interference from other circuits.
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LIU et al.: 12 BIT 100 MS/s SAR-ASSISTED DIGITAL-SLOPE ADC 7

Fig. 14. Measured dynamic performance versus input frequency at 0.9 V

and 100 MS/s.

Fig. 12. Chip micrograph and delayered zoomed-in view of ADC core.
A. Static Performance
The static performance of the proposed ADC was evaluated
with a 0.9 V supply and a 100 MS/s sampling rate and an input
signal frequency of close to 1 MHz. The measured differential
nonlinearity (DNL) and integral nonlinearity (INL) are shown
in Fig. 14. The peak DNL and INL are +0.53 / 0.53 LSB and
+0.79 / 0.83 LSB, respectively.

B. Dynamic Performance
Fig. 14 shows a plot of the measured SFDR and SNDR
versus the input frequency with 0.9 V and 100 MS/s. At a
low input frequency, the measured SNDR and SFDR are
65.67 and 75.87 dB, respectively. The resultant effective
number of bits (ENOB) is 10.62 bits. When the input fre-
quency is increased to the Nyquist frequency, the measured
SNDR and SFDR are 64.43 and 75.42 dB, respectively.
The resultant ENOB is 10.41 bits. The effective resolution
Fig. 13. Measured static performance. (a) DNL. (b) INL. bandwidth (ERBW) is around 80 MHz and the SNDR is still
greater than 60 dB when the input frequency is increased
to 100 MHz.
There is a serious non-ideal effect when using an on-chip Fig. 15 shows a plot of the measured FFT spectrum with
reference buffer. The number of unit capacitors connected to a Nyquist frequency input. The second and third harmonics
the reference voltage depends on the input signal after the mainly result from the output impedance of the on-chip
SAR operation. The digital ramping sinks a signal-dependent reference buffer, as mentioned in Section III-F.
current from the reference buffer during the digital-slope ADC
conversion. The output impedance of the reference buffer
generates a signal-dependent drop in the reference voltage, C. Power Consumption
which causes a bowing effect on ADC conversion, which is With a 100 MS/s sampling rate, the ADC consumes a
similar to the problem in zero-crossing pipelined ADCs [21]. total power of 0.35 mW from a 0.9 V supply and a 0.9 V
This problem can be alleviated by enlarging the output stage reference. The power consumption breakdown is shown
current to reduce the output impedance, or adding a replica in Fig. 16. The analog blocks consume 34% of the total
cross-coupled capacitor DAC for current compensation [21]. power, including 64 μW for the S/H circuit and the D-CMP,
and 56 μW for the CT-CMP. The digital blocks consume
IV. M EASUREMENT R ESULTS 41% of the total power, including 70 μW for the delay line,
D flip-flops, and encoder, 53 μW for the SAR control logic,
A prototype was fabricated in one-poly eight-metal (1P8M) and 21 μW for the DEC logic. The power dissipation of the
28 nm HPM CMOS technology. A chip micrograph and a de- capacitor DAC and the leakage current are 80 and 6 μW,
layered magnified view of the ADC core are shown in Fig. 12. respectively.
The ADC core occupies an active area of 66 μm × 71 μm. In this work, the power consumption of the reference buffer
The unit capacitance in the capacitor DAC is 0.8 fF. The total was not optimized. The current of the reference buffer was just
sampling capacitance of the single-ended capacitor network increased to alleviate the bowing effect. The on-chip reference
is 0.9 pF. The measurement results of the prototype are buffer occupies an area of 70 μm × 40 μm and consumes
presented below. up to 1.56 mW of power, which is much higher than that
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8 IEEE JOURNAL OF SOLID-STATE CIRCUITS

TABLE II
P ERFORMANCE S UMMARY AND C OMPARISON W ITH S TATE - OF - THE -A RT ADCs

Fig. 15. FFT plot with input frequency close to Nyquist frequency.

Fig. 16. Power consumption breakdown.

consumed by the proposed ADC. If the reference buffer is
optimized by adding a replica cross-coupled capacitor DAC where f S is the sampling frequency. At low input frequency,
for current compensation [21], its power consumption can be the Walden and Schreier FoMs are 2.2 fJ/conversion-step
reduced to 0.4 mW according to simulation. and 177.2 dB, respectively. At the Nyquist input frequency,
the Walden and Schreier FoMs are 2.6 fJ/conversion-step
D. Performance Summary and Comparison and 176.0 dB, respectively. Table II summarizes the ADC
performance and compares the proposed design to pub-
The Walden and Schreier FoM equations are defined, lished ADCs with comparable sampling rates and resolu-
respectively, in tions [9], [10], [12], [22]. Only one published work [10] used
Power an on-chip reference buffer, the other works [9], [12], [22]
FoMW = (4) used large on-chip decoupling capacitances to stabilize the
2E N O B × f S
  reference voltage. It is unfair to compare these different
fS designs because the on-chip reference buffer consumes static
FoM S = S N D R + 10 log (5)
2 × Power power and contributes extra noise to the ADC. Therefore, we
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LIU et al.: 12 BIT 100 MS/s SAR-ASSISTED DIGITAL-SLOPE ADC 9

occupies an active area of 66 μm × 71 μm. The experimental

results demonstrate the power and hardware efficiency of the
proposed hybrid ADC.

ACKNOWLEDGEMENT
The authors would like to thank ADCT/CT1/AL2 of
MediaTek Inc. for chip layout support.

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 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE JOURNAL OF SOLID-STATE CIRCUITS

[22] C. C. Lee, C.-Y. Lu, R. Narayanaswamy, and J. B. Rizk, “A 12 b 70 MS/s Mu-Chen Huang received the B.S. and
SAR ADC with digital startup calibration in 14 nm CMOS,” in Proc. M.S. degrees from National Taiwan University
IEEE Symp. VLSI Circuits, Jun. 2015, pp. 62–63. (NTU), Taipei, Taiwan, in 2007 and 2009,
[23] B. Murmann. Adc Performance Survey 1997 –2015. [Online]. Available: respectively. His thesis focused on the design and
http://web.stanford.edu/murmann/adcsurvey.html implementation of fully differential comparator-
based analog-to-digital converters.
In December 2008, he joined MediaTek Inc.,
Hsinchu, Taiwan, where he has been involved in
various analog/mixed-signal circuit designs for
DTV front-end including CVBS, YPbPr/RGB,
and IF-demodulator. He is currently a Technical
Chun-Cheng Liu (S’07–M’11) received the B.S. Manager of MediaTek’s Analog Circuit Design division, focusing on
and Ph.D. degrees from National Cheng Kung the development of high-end TV products. His research interests include
University (NCKU), Taiwan, in 2005 and 2010, analog-to-digital converters and analog front-end designs.
respectively.
In 2011, he joined the Analog Circuit Design divi-
sion, MediaTek, Hsinchu, Taiwan, where he has been
working on analog-to-digital converters for video
receivers and wireless communication systems. He is Yu-Hsuan Tu received the B.S. and Ph.D. degrees
currently a Technical Manager working on high- from National Chiao-Tung University (NCTU),
performance data converters and analog circuits. His Hsinchu, Taiwan, in 2002 and 2006, respectively.
main research interests include analog/mixed-signal His doctoral dissertation focuses on electronic exci-
circuits and analog-to-digital converters. tations and solid-state physics.
Dr. Liu was the recipient of the 2007 Third Prize and 2008 First Prize In 2006, he joined the Analog Circuit Design divi-
in the IC design contests (Analog Circuit Category) held by Ministry of sion, MediaTek Inc., Hsinchu, Taiwan, where he is
Education, Taiwan. In 2010, he was the winner of the Gold Prize in Macronix now a Senior Manager. His research interests include
Golden Silicon Award and the Best Ph.D. Dissertation Award of Taiwan IC data conversion, signal processing, analog/mixed-
Design Society. He also received the Best Design Awards of National Chip signal circuit design, and he is also interested in the
Implementation Center (CIC) Outstanding Chip Award in 2010 and 2011. programming language.