CHAPTER - 3 - Logic - Circuits
CHAPTER - 3 - Logic - Circuits
LOGIC CIRCUITS
Digital computers are based upon electronic components
whose inputs and outputs are at anyone point in one of two
possible states; the states are mostly voltage levels;
One voltage level can be denoted by a 1 and another by a 0.
If the higher voltage is associated with 1, the circuit is said to
be based upon positive logic. If the lower voltage is associated
with a 1, the circuit is said to be based on negative logic.
A variable that can take on two states e.g. (0, 1, True, false;
on/off) is called a logical variable.
A circuit whose inputs and outputs are described by logical
variables is called a logical network.
INPUTS OUTPUTS
Logical Network
Logic Gates
A combinatorial circuit with only one output is called a logic gate. They
accept logical values at their inputs and they produce corresponding
logical values at their outputs.
A table listing all the outputs for the various inputs is called a
truth table (derived from the True/ False logic in mathematics.)
All combinatorial circuits can be constructed from the
elementary logic gates.
1 0
Input Output
A B AB
0 0 0
0 1 0
1 0 0
1 1 1
The output is 1 if all the inputs are 1’s
Switch A Switch B
Lamp
'AND' gates are like two or more switches in series. All the switches
have to be closed (‘ON’ or a value of '1') in order to make the lamp
(output C) turn on. If all inputs are not "ON", the output is "OFF".
.
3. The OR Gate:
A
A OR B
A+B
B
Input Output
A B A + B
0 0 0
0 1 1
1 0 1
1 1 1
Switch B
An 'OR' gate is like two or more switches in parallel. Only one switch
needs to be closed ('ON' or a value of '1') in order to make the lamp
(output C) turn 'ON' with a value of '1'.
Input Output
__
A B AB
0 0 1
0 1 1
1 0 1
1 1 0
AB = A + B
The output is 0 if all the inputs are 1’s.
5. The NOR (Not OR) Gate:
A A OR B A
B _____
A+B B
_____ _ _
A+B = AB
Input Output
____
A B A+B
0 0 1
0 1 0
1 0 0
1 1 0
The output is 1 if all the inputs are 0’s.
Input Output
A B A + B
0 0 0
0 1 1
1 0 1
1 1 0
The output is 0 if all the inputs are the same. OR
It outputs a 1 if the number of 1’s in the inputs is odd.
Input Output
_____
A B A +B
0 0 1
0 1 0
1 0 0
1 1 1
The output is 1 if all the inputs are the same.
C _
AC + BC
_
(A + B) C
C
_ _ _ _ _
A B C B AC BC AC + BC A+B (A + B)C
0 0 0 1 0 0 0 1 0
0 0 1 1 0 1 1 1 1
0 1 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 0
1 0 0 1 0 0 0 1 0
1 0 1 1 1 1 1 1 1
1 1 0 0 0 0 0 1 0
1 1 1 0 1 0 1 1 1
To try Circuits for AB(C+D) and (ABC + ABD) and their Truth Tables.
X = AB + ACD + ACEF + ACEG
A A B C D E F G
B
C
D
E
F
G
X
(Causes minimum delay)
e.g.
__
ABC + BC + AB
__
C(AB + B) + AB
_
C(A + B) + AB (third equivalence from the bottom)
_
AC + BC + AB
_ _
AC + (A + A)BC + AB
_ _
AC + ABC + ABC + AB
_
AC(1 + B) + AB(C + 1)
_
AC + AB
_ _ _
ABC + ABC + ABC + ABC
_ _ _
ABC + ABC + ABC + ABC + ABC + ABC
_ _ _
(A + A)BC + (B + B)AC + (C + C)AB
BC + AC + AB
Digital Design Process
1. Determine all the input/output relationships that must be true for
the network being designed and put them in convenient tabular
form.
2. Use the drawn up table to find Boolean expressions for each
output.
3. Simplify the expressions from 2 above
4. Use the expressions resulting from step 3 to develop the desired
logical diagram.
Example
Suppose that a three input network is needed that will output a 1 if the majority of the
inputs are 1’s otherwise the output is zero.
A B C X
0 0 0 0 X0
0 0 1 0 X1
0 1 0 0 X2
0 1 1 1 X3
1 0 0 0 X4
1 0 1 1 X5
1 1 0 1 X6
1 1 1 1 X7
BC
AC BC + AC + AB
AB
A Karnaugh map is a truth table for a single output consisting of arrays of squares
where each square corresponds to a row of a truth table.
The symbols at the top represent the variables associated with the
columns and the symbols on the left represent the variables associated
with the rows.
The value of each output for each input is put in the corresponding
square.
For each 1 in the Karnaugh map there is a corresponding miniterm in the
output’s Sum of product expression and each 0 represents a maxiterm in
the Product of Sums expression.
Two inputs Three inputs Four inputs
A AB AB
0 1 00 01 11 10 00 01 11 10
0 0 2 0 0 2 6 4 00 0 4 12 8
B C 01 1 5 13 9
1 1 3 1 1 3 7 5 CD
11 3 7 15 11
10 2 6 14 10
Example 1
A B C X Using Boolean simplification:
0 0 0 0 _ _
0 0 1 0 ABC +ABC + ABC
0 1 0 0 _ _
0 1 1 1 ABC +ABC + ABC + ABC
1 0 0 0
1 0 1 0 = AB + BC AB
1 1 0 1 00 01 11 10
1 1 1 1 0 0 0 1 0
C 1 0 1 1 0
Look for adjacent groups that include 2n miniterms where n is an integer.
The larger the group the greater is the reduction.
Example 2
A B C X Using Boolean simplification:
0 0 0 0 _ _ _
0 0 1 0 ABC +ABC + ABC + ABC
0 1 0 0 _ _ _
0 1 1 1 ABC +ABC + ABC + ABC + ABC + ABC
1 0 0 0
1 0 1 1 = BC + AC + AB
1 1 0 1
1 1 1 1
AB
00 01 11 10
0 0 0 1 0
C
1 0 1 1 1
Example 3
F(A,B,C) = (0,1,2,3,7) AB
_ 00 01 11 10
A 0 1 1 0 0 _
C A + BC
BC 1 1 1 1 0
AB AB
00 01 11 10 00 01 11 10
0 1 0 1 1 _ 0 1 0 0 1
C AC C
1 1 0 0 1 1 0 1 0 0
_ _ _ __
B + AC ABC + BC
AB AB
00 01 11 10 00 01 11 10
00 0 1 1 1 00
1 0 0 1
01 0 1 0 1 01
CD CD 1 0 0 0
11 0 0 0 1 11
1 0 0 1
10 0 0 0 1 10
1 0 0 1
_ _ __ _ __ _ _ _
ABC + ACD + AB AB + BC + BD
For some designs some input combinations cannot occur. Outputs
corresponding to these combinations are optional. These combinations
may be chosen to be either 0 or 1 as is convenient in the maximization
process.
These outputs are represented by X’s in the Karnaugh Map and they
may or may not be included in the prime implicants.
They are called Don’t Care Cases denoted by the function d(A,B,C) =
(….) AB
00 01 11 10
00 X
01 1
CD _
11 1 AB + AC
10 X 1 1
___ _ _
It is important to include the miniterm ABCD in C but not ABCD
Example
A network is needed that will output a 1 if the binary A 3A2A1A0 is greater
than 0 and less than 4.
Assume also the inputs are controlled by a rotary switch such that only
one input can be a 1 at any given time except when the switch position
will also allow all inputs to be 1.
A3 A2 A1 A0 X A3A2
0 0 0 0 0 00 01 11 10
0 0 0 1 1 00 0 0 X X
0 0 1 0 1
0 0 1 1 X 01 1 X X X
0 1 0 0 0 A1A0
0 1 0 1 X 11 X X 0 X
0 1 1 0 X
0 1 1 1 X 10 1 X X X
1 0 0 0 0
1 0 0 1 X
1 0 1 0 X _ _
1 0 1 1 X = A 1A 0 + A0A3
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 0