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    Ec3352 - Digital Systems Design Set Ii - Iat2

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    venki08
    This document is an internal assessment test for a Digital Systems Design course covering combinational and sequential digital circuits. It contains 3 parts testing different cognitive levels based on Bloom's taxonomy: Part A contains 5 short answer questions worth 2 marks each about topics like parity generators, priority encoders, and the difference between combinational and sequential logic circuits. Part B contains 2 long answer questions worth 13 marks each, asking students to either explain the working of an 8:1 demultiplexer or a shift register and its SIPO configuration. Part C contains 1 long answer question worth 14 marks asking students to diagram and explain a 4-bit look ahead carry adder or the working of an 8-bit ALU.

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    Ec3352 - Digital Systems Design Set Ii - Iat2

    Uploaded by

    venki08
    118 views1 page
    This document is an internal assessment test for a Digital Systems Design course covering combinational and sequential digital circuits. It contains 3 parts testing different cognitive levels based on Bloom's taxonomy: Part A contains 5 short answer questions worth 2 marks each about topics like parity generators, priority encoders, and the difference between combinational and sequential logic circuits. Part B contains 2 long answer questions worth 13 marks each, asking students to either explain the working of an 8:1 demultiplexer or a shift register and its SIPO configuration. Part C contains 1 long answer question worth 14 marks asking students to diagram and explain a 4-bit look ahead carry adder or the working of an 8-bit ALU.

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    EC3352- DIGITAL SYSTEMS DESIGN SET II - IAT2

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    This document is an internal assessment test for a Digital Systems Design course covering combinational and sequential digital circuits. It contains 3 parts testing different cognitive levels based on Bloom's taxonomy: Part A contains 5 short answer questions worth 2 marks each about topics like parity generators, priority encoders, and the difference between combinational and sequential logic circuits. Part B contains 2 long answer questions worth 13 marks each, asking students to either explain the working of an 8:1 demultiplexer or a shift register and its SIPO configuration. Part C contains 1 long answer question worth 14 marks asking students to diagram and explain a 4-bit look ahead carry adder or the working of an 8-bit ALU.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    118 views1 page

    Ec3352 - Digital Systems Design Set Ii - Iat2

    Uploaded by

    venki08
    This document is an internal assessment test for a Digital Systems Design course covering combinational and sequential digital circuits. It contains 3 parts testing different cognitive levels based on Bloom's taxonomy: Part A contains 5 short answer questions worth 2 marks each about topics like parity generators, priority encoders, and the difference between combinational and sequential logic circuits. Part B contains 2 long answer questions worth 13 marks each, asking students to either explain the working of an 8:1 demultiplexer or a shift register and its SIPO configuration. Part C contains 1 long answer question worth 14 marks asking students to diagram and explain a 4-bit look ahead carry adder or the working of an 8-bit ALU.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 1

    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

    INTERNAL ASSESMENT TEST –II (SET II)


    SUBJECT CODE/NAME : EC3352 DIGITAL SYSTEMS DESIGN DATE :
    BRANCH / SEMESTER : II ECE / III TIME :
    ACADEMIC YEAR : 2023-24 MARK : 50
    CO2: Design various combinational digital circuits using logic gates.
    CO3: Analyse and design asynchronous sequential circuits.
    BLOOM'S TAXONOMY
    Remembering Applying Evaluating
    Understanding Analyzing Creating

    PART A (5 x 2 = 10 marks)
    CO2 R 1. Draw the circuit diagram for 3-bit parity generator. (2)
    CO2 U 2. What is Priority encoder? (2)
    CO2 R 3. Enumerate some of the combinational circuits? (2)
    CO3 U 4. Distinguish between Combinational & Sequential Logic Circuits (2)
    CO3 C 5. What is Shift Register? List the types. (2)

    PART B (2 x 13= 26 marks)


    CO2 a) What is De-Multiplexer? With a neat Logic diagram explain in detail function of
    8:1 De-Multiplexer? (OR)
    U
    CO3 R 6. b) Define Shift Register & explain the working principle of SIPO? (13)

    CO2 U a) What is Code converter & with a neat logic diagram explain in detail about
    the function of Binary to BCD code converter. (OR)
    7. (13)
    CO2 U b) What is Decoder? With a neat logic diagram explain in detail abut 8:2
    decoder.
    PART C (1x 14 = 14 marks)
    CO2 U a) With a neat diagram explain in detail about the working principle of a 4-bit
    8. look ahead carry adder. (OR)
    (14)
    CO2 U b) Explain in detail about the working principle of 8-bit ALU?

    Prepared by Verified by Approved by

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