PIC16LF1885777 Data Sheet 40001825F

PIC16(L)F18857/77
Full-Featured 28/40/44-Pin Microcontrollers
Description
PIC16(L)F18857/77 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,
combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.
The family will feature the CRC/SCAN, Hardware Limit Timer (HLT) and Windowed Watchdog Timer (WWDT) to support
customers looking to add safety to their application. Additionally, this family includes up to 56 KB of Flash memory, along
with a 10-bit ADC with Computation (ADC2) extensions for automated signal analysis to reduce the complexity of the
application.
Core Features Power-Saving Functionality

• C Compiler Optimized RISC Architecture • DOZE mode: Ability to run the CPU core slower
• Only 49 Instructions than the system clock
• Operating Speed: • IDLE mode: Ability to halt CPU core while internal
- DC – 32 MHz clock input peripherals continue operating
- 125 ns minimum instruction cycle • Sleep mode: Lowest Power Consumption
• Interrupt Capability • Peripheral Module Disable (PMD):
• 16-Level Deep Hardware Stack - Ability to disable hardware module to
• Three 8-Bit Timers (TMR2/4/6) with Hardware minimize power consumption of unused
Limit Timer (HLT) Extensions peripherals
• Four 16-Bit Timers (TMR0/1/3/5)
• Low-Current Power-on Reset (POR) eXtreme Low-Power (XLP) Features
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR) with Fast Recovery • Sleep mode: 50 nA @ 1.8V, typical
• Low-Power BOR (LPBOR) Option • Watchdog Timer: 500 nA @ 1.8V, typical
• Windowed Watchdog Timer (WWDT): • Secondary Oscillator: 500 nA @ 32 kHz
- Variable prescaler selection • Operating Current:
- Variable window size selection - 8 A @ 32 kHz, 1.8V, typical
- All sources configurable in hardware or - 32 A/MHz @ 1.8V, typical
software
• Programmable Code Protection Digital Peripherals
• Four Configurable Logic Cells (CLC):
Memory - Integrated combinational and sequential logic
• Up to 56 KB Flash Program Memory • Three Complementary Waveform Generators
• Up to 4 KB Data SRAM (CWG):
• 256B of EEPROM - Rising and falling edge dead-band control
• Direct, Indirect and Relative Addressing modes - Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
Operating Characteristics • Five Capture/Compare/PWM (CCP) module:
- 16-bit resolution for Capture/Compare modes
• Operating Voltage Range: - 10-bit resolution for PWM mode
- 1.8V to 3.6V (PIC16LF18857/77) • 10-bit PWM:
- 2.3V to 5.5V (PIC16F18857/77) - Two 10-bit PWMs
• Temperature Range: • Numerically Controlled Oscillator (NCO):
- Industrial: -40°C to 85°C - Generates true linear frequency control and
- Extended: -40°C to 125°C increased frequency resolution
- Input Clock: 0 Hz < FNCO < 32 MHz
- Resolution: FNCO/220
• Two Signal Measurement Timers (SMT):
- 24-bit Signal Measurement Timer
- Up to 12 different Acquisition modes
 2016-2021 Microchip Technology Inc. DS40001825F-page 1

PIC16(L)F18857/77
Digital Peripherals (Cont.) Flexible Oscillator Structure
• Cyclical Redundancy Check (CRC/SCAN): • High-Precision Internal Oscillator:
- 16-bit CRC - Software selectable frequency range up to 32
- Scans memory for NVM integrity MHz, ±1% typical
• Communication: • x2/x4 PLL with Internal and External Sources
- EUSART, RS-232, RS-485, LIN compatible • Low-Power Internal 32 kHz Oscillator
- Two SPI (LFINTOSC)
- Two I2C, SMBus, PMBus™ compatible • External 32 kHz Crystal Oscillator (SOSC)
• Up to 36 I/O Pins: • External Oscillator Block with:
- Individually programmable pull-ups - Three crystal/resonator modes up to 20 MHz
- Slew rate control - Three external clock modes up to 20 MHz
- Interrupt-on-change with edge-select • Fail-Safe Clock Monitor:
- Input level selection control (ST or TTL) - Allows for safe shutdown if peripheral clock
- Digital open-drain enable stops
- Current mode enable • Oscillator Start-up Timer (OST)
• Peripheral Pin Select (PPS): - Ensures stability of crystal oscillator
- Enables pin mapping of digital I/O resources
• Data Signal Modulator (DSM)
- Modulates a carrier signal with digital data to
create custom carrier synchronized output
waveforms
Analog Peripherals
• Analog-to-Digital Converter with Computation
(ADC2):
- 10-bit with up to 35 external channels
- Automated post-processing
- Automates math functions on input signals:
averaging, filter calculations, oversampling
and threshold comparison
- Operates in Sleep
• Two Comparators (COMP):
- Fixed Voltage Reference at (non) inverting
input(s)
- Comparator outputs externally accessible
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels

PIC16(L)F18857/77
PIC16(L)F188XX Family Types
CRC and Memory Scan
Peripheral Pin Select

Peripheral Module
Zero-Cross Detect
10-Bit ADC2 (ch)
Data Sheet Index
CCP/10-Bit PWM
Memory (Words)
Watchdog Timer
EUSART/I2C/SPI
8-Bit (with HLT)/
Program Flash
Program Flash
16-Bit Timers
Memory (KB)
Comparator
Data SRAM
Windowed
I/O Pins(1)
Disable
5-Bit DAC
EEPROM
(bytes)
(bytes)
CWG
NCO
DSM
SMT
CLC
Device
PIC16(L)F18854 (1) 4096 7 256 512 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y

PIC16(L)F18855 (2) 8192 14 256 1024 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18856 (3) 16384 28 256 2048 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18857 (4) 32768 56 256 4096 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18875 (2) 8192 14 256 1024 36 35 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18876 (3) 16384 28 256 2048 36 35 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
PIC16(L)F18877 (4) 32768 56 256 4096 36 35 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y
Note 1: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document)
1: DS40001826 PIC16(L)F18854 Data Sheet, 28-Pin, Full-Featured 8-bit Microcontrollers
2: DS40001802 PIC16(L)F18855/75 Data Sheet, 28/40-Pin, Full-Featured 8-bit Microcontrollers
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.

PIC16(L)F18857/77
TABLE 1: PACKAGES
QFN UQFN QFN UQFN VQFN
Packages (S)PDIP SOIC SSOP TQFP
(6x6) (4x4) (8x8) (5x5) (5x5)
PIC16(L)F18857    
PIC16(L)F18877     
Note: Pin details are subject to change.
PIN DIAGRAMS
28-pin SPDIP, SOIC, SSOP
VPP/MCLR/RE3 1 28 RB7
RA0 2 27 RB6
RA1 3 26 RB5
RA2 4 25 RB4
RA3 5 24 RB3
RA4 6 23 RB2
RA5 7 PIC16(L)F18857 22 RB1
VSS 8 21 RB0
RA7 9 20 VDD
RA6 10 19 VSS
RC0 11 18 RC7
RC1 12 17 RC6
RC2 13 16 RC5
RC3 14 15 RC4
Note 1: See Table 2 for location of all peripheral functions.

2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins
to float may result in degraded electrical performance or non-functionality.

PIC16(L)F18857/77
28-pin QFN (6x6)
RE3/MCLR/VPP
RA1
RA0
RB7
RB6
RB5
RB4
28
27
26
24
23
22
25
RA2 1 21 RB3
RA3 2 20 RB2
RA4 3 19 RB1
RA5 PIC16(L)F18857
4 18 RB0
VSS 5 17 VDD
RA7 6 16 VSS
RA6 7 15 RC7
10
12
13
14
11
8
9
RC4
RC2
RC3
RC5
RC6
RC1
Note 1: RC0
See Table 2 for location of all peripheral functions.
2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
3: The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.
40-pin PDIP
VPP/MCLR/RE3 1 40 RB7/ICSPDAT
RA0 2 39 RB6/ICSPCLK
RA1 3 38 RB5
RA2 4 37 RB4
RA3 5 36 RB3
RA4 6 35 RB2
RA5 7 34 RB1
RE0 RB0
PIC16(L)F18877
8 33
RE1 9 32 VDD
RE2 10 31 VSS
VDD 11 30 RD7
VSS 12 29 RD6
RA7 13 28 RD5
RA6 14 27 RD4
RC0 15 26 RC7
RC1 16 25 RC6
RC2 17 24 RC5
RC3 18 23 RC4
RD0 19 22 RD3
RD1 20 21 RD2
Note 1: See Table 3 for location of all peripheral function.


PIC16(L)F18857/77
40-pin UQFN (5x5)
RC5
RC6
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1 31
34
40
39
37
36
35
33
32
38
RC7 1
RD4 2 30 RC0
RD5 3 29 RA6
RD6 4 28 RA7
RD7 5 27 VSS
VSS 6
PIC16(L)F18877 26 VDD
VDD 7 25 RE2
RB0 8 24 RE1
RB1 9 23 RE0
RB2 10 22 RA5
21 RA4
12
13
14
15
16
17
18
19
20
11
ICSPCLK/RB6
ICSPDAT/RB7
RB3
RA1
RA2
RA3
RB4
RB5
VPP/MCLR/RE3
RA0

40-pin VQFN (5x5)

RC5
RC6
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1 31
34
40
39
37
36
35
33
32
38
RC7 1
RD4 2 30 RC0
RD5 3 29 RA6
RD6 4 28 RA7
RD7 5 27 VSS
VSS 6
PIC16(L)F18877 26 VDD
VDD 7 25 RE2
RB0 8 24 RE1
RB1 9 23 RE0
RB2 10 22 RA5
21 RA4
12
13
14
15
16
17
18
19
20
11
ICSPCLK/RB6
ICSPDAT/RB7
RB3
RA1
RA2
RA3
RB4
RB5
VPP/MCLR/RE3
RA0

3: The bottom pad of the VQFN package should be connected to VSS at the circuit board level.

PIC16(L)F18857/77
44-pin TQFP (10x10)
RC5
RC6
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
41
40
39
37
36
35
34
42
44
43
38
RC7 1 33 NC
RD4 2 32 RC0
RD5 3 31 RA6
4 30 RA7
RD6
5 29 VSS
RD7
PIC16(L)F18877 28 VDD
VSS 6
27 RE2
VDD 7
RB0 8 26 RE1
25 RE0
RB1 9
24 RA5
RB2 10
23 RA4
RB3 11 12
13
14
15
16
17
18
19
20
21
22
NC
NC
ICSPCLK/RB6
ICSPDAT/RB7
RA2
RA3
RB4
RB5
VPP/MCLR/RE3
AN0/RA0
RA1

44-pin QFN (8x8)

RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
44
43
42
41
40
39
37
36
35
34
38
RC7 1 33 RA6
RD4 2 32 RA7
RD5 3 31 NC
RD6 4 30 VSS
RD7 5 29 NC
VSS 6 PIC16(L)F18877 28 VDD
VDD 7 27 RE2
NC 8 26 RE1
RB0 9 25 RE0
RB1 10 24 RA5
RB2 11 23 RA4
22
12
13
14
15
16
17
18
19
20
21
RA1
RA2
ICSPDAT/RB7
RA0
VPP/MCLR/RE3
ICSPCLK/RB6
RA3
RB3
RB4
RB5
NC


PIN ALLOCATION TABLES
 2016-2021 Microchip Technology Inc.
PIC16(L)F18857/77
TABLE 2: 28-PIN ALLOCATION TABLE (PIC16(L)F18857)
28-Pin SPDIP/SOIC/SSOP
Clock Reference (CLKR)
Interrupt-on-Change
Zero-Cross Detect
Voltage Reference
MSSP (SPI/I2C)
CCP and PWM

28-Pin (U)QFN
Comparators
Timers/SMT
EUSART
Basic
CWG
DSM
NCO
ADC
DAC
CLC
I/O
RA0 2 27 ANA0 — — C1IN0- — — — — — — — CLCIN0(1) — — IOCA0 —

C2IN0-
RA1 3 28 ANA1 — — C1IN1- — — — — — — — CLCIN1(1) — — IOCA1 —
C2IN1-
RA2 4 1 ANA2 VREF- DAC1OUT1 C1IN0+ — — — — — — — — — — IOCA2 —
C2IN0+
RA3 5 2 ANA3 VREF+ — C1IN1+ — — — MDCARL(1) — — — — — — IOCA3 —
RA4 6 3 ANA4 — — — — — — MDCARH(1) T0CKI(1) CCP5(1) — — — — IOCA4 —
RA5 7 4 ANA5 — — — — SS1(1) — MDSRC(1) — — — — — — IOCA5 —
RA6 10 7 ANA6 — — — — — — — — — — — — — IOCA6 OSC2

CLKOUT
RA7 9 6 ANA7 — — — — — — — — — — — — — IOCA7 OSC1
CLKIN
RB0 21 18 ANB0 — — C2IN1+ ZCD SS2(1) — — — CCP4(1) CWG1IN(1) — — — INT(1) —
IOCB0
RB1 22 19 ANB1 — — C1IN3- — SCL2(3,4) — — — — CWG2IN(1) — — — IOCB1 —
C2IN3- SCK2(1)
RB2 23 20 ANB2 — — — — SDA2(3,4) — — — — CWG3IN(1) — — — IOCB2 —
SDI2(1)
RB3 24 21 ANB3 — — C1IN2- — — — — — — — — — — IOCB3 —
C2IN2-
RB4 25 22 ANB4 — — — — — — — T5G(1) — — — — — IOCB4 —
ADCACT(1) SMTWIN2(1)
DS40001825F-page 8
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTX pins. Refer to Table 13-1 for details on which port pins may be
used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTX pin options as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I2C specific or SMbus input buffer thresholds.
TABLE 2: 28-PIN ALLOCATION TABLE (PIC16(L)F18857) (CONTINUED)
PIC16(L)F18857/77
Interrupt-on-Change
Zero-Cross Detect
Voltage Reference
MSSP (SPI/I2C)
CCP and PWM

28-Pin (U)QFN
Comparators
Timers/SMT
EUSART
Basic
CWG
NCO
DSM
ADC
DAC
CLC
I/O
RB5 26 23 ANB5 — — — — — — — T1G(1) CCP3(1) — — — — IOCB5 —

SMTSIG2(1)
RB6 27 24 ANB6 — — — — — — — — — — CLCIN2(1) — — IOCB6 ICSPCLK
RB7 28 25 ANB7 — DAC1OUT2 — — — — — T6IN(1) — — CLCIN3(1) — — IOCB7 ICSPDAT
RC0 11 8 ANC0 — — — — — — — T1CKI(1) — — — — — IOCC0 SOSCO

T3CKI(1)
T3G(1)
SMTWIN1(1)
RC1 12 9 ANC1 — — — — — — — SMTSIG1(1) CCP2(1) — — — — IOCC1 SOSCI
(1) (1)
RC2 13 10 ANC2 — — — — — — — T5CKI CCP1 — — — — IOCC2 —
RC3 14 11 ANC3 — — — — SCL1(3,4) — — T2IN(1) — — — — — IOCC3 —

SCK1(1)
RC4 15 12 ANC4 — — — — SDA1(3,4) — — — — — — — — IOCC4 —
SDI1(1)
RC5 16 13 ANC5 — — — — — — — T4IN(1) — — — — — IOCC5 —
RC6 17 14 ANC6 — — — — — CK(3) — — — — — — — IOCC6 —
RC7 18 15 ANC7 — — — — — RX(1) — — — — — — — IOCC7 —

DT(3)
RE3 1 26 — — — — — — — — — — — — — — IOCE3 MCLR
VPP
VDD 20 17 — — — — — — — — — — — — — — — —
VSS 8, 5, — — — — — — — — — — — — — — — —
19 16
DS40001825F-page 9
TABLE 2: 28-PIN ALLOCATION TABLE (PIC16(L)F18857) (CONTINUED)
PIC16(L)F18857/77
Interrupt-on-Change
Zero-Cross Detect
Voltage Reference
MSSP (SPI/I2C)
CCP and PWM

28-Pin (U)QFN
Comparators
Timers/SMT
EUSART
Basic
CWG
NCO
DSM
ADC
DAC
CLC
I/O
OUT(2) — — ADGRDA — — C1OUT — SDO1 TX/ DSM TMR0 CCP1 CWG1A CLC1OUT NCO CLKR — —
ADGRDB C2OUT SCK1 CK(3) CCP2 CWG1B CLC2OUT
SDO2 DT(3) CCP3 CWG1C CLC3OUT
SCK2 CCP4 CWG1D CLC4OUT
CCP5 CWG2A
PWM6OUT CWG2B
PWM7OUT CWG2C
CWG2D
CWG3A
CWG3B
CWG3C
CWG3D
DS40001825F-page 10
PIC16(L)F18857/77
TABLE 3: 40/44-PIN ALLOCATION TABLE (PIC16(L)F18877)
Interrupt-on-Change
Voltage Reference
Zero-Cross Detect
MSSP (SPI/I2C)
CCP and PWM

Comparators
40-Pin UQFN
44-Pin TQFP
Timers/SMT
40-Pin PDIP
44-Pin QFN
EUSART
Basic
CWG
DSM
NCO
ADC
DAC
CLC
!/O
RA0 2 17 19 19 ANA0 — — C1IN0- — — — — — — — CLCIN0(1) — — IOCA0 —

C2IN0-
RA1 3 18 20 20 ANA1 — — C1IN1- — — — — — — — CLCIN1(1) — — IOCA1 —
C2IN1-
RA2 4 19 21 21 ANA2 VREF- DAC1OUT1 C1IN0+ — — — — — — — — — — IOCA2 —
C2IN0+
RA3 5 20 22 22 ANA3 VREF+ — C1IN1+ — — — MDCARL(1) — — — — — — IOCA3 —
(1) (1) (1)
RA4 6 21 23 23 ANA4 — — — — — — MDCARH T0CKI CCP5 — — — — IOCA4 —
RA5 7 22 24 24 ANA5 — — — — SS1(1) — MDSRC(1) — — — — — — IOCA5 —
RA6 14 29 33 31 ANA6 — — — — — — — — — — — — — IOCA6 OSC2

CLKOUT
RA7 13 28 32 30 ANA7 — — — — — — — — — — — — — IOCA7 OSC1
CLKIN
RB0 33 8 9 8 ANB0 — — C2IN1+ ZCD SS2(1) — — — CCP4(1) CWG1IN(1) — — — INT(1) —
IOCB0
RB1 34 9 10 9 ANB1 — — C1IN3- — SCL2(3,4) — — — — CWG2IN(1) — — — IOCB1 —
C2IN3- SCK2(1)
RB2 35 10 11 10 ANB2 — — — — SDA2(3,4) — — — — CWG3IN(1) — — — IOCB2 —
SDI2(1)
RB3 36 11 12 11 ANB3 — — C1IN2- — — — — — — — — — — IOCB3 —
C2IN2-
RB4 37 12 14 14 ANB4 — — — — — — — T5G(1) — — — — — IOCB4 —
ADCACT(1) SMTWIN2(1)
RB5 38 13 15 15 ANB5 — — — — — — — T1G(1) CCP3(1) — — — — IOCB5 —
SMTSIG2(1)
RB6 39 14 16 16 ANB6 — — — — — — — — — — CLCIN2(1) — — IOCB6 ICSPCLK
DS40001825F-page 11
RB7 40 15 17 17 ANB7 — DAC1OUT2 — — — — — T6IN(1) — — CLCIN3(1) — — IOCB7 ICSPDAT
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 13-1 for details on which port pins may be
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 13-3.
TABLE 3: 40/44-PIN ALLOCATION TABLE (PIC16(L)F18877) (CONTINUED)
PIC16(L)F18857/77
Interrupt-on-Change
Zero-Cross Detect
Voltage Reference
MSSP (SPI/I2C)
CCP and PWM

Comparators
40-Pin UQFN
44-Pin TQFP
Timers/SMT
40-Pin PDIP
44-Pin QFN
EUSART
Basic
CWG
NCO
DSM
ADC
DAC
CLC
!/O
RC0 15 30 34 32 ANC0 — — — — — — — T1CKI(1) — — — — — IOCC0 SOSCO

T3CKI(1)
T3G(1)
SMTWIN1(1)
RC1 16 31 35 35 ANC1 — — — — — — — SMTSIG1(1) CCP2(1) — — — — IOCC1 SOSCI
RC2 17 32 36 36 ANC2 — — — — — — — T5CKI(1) CCP1(1) — — — — IOCC2 —
RC3 18 33 37 37 ANC3 — — — — SCL1(3,4) — — T2IN (1)

— — — — — IOCC3 —
SCK1(1)
RC4 23 38 42 42 ANC4 — — — — SDA1(3,4) — — — — — — — — IOCC4 —
SDI1(1)
RC5 24 39 43 43 ANC5 — — — — — — — T4IN(1) — — — — — IOCC5 —
RC6 25 40 44 44 ANC6 — — — — — CK(3) — — — — — — — IOCC6 —
RC7 26 1 1 1 ANC7 — — — — — RX(1) — — — — — — — IOCC7 —

DT(3)
RD0 19 34 38 38 AND0 — — — — — — — — — — — — — — —
RD1 20 35 39 39 AND1 — — — — — — — — — — — — — — —
RD2 21 36 40 40 AND2 — — — — — — — — — — — — — — —
RD3 22 37 41 41 AND3 — — — — — — — — — — — — — — —
RD4 27 2 2 2 AND4 — — — — — — — — — — — — — — —
RD5 28 3 3 3 AND5 — — — — — — — — — — — — — — —
RD6 29 4 4 4 AND6 — — — — — — — — — — — — — — —
RD7 30 5 5 5 AND7 — — — — — — — — — — — — — — —
RE0 8 23 25 25 ANE0 — — — — — — — — — — — — — — —
DS40001825F-page 12
RE1 9 24 26 26 ANE1 — — — — — — — — — — — — — — —
RE2 10 25 27 27 ANE2 — — — — — — — — — — — — — — —
TABLE 3: 40/44-PIN ALLOCATION TABLE (PIC16(L)F18877) (CONTINUED)
PIC16(L)F18857/77
Interrupt-on-Change
Zero-Cross Detect
Voltage Reference
MSSP (SPI/I2C)
CCP and PWM

Comparators
40-Pin UQFN
44-Pin TQFP
Timers/SMT
40-Pin PDIP
44-Pin QFN
EUSART
Basic
CWG
NCO
DSM
ADC
DAC
CLC
!/O
RE3 1 16 18 18 — — — — — — — — — — — — — — IOCE3 MCLR

VPP
VDD 11, 7, 7, 7, — — — — — — — — — — — — — — — —
32 26 28 28
VSS 12, 6, 6, 6, — — — — — — — — — — — — — — — —
31 27 30 29
OUT(2) — — — — ADGRDA — — C1OUT — SDO1 TX/ DSM TMR0 CCP1 CWG1A CLC1OUT NCO CLKR — —
ADGRDB C2OUT SCK1 CK(3) CCP2 CWG1B CLC2OUT
SDO2 DT(3) CCP3 CWG1C CLC3OUT
SCK2 CCP4 CWG1D CLC4OUT
CCP5 CWG2A
PWM6OUT CWG2B
PWM7OUT CWG2C
CWG2D
CWG3A
CWG3B
CWG3C
CWG3D
DS40001825F-page 13
PIC16(L)F18857/77
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 16
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 33
3.0 Memory Organization ................................................................................................................................................................. 35
4.0 Device Configuration .................................................................................................................................................................. 91
5.0 Resets ...................................................................................................................................................................................... 100
6.0 Oscillator Module (with Fail-Safe Clock Monitor) ..................................................................................................................... 109
7.0 Interrupts .................................................................................................................................................................................. 128
8.0 Power-Saving Operation Modes .............................................................................................................................................. 154
9.0 Windowed Watchdog Timer (WWDT) ...................................................................................................................................... 161
10.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 169
11.0 Cyclic Redundancy Check (CRC) Module ............................................................................................................................... 187
12.0 I/O Ports ................................................................................................................................................................................... 199
13.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 234
14.0 Peripheral Module Disable ....................................................................................................................................................... 244
15.0 Interrupt-On-Change ................................................................................................................................................................ 251
16.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 259
17.0 Temperature Indicator Module ................................................................................................................................................. 262
18.0 Comparator Module.................................................................................................................................................................. 264
19.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 274
20.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 281
21.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 305
22.0 Configurable Logic Cell (CLC).................................................................................................................................................. 311
23.0 Analog-to-Digital Converter With Computation (ADC2) Module............................................................................................... 328
24.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 366
25.0 5-Bit Digital-to-Analog Converter (DAC1) Module.................................................................................................................... 376
26.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 381
27.0 Timer0 Module ......................................................................................................................................................................... 393
28.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 399
29.0 Timer2/4/6 Module ................................................................................................................................................................... 413
30.0 Capture/Compare/PWM Modules ............................................................................................................................................ 434
31.0 Host Synchronous Serial Port (MSSP) Modules ...................................................................................................................... 447
32.0 Signal Measurement Timer (SMT) ........................................................................................................................................... 498
33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 543
34.0 Reference Clock Output Module .............................................................................................................................................. 571
35.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 575
36.0 Instruction Set Summary .......................................................................................................................................................... 577
37.0 Electrical Specifications............................................................................................................................................................ 591
38.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 621
39.0 Development Support............................................................................................................................................................... 637
40.0 Packaging Information.............................................................................................................................................................. 638
Appendix A: Data Sheet Revision History ......................................................................................................................................... 664

PIC16(L)F18857/77
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PIC16(L)F18857/77
1.0 DEVICE OVERVIEW
TABLE 1-1: DEVICE PERIPHERAL
The PIC16(L)F18857/77 are described within this data
SUMMARY
sheet. The PIC16(L)F18857 devices are available in
28-pin SPDIP, SSOP, SOIC, and QFN packages. The
PIC16(L)F18857
PIC16(L)F18857
PIC16(L)F18877 devices are available in 40-pin PDIP
and QFN and 44-pin TQFP and QFN packages. Peripheral
Figure 1-1 shows a block diagram of the
PIC16(L)F18857/77 devices. Table 1-2 and Table 1-3
show the pinout descriptions.
Analog-to-Digital Converter with Computation (ADC2) ● ●
Reference Table 1-1 for peripherals available per device. Cyclic Redundancy Check (CRC) ● ●
Digital-to-Analog Converter (DAC) ● ●
Fixed Voltage Reference (FVR) ● ●
Enhanced Universal Synchronous/Asynchronous Receiver/ ● ●
Transmitter (EUSART1)
Digital Signal Modulator (DSM) ● ●
Numerically Controlled Oscillator (NCO1) ● ●
Temperature Indicator ● ●
Zero-Cross Detect (ZCD) ● ●
Capture/Compare/PWM (CCP/ECCP) Modules
CCP1 ● ●
CCP2 ● ●
CCP3 ● ●
CCP4 ● ●
CCP5 ● ●
Comparators
C1 ● ●
C2 ● ●
Configurable Logic Cell (CLC)
CLC1 ● ●
CLC2 ● ●
CLC3 ● ●
CLC4 ● ●
Complementary Waveform Generator (CWG)
CWG1 ● ●
CWG2 ● ●
CWG3 ● ●
Host Synchronous Serial Ports
MSSP1 ● ●
MSSP2 ● ●
Pulse-Width Modulator (PWM)
PWM6 ● ●
PWM7 ● ●
Signal Measure Timer (SMT)
SMT1 ● ●
SMT2 ● ●
Timers
Timer0 ● ●
Timer1 ● ●
Timer2 ● ●
Timer3 ● ●
Timer4 ● ●
Timer5 ● ●
Timer6 ● ●

PIC16(L)F18857/77
1.1 Register and Bit naming 1.1.2.3 Bit Fields
conventions Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
1.1.1 REGISTER NAMES convention. For example, the three Least Significant
When there are multiple instances of the same bits of the COG1CON0 register contain the mode
peripheral in a device, the peripheral control registers control bits. The short name for this field is MD. There
will be depicted as the concatenation of a peripheral is no long bit name variant. Bit field access is only
identifier, peripheral instance, and control identifier. possible in C programs. The following example
The control registers section will show just one demonstrates a C program instruction for setting the
instance of all the register names with an ‘x’ in the place COG1 to the Push-Pull mode:
of the peripheral instance number. This naming COG1CON0bits.MD = 0x5;
convention may also be applied to peripherals when
Individual bits in a bit field can also be accessed with
there is only one instance of that peripheral in the
long and short bit names. Each bit is the field name
device to maintain compatibility with other devices in
appended with the number of the bit position within the
the family that contain more than one.
field. For example, the Most Significant mode bit has
1.1.2 BIT NAMES the short bit name MD2 and the long bit name is
G1MD2. The following two examples demonstrate
There are two variants for bit names: assembly program sequences for setting the COG1 to
• Short name: Bit function abbreviation Push-Pull mode:
• Long name: Peripheral abbreviation + short name Example 1:
MOVLW ~(1<<G1MD1)
1.1.2.1 Short Bit Names ANDWF COG1CON0,F
Short bit names are an abbreviation for the bit function. MOVLW 1<<G1MD2 | 1<<G1MD0
For example, some peripherals are enabled with the IORWF COG1CON0,F
EN bit. The bit names shown in the registers are the Example 2:
short name variant.
BSF COG1CON0,G1MD2
Short bit names are useful when accessing bits in C BCF COG1CON0,G1MD1
programs. The general format for accessing bits by the BSF COG1CON0,G1MD0
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 regis- 1.1.3 REGISTER AND BIT NAMING
ter can be set in C programs with the instruction EXCEPTIONS
COG1CON0bits.EN = 1.
1.1.3.1 Status, Interrupt, and Mirror Bits
Short names are generally not useful in assembly
programs because the same name may be used by Status, interrupt enables, interrupt flags, and mirror bits
different peripherals in different bit positions. When this are contained in registers that span more than one
occurs, during the include file generation, all instances peripheral. In these cases, the bit name shown is
of that short bit name are appended with an underscore unique so there is no prefix or short name variant.
plus the name of the register in which the bit resides to
avoid naming contentions. 1.1.3.2 Legacy Peripherals
There are some peripherals that do not strictly adhere
1.1.2.2 Long Bit Names to these naming conventions. Peripherals that have
Long bit names are constructed by adding a peripheral existed for many years and are present in almost every
abbreviation prefix to the short name. The prefix is device are the exceptions. These exceptions were
unique to the peripheral thereby making every long bit necessary to limit the adverse impact of the new
name unique. The long bit name for the COG1 enable conventions on legacy code. Peripherals that do
bit is the COG1 prefix, G1, appended with the enable adhere to the new convention will include a table in the
bit short name, EN, resulting in the unique bit name registers section indicating the long name prefix for
G1EN. each peripheral instance. Peripherals that fall into the
exception category will not have this table. These
Long bit names are useful in both C and assembly pro-
peripherals include, but are not limited to, the following:
grams. For example, in C the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly, • EUSART
this bit can be set with the BSF COG1CON0,G1EN • MSSP
instruction.

FIGURE 1-1: PIC16(L)F18857/77 BLOCK DIAGRAM
PIC16(L)F18857/77
Rev. 10-000039J
Program 11/20/2015
Flash Memory
RAM
PORTA
CLKOUT
/OSC2 Timing PORTB
Generation
CPU
CLKIN/
OSC1 INTRC PORTC
Oscillator
(Note 3)
(4)
PORTD
MCLR
PORTE
Temp ADC
TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 Scanner CRC DSM C2 C1 DAC FVR
Indicator 10-bit
CWG1 CWG2 CWG3 SMT2 SMT1 NCO1 EUSART MSSP2 MSSP1 CLC4 CLC3 CLC2 CLC1 ZCD1 PWM6/7 CCPs(5)
Note 1: See applicable chapters for more information on peripherals.

2: See Table 1-1 for peripherals available on specific devices.
3: See Figure 2-1.
DS40001825F-page 18
4: PIC16(L)F18877 only.
PIC16(L)F18857/77
TABLE 1-2: PIC16F18857 PINOUT DESCRIPTION

Input
Name Function Output Type Description
Type
RA0/ANA0/C1IN0-/C2IN0-/CLCIN0(1)/ RA0 TTL/ST CMOS/OD General purpose I/O.

IOCA0
ANA0 AN — ADC Channel A0 input.
C1IN0- AN — Comparator negative input.
CLCIN0(1) TTL/ST — Configurable Logic Cell source input.
IOCA0 TTL/ST — Interrupt-on-change input.
RA1/ANA1/C1IN1-/C2IN1-/CLCIN1(1)/ RA1 TTL/ST CMOS/OD General purpose I/O.

IOCA1
RA2/ANA2/C1IN0+/C2IN0+/VREF-/ RA2 TTL/ST CMOS/OD General purpose I/O.

DAC1OUT1/IOCA2
C1IN0+ AN — Comparator positive input.
VREF- AN — External ADC and/or DAC negative reference input.
DAC1OUT1 — AN Digital-to-Analog Converter output.
RA3/ANA3/C1IN1+/VREF+/MDCARL(1)/ RA3 TTL/ST CMOS/OD General purpose I/O.

IOCA3
VREF+ AN — External ADC and/or DAC positive reference input.
MDCARL(1) TTL/ST — Modular Carrier input 1.
RA4/ANA4/MDCARH(1)/T0CKI(1)/ RA4 TTL/ST CMOS/OD General purpose I/O.

CCP5(1)/IOCA4
(1)
MDCARH TTL/ST — Modular Carrier input 2.
T0CKI(1) TTL/ST — Timer0 clock input.
CCP5(1) TTL/ST CMOS/OD Capture/compare/PWM5 (default input location for capture

function).
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.

PIC16(L)F18857/77
TABLE 1-2: PIC16F18857 PINOUT DESCRIPTION (CONTINUED)
Input
Type
RA5/ANA5/SS1(1)/MDSRC(1)/IOCA5 RA5 TTL/ST CMOS/OD General purpose I/O.

(1)
SS1 TTL/ST — MSSP1 SPI client select input.
MDSRC(1) TTL/ST — Modulator Source input.
RA6/ANA6/OSC2/CLKOUT/IOCA6 RA6 TTL/ST CMOS/OD General purpose I/O.
OSC2 — XTAL External Crystal/Resonator (LP, XT, HS modes) driver output.
CLKOUT — CMOS/OD FOSC/4 digital output (in non-crystal/resonator modes).
RA7/ANA7/OSC1/CLKIN/IOCA7 RA7 TTL/ST CMOS/OD General purpose I/O.
OSC1 XTAL — External Crystal/Resonator (LP, XT, HS modes) driver input.
CLKIN TTL/ST — External digital clock input.

(1)
RB0/ANB0/C2IN1+/ZCD/SS2 / RB0 TTL/ST CMOS/OD General purpose I/O.
CCP4(1)/CWG1IN(1)/INT(1)/IOCB0
ANB0 AN — ADC Channel B0 input.
ZCD AN AN Zero-cross detect input pin.
SS2(1) TTL/ST — MSSP2 SPI client select input.

(1)
CCP4 TTL/ST CMOS/OD Capture/compare/PWM4 (default input location for capture
function).
CWG1IN(1) TTL/ST — Complementary Waveform Generator 1 input.
(1)
INT TTL/ST — External interrupt request input.
IOCB0 TTL/ST — Interrupt-on-change input.
RB1/ANB1/C1IN3-/C2IN3-/SCL2(3,4)/ RB1 TTL/ST CMOS/OD General purpose I/O.

SCK2(1)/CWG2IN(1)/IOCB1
SCL2(3,4) I2C/ OD MSSP2 I2C clock input/output.

SMBus
SCK2(1) TTL/ST CMOS/OD MSSP2 SPI serial clock (default input location, SCK2 is a PPS
remappable input and output).

PIC16(L)F18857/77
Input
Type
RB2/ANB2/SDA2(3,4)/SDI2(1)/ RB2 TTL/ST CMOS/OD General purpose I/O.

CWG3IN(1)/IOCB2
(3,4) 2
SDA2 I C/ OD MSSP2 I2C serial data input/output.
SMBus
SDI2(1) TTL/ST — MSSP2 SPI serial data input.
RB3/ANB3/C1IN2-/C2IN2-/IOCB3 RB3 TTL/ST CMOS/OD General purpose I/O.

(1) (1)
RB4/ANB4/ADCACT /T5G / RB4 TTL/ST CMOS/OD General purpose I/O.
SMTWIN2(1)/IOCB4
ADCACT(1) TTL/ST — ADC Auto-Conversion Trigger input.

(1)
T5G TTL/ST — Timer5 gate input.
SMTWIN2(1) TTL/ST — Signal Measurement Timer 2 (SMT2) window input.
RB5/ANB5/T1G(1)/SMTSIG2(1)/ RB5 TTL/ST CMOS/OD General purpose I/O.

CCP3(1)/IOCB5
(1)
SMTSIG2(1) TTL/ST — Signal Measurement Timer 2 (SMT2) signal input.

function).
(1)
RB6/ANB6/CLCIN2 /IOCB6/ICSPCLK RB6 TTL/ST CMOS/OD General purpose I/O.
ICSPCLK ST — In-Circuit Serial Programming™ and debugging clock input.

PIC16(L)F18857/77
Input
Type
RB7/ANB7/DAC1OUT2/T6IN(1)/ RB7 TTL/ST CMOS/OD General purpose I/O.

CLCIN3(1)/IOCB7/ICSPDAT
T6IN(1) TTL/ST — Timer6 external digital clock input.
ICSPDAT ST CMOS In-Circuit Serial Programming™ and debugging data input/out-

put.
RC0/ANC0/T1CKI(1)/T3CKI(1)/T3G(1)/ RC0 TTL/ST CMOS/OD General purpose I/O.
SMTWIN1(1)/IOCC0/SOSCO
ANC0 AN — ADC Channel C0 input.
T1CKI(1) TTL/ST — Timer1 external digital clock input.

(1)
T3CKI TTL/ST — Timer3 external digital clock input.
(1)
SMTWIN1(1) TTL/ST — Signal Measurement Timer1 (SMT1) input.
IOCC0 TTL/ST — Interrupt-on-change input.
SOSCO — AN 32.768 kHz secondary oscillator crystal driver output.
RC1/ANC1/SMTSIG1(1)/CCP2(1)/ RC1 TTL/ST CMOS/OD General purpose I/O.

IOCC1/SOSCI
SMTSIG1(1) TTL/ST — Signal Measurement Timer1 (SMT1) signal input.

function).
SOSCI AN — 32.768 kHz secondary oscillator crystal driver input.
RC2/ANC2/T5CKI(1)/CCP1(1)/IOCC2 RC2 TTL/ST CMOS/OD General purpose I/O.

(1)

function).
RC3/ANC3/SCL1(3,4)/SCK1(1)/T2IN(1)/ RC3 TTL/ST CMOS/OD General purpose I/O.

IOCC3
(3,4) 2
SCL1 I C/ OD MSSP1 I2C clock input/output.
SMBus
SCK1(1) TTL/ST CMOS/OD MSSP1 SPI clock input/output (default input location, SCK1 is a
PPS remappable input and output).
T2IN(1) TTL/ST — Timer2 external input.

PIC16(L)F18857/77
Input
Type
RC4/ANC4/SDA1(3,4)/SDI1(1)/IOCC4 RC4 TTL/ST CMOS/OD General purpose I/O.

(3,4) 2
SDA1 I C/ OD MSSP1 I2C serial data input/output.
SMBus
SDI1(1) TTL/ST — MSSP1 SPI serial data input.

(1)
RC5/ANC5/T4IN /IOCC5 RC5 TTL/ST CMOS/OD General purpose I/O.
RC6/ANC6/CK(3)/IOCC6 RC6 TTL/ST CMOS/OD General purpose I/O.

(3)
CK TTL/ST CMOS/OD EUSART synchronous mode clock input/output.

(1) (3)
RC7/ANC7/RX /DT /IOCC7 RC7 TTL/ST CMOS/OD General purpose I/O.
RX(1) TTL/ST — EUSART Asynchronous mode receiver data input.

(3)
DT TTL/ST CMOS/OD EUSART Synchronous mode data input/output.
RE3/IOCE3/MCLR/VPP RE3 TTL/ST — General purpose input only (when MCLR is disabled by the
Configuration bit).
IOCE3 TTL/ST — Interrupt-on-change input.
MCLR ST — Master clear input with internal weak pull up resistor.
VPP HV — ICSP™ High-Voltage Programming mode entry input.
VDD VDD Power — Positive supply voltage input.

PIC16(L)F18857/77
Input
Type
VSS VSS Power — Ground reference.
OUT(2) ADGRDA — CMOS/OD ADC Guard Ring A output.
ADGRDB — CMOS/OD ADC Guard Ring B output.
C1OUT — CMOS/OD Comparator 1 output.
SDO1 — CMOS/OD MSSP1 SPI serial data output.
SCK1 — CMOS/OD MSSP1 SPI serial clock output.
TX — CMOS/OD EUSART Asynchronous mode transmitter data output.
CK(3) — CMOS/OD EUSART Synchronous mode clock output.
DT(3) — CMOS/OD EUSART Synchronous mode data output.
DSM — CMOS/OD Data Signal Modulator output.
TMR0 — CMOS/OD Timer0 output.
CCP1 — CMOS/OD Capture/Compare/PWM1 output (compare/PWM functions).
PWM6OUT — CMOS/OD PWM6 output.
CWG1A — CMOS/OD Complementary Waveform Generator 1 output A.
CWG1B — CMOS/OD Complementary Waveform Generator 1 output B.
CWG1C — CMOS/OD Complementary Waveform Generator 1 output C.
CWG1D — CMOS/OD Complementary Waveform Generator 1 output D.

PIC16(L)F18857/77
Input
Type
OUT(2) CWG3C — CMOS/OD Complementary Waveform Generator 3 output C.
CLC1OUT — CMOS/OD Configurable Logic Cell 1 output.
NCO1 — CMOS/OD Numerically Controller Oscillator output.
CLKR — CMOS/OD Clock Reference module output.

PIC16(L)F18857/77
TABLE 1-3: PIC16F18877 PINOUT DESCRIPTION

Name Function Input Type Output Type Description
RA0/ANA0/C1IN0-/C2IN0-/ RA0 TTL/ST CMOS/OD General purpose I/O.

CLCIN0(1)/IOCA0

(1)
CLCIN0 TTL/ST — Configurable Logic Cell source input.
RA1/ANA1/C1IN1-/C2IN1-/ RA1 TTL/ST CMOS/OD General purpose I/O.

CLCIN1(1)/IOCA1

(1)
RA2/ANA2/C1IN0+/C2IN0+/VREF-/ RA2 TTL/ST CMOS/OD General purpose I/O.

DAC1OUT1/IOCA2
VREF- AN — External ADC and/or DAC negative reference input.
RA3/ANA3/C1IN1+/VREF+/ RA3 TTL/ST CMOS/OD General purpose I/O.

MDCARL(1)/IOCA3
VREF+ AN — External ADC and/or DAC positive reference input.
MDCARL(1) TTL/ST — Modular Carrier input 1.
RA4/ANA4/MDCARH(1)/T0CKI(1)/ RA4 TTL/ST CMOS/OD General purpose I/O.

CCP5(1)/IOCA4
(1)
MDCARH TTL/ST — Modular Carrier input 2.
T0CKI(1) TTL/ST — Timer0 clock input.

function).
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2CHV=
High Voltage XTAL= Crystal levels

PIC16(L)F18857/77
RA5/ANA5/SS1(1)/MDSRC(1)/IOCA5 RA5 TTL/ST CMOS/OD General purpose I/O.

(1)
SS1 TTL/ST — MSSP1 SPI client select input.
MDSRC(1) TTL/ST — Modulator Source input.
RA6/ANA6/OSC2/CLKOUT/IOCA6 RA6 TTL/ST CMOS/OD General purpose I/O.
OSC2 — XTAL External Crystal/Resonator (LP, XT, HS modes) driver out-

put.
CLKOUT — CMOS/OD FOSC/4 digital output (in non-crystal/resonator modes).
RA7/ANA7/OSC1/CLKIN/IOCA7 RA7 TTL/ST CMOS/OD General purpose I/O.
OSC1 XTAL — External Crystal/Resonator (LP, XT, HS modes) driver input.
CLKIN TTL/ST — External digital clock input.
RB0/ANB0/C2IN1+/ZCD/SS2(1)/ RB0 TTL/ST CMOS/OD General purpose I/O.

CCP4(1)/CWG1IN(1)/INT(1)/IOCB0
ZCD AN AN Zero-cross detect input pin.
SS2(1) TTL/ST — MSSP2 SPI client select input.

(1)
CCP4 TTL/ST CMOS/OD Capture/compare/PWM4 (default input location for capture
function).
(1)
INT TTL/ST — External interrupt request input.

(3,4)
RB1/ANB1/C1IN3-/C2IN3-/SCL2 / RB1 TTL/ST CMOS/OD General purpose I/O.
SCK2(1)/CWG2IN(1)/IOCB1
SCL2(3,4) I2C/SMBus OD MSSP2 I2C clock input/output.
SCK2(1) TTL/ST CMOS/OD MSSP2 SPI serial clock (default input location, SCK2 is a
PPS remappable input and output).

PIC16(L)F18857/77
RB2/ANB2/SDA2(3,4)/SDI2(1)/ RB2 TTL/ST CMOS/OD General purpose I/O.

CWG3IN(1)/IOCB2
(3,4) 2
SDA2 I C/SMBus OD MSSP2 I2C serial data input/output.
(1)
SDI2 TTL/ST — MSSP2 SPI serial data input.
(1)
CWG3IN TTL/ST — Complementary Waveform Generator 3 input.
RB3/ANB3/C1IN2-/C2IN2-/IOCB3 RB3 TTL/ST CMOS/OD General purpose I/O.
RB4/ANB4/ADCACT(1)/T5G(1)/ RB4 TTL/ST CMOS/OD General purpose I/O.

(1)
SMTWIN2 /IOCB4
ADCACT(1) TTL/ST — ADC Auto-Conversion Trigger input.

(1)
SMTWIN2(1) TTL/ST — Signal Measurement Timer2 (SMT2) window input.
RB5/ANB5/T1G(1)/SMTSIG2(1)/ RB5 TTL/ST CMOS/OD General purpose I/O.

CCP3(1)/IOCB5
(1)

function).
RB6/ANB6/CLCIN2(1)/IOCB6/ RB6 TTL/ST CMOS/OD General purpose I/O.

ICSPCLK
(1)
ICSPCLK ST — In-Circuit Serial Programming™ and debugging clock input.
RB7/ANB7/DAC1OUT2/T6IN(1)/ RB7 TTL/ST CMOS/OD General purpose I/O.

CLCIN3(1)/IOCB7/ICSPDAT

(1)
T6IN TTL/ST — Timer6 external digital clock input.
ICSPDAT ST CMOS In-Circuit Serial Programming™ and debugging data input/

output.

PIC16(L)F18857/77
RC0/ANC0/T1CKI(1)/T3CKI(1)/T3G(1)/ RC0 TTL/ST CMOS/OD General purpose I/O.

SMTWIN1(1)/IOCC0/SOSCO
(1)

(1)
SMTWIN1(1) TTL/ST — Signal Measurement Timer1 (SMT1) input.
SOSCO — AN 32.768 kHz secondary oscillator crystal driver output.
RC1/ANC1/SMTSIG1(1)/CCP2(1)/ RC1 TTL/ST CMOS/OD General purpose I/O.

IOCC1/SOSCI

function).
SOSCI AN — 32.768 kHz secondary oscillator crystal driver input.
RC2/ANC2/T5CKI(1)/CCP1(1)/IOCC2 RC2 TTL/ST CMOS/OD General purpose I/O.

function).
RC3/ANC3/SCL1(3,4)/SCK1(1)/ RC3 TTL/ST CMOS/OD General purpose I/O.

T2IN(1)/IOCC3
SCL1(3,4) I2C/SMBus OD MSSP1 I2C clock input/output.

(1)
SCK1 TTL/ST CMOS/OD MSSP1 SPI clock input/output (default input location, SCK1
is a PPS remappable input and output).
RC4/ANC4/SDA1(3,4)/SDI1(1)/IOCC4 RC4 TTL/ST CMOS/OD General purpose I/O.

(3,4) 2
SDA1 I C/SMBus OD MSSP1 I2C serial data input/output.
(1)
SDI1 TTL/ST — MSSP1 SPI serial data input.
RC5/ANC5/T4IN(1)/IOCC5 RC5 TTL/ST CMOS/OD General purpose I/O.

PIC16(L)F18857/77
RC6/ANC6/CK(3)/IOCC6 RC6 TTL/ST CMOS/OD General purpose I/O.

(3)
CK TTL/ST CMOS/OD EUSART synchronous mode clock input/output.

(1) (3)
RC7/ANC7/RX /DT /IOCC7 RC7 TTL/ST CMOS/OD General purpose I/O.
RX(1) TTL/ST — EUSART Asynchronous mode receiver data input.

(3)
DT TTL/ST CMOS/OD EUSART Synchronous mode data input/output.
RD0 RD0 TTL/ST CMOS/OD General purpose I/O.
AND0 AN — ADC Channel D0 input.
RE0 RE0 TTL/ST CMOS/OD General purpose I/O.
ANE0 AN — ADC Channel E0 input.
RE3/IOCE3/MCLR/VPP RE3 TTL/ST — General purpose input-only (when MCLR is disabled by

config bit).
IOCE3 TTL/ST — Interrupt-on-change input.
MCLR ST — Master clear input with internal weak pull-up resistor.
VPP HV — ICSP™ high voltage programming mode entry input.
VDD VDD Power — Positive supply voltage input.

PIC16(L)F18857/77
VSS VSS Power — Ground reference.
OUT(2) ADGRDA — CMOS/OD ADC Guard Ring A output.
ADGRDB — CMOS/OD ADC Guard Ring B output.
TX — CMOS/OD EUSART Asynchronous mode transmitter data output.
CK(3) — CMOS/OD EUSART Synchronous mode clock output.
DT(3) — CMOS/OD EUSART Synchronous mode data output.
DSM — CMOS/OD Data Signal Modulator output.
TMR0 — CMOS/OD Timer0 output.

PIC16(L)F18857/77
OUT(2) CCP3 — CMOS/OD Capture/Compare/PWM3 output (compare/PWM functions).
NCO — CMOS/OD Numerically Controller Oscillator output.
CLKR — CMOS/OD Clock Reference module output.

PIC16(L)F18857/77
2.0 ENHANCED MID-RANGE CPU Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
This family of devices contains an enhanced mid-range program and data memory.
8-bit CPU core. The CPU has 49 instructions. Interrupt
• Automatic Interrupt Context Saving
capability includes automatic context saving. The
hardware stack is 16-levels deep and has Overflow and • 16-level Stack with Overflow and Underflow
Underflow Reset capability. Direct, Indirect, and • File Select Registers
• Instruction Set
FIGURE 2-1: CORE BLOCK DIAGRAM
15
Configuration 15 8
Data Bus
Program Counter
MUX
Nonvolatile
Memory 16-Level
8 Level Stack
Stack
RAM
(13-bit)
(15-bit)
Program
14 Program Memory 12 RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction
Instruction Reg
reg
Indirect
Direct Addr 7 Addr
5 12 12
15 BSR
FSR Reg
reg
FSR0reg
FSR Reg
FSR1 Reg
FSR reg
15 STATUS Reg
STATUS reg
8
3 MUX
Power-up
Timer
Instruction Oscillator
Decodeand
Decode & Start-up Timer
ALU
Control
OSC1/CLKIN Power-on
Reset 8
Timing Watchdog
OSC2/CLKOUT Generation Timer W reg
Brown-out
Reset
Internal
Oscillator
Block
VDD VSS

PIC16(L)F18857/77
2.1 Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”
for more information.
2.2 16-Level Stack with Overflow and

Underflow
These devices have a hardware stack memory 15 bits
wide and 16 words deep. A Stack Overflow or
Underflow will set the appropriate bit (STKOVF or
STKUNF) in the PCON register, and if enabled, will
cause a software Reset. See Section 3.4 “Stack” for
more details.
2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.5 “Indirect Addressing” for more details.
2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 36.0 “Instruction Set Summary” for more
details.

PIC16(L)F18857/77
3.0 MEMORY ORGANIZATION 3.1 Program Memory Organization
These devices contain the following types of memory: The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
• Program Memory
memory space. Table 3-1 shows the memory sizes
- Configuration Words implemented. Accessing a location above these
- Device ID boundaries will cause a wrap-around within the
- User ID implemented memory space. The Reset vector is at
- Program Flash Memory 0000h and the interrupt vector is at 0004h (see
• Data Memory Figure 3-1).
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
- Data EEPROM Memory
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing
• NVMREG access
TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Size (Words) Last Program Memory Address
PIC16(L)F18857/77 32,768 7FFFh

PIC16(L)F18857/77
3.1.1 READING PROGRAM MEMORY AS
FIGURE 3-1: PROGRAM MEMORY MAP DATA
AND STACK FOR There are two methods of accessing constants in
PIC16(L)F18857/77 program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
Rev. 10-000040F
10/6/2015 FSR to point to the program memory.
PC<14:0>
3.1.1.1 RETLW Instruction
CALL, CALLW
RETURN, RETLW 15 The RETLW instruction can be used to provide access
Interrupt, RETFIE to tables of constants. The recommended way to create
Stack Level 0 such a table is shown in Example 3-1.
Stack Level 1
EXAMPLE 3-1: RETLW INSTRUCTION
constants
BRW ;Add Index in W to
Stack Level 15
;program counter to
;select data
0000h RETLW DATA0 ;Index0 data
Reset Vector
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
Interrupt Vector 0004h
0005h
my_function
07FFh ;… LOTS OF CODE…
0800h MOVLW DATA_INDEX
call constants
0FFFh ;… THE CONSTANT IS IN W
1000h
The BRW instruction makes this type of table very
17FFh simple to implement. If your code must remain portable
1800h with previous generations of microcontrollers, the older
On-chip table read method must be used because the BRW
Program Page 0 1FFFh
2000h instruction is not available in some devices.
Memory
3FFFh
4000h
7FFFh

PIC16(L)F18857/77
3.1.1.2 Indirect Read with FSR 3.2.1 CORE REGISTERS
The program memory can be accessed as data by The core registers contain the registers that directly
setting bit 7 of the FSRxH register and reading the affect the basic operation. The core registers occupy
matching INDFx register. The MOVIW instruction will the first 12 addresses of every data memory bank
place the lower eight bits of the addressed word in the (addresses x00h/x08h through x0Bh/x8Bh). These
W register. Writes to the program memory cannot be registers are listed below in Table 3-2. For detailed
performed via the INDF registers. Instructions that information, see Table 3-13.
access the program memory via the FSR require one
extra instruction cycle to complete. Example 3-2 TABLE 3-2: CORE REGISTERS
demonstrates accessing the program memory via an
FSR.
Addresses BANKx
The HIGH directive will set bit 7 if a label points to a
location in the program memory. x00h or x80h INDF0
x01h or x81h INDF1
EXAMPLE 3-2: ACCESSING PROGRAM x02h or x82h PCL
MEMORY VIA FSR x03h or x83h STATUS
constants x04h or x84h FSR0L
RETLW DATA0 ;Index0 data x05h or x85h FSR0H
RETLW DATA1 ;Index1 data x06h or x86h FSR1L
RETLW DATA2 x07h or x87h FSR1H
RETLW DATA3
x08h or x88h BSR
my_function
;… LOTS OF CODE… x09h or x89h WREG
MOVLW LOW constants x0Ah or x8Ah PCLATH
MOVWF FSR1L x0Bh or x8Bh INTCON
MOVLW HIGH constants
MOVWF FSR1H
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
3.2 Data Memory Organization

The data memory is partitioned into 32 memory banks
with 128 bytes in each bank. Each bank consists of
(Figure 3-2):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect
Addressing”” for more information.
Data memory uses a 13-bit address. The upper six bits
of the address define the Bank address and the lower
seven bits select the registers/RAM in that bank.

PIC16(L)F18857/77
3.2.1.1 STATUS Register For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
The STATUS register, shown in Register 3-1, contains:
as ‘000u u1uu’ (where u = unchanged).
• the arithmetic status of the ALU
It is recommended, therefore, that only BCF, BSF,
• the Reset status SWAPF and MOVWF instructions are used to alter the
The STATUS register can be the destination for any STATUS register, because these instructions do not
instruction, like any other register. If the STATUS affect any Status bits. For other instructions not
register is the destination for an instruction that affects affecting any Status bits (refer to Section 3.0 “Memory
the Z, DC or C bits, then the write to these three bits is Organization”).
disabled. These bits are set or cleared according to the
Note 1: The C and DC bits operate as Borrow
device logic. Furthermore, the TO and PD bits are not
and Digit Borrow out bits, respectively, in
writable. Therefore, the result of an instruction with the
subtraction.
STATUS register as destination may be different than
intended.
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — — TO PD Z DC(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

PIC16(L)F18857/77
3.2.2 SPECIAL FUNCTION REGISTER FIGURE 3-2: BANKED MEMORY
The Special Function Registers are registers used by PARTITIONING
the application to control the desired operation of
peripheral functions in the device. The Special Function Memory Region
7-bit Bank Offset
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the 00h
operation of the peripherals are described in the Core Registers
appropriate peripheral chapter of this data sheet. (12 bytes)
0Bh
3.2.3 GENERAL PURPOSE RAM 0Ch
There are up to 80 bytes of GPR in each data memory Special Function Registers
bank. The Special Function Registers occupy the 20 (20 bytes maximum)
bytes after the core registers of every data memory 1Fh
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
20h
3.2.3.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information. General Purpose RAM
(80 bytes maximum)
3.2.4 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.2.5 DEVICE MEMORY MAPS

The memory maps are as shown in Table 3-4 through
Table 3-14.

TABLE 3-3: PIC16(L)F18857 MEMORY MAP BANK 0-7
PIC16(L)F18857/77
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch ADRESL 10Ch ADCNT 18Ch SSP1BUF 20Ch TMR1L 28Ch T2TMR 30Ch CCPR1L 38Ch PWM6DCL
00Dh PORTB 08Dh ADRESH 10Dh ADRPT 18Dh SSP1ADD 20Dh TMR1H 28Dh T2PR 30Dh CCPR1H 38Dh PWM6DCH
00Eh PORTC 08Eh ADPREVL 10Eh ADLTHL 18Eh SSP1MSK 20Eh T1CON 28Eh T2CON 30Eh CCP1CON 38Eh PWM6CON
00Fh — 08Fh ADPREVH 10Fh ADLTHH 18Fh SSP1STAT 20Fh T1GCON 28Fh T2HLT 30Fh CCP1CAP 38Fh —
010h PORTE 090h ADACCL 110h ADUTHL 190h SSP1CON1 210h T1GATE 290h T2CLKCON 310h CCPR2L 390h PWM7DCL
011h TRISA 091h ADACCH 111h ADUTHH 191h SSP1CON2 211h T1CLK 291h T2RST 311h CCPR2H 391h PWM7DCH
012h TRISB 092h — 112h ADSTPTL 192h SSP1CON3 212h TMR3L 292h T4TMR 312h CCP2CON 392h PWM7CON
013h TRISC 093h ADCON0 113h ADSTPTH 193h — 213h TMR3H 293h T4PR 313h CCP2CAP 393h —
014h — 094h ADCON1 114h ADFLTRL 194h — 214h T3CON 294h T4CON 314h CCPR3L 394h —
015h — 095h ADCON2 115h ADFLTRH 195h — 215h T3GCON 295h T4HLT 315h CCPR3H 395h —
016h LATA 096h ADCON3 116h ADERRL 196h SSP2BUF 216h T3GATE 296h T4CLKCON 316h CCP3CON 396h —
017h LATB 097h ADSTAT 117h ADERRH 197h SSP2ADD 217h T3CLK 297h T4RST 317h CCP3CAP 397h —
018h LATC 098h ADCLK 118h — 198h SSP2MSK 218h TMR5L 298h T6TMR 318h CCPR4L 398h —
019h — 099h ADACT 119h RC1REG 199h SSP2STAT 219h TMR5H 299h T6PR 319h CCPR4H 399h —
01Ah — 09Ah ADREF 11Ah TX1REG 19Ah SSP2CON1 21Ah T5CON 29Ah T6CON 31Ah CCP4CON 39Ah —
01Bh — 09Bh ADCAP 11Bh SP1BRGL 19Bh SSP2CON2 21Bh T5GCON 29Bh T6HLT 31Bh CCP4CAP 39Bh —
01Ch TMR0L 09Ch ADPRE 11Ch SP1BRGH 19Ch SSP2CON3 21Ch T5GATE 29Ch T6CLKCON 31Ch CCPR5L 39Ch —
01Dh TMR0H 09Dh ADACQ 11Dh RC1STA 19Dh — 21Dh T5CLK 29Dh T6RST 31Dh CCPR5H 39Dh —
01Eh T0CON0 09Eh ADPCH 11Eh TX1STA 19Eh — 21Eh CCPTMRS0 29Eh — 31Eh CCP5CON 39Eh —
01Fh T0CON1 09Fh — 11Fh BAUD1CON 19Fh — 21Fh CCPTMRS1 29Fh — 31Fh CCP5CAP 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h
General General General General General General General

Purpose Purpose Purpose Purpose Purpose Purpose Purpose
General Register Register Register Register Register Register Register
Purpose 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes
Register
96 Bytes
0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
0F0h Common RAM 170h Common RAM 1F0h Common RAM 270h Common RAM 2F0h Common RAM 370h Common RAM 3F0h Common RAM
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
07Fh 0FFh 70h – 7Fh) 17Fh 70h – 7Fh) 1FFh 70h – 7Fh) 27Fh 70h – 7Fh) 2FFh 70h – 7Fh) 37Fh 70h – 7Fh) 3FFh 70h – 7Fh)
Legend: = Unimplemented data memory locations, read as ‘0’.

DS40001825F-page 40
TABLE 3-4: PIC16(L)F18877 MEMORY MAP BANK 0-7
PIC16(L)F18857/77
000h 080h 100h 180h 200h 280h 300h 380h
00Ch PORTA 08Ch ADRESL 10Ch ADCNT 18Ch SSP1BUF 20Ch TMR1L 28Ch T2TMR 30Ch CCPR1L 38Ch PWM6DCL
00Dh PORTB 08Dh ADRESH 10Dh ADRPT 18Dh SSP1ADD 20Dh TMR1H 28Dh T2PR 30Dh CCPR1H 38Dh PWM6DCH
00Eh PORTC 08Eh ADPREVL 10Eh ADLTHL 18Eh SSP1MSK 20Eh T1CON 28Eh T2CON 30Eh CCP1CON 38Eh PWM6CON
00Fh PORTD 08Fh ADPREVH 10Fh ADLTHH 18Fh SSP1STAT 20Fh T1GCON 28Fh T2HLT 30Fh CCP1CAP 38Fh —
010h PORTE 090h ADACCL 110h ADUTHL 190h SSP1CON1 210h T1GATE 290h T2CLKCON 310h CCPR2L 390h PWM7DCL
011h TRISA 091h ADACCH 111h ADUTHH 191h SSP1CON2 211h T1CLK 291h T2RST 311h CCPR2H 391h PWM7DCH
012h TRISB 092h — 112h ADSTPTL 192h SSP1CON3 212h TMR3L 292h T4TMR 312h CCP2CON 392h PWM7CON
013h TRISC 093h ADCON0 113h ADSTPTH 193h — 213h TMR3H 293h T4PR 313h CCP2CAP 393h —
014h TRISD 094h ADCON1 114h ADFLTRL 194h — 214h T3CON 294h T4CON 314h CCPR3L 394h —
015h TRISE 095h ADCON2 115h ADFLTRH 195h — 215h T3GCON 295h T4HLT 315h CCPR3H 395h —
016h LATA 096h ADCON3 116h ADERRL 196h SSP2BUF 216h T3GATE 296h T4CLKCON 316h CCP3CON 396h —
017h LATB 097h ADSTAT 117h ADERRH 197h SSP2ADD 217h T3CLK 297h T4RST 317h CCP3CAP 397h —
018h LATC 098h ADCLK 118h — 198h SSP2MSK 218h TMR5L 298h T6TMR 318h CCPR4L 398h —
019h LATD 099h ADACT 119h RC1REG 199h SSP2STAT 219h TMR5H 299h T6PR 319h CCPR4H 399h —
01Ah LATE 09Ah ADREF 11Ah TX1REG 19Ah SSP2CON1 21Ah T5CON 29Ah T6CON 31Ah CCP4CON 39Ah —
01Bh — 09Bh ADCAP 11Bh SP1BRGL 19Bh SSP2CON2 21Bh T5GCON 29Bh T6HLT 31Bh CCP4CAP 39Bh —
01Ch TMR0L 09Ch ADPRE 11Ch SP1BRGH 19Ch SSP2CON3 21Ch T5GATE 29Ch T6CLKCON 31Ch CCPR5L 39Ch —
01Dh TMR0H 09Dh ADACQ 11Dh RC1STA 19Dh — 21Dh T5CLK 29Dh T6RST 31Dh CCPR5H 39Dh —
01Eh T0CON0 09Eh ADPCH 11Eh TX1STA 19Eh — 21Eh CCPTMRS0 29Eh — 31Eh CCP5CON 39Eh —
01Fh T0CON1 09Fh — 11Fh BAUD1CON 19Fh — 21Fh CCPTMRS1 29Fh — 31Fh CCP5CAP 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h
General General General General General General General

Purpose Purpose Purpose Purpose Purpose Purpose Purpose
General Register Register Register Register Register Register Register
Purpose 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes
Register
96 Bytes
0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
0F0h Common RAM 170h Common RAM 1F0h Common RAM 270h Common RAM 2F0h Common RAM 370h Common RAM 3F0h Common RAM
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
07Fh 0FFh 70h – 7Fh) 17Fh 70h – 7Fh) 1FFh 70h – 7Fh) 27Fh 70h – 7Fh) 2FFh 70h – 7Fh) 37Fh 70h – 7Fh) 3FFh 70h – 7Fh)

DS40001825F-page 41
TABLE 3-5: PIC16F18857/77 MEMORY MAP BANK 8-15
PIC16(L)F18857/77
400h 480h 500h 580h 600h 680h 700h 780h
40Ch SCANLADRL 48Ch SMT1TMRL 50Ch SMT2TMRL 58Ch NCO1ACCL 60Ch CWG1CLKCON 68Ch CWG3CLKCON 70Ch PIR0 78Ch —
40Dh SCANLADRH 48Dh SMT1TMRH 50Dh SMT2TMRH 58Dh NCO1ACCH 60Dh CWG1ISM 68Dh CWG3ISM 70Dh PIR1 78Dh —
40Eh SCANHADRL 48Eh SMT1TMRU 50Eh SMT2TMRU 58Eh NCO1ACCU 60Eh CWG1DBR 68Eh CWG3DBR 70Eh PIR2 78Eh —
40Fh SCANHADRH 48Fh SMT1CPRL 50Fh SMT2CPRL 58Fh NCO1INCL 60Fh CWG1DBF 68Fh CWG3DBF 70Fh PIR3 78Fh —
410h SCANCON0 490h SMT1CPRH 510h SMT2CPRH 590h NCO1INCH 610h CWG1CON0 690h CWG3CON0 710h PIR4 790h —
411h SCANTRIG 491h SMT1CPRU 511h SMT2CPRU 591h NCO1INCU 611h CWG1CON1 691h CWG3CON1 711h PIR5 791h —
412h — 492h SMT1CPWL 512h SMT2CPWL 592h NCO1CON 612h CWG1AS0 692h CWG3AS0 712h PIR6 792h —
413h — 493h SMT1CPWH 513h SMT2CPWH 593h NCO1CLK 613h CWG1AS1 693h CWG3AS1 713h PIR7 793h —
414h — 494h SMT1CPWU 514h SMT2CPWU 594h — 614h CWG1STR 694h CWG3STR 714h PIR8 794h —
415h — 495h SMT1PRL 515h SMT2PRL 595h — 615h — 695h — 715h — 795h —
416h CRCDATL 496h SMT1PRH 516h SMT2PRH 596h — 616h CWG2CLKCON 696h — 716h PIE0 796h PMD0
417h CRCDATH 497h SMT1PRU 517h SMT2PRU 597h — 617h CWG2ISM 697h — 717h PIE1 797h PMD1
418h CRCACCL 498h SMT1CON0 518h SMT2CON0 598h — 618h CWG2DBR 698h — 718h PIE2 798h PMD2
419h CRCACCH 499h SMT1CON1 519h SMT2CON1 599h — 619h CWG2DBF 699h — 719h PIE3 799h PMD3
41Ah CRCSHIFTL 49Ah SMT1STAT 51Ah SMT2STAT 59Ah — 61Ah CWG2CON0 69Ah — 71Ah PIE4 79Ah PMD4
41Bh CRCSHIFTH 49Bh SMT1CLK 51Bh SMT2CLK 59Bh — 61Bh CWG2CON1 69Bh — 71Bh PIE5 79Bh PMD5
41Ch CRCXORL 49Ch SMT1SIG 51Ch SMT2SIG 59Ch — 61Ch CWG2AS0 69Ch — 71Ch PIE6 79Ch —
41Dh CRCXORH 49Dh SMT1WIN 51Dh SMT2WIN 59Dh — 61Dh CWG2AS1 69Dh — 71Dh PIE7 79Dh —
41Eh CRCCON0 49Eh — 51Eh — 59Eh — 61Eh CWG2STR 69Eh — 71Eh PIE8 79Eh —
41Fh CRCCON1 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh —
420h 4A0h 520h 5A0h 620h 6A0h 720h 7A0h
General General General General General General General General
Purpose Purpose Purpose Purpose Purpose Purpose Purpose Purpose
Register Register Register Register Register Register Register Register
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

DS40001825F-page 42
TABLE 3-6: PIC16F18857/77 MEMORY MAP BANK 16-23
PIC16(L)F18857/77
800h 880h 900h 980h A00h A80h B00h B80h
(Table 3-2 ) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh
80Ch WDTCON0 88Ch CPUDOZE 90Ch FVRCON 98Ch — A0Ch A8Ch B0Ch B8Ch
80Dh WDTCON1 88Dh OSCCON1 90Dh — 98Dh —
80Eh WDTPSL 88Eh OSCCON2 90Eh DAC1CON0 98Eh —
80Fh WDTPSH 88Fh OSCCON3 90Fh DAC1CON1 98Fh CMOUT
810h WDTTMR 890h OSCSTAT 910h — 990h CM1CON0
811h BORCON 891h OSCEN 911h — 991h CM1CON1
812h VREGCON(1) 892h OSCTUNE 912h — 992h CM1NSEL
813h PCON0 893h OSCFRQ 913h — 993h CM1PSEL
814h —(2) 894h — 914h — 994h CM2CON0
815h — 895h CLKRCON 915h — 995h CM2CON1 Unimplemented Unimplemented Unimplemented Unimplemented
816h — 896h CLKRCLK 916h — 996h CM2NSEL Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
817h — 897h MDCON0 917h — 997h CM2PSEL
818h — 898h MDCON1 918h — 998h —
819h — 899h MDSRC 919h — 999h —
81Ah NVMADRL 89Ah MDCARL 91Ah — 99Ah —
81Bh NVMADRH 89Bh MDCARH 91Bh — 99Bh —
81Ch NVMDATL 89Ch — 91Ch — 99Ch —
81Dh NVMDATH 89Dh — 91Dh — 99Dh —
81Eh NVMCON1 89Eh — 91Eh — 99Eh —
81Fh NVMCON2 89Fh — 91Fh ZCDCON 99Fh — A1Fh A9Fh B1Fh B9Fh
820h General 8A0h General 920h General 9A0h General A20h General AA0h General B20h General BA0h General
80 Bytes 80 Bytes 96Fh 80 Bytes 9EFh 80 Bytes 80 Bytes AEFh 80 Bytes 80 Bytes BEFh 80 Bytes
86Fh 8EFh A6Fh B6Fh
870h Common RAM 8F0h Common RAM 970h Common RAM 9F0h Common RAM A70h Common RAM AF0h Common RAM B70h Common RAM BF0h Common RAM
87Fh 70h – 7Fh 8FFh 70h – 7Fh 97Fh 70h – 7Fh 9FFh 70h – 7Fh A7Fh 70h – 7Fh AFFh 70h – 7Fh B7Fh 70h – 7Fh BFFh 70h – 7Fh
Note 1: PIC16F18857/77 only.

2: Reserved, maintain as ‘0’.
DS40001825F-page 43
TABLE 3-7: PIC16(L)F18857/77 MEMORY MAP BANK 24-31
PIC16(L)F18857/77
C00h C80h D00h D80h E00h E80h F00h F80h
C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh F8Bh
C0Ch C8Ch D0Ch D8Ch E0Ch E8Ch F0Ch F8Ch
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented

Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
C1Fh C9Fh D1Fh D9Fh E1Fh E9Fh F1Fh F9Fh

C20h CA0h D20h DA0h E20h EA0h F20h FA0h
General General General General General General General General
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh
C70h Common RAM CF0h Common RAM D70h Common RAM DF0h Common RAM E70h Common RAM EF0h Common RAM F70h Common RAM FF0h Common RAM
C7Fh 70h – 7Fh CFFh 70h – 7Fh D7Fh 70h – 7Fh DFFh 70h – 7Fh E7Fh 70h – 7Fh EFFh 70h – 7Fh F7Fh 70h – 7Fh FFFh 70h – 7Fh
DS40001825F-page 44
TABLE 3-8: PIC16(L)F18857/77 MEMORY MAP BANK 32-63
PIC16(L)F18857/77
1000h Core Registers 1080h Core Registers 1100h Core Registers 1180h Core Registers 1200h Core Registers 1280h Core Registers 1300h Core Registers 1380h Core Registers
100Bh 108Bh 110Bh 118Dh 120Dh 128Dh 130Dh 138Dh
100Ch Unimplemented 108Ch Unimplemented 110Ch Unimplemented 118Eh Unimplemented 120Eh Unimplemented 128Eh Unimplemented 130Eh Unimplemented 138Eh Unimplemented
101Fh 109Fh 111Fh 119Fh 121Fh 129Fh 131Fh 139Fh
1020h General Purpose 10A0h General Purpose 1120h General Purpose 11A0h General Purpose 1220h General Purpose 12A0h General Purpose 1320h General Purpose 13A0h General Purpose
Register 80 Bytes Register 80 Bytes Register 80 Bytes Register 80 Bytes Register 80 Bytes Register 80 Bytes Register 80 Bytes Register 80 Bytes
1070h Common RAM 10F0h Common RAM 1170h Common RAM 11F0h Common RAM 1270h Common RAM 12F0h Common RAM 1370h Common RAM 13F0h Common RAM
107Fh 70h – 7Fh 10FFh 70h – 7Fh 117Fh 70h – 7Fh 11FFh 70h – 7Fh 127Fh 70h – 7Fh 12FFh 70h – 7Fh 137Fh 70h – 7Fh 13FFh 70h – 7Fh
1400h Core Registers 1480h Core Registers 1500h Core Registers 1580h Core Registers 1600h Core Registers 1680h Core Registers 1700h Core Registers 1780h Core Registers
140Ch Unimplemented 148Ch Unimplemented 150Ch Unimplemented 158Ch Unimplemented 160Ch Unimplemented 168Ch Unimplemented 170Ch Unimplemented 178Ch Unimplemented
141Fh 149Fh 151Fh 159Fh 161Fh 169Fh 171Fh 179Fh
1420h General Purpose 14A0h General Purpose 1520h General Purpose 15A0h General Purpose 1620h General Purpose 16A0h General Purpose 1720h General Purpose 17A0h General Purpose
Register 80 Bytes Register 80 Bytes Register 80 Bytes Register 80 Bytes Register 80 Bytes Register 80 Bytes Register 80 Bytes Register 80 Bytes
1470h Common RAM 14F0h Common RAM 1570h Common RAM 15F0h Common RAM 1670h Common RAM 16F0h Common RAM 1770h Common RAM 17F0h Common RAM
147Fh 70h – 7Fh 14FFh 70h – 7Fh 157Fh 70h – 7Fh 15FFh 70h – 7Fh 167Fh 70h – 7Fh 16FFh 70h – 7Fh 177Fh 70h – 7Fh 17FFh 70h – 7Fh
1800h Core Registers 1880h Core Registers 1900h Core Registers 1980h Core Registers 1A00h Core Registers 1A80h Core Registers 1B00h Core Registers 1B80h Core Registers
180Bh 188Bh 190Bh 198Bh 1A0Bh 1A8Bh 1B0Bh 1B8Bh
180Ch Unimplemented 188Ch Unimplemented 190Ch Unimplemented 198Ch 1A0Ch 1A8Ch 1B0Ch 1B8Ch
Read as ‘0’ Read as ‘0’ Read as ‘0’
181Fh 189Fh 191Fh Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
1820h General Purpose 18A0h General Purpose 1920h General Purpose Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
Register 80 Bytes Register 80 Bytes Register 80 Bytes
186Fh 18EFh 196Fh 19EFh 1A6Fh 1AEFh 1B6Fh 1BEFh
1870h Common RAM 18F0h Common RAM 1970h Common RAM 19F0h Common RAM 1A70h Common RAM 1AF0h Common RAM 1B70h Common RAM 1BF0h Common RAM
187Fh 70h – 7Fh 18FFh 70h – 7Fh 197Fh 70h – 7Fh 19FFh 70h – 7Fh 1A7Fh 70h – 7Fh 1AFFh 70h – 7Fh 1B7Fh 70h – 7Fh 1BFFh 70h – 7Fh
1C00h Core Registers 1C80h Core Registers 1D00h Core Registers 1D80h Core Registers 1E00h Core Registers 1E80h Core Registers 1F00h Core Registers 1F80h Core Registers
1C0Bh 1C8Bh 1D0Bh 1D8Bh 1E0Bh 1E8Bh 1F0Bh 1F8Bh
1C20h 1CA0h 1D20h 1DA0h 1E20h See Table 3-9 for 1EA0h See Table 3-9 for 1F20h See Table 3-11 1FA0h See Table 3-10
Unimplemented Unimplemented Unimplemented Unimplemented and Table 3-12 for
DS40001825F-page 45
register mapping register mapping for register

Read as ‘0’ 1CEF Read as ‘0’ Read as ‘0’ 1DEF Read as ‘0’ register mapping
details details mapping details
1C6Fh h 1D6Fh h 1E6Fh 1EEFh 1F6Fh details 1FEFh
1C70h Common RAM 1CF0h Common RAM 1D70h Common RAM 1DF0h Common RAM 1E70h Common RAM 1EF0h Common RAM 1F70h Common RAM 1FF0h Common RAM
1C7Fh 70h – 7Fh 1CFFh 70h – 7Fh 1D7Fh 70h – 7Fh 1DFFh 70h – 7Fh 1E7Fh 70h – 7Fh 1EFFh 70h – 7Fh 1F7Fh 70h – 7Fh 1FFFh 70h – 7Fh
PIC16(L)F18857/77
TABLE 3-9: PIC16F18857/77 MEMORY TABLE 3-10: PIC16(L)F18857/77 MEMORY
MAP BANK 60-61 MAP, BANK 63
BANK 60 BANK 61
1E80h
Bank 63
1E00h Core Registers
Core Registers
1F80h
(Table 3-2)
1E8Bh
(Table 3-2) Core Registers
1E0Bh
1E0Ch — 1E8Ch — (Table 3-2)
1E0Dh — 1E8Dh — 1F8Bh
1E0Eh — 1E8Eh — 1F8Ch
1E0Fh CLCDATA 1E8Fh PPSLOCK —
1E10h CLC1CON 1E90h INTPPS
1E11h CLC1POL 1E91h T0CKIPPS 1FE3h
1E12h CLC1SEL0 1E92h T1CKIPPS 1FE4h STATUS_SHAD
1E13h CLC1SEL1 1E93h T1GPPS WREG_SHAD
1FE5h
1E14h CLC1SEL2 1E94h T3CKIPPS
CLC1SEL3 1E95h T3GPPS 1FE6h BSR_SHAD
1E15h
1E16h CLC1GLS0 1E96h T5CKIPPS 1FE7h PCLATH_SHAD
1E17h CLC1GLS1 1E97h T5GPPS FSR0L_SHAD
1FE8h
1E18h CLC1GLS2 1E98h
CLC1GLS3 — 1FE9h FSR0H_SHAD
1E19h
1E1Ah CLC2CON 1E9Bh 1FEAh FSR1L_SHAD
1E1Bh CLC2POL 1E9Ch T2AINPPS 1FEBh FSR1H_SHAD
1E1Ch CLC2SEL0 1E9Dh T4AINPPS
CLC2SEL1 1E9Eh T6AINPPS 1FECh —
1E1Dh
1E1Eh CLC2SEL2 1E9Fh — 1FEDh STKPTR
1E1Fh CLC2SEL3 1EA0h — 1FEEh TOSL
1E20h CLC2GLS0 1EA1h CCP1PPS
1E21h CLC2GLS1 1EA2h CCP2PPS 1FEFh TOSH
1E22h CLC2GLS2 1EA3h CCP3PPS 1FF0h
1E23h CLC2GLS3 1EA4h CCP4PPS —
1E24h CLC3CON 1EA5h CCP5PPS
1E25h CLC3POL 1EA6h 1FFFh
1E26h CLC3SEL0 —
Legend: = Unimplemented data memory locations,
1E27h CLC3SEL1 1EA8h
read as ‘0’,
1E28h CLC3SEL2 1EA9h SMT1WINPPS
1E29h CLC3SEL3 1EAAh SMT1SIGPPS
1E2Ah CLC3GLS0 1EABh SMT2WINPPS
1E2Bh CLC3GLS1 1EACh SMT2SIGPPS
1E2Ch CLC3GLS2 1EADh
1E2Dh CLC3GLS3 —
1E2Eh CLC4CON 1EB0h
1E2Fh CLC4POL 1EB1h CWG1PPS
1E30h CLC4SEL0 1EB2h CWG2PPS
1E31h CLC4SEL1 1EB3h CWG3PPS
1E32h CLC4SEL2 1EB4h
CLC4SEL3 —
1E33h
1E34h CLC4GLS0 1EB7h
1E35h CLC4GLS1 1EB8h MDCARLPPS
1E36h CLC4GLS2 1EB9h MDCARHPPS
1E37h CLC4GLS3 1EBAh MDSRCPPS
1E38h 1EBBh CLC1IN0PPS
— 1EBCh CLC1IN1PPS
1E6Fh 1EBDh CLC1IN2PPS
1E70h 1EBEh CLC1IN3PPS
General Purpose 1EBFh
Register 80 Bytes —
1E7Fh
1EC2h
1EC3h ADCACTPPS
1EC4h —
1EC5h SS1CLKPPS
1EC6h SS1CLKPPS
1EC7h SS1CLKPPS
1EC8h SS2CLKPPS
1EC9h SS2CLKPPS
1ECAh SS2CLKPPS
1ECBh RXPPS
1ECCh TXPPS
1ECDh
—
1EEFh
1EF0h General Purpose
Register 80 Bytes
147Fh

PIC16(L)F18857/77
TABLE 3-11: PIC16F18857 MEMORY MAP TABLE 3-12: PIC16F18877 MEMORY MAP
BANK 62 BANK 62
BANK 62 BANK 62 (Cont.) BANK 62 BANK 62 (Cont.)
1F00h 1F4Eh ANSELC 1F00h 1F4Eh ANSELC
Core Registers Core Registers
(Table 3-2) 1F4Fh WPUC (Table 3-2) 1F4Fh WPUC
1F0Bh 1F50h ODCONC 1F0Bh 1F50h ODCONC
1F0Ch 1F0Ch
1F51h SLRCONC 1F51h SLRCONC
— —
1F52h INLVLC 1F52h INLVLC
1F0Fh 1F0Fh
1F10h RA0PPS 1F53h IOCCP 1F10h RA0PPS 1F53h IOCCP
1F11h RA1PPS 1F54h IOCCN 1F11h RA1PPS 1F54h IOCCN
1F12h RA2PPS 1F55h IOCCF 1F12h RA2PPS 1F55h IOCCF
1F13h RA3PPS —(1) 1F13h RA3PPS —(1)
1F56h 1F56h
1F14h RA4PPS 1F14h RA4PPS
RA5PPS 1F57h —(1) RA5PPS 1F57h —(1)
1F15h 1F15h
1F16h RA6PPS 1F58h — 1F16h RA6PPS 1F58h —
RA7PPS 1F59h — RA7PPS 1F59h ANSELD
1F17h 1F17h
1F18h RB0PPS 1F5Ah — 1F18h RB0PPS 1F5Ah WPUD
1F19h RB1PPS 1F5Bh — 1F19h RB1PPS 1F5Bh ODCOND
1F1Ah RB2PPS 1F5Ch — 1F1Ah RB2PPS 1F5Ch SLRCOND
1F1Bh RB3PPS 1F5Dh — 1F1Bh RB3PPS INLVLD
1F5Dh
1F1Ch RB4PPS 1F5Eh — 1F1Ch RB4PPS 1F5Eh —
1F1Dh RB5PPS 1F5Fh — 1F1Dh RB5PPS 1F5Fh —
1F1Eh RB6PPS 1F60h — 1F1Eh RB6PPS 1F60h —
1F1Fh RB7PPS 1F61h — 1F1Fh RB7PPS
1F62h — 1F61h —(1)
1F20h RC0PPS 1F20h RC0PPS
1F21h RC1PPS 1F63h — 1F21h RC1PPS 1F62h —(1)
1F22h RC2PPS 1F64h — 1F22h RC2PPS 1F63h —
RC3PPS 1F65h WPUE RC3PPS 1F64h ANSELE
1F23h 1F23h
1F24h RC4PPS 1F66h — 1F24h RC4PPS 1F65h WPUE
1F25h RC5PPS 1F67h — 1F25h RC5PPS 1F66h ODCONE
1F26h RC6PPS 1F68h INLVLE 1F26h RC6PPS 1F67h SLRCONE
1F27h RC7PPS 1F69h IOCEP 1F27h RC7PPS 1F68h INLVLE
1F28h — 1F69h IOCEN 1F28h RD0PPS IOCEP
1F69h
1F29h — 1F6Ah IOCEF 1F29h RD1PPS
1F69h IOCEN
1F2Ah — 1F6Bh — 1F2Ah RD2PPS
1F6Ah IOCEF
1F2Bh — 1F6Ch — 1F2Bh RD3PPS
1F2Ch — 1F6Dh 1F2Ch RD4PPS 1F6Bh —(1)
—
1F2Dh — 1F6Eh — 1F2Dh RD5PPS 1F6Ch —(1)
1F2Eh — 1F70h General Purpose 1F2Eh RD6PPS 1F6Dh —
1F2Fh — 1F2Fh RD7PPS 1F6Eh —
Register 80 Bytes RE0PPS
1F30h — 1F7Fh 1F30h 1F70h General Purpose
1F31h — 1F31h RE1PPS
Register 80 Bytes
1F32h — 1F32h RE2PPS 1F7Fh
1F33h 1F33h
— —
1F37h 1F37h
1F38h ANSELA 1F38h ANSELA
1F39h WPUA 1F39h WPUA
1F3Ah ODCONA 1F3Ah ODCONA
1F3Bh SLRCONA 1F3Bh SLRCONA
1F3Ch INLVLA 1F3Ch INLVLA
1F3Dh IOCAP 1F3Dh IOCAP
1F3Eh IOCAN 1F3Eh IOCAN
1F3Fh IOCAF 1F3Fh IOCAF
1F40h —(1) 1F40h —(1)
1F41h —(1) 1F41h —(1)
1F42h — 1F42h —
1F43h ANSELB 1F43h ANSELB
1F44h WPUB 1F44h WPUB
1F45h ODCONB 1F45h ODCONB
1F46h SLRCONB 1F46h SLRCONB
1F47h INLVLB 1F47h INLVLB
1F48h IOCBP 1F48h IOCBP
1F49h IOCBN 1F49h IOCBN
1F4Ah IOCBF 1F4Ah IOCBF
1F4Bh —(1) 1F4Bh —(1)
1F4Ch —(1) 1F4Ch —(1)
1F4Dh — 1F4Dh —
Legend: = Unimplemented data memory locations, read as ‘0’. Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: Reserved, maintain as ‘0’. Note 1: Reserved, maintain as ‘0’.

PIC16(L)F18857/77
TABLE 3-13: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-64 (ALL BANKS)
Value on all
Value on:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets
All Banks
000h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a xxxx xxxx xxxx xxxx
physical register)
001h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a xxxx xxxx xxxx xxxx
physical register)
002h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
003h STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
004h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
005h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
006h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
007h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
008h BSR — — BSR5 BSR4 BSR3 BSR2 BSR1 BSR0 --00 0000 --00 0000
009h WREG Working Register 0000 0000 uuuu uuuu
00Ah PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
00Bh INTCON GIE PEIE — — — — — INTEDG 00-- ---1 00-- ---1
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations
unimplemented, read as ‘0’.
Note 1: These Registers can be accessed from any bank

PIC16(L)F18857/77
TABLE 3-14: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63
PIC16(L)F18857
PIC16(L)F18877
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 0
CPU CORE REGISTERS; see Table 3-2 for specifics
00Ch PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx xxxx xxxx
00Dh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx xxxx xxxx
00Eh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx
00Fh PORTD X — Unimplemented — —
— X RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx xxxx xxxx
010h PORTE X — — — — — RE3 — — — — —
— X — — — — RE3 RE2 RE1 RE0 ---- xxxx ---- xxxx
011h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
012h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
013h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
014h TRISD X — Unimplemented ---- ---- ---- ----
— X TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
015h TRISE X — Unimplemented — —
— X — — — — — TRISE2 TRISE1 TRISE0 ---- -111 ---- -111
016h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx uuuu uuuu
017h LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx uuuu uuuu
018h LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu
019h LATD X — Unimplemented — —
— X LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx uuuu uuuu
DS40001825F-page 49
01Ah LATE X - Unimplemented — —
— X — — — — — LATE2 LATE1 LATE0 ---- -xxx ---- -uuu
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18857/77 devices only.
2: Unimplemented, read as ‘1’.
TABLE 3-14: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (CONTINUED)
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 0 (Continued)
01Bh — — Unimplemented — —
01Ch TMR0L Holding Register for the Least Significant Byte of the 16-bit TMR0 Register 0000 0000 0000 0000
01Dh TMR0H Holding Register for the Most Significant Byte of the 16-bit TMR0 Register 1111 1111 1111 1111
01Eh T0CON0 T0EN — T0OUT T016BIT T0OUTPS<3:0> 0-00 0000 0-00 0000
01Fh T0CON1 T0CS<2:0> T0ASYNC T0CKPS<3:0> 0000 0000 0000 0000
DS40001825F-page 50
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 1
08Ch ADRESL ADRESL<7:0> 0000 0000 0000 0000
08Dh ADRESH ADRESH<7:0> 0000 0000 0000 0000
08Eh ADPREVL ADPREVL<7:0> 0000 0000 0000 0000
08Fh ADPREVH ADPREVH<7:0> 0000 0000 0000 0000
090h ADACCL ADACCL<7:0> xxxx xxxx uuuu uuuu
091h ADACCH ADACCH<7:0> xxxx xxxx uuuu uuuu
092h — — Unimplemented — —
093h ADCON0 ADON ADCONT — ADCS — ADFRM0 — ADGO 00-0 -0-0 00-0 -0-0
094h ADCON1 ADPPOL ADIPEN ADGPOL — — — — ADDSEN 000- ---0 000- ---0
095h ADCON2 ADPSIS ADCRS<2:0> ADACLR ADMD<2:0> 0000 0000 0000 0000
096h ADCON3 — ADCALC<2:0> ADSOI ADTMD<2:0> -000 0000 -000 0000
097h ADSTAT ADAOV ADUTHR ADLTHR ADMATH — ADSTAT<2:0> 0000 -000 0000 -000
098h ADCLK — — ADCCS<5:0> --00 0000 --00 0000
099h ADACT — — — ADACT<4:0> ---0 0000 ---0 0000
09Ah ADREF — — — ADNREF — — ADPREF<1:0> ---0 --00 ---0 --00
09Bh ADCAP — — — ADCAP<4:0> ---0 0000 ---0 0000
09Ch ADPRE ADPRE<7:0> 0000 0000 0000 0000
09Dh ADACQ ADACQ<7:0> 0000 0000 0000 0000
09Eh ADPCH — — ADPCH<5:0> --00 0000 --00 0000

DS40001825F-page 51
09Fh — — Unimplemented — —
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 2
10Ch ADCNT ADCNT<7:0> xxxx xxxx uuuu uuuu

10Dh ADRPT ADRPT<7:0> 0000 0000 0000 0000
10Eh ADLTHL ADLTH<7:0> 0000 0000 0000 0000
10Fh ADLTHH ADLTH<15:8> 0000 0000 0000 0000
110h ADUTHL ADUTH<7:0> 0000 0000 0000 0000
111h ADUTHH ADUTH<15:8> 0000 0000 0000 0000
112h ADSTPTL ADSTPT<7:0> 0000 0000 0000 0000
113h ADSTPTH ADSTPT<15:8> 0000 0000 0000 0000
114h ADFLTRL ADFLTR<7:0> xxxx xxxx uuuu uuuu
115h ADFLTRH ADFLTR<15:8> xxxx xxxx uuuu uuuu
116h ADERRL ADERR<7:0> 0000 0000 0000 0000
117h ADERRH ADERR<15:8> 0000 0000 0000 0000
119h RC1REG RC1REG<7:0> 0000 0000 0000 0000

11Ah TX1REG TX1REG<7:0> 0000 0000 0000 0000
11Bh SP1BRGL SP1BRGL<7:0> 0000 0000 0000 0000
11Ch SP1BRGH SP1BRGH<7:0> 0000 0000 0000 0000
11Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
11Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
DS40001825F-page 52
11Fh BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 3
18Ch SSP1BUF SSPBUF<7:0> xxxx xxxx xxxx xxxx
18Dh SSP1ADD SSPADD<7:0> 0000 0000 0000 0000
18Eh SSP1MSK SSPMSK<7:0> 1111 1111 1111 1111
18Fh SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
190h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
191h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
192h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
196h SSP2BUF SSPBUF<7:0> xxxx xxxx xxxx xxxx
197h SSP2ADD SSPADD<7:0> 0000 0000 0000 0000
198h SSP2MSK SSPMSK<7:0> 1111 1111 1111 1111
199h SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
19Ah SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
19Bh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
19Ch SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
19Dh — — Unimplemented — —
19Eh — — Unimplemented — —
DS40001825F-page 53
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 4
20Ch TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 0000 0000 uuuu uuuu
20Dh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 0000 0000 uuuu uuuu
20Eh T1CON — — CKPS<1:0> — SYNC RD16 ON --00 -000 --uu -uuu
20Fh T1GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 0000 0x-- uuuu ux--
210h T1GATE — — — GSS<4:0> ---0 0000 ---u uuuu
211h T1CLK — — — — CS<3:0> ---- 0000 ---- uuuu
212h TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register 0000 0000 uuuu uuuu
213h TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register 0000 0000 uuuu uuuu
214h T3CON — — CKPS<1:0> — SYNC RD16 ON --00 -000 --uu -uuu
215h T3GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 0000 0x-- uuuu ux--
216h T3GATE — — — GSS<4:0> ---0 0000 ---u uuuu
217h T3CLK — — — — CS<3:0> ---- 0000 ---- uuuu
218h TMR5L Holding Register for the Least Significant Byte of the 16-bit TMR5 Register 0000 0000 uuuu uuuu
219h TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register 0000 0000 uuuu uuuu
21Ah T5CON — — CKPS<1:0> — SYNC RD16 ON --00 -000 --uu -uuu
21Bh T5GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 0000 0x-- uuuu ux--
21Ch T5GATE — — — GSS<4:0> ---0 0000 ---u uuuu
21Dh T5CLK — — — — CS<3:0> ---- 0000 ---- uuuu
21Eh CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 0101 0101 0101 0101
DS40001825F-page 54
21Fh CCPTMRS1 — — P7TSEL<1:0> P6TSEL<1:0> C5TSEL<1:0> --01 0101 --01 0101
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 5
28Ch T2TMR Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000
28Dh T2PR TMR2 Period Register 1111 1111 1111 1111
28Eh T2CON ON CKPS<2:0> OUTPS<3:0> 0000 0000 0000 0000
28Fh T2HLT PSYNC CKPOL CKSYNC — MODE 000- 0000 000- 0000
290h T2CLKCON — — — — — CS<2:0> ---- -000 ---- -000
291h T2RST — — — RSEL<4:0> ---0 0000 ---0 0000
292h T4TMR Holding Register for the 8-bit TMR4 Register 0000 0000 0000 0000
293h T4PR TMR4 Period Register 1111 1111 1111 1111
294h T4CON ON CKPS<2:0> OUTPS<3:0> 0000 0000 0000 0000
295h T4HLT PSYNC CKPOL CKSYNC — MODE<3:0> 000- 0000 000- 0000
296h T4CLKCON — — — — — CS<2:0> ---- -000 ---- -000
297h T4RST — — — RSEL<4:0> ---0 0000 ---0 0000
298h T6TMR Holding Register for the 8-bit TMR6 Register 0000 0000 0000 0000
299h T6PR TMR6 Period Register 1111 1111 1111 1111
29Ah T6CON ON CKPS<2:0> OUTPS<3:0> 0000 0000 0000 0000
29Bh T6HLT PSYNC CKPOL CKSYNC — MODE<3:0> 000- 0000 000- 0000
29Ch T6CLKCON — — — — — CS<2:0> ---- -000 ---- -000
29Dh T6RST — — — RSEL<4:0> ---0 0000 ---0 0000
DS40001825F-page 55
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 6
30Ch CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx xxxx xxxx
30Dh CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx xxxx xxxx
30Eh CCP1CON EN — OUT FMT MODE<3:0> 0-00 0000 0-00 0000
30Fh CCP1CAP — — — — — CTS<2:0> ---- 0000 ---- 0000
310h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx xxxx xxxx
311h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx xxxx xxxx
312h CCP2CON EN — OUT FMT MODE<3:0> 0-00 0000 0-00 0000
313h CCP2CAP — — — — — CTS<2:0> ---- 0000 ---- 0000
316h CCP3CON EN — OUT FMT MODE<3:0> 0-00 0000 0-00 0000
317h CCP3CAP — — — — CTS<3:0> ---- 0000 ---- 0000
31Ah CCP4CON EN — OUT FMT MODE<3:0> 0-00 0000 0-00 0000
31Bh CCP4CAP — — — — CTS<3:0> ---- 0000 ---- 0000
31Ch CCPR5L Capture/Compare/PWM Register 5 (LSB) xxxx xxxx xxxx xxxx
31Dh CCPR5H Capture/Compare/PWM Register 5 (MSB) xxxx xxxx xxxx xxxx
31Eh CCP5CON EN — OUT FMT MODE<3:0> 0-00 0000 0-00 0000

DS40001825F-page 56
31Fh CCP5CAP — — — — CTS<3:0> ---- 0000 ---- 0000
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 7
38Ch PWM6DCL DC<1:0> — — — — — — xx-- ---- uu-- ----
38Dh PWM6DCH DC<9:2> xxxx xxxx uuuu uuuu
38Eh PWM6CON EN OE OUT POL — — — — 0000 ---- 0-00 ----
390h PWM7DCL DC<1:0> — — — — — — xx-- ---- uu-- ----
391h PWM7DCH DC<9:2> xxxx xxxx uuuu uuuu
392h PWM7CON EN OE OUT POL — — — — 0000 ---- 0-00 ----
39Ah — — Unimplemented — —
39Ch — — Unimplemented — —
DS40001825F-page 57
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 8
40Ch SCANLADRL LADR<7:0> 0000 0000 0000 0000
40Dh SCANLADRH LADR<15:8> 0000 0000 0000 0000
40Eh SCANHADRL HADR<7:0> 1111 1111 1111 1111
40Fh SCANHADRH HADR<15:8> 1111 1111 1111 1111
410h SCANCON0 EN SCANGO BUSY INVALID INTM — MODE<1:0> 0000 0-00 0000 0-00
411h SCANTRIG — — — — TSEL<3:0> ---- 0000 ---- 0000
416h CRCDATL DATA<7:0> xxxx xxxx xxxx xxxx
417h CRCDATH DATA<15:8> xxxx xxxx xxxx xxxx
418h CRCACCL ACC<7:0> 0000 0000 0000 0000
419h CRCACCH ACC<15:8> 0000 0000 0000 0000
41Ah CRCSHIFTL SHIFT<7:0> 0000 0000 0000 0000
41Bh CRCSHIFTH SHIFT<15:8> 0000 0000 0000 0000
41Ch CRCXORL X<7:1> — xxxx xxx- xxxx xxx-
41Dh CRCXORH X<15:8> xxxx xxxx xxxx xxxx
41Eh CRCCON0 EN CRCGO BUSY ACCM — — SHIFTM FULL 0000 --00 0000 --00
DS40001825F-page 58
41Fh CRCCON1 DLEN<3:0> PLEN<3:0> 0000 0000 0000 0000
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 9
48Ch SMT1TMRL TMR<7:0> 0000 0000 0000 0000
48Dh SMT1TMRH TMR<15:8> 0000 0000 0000 0000
48Eh SMT1TMRU TMR<23:16> 0000 0000 0000 0000
48Fh SMT1CPRL CPR<7:0> xxxx xxxx uuuu uuuu
490h SMT1CPRH CPR<15:8> xxxx xxxx uuuu uuuu
491h SMT1CPRU CPR<23:16> xxxx xxxx uuuu uuuu
492h SMT1CPWL CPW<7:0> xxxx xxxx uuuu uuuu
493h SMT1CPWH CPW<15:8> xxxx xxxx uuuu uuuu
494h SMT1CPWU CPW<23:16> xxxx xxxx uuuu uuuu
495h SMT1PRL PR<7:0> 1111 1111 1111 1111
496h SMT1PRH PR<15:8> 1111 1111 1111 1111
497h SMT1PRU PR<23:16> 1111 1111 1111 1111
498h SMT1CON0 EN — STP WPOL SPOL CPOL SMT1PS<1:0> 0-00 0000 0-00 0000
499h SMT1CON1 SMT1GO REPEAT — — MODE<3:0> 00-- 0000 00-- 0000
49Ah SMT1STAT CPRUP CPWUP RST — — TS WS AS 000- -000 000- -000
49Bh SMT1CLK — — — — — CSEL<2:0> ---- -000 ---- -000
49Ch SMT1SIG — — — SSEL<4:0> ---0 0000 ---0 0000
49Dh SMT1WIN — — — WSEL<4:0> ---0 0000 ---0 0000
DS40001825F-page 59
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 10
50Ch SMT2TMRL TMR<7:0> 0000 0000 0000 0000
50Dh SMT2TMRH TMR<15:8> 0000 0000 0000 0000
50Eh SMT2TMRU TMR<23:16> 0000 0000 0000 0000
50Fh SMT2CPRL CPR<7:0> xxxx xxxx uuuu uuuu
510h SMT2CPRH CPR<15:8> xxxx xxxx uuuu uuuu
511h SMT2CPRU CPR<23:16> xxxx xxxx uuuu uuuu
512h SMT2CPWL CPW<7:0> xxxx xxxx uuuu uuuu
513h SMT2CPWH CPW<15:8> xxxx xxxx uuuu uuuu
514h SMT2CPWU CPW<23:16> xxxx xxxx uuuu uuuu
515h SMT2PRL PR<7:0> 1111 1111 1111 1111
516h SMT2PRH PR<15:8> 1111 1111 1111 1111
517h SMT2PRU PR<23:16> 1111 1111 1111 1111
518h SMT2CON0 EN — STP WPOL SPOL CPOL SMT2PS<1:0> 0-00 0000 0-00 0000
519h SMT2CON1 SMT2GO REPEAT — — MODE<3:0> 00-- 0000 00-- 0000
51Ah SMT2STAT CPRUP CPWUP RST — — TS WS AS 000- -000 000- -000
51Bh SMT2CLK — — — — — CSEL<2:0> ---- -000 ---- -000
51Ch SMT2SIG — — — SSEL<4:0> ---0 0000 ---0 0000
51Dh SMT2WIN — — — WSEL<4:0> ---0 0000 ---0 0000
DS40001825F-page 60
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 11
58Ch NCO1ACCL NCO1ACC<7:0> 0000 0000 0000 0000
58Dh NCO1ACCH NCO1ACC<15:8> 0000 0000 0000 0000
58Eh NCO1ACCU — — — — NCO1ACC<19:16> ---- 0000 ---- 0000
58Fh NCO1INCL NCO1INC<7:0> 0000 0001 0000 0001
590h NCO1INCH NCO1INC<15:8> 0000 0000 0000 0000
591h NCO1INCU — — — — NCO1INC<19:16> ---- 0000 ---- 0000
592h NCO1CON N1EN — N1OUT N1POL — — — N1PFM 0-00 ---0 0-00 ---0
593h NCO1CLK N1PWS<2:0> — — N1CKS<2:0> 000- -000 000- -000
DS40001825F-page 61
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Banks 12
60Ch CWG1CLKCON — — — — — — — CS ---- ---0 ---- ---0
60Dh CWG1ISM — — — — IS<3:0> ---- 0000 ---- 0000
60Eh CWG1DBR — — DBR<5:0> --00 0000 --00 0000
60Fh CWG1DBF — — DBF<5:0> --00 0000 --00 0000
610h CWG1CON0 EN LD — — — MODE<2:0> 00-- -000 00-- -000
611h CWG1CON1 — — IN — POLD POLC POLB POLA --x- 0000 --u- 0000
612h CWG1AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 0001 01-- 0001 01--
613h CWG1AS1 — AS6E AS5E AS4E AS3E AS2E AS1E AS0E -000 0000 -000 0000
614h CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000
616h CWG2CLKCON — — — — — — — CS ---- ---0 ---- ---0
617h CWG2ISM — — — — IS<3:0> ---- 0000 ---- 0000
618h CWG2DBR — — DBR<5:0> --00 0000 --00 0000
619h CWG2DBF — — DBF<5:0> --00 0000 --00 0000
61Ah CWG2CON0 EN LD — — — MODE<2:0> 00-- -000 00-- -000
61Bh CWG2CON1 — — IN — POLD POLC POLB POLA --x- 0000 --u- 0000
61Ch CWG2AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 0001 01-- 0001 01--
61Dh CWG2AS1 — AS6E AS5E AS4E AS3E AS2E AS1E AS0E -000 0000 -000 0000
61Eh CWG2STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000
DS40001825F-page 62
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 13
68Ch CWG3CLKCON — — — — — — — CS ---- ---0 ---- ---0
68Dh CWG3ISM — — — — IS<3:0> ---- 0000 ---- 0000
68Eh CWG3DBR — — DBR<5:0> --00 0000 --00 0000
68Fh CWG3DBF — — DBF<5:0> --00 0000 --00 0000
690h CWG3CON0 EN LD — — — MODE<2:0> 00-- -000 00-- -000
691h CWG3CON1 — — IN — POLD POLC POLB POLA --x- 0000 --u- 0000
692h CWG3AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 0001 01-- 0001 01--
693h CWG3AS1 — AS6E AS5E AS4E AS3E AS2E AS1E AS0E -000 0000 -000 0000
694h CWG3STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000
DS40001825F-page 63
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 14
70Ch PIR0 — — TMR0IF IOCIF — — — INTF --00 ---0 --00 ---0
70Dh PIR1 OSFIF CSWIF — — — — ADTIF ADIF 00-- --00 00-- --00
70Eh PIR2 — ZCDIF — — — — C2IF C1IF -0-- --00 -0-- --00
70Fh PIR3 — — RCIF TXIF BCL2IF SSP2IF BCL1IF SSP1IF --00 0000 --00 0000
710h PIR4 — — TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF --00 0000 --00 0000
711h PIR5 CLC4IF CLC3IF CLC2IF CLC1IF — TMR5GIF TMR3GIF TMR1GIF 0000 -000 0000 -000
712h PIR6 — — — CCP5IF CCP4IF CCP3IF CCP2IF CCP1IF ---0 0000 ---0 0000
713h PIR7 SCANIF CRCIF NVMIF NCO1IF — CWG3IF CWG2IF CWG1IF 0000 -000 0000 -000
714h PIR8 — — SMT2PWAIF SMT2PRAIF SMT2IF SMT1PWAIF SMT1PRAIF SMT1IF --00 0000 --00 0000
716h PIE0 — — TMR0IE IOCIE — — — INTE --00 ---0 --00 ---0
717h PIE1 OSFIE CSWIE — — — — ADTIE ADIE 00-- --00 00-- --00
718h PIE2 — ZCDIE — — — — C2IE C1IE -0-- --00 -0-- --00
719h PIE3 — — RCIE TXIE BCL2IE SSP2IE BCL1IE SSP1IE --00 0000 --00 0000
71Ah PIE4 — — TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE --00 0000 --00 0000
71Bh PIE5 CLC4IE CLC3IE CLC2IE CLC1IE — TMR5GIE TMR3GIE TMR1GIE 0000 -000 0000 -000
71Ch PIE6 — — — CCP5IE CCP4IE CCP3IE CCP2IE CCP1IE ---0 0000 ---0 0000
71Dh PIE7 SCANIE CRCIE NVMIE NCO1IE — CWG3IE CWG2IE CWG1IE 0000 -000 0000 -000
71Eh PIE8 — — SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE --00 0000 --00 0000
DS40001825F-page 64
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Banks 15
796h PMD0 SYSCMD FVRMD — CRCMD SCANMD NVMMD CLKRMD IOCMD 00-0 0000 00-0 0000
797h PMD1 NCOMD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD 0000 0000 0000 0000
798h PMD2 — DACMD ADCMD — — CMP2MD CMP1MD ZCDMD -00- -000 -00- -000
799h PMD3 — PWM7MD PWM6MD CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD -000 0000 -000 0000
79Ah PMD4 — UART1MD MSSP2MD MSSP1MD — CWG3MD CWG2MD CWG1MD -000 -000 -000 -000
79Bh PMD5 SMT2MD SMT1MD — CLC4MD CLC3MD CLC2MD CLC1MD DSMMD 00-0 0000 00-0 0000
DS40001825F-page 65
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Banks 16
80Ch WDTCON0 — — PS<4:0> SEN --qq qqq0 --qq qqq0
80Dh WDTCON1 — WDTCS<2:0> — WINDOW<2:0> -qqq -qqq -qqq -qqq
80Eh WDTPSL PSCNT<7:0> 0000 0000 0000 0000
80Fh WDTPSH PSCNT<7:0> 0000 0000 0000 0000
810h WDTTMR — WDTTMR<3:0> STATE PSCNT<17:16> -000 0000 -000 0000
811h BORCON SBOREN — — — — — — BORRDY 1--- ---q u--- ---u
812h VREGCON(1) — — — — — — VREGPM Reserved ---- --01 ---- --01
813h PCON0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 0011 11qq qqqq qquu
814h —(3) — Reserved, maintain as ‘0’ rrrr rrrr rrrr rrrr
81Ah NVMADRL NVMADR<7:0> 0000 0000 0000 0000
81Bh NVMADRH —(2) NVMADR<14:8> 1000 0000 1000 0000
81Ch NVMDATL NVMDAT<7:0> 0000 0000 0000 0000
81Dh NVMDATH — — NVMDAT<13:8> --00 0000 --00 0000
81Eh NVMCON1 — NVMREGS LWLO FREE WRERR WREN WR RD -000 x000 -000 q000
DS40001825F-page 66
81Fh NVMCON2 NVMCON2<7:0> 0000 0000 0000 0000
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Banks 17
88Ch CPUDOZE IDLEN DOZEN ROI DOE — DOZE2 DOZE1 DOZE0 0000 -000 0000 -000
88Dh OSCCON1 — NOSC<2:0> NDIV<3:0> -qqq 0000 -qqq 0000
88Eh OSCCON2 — COSC<2:0> CDIV<3:0> -qqq qqqq -qqq qqqq
88Fh OSCCON3 CSWHOLD SOSCPWR — ORDY NOSCR — — — 00-0 0--- 00-0 0---
890h OSCSTAT EXTOR HFOR MFOR LFOR SOR ADOR — PLLR q0-0 qq-0 q0-0 qq-0
891h OSCEN EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN — — 00-0 00-- 00-0 00--
892h OSCTUNE — — HFTUN<5:0> --10 0000 --10 0000
893h OSCFRQ — — — — — HFFRQ<2:0> ---- -qqq ---- -qqq
895h CLKRCON CLKREN — — CLKRDC<1:0> CLKRDIV<2:0> 0--1 0000 0--1 0000
896h CLKRCLK — — — — CLKRCLK<3:0> ---- 0000 ---- 0000
897h MDCON0 MDEN — MDOUT MDOPOL — — — MDBIT 0-00 ---0 0-00 ---0
898h MDCON1 — — MDCHPOL MDCHSYNC — — MDCLPOL MDCLSYNC --00 --00 --00 --00
899h MDSRC — — — MDMS<4:0> ---0 0000 ---0 0000
89Ah MDCARL — — — — MDCLS<3:0> ---- 0000 ---- 0000
89Bh MDCARH — — — — MDCHS<3:0> ---- 0000 ---- 0000
DS40001825F-page 67
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 18
90Ch FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
90Eh DAC1CON0 DAC1EN — DAC1OE — DAC1PSS<1:0> — DAC1NSS 0-0- 00-- 0-0- 00--
90Fh DAC1CON1 — — — DAC1R<4:0> ---0 0000 ---0 0000
DS40001825F-page 68
91Fh ZCDCON EN — OUT POL — — INTP INTN 0-x0 --00 0-x0 --00
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 19
98Fh CMOUT — — — — — — MC2OUT MC1OUT ---- --xx ---- --xx
990h CM1CON0 ON OUT — POL — — HYS SYNC 0x-0 -100 0x-0 -100
991h CM1CON1 — — — — — — INTP INTN ---- --00 ---- --00
992h CM1NSEL — — — — — NCH<2:0> ---- -000 ---- -000
993h CM1PSEL — — — — — PCH<2:0> ---- -000 ---- -000
994h CM2CON0 ON OUT — POL — — HYS SYNC 0x-0 -100 0x-0 -100
995h CM2CON1 — — — — — — INTP INTN ---- --00 ---- --00
996h CM2NSEL — — — — — NCH<2:0> ---- -000 ---- -000
997h CM2PSEL — — — — — PCH<2:0> ---- -000 ---- -000
DS40001825F-page 69
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 20-59
x0Ch/
x8Ch
— — — Unimplemented — —
x1Fh/
x9Fh
DS40001825F-page 70
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 60
1E0Ch — — Unimplemented — —
1E0Dh — — Unimplemented — —
1E0Eh — — Unimplemented — —
1E0Fh CLCDATA — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT ---- 0000 ---- 0000
1E10h CLC1CON LC1EN — LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 0-x0 0000 0-x0 0000
1E11h CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu
1E12h CLC1SEL0 — — LC1D1S<5:0> --xx xxxx --uu uuuu
1E16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu
1E1Ah CLC2CON LC2EN — LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 0-x0 0000 0-x0 0000
1E1Bh CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- uuuu
1E1Ch CLC2SEL0 — — LC2D1S<5:0> --xx xxxx --uu uuuu
1E1Dh CLC2SEL1 — — LC2D2S<5:0> --xx xxxx --uu uuuu
1E1Eh CLC2SEL2 — — LC2D3S<5:0> --xx xxxx --uu uuuu

DS40001825F-page 71
1E1Fh CLC2SEL3 — — LC2D4S<5:0> --xx xxxx --uu uuuu
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 60 (Continued)
1E24h CLC3CON LC3EN — LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 0-x0 0000 0-x0 0000
1E25h CLC3POL LC3POL — — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL 0--- xxxx 0--- uuuu
1E2Ah CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu
1E2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu
1E2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu
1E2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu
1E2Eh CLC4CON LC4EN — LC4OUT LC4INTP LC4INTN LC4MODE<2:0> 0-x0 0000 0-x0 0000
1E2Fh CLC4POL LC4POL — — — LC4G4POL LC4G3POL LC4G2POL LC4G1POL 0--- xxxx 0--- uuuu
DS40001825F-page 72
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 60 (Continued)
E38h to — — Unimplemented — —
1E6Fh
DS40001825F-page 73
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 61
1E8Ch — — Unimplemented — —
1E8Dh — — Unimplemented — —
1E8Eh — — Unimplemented — —
1E8Fh PPSLOCK — — — — — — — PPSLOCKED ---- ---0 ---- ---0
1E90h INTPPS — — — — INTPPS<3:0> ---- 1000 ---- uuuu
1E91h T0CKIPPS — — — — T0CKIPPS<3:0> ---- 0100 ---- uuuu
1E92h T1CKIPPS — — — T1CKIPPS<4:0> ---1 0000 ---u uuuu
1E93h T1GPPS — — — T1GPPS<4:0> ---0 1101 ---u uuuu
1E98h — — Unimplemented — —
1E99h — — Unimplemented — —
1E9Ah — — Unimplemented — —
1E9Bh — — Unimplemented — —
1E9Ch T2AINPPS — — — T2AINPPS<4:0> ---1 0011 ---u uuuu
1E9Dh T4AINPPS — — — T4AINPPS<4:0> ---1 0101 ---u uuuu
1E9Eh T6AINPPS — — — T6AINPPS<4:0> ---0 1111 ---u uuuu

DS40001825F-page 74
1E9Fh — — Unimplemented — —
1EA0h — — Unimplemented — —
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 61 (Continued)
1EA1h CCP1PPS — — — CCP1PPS<4:0> ---1 0010 ---u uuuu
1EA5h CCP5PPS — — CCP5PPS<5:0> --00 0100 --uu uuuu
1EA9h SMT1WINPPS — — — SMT1WINPPS<4:0> ---1 0000 ---u uuuu
1EAAh SMT1SIGPPS — — — SMT1SIGPPS<4:0> ---1 0001 ---u uuuu
1EABh SMT2WINPPS — — — SMT2WINPPS<4:0> ---1 0000 ---u uuuu
1EACh SMT2SIGPPS — — — SMT2SIGPPS<4:0> ---1 0001 ---u uuuu
1EADh — — Unimplemented — —
1EAEh — — Unimplemented — —
1EAFh — — Unimplemented — —
1EB0h — — Unimplemented — —
1EB1h CWG1PPS — — — CWG1PPS<4:0> ---0 1000 ---u uuuu
DS40001825F-page 75
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 61 (Continued)
1EB8h MDCARLPPS — — — MDCARLPPS<4:0> ---0 0011 ---u uuuu
1EB9h MDCARHPPS — — — MDCARHPPS<4:0> ---0 0100 ---u uuuu
1EBAh MDSRCPPS — — — MDSRCPPS<4:0> ---0 0101 ---u uuuu
1EBBh CLCIN0PPS — — — CLCIN0PPS<4:0> ---0 0000 ---u uuuu
1EBCh CLCIN1PPS — — — CLCIN1PPS<4:0> ---0 0001 ---u uuuu
1EBDh CLCIN2PPS — — — CLCIN2PPS<4:0> ---0 1110 ---u uuuu
1EBEh CLCIN3PPS — — — CLCIN3PPS<4:0> ---0 1111 ---u uuuu
1EBFh — — Unimplemented — —
1EC0h — — Unimplemented — —
1EC3h ADCACTPPS — — — ADCACTPPS<4:0> ---0 1100 ---u uuuu
1EC5h SSP1CLKPPS — — — SSP1CLKPPS<4:0> ---1 0011 ---u uuuu
1EC6h SSP1DATPPS — — — SSP1DATPPS<4:0> ---1 0100 ---u uuuu
1EC7h SSP1SSPPS — — — SSP1SSPPS<4:0> ---0 0101 ---u uuuu
1EC8h SSP2CLKPPS — — — SSP2CLKPPS<4:0> ---0 1001 ---u uuuu
1EC9h SSP2DATPPS — — — SSP2DATPPS<4:0> ---0 0010 ---u uuuu
1ECAh SSP2SSPPS — — — SSP2SSPPS<4:0> ---0 1000 ---u uuuu
1ECBh RXPPS — — — RXPPS<4:0> ---1 0111 ---u uuuu
1ECCh TXPPS — — — TXPPS<4:0> ---1 0110 ---u uuuu

DS40001825F-page 76
1ECDh to — — Unimplemented — —
1EEFh
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 62
1F0Ch — — Unimplemented — —
—
1F0Fh
1F10h RA0PPS — — RA0PPS<5:0> --00 0000 --uu uuuu
1F18h RB0PPS — — RB0PPS<5:0> --00 0000 --uu uuuu
1F19h RB1PPS — — RB1PPS<5:0> --00 0000 --uu uuuu
1F1Ah RB2PPS — — RB2PPS<5:0> --00 0000 --uu uuuu
1F1Bh RB3PPS — — RB3PPS<5:0> --00 0000 --uu uuuu
1F1Ch RB4PPS — — RB4PPS<5:0> --00 0000 --uu uuuu
1F1Dh RB5PPS — — RB5PPS<5:0> --00 0000 --uu uuuu
1F1Eh RB6PPS — — RB6PPS<5:0> --00 0000 --uu uuuu
1F1Fh RB7PPS — — RB7PPS<5:0> --00 0000 --uu uuuu
1F20h RC0PPS — — RC0PPS<5:0> --00 0000 --uu uuuu

DS40001825F-page 77
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 62 (Continued)
— X — — RD0PPS<5:0> --00 0000 --uu uuuu

1F28h RD0PPS
X — Unimplemented — —
— X — — RD1PPS<5:0> --00 0000 --uu uuuu

1F29h RD1PPS
— X — — RD2PPS<5:0> --00 0000 --uu uuuu

1F2Ah RD2PPS
— X — — RD3PPS<5:0> --00 0000 --uu uuuu

1F2Bh RD3PPS
— X — — RD4PPS<5:0> --00 0000 --uu uuuu

1F2Ch RD4PPS
— X — — RD5PPS<5:0> --00 0000 --uu uuuu

1F2Dh RD5PPS
— X — — RD6PPS<5:0> --00 0000 --uu uuuu

1F2Eh RD6PPS
— X — — RD7PPS<5:0> --00 0000 --uu uuuu

1F2Fh RD7PPS
— X — — RE0PPS<5:0> --00 0000 --uu uuuu

1F30h RE0PPS
DS40001825F-page 78
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 62 (Continued)
— X — — RE1PPS<5:0> --00 0000 --uu uuuu
1F31h RE1PPS
— X — — RE2PPS<5:0> --00 0000 --uu uuuu

1F32h RE2PPS
1F33h — — Unimplemented — —
—
1F37h
1F38h ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111
1F39h WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 0000 0000 0000 0000
1F3Ah ODCONA ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 0000 0000 0000
1F3Bh SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 1111 1111 1111 1111
1F3Ch INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 1111 1111 1111 1111
1F3Dh IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 0000 0000 0000 0000
1F3Eh IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 0000 0000 0000 0000
1F3Fh IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 0000 0000 0000 0000
1F40h — Reserved, maintain as ‘0’ rrrr rrrr rrrr rrrr
1F43h ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111
1F44h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 0000 0000 0000 0000
1F45h ODCONB ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 0000 0000 0000
1F46h SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 1111 1111 1111 1111
DS40001825F-page 79
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 62 (Continued)
1F47h INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 1111 1111 1111 1111
1F48h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000
1F49h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000
1F4Ah IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000
1F4Bh — Reserved, maintain as ‘0’ rrrr rrrr rrrr rrrr
1F4Ch — Reserved, maintain as ‘0’ rrrr rrrr rrrr rrrr
1F4Dh — — Unimplemented — —
1F4Eh ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 1111 1111 1111 1111
1F4Fh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 0000 0000 0000 0000
1F50h ODCONC ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0000 0000 0000 0000
1F51h SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 1111 1111 1111 1111
1F52h INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111
1F53h IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0000 0000 0000
1F54h IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000
1F55h IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000
— X ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111
1F59h ANSELD
— X WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 0000 0000 0000 0000
1F5Ah WPUD
DS40001825F-page 80
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 62 (Continued)
— X ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 0000 0000 0000
1F5Bh ODCOND
— X SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 1111 1111 1111 1111
1F5Ch SLRCOND
— X INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 1111 1111 1111 1111
1F5Dh INLVLD
1F5Eh
— — — Unimplemented — —
1F60h
— X — — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111

1F64h ANSELE
— X — — — — WPUE3 WPUE2 WPUE1 WPUE0 ---- 0000 ---- 0000

1F65h WPUE
X — — — — — WPUE3 — — — ---- 0--- ---- 0---
— X — — — — — ODCE2 ODCE1 ODCE0 ---- -000 ---- -000

1F66h ODCONE
— X — — — — — SLRE2 SLRE1 SLRE0 ---- -111 ---- -111

1F67h SLRCONE
— X — — — — INLVLE3 INLVLE2 INLVLE1 INLVLE0 ---- 1111 ---- 1111

1F68h INLVLE
X — — — — — INLVLE3 — — — ---- 1--- ---- 1---
DS40001825F-page 81
1F69h IOCEP — — — — IOCEP3 — — — ---- 0--- ---- 0---
1F6Ah IOCEN — — — — IOCEN3 — — — ---- 0--- ---- 0---
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 62 (Continued)
1F6Bh IOCEF — — — — IOCEF3 — — — ---- 0--- ---- 0---
1F6Ch — Reserved, maintain as ‘0’ rrrr rrrr rrrr rrrr
— Unimplemented — —
1F6Dh — Reserved, maintain as ‘0’ rrrr rrrr rrrr rrrr
1F6Eh — — Unimplemented — —
1F6Fh — — Unimplemented — —
DS40001825F-page 82
PIC16(L)F18857/77
PIC16(L)F18857
PIC16(L)F18877
Bank 63
1F8Ch —
1FE3h
1FE4h STATUS_SHAD — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu
1FE5h WREG_SHAD WREG_SHAD xxxx xxxx uuuu uuuu
1FE6h BSR_SHAD — — BSR_SHAD --xx uxxx --uu uuuu
1FE7h PCLATH_SHAD — PCLATH_SHAD -xxx xxxx -uuu uuuu
1FE8h FSR0L_SHAD FSR0L_SHAD xxxx xxxx uuuu uuuu
1FE9h FSR0H_SHAD FSR0H_SHAD xxxx xxxx uuuu uuuu
1FEAh FSR1L_SHAD FSR1L_SHAD xxxx xxxx uuuu uuuu
1FEBh FSR1H_SHAD FSR1H_SHAD xxxx xxxx uuuu uuuu
1FECh — — Unimplemented —
1FEDh STKPTR — — — STKPTR<4;0> ---1 1111 ---1 1111
1FEEh TOSL TOSL<7:0> xxxx xxxx xxxx xxxx
1FEFh TOSH — TOSH<6:0> -xxx xxxx -xxx xxxx
1FF0h to — — Unimplemented — —
1FFFh
DS40001825F-page 83
PIC16(L)F18857/77
3.3 PCL and PCLATH 3.3.2 COMPUTED GOTO
The Program Counter (PC) is 15 bits wide. The low byte A computed GOTO is accomplished by adding an offset to
comes from the PCL register, which is a readable and the program counter (ADDWF PCL). When performing a
writable register. The high byte (PC<14:8>) is not directly table read using a computed GOTO method, care should
readable or writable and comes from PCLATH. On any be exercised if the table location crosses a PCL memory
Reset, the PC is cleared. Figure 3-3 shows the five boundary (each 256-byte block). Refer to Application
situations for the loading of the PC. Note AN556, “Implementing a Table Read” (DS00556).
3.3.3 COMPUTED FUNCTION CALLS

FIGURE 3-3: LOADING OF PC IN
DIFFERENT SITUATIONS A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
Rev. 10-000042A
7/30/2013
table read using a computed function CALL, care

14 PCH PCL 0
PC
Instruction should be exercised if the table location crosses a PCL
with PCL as
Destination
memory boundary (each 256-byte block).
7 8
6 0 If using the CALL instruction, the PCH<2:0> and PCL
PCLATH ALU result
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
14 PCH PCL 0 GOTO, The CALLW instruction enables computed calls by
PC
CALL combining PCLATH and W to form the destination
4 11 address. A computed CALLW is accomplished by
6 0
PCLATH OPCODE <10:0> loading the W register with the desired address and
executing CALLW. The PCL register is loaded with the
value of W and PCH is loaded with PCLATH.
14 PCH PCL 0
PC CALLW
3.3.4 BRANCHING
6
7
0 8 The branching instructions add an offset to the PC.
PCLATH W This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
14 PCH PCL 0
BRW and BRA. The PC will have incremented to fetch
PC BRW the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
15
crossed.
PC + W
If using BRW, load the W register with the desired
14 PCH PCL 0
PC BRA unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
15
If using BRA, the entire PC will be loaded with PC + 1,
PC + OPCODE <8:0>
the signed value of the operand of the BRA instruction.
3.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by writ-
ing the desired upper seven bits to the PCLATH regis-
ter. When the lower eight bits are written to the PCL
register, all 15 bits of the program counter will change
to the values contained in the PCLATH register and
those being written to the PCL register.

PIC16(L)F18857/77
3.4 Stack 3.4.1 ACCESSING THE STACK
All devices have a 16-level x 15-bit wide hardware The stack is available through the TOSH, TOSL and
stack (refer to Figure 3-4 through Figure 3-7). The STKPTR registers. STKPTR is the current value of the
stack space is not part of either program or data space. Stack Pointer. TOSH:TOSL register pair points to the
The PC is PUSHed onto the stack when CALL or TOP of the stack. Both registers are read/writable. TOS
CALLW instructions are executed or an interrupt causes is split into TOSH and TOSL due to the 15-bit size of the
a branch. The stack is POPed in the event of a PC. To access the stack, adjust the value of STKPTR,
RETURN, RETLW or a RETFIE instruction execution. which will position TOSH:TOSL, then read/write to
PCLATH is not affected by a PUSH or POP operation. TOSH:TOSL. STKPTR is five bits to allow detection of
overflow and underflow.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Words). This Note: Care should be taken when modifying the
means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled.
times, the seventeenth PUSH overwrites the value that
During normal program operation, CALL, CALLW and
was stored from the first PUSH. The eighteenth PUSH
interrupts will increment STKPTR while RETLW,
overwrites the second PUSH (and so on). The
RETURN, and RETFIE will decrement STKPTR. At any
STKOVF and STKUNF flag bits will be set on an
time, STKPTR can be inspected to see how much
Overflow/Underflow, regardless of whether the Reset is
stack is left. The STKPTR always points at the currently
enabled.
used place on the stack. Therefore, a CALL or CALLW
Note 1: There are no instructions/mnemonics will increment the STKPTR and then write the PC, and
called PUSH or POP. These are actions a return will unload the PC and then decrement the
that occur from the execution of the STKPTR.
CALL, CALLW, RETURN, RETLW and Reference Figure 3-4 through Figure 3-7 for examples
RETFIE instructions or the vectoring to of accessing the stack.
an interrupt address.
FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1
Rev. 10-000043A
7/30/2013
Stack Reset Disabled

TOSH:TOSL 0x0F STKPTR = 0x1F
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
Initial Stack Configuration:
0x0A
0x09 After Reset, the stack is empty. The
empty stack is initialized so the Stack
0x08 Pointer is pointing at 0x1F. If the Stack
0x07 Overflow/Underflow Reset is enabled, the
TOSH/TOSL register will return ‘0’. If the
0x06 Stack Overflow/Underflow Reset is
0x05 disabled, the TOSH/TOSL register will
return the contents of stack address
0x04 0x0F.
0x03
0x02
0x01
0x00
Stack Reset Enabled
TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F
(STVREN = 1)

PIC16(L)F18857/77
Rev. 10-000043B
7/30/2013
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00
Rev. 10-000043C
7/30/2013
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure on
the left. A series of RETURN instructions will
0x0A
repeatedly place the return addresses into
0x09 the Program Counter and pop the stack.
0x08
0x07
0x05 Return Address

0x04 Return Address
0x03 Return Address
0x02 Return Address
0x01 Return Address
0x00 Return Address

PIC16(L)F18857/77
Rev. 10-000043D
7/30/2013
0x0F Return Address

0x0E Return Address
0x0D Return Address
0x0C Return Address
0x0B Return Address
0x0A Return Address When the stack is full, the next CALL or
0x09 Return Address an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00 so
0x08 Return Address the stack will wrap and overwrite the
0x07 Return Address return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
0x06 Return Address Reset will occur and location 0x00 will
0x05 Return Address not be overwritten.
0x04 Return Address

0x03 Return Address
0x02 Return Address
0x01 Return Address
3.4.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be Reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.5 Indirect Addressing

The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Data EEPROM Memory
• Program Flash Memory

PIC16(L)F18857/77
FIGURE 3-8: INDIRECT ADDRESSING
Rev. 10-000044E
10/25/2016
0x0000 0x0000
Traditional
Data Memory
0x1FFF
0x2000
Linear
Data Memory
0X2FEF
0X2FF0
Reserved
0x7FFF
FSR
0x8000 PC value = 0x0000
Address
Range
Program
Flash Memory
0xFFFF PC value = 0x7FFF

PIC16(L)F18857/77
3.5.1 TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-9: TRADITIONAL DATA MEMORY MAP
Rev. 10-000056B
12/14/2016
Direct Addressing Indirect Addressing
From Opcode
5 BSR 0 6 0 7 FSRxH 0 7 FSRxL 0
0 0 0
Bank Select Location Select Bank Select Location Select
000000 000001 000010 111111

0x00
0x7F
Bank 0 Bank 1 Bank 2 Bank 63

PIC16(L)F18857/77
3.5.2 LINEAR DATA MEMORY 3.5.3 DATA EEPROM MEMORY
The linear data memory is the region from FSR The EEPROM memory can be read or written through
address 0x2000 to FSR address 0x2FEF. This region is the NVMCONx/NVMADRx/NVMDATx register
a virtual region that points back to the 80-byte blocks of interface (see section Section 10.2 “Data EEPROM
GPR memory in all the banks. Memory”). However, to make access to the EEPROM
Unimplemented memory reads as 0x00. Use of the memory easier, read-only access to the EEPROM
linear data memory region allows buffers to be larger contents are also available through indirect addressing
than 80 bytes because incrementing the FSR beyond by an FSR. When the MSB of the FSR (ex: FSRxH) is
one bank will go directly to the GPR memory of the next set to 0x70, the lower 8-bit address value (in FSRxL)
bank. determines the EEPROM location that may be read
from (through the INDF register). In other words, the
The 16 bytes of common memory are not included in EEPROM address range 0x00-0xFF is mapped into the
the linear data memory region. FSR address space between 0x7000-0x70FF. Writing
to the EEPROM cannot be accomplished via the
FIGURE 3-10: TRADITIONAL DATA FSR/INDF interface. Reads from the EEPROM through
the FSR/INDF interface will require one additional
MEMORY MAP
instruction cycle to complete.
3.5.4 PROGRAM FLASH MEMORY

Rev. 10-000057B
8/24/2016
To make constant data access easier, the entire

7 FSRnH 0 7 FSRnL 0 Program Flash Memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
Location Select
0x2000 set, the lower 15 bits are the address in program
0x020 memory which will be accessed through INDF. Only the
Bank 0
0x06F lower eight bits of each memory location is accessible
0x0A0
via INDF. Writing to the Program Flash Memory cannot
Bank 1 be accomplished via the FSR/INDF interface. All
0x0EF instructions that access Program Flash Memory via the
0x120 FSR/INDF interface will require one additional
Bank 2 instruction cycle to complete.
0x16F
FIGURE 3-11: PROGRAM FLASH

MEMORY MAP
0x1920
Bank 50 7 FSRnH 0 7 FSRnL 0
0x196F
0x2FEF 1
Location Select 0x8000 0x0000
Program
Flash
Memory
(low 8
bits)
0xFFFF 0x7FFF

PIC16(L)F18857/77
4.0 DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
Code Protection and Device ID.
4.1 Configuration Words

There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as shown in Table 4-1.
TABLE 4-1: CONFIGURATION WORD

LOCATIONS
Configuration Word Location
CONFIG1 8007h
CONFIG2 8008h
CONFIG3 8009h
CONFIG4 800Ah
CONFIG5 800Bh
Note: The DEBUG bit in Configuration Words is

managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.

PIC16(L)F18857/77
4.2 Register Definitions: Configuration Words
REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1: OSCILLATORS

R/P-1 U-1 R/P-1 U-1 U-1 R/P-1
FCMEN — CSWEN — — CLKOUTEN
bit 13 bit 8
U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1

— RSTOSC<2:0> — FEXTOSC<2:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is n = Value when blank or after Bulk Erase
set
bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = ON FSCM timer enabled
0 = OFF FSCM timer disabled
bit 12 Unimplemented: Read as ‘1’
bit 11 CSWEN: Clock Switch Enable bit
1 = ON Writing to NOSC and NDIV is allowed
0 = OFF The NOSC and NDIV bits cannot be changed by user software
bit 8 CLKOUTEN: Clock Out Enable bit
If FEXTOSC = EC (high, mid or low) or Not Enabled
1 = OFF CLKOUT function is disabled; I/O or oscillator function on OSC2
0 = ON CLKOUT function is enabled; FOSC/4 clock appears at OSC2
Otherwise
This bit is ignored.
bit 6-4 RSTOSC<2:0>: Power-up Default Value for COSC bits
This value is the Reset default value for COSC, and selects the oscillator first used by user software
111 = EXT1X EXTOSC operating per FEXTOSC bits
110 = HFINT1 HFINTOSC (1 MHz)
101 = LFINT LFINTOSC
100 = SOSC SOSC
011 = Reserved
010 = EXT4X EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits
001 = HFINTPLL HFINTOSC with 2x PLL, with OSCFRQ = 16 MHz and CDIV = 1:1(FOSC = 32 MHz)
000 = HFINT32 HFINTOSC with OSCFRQ= 32 MHz and CDIV = 1:1
bit 2-0 FEXTOSC<2:0>: FEXTOSC External Oscillator mode Selection bits
111 = ECH EC(External Clock)
110 = ECM EC(External Clock)
101 = ECL EC(External Clock)
100 = OFF External Oscillator is disabled. RA7 is available as a general purpose I/O.
011 = Reserved
010 = HS HS(Crystal oscillator)
001 = XT XT(Crystal oscillator)
000 = LP LP(Crystal oscillator)

PIC16(L)F18857/77
REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2: SUPERVISORS
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
DEBUG STVREN PPS1WAY ZCDDIS BORV —
bit 13 bit 8
R/P-1 R/P-1 R/P-1 U-1 U-1 U-1 R/P-1 R/P-1
BOREN<1:0> LPBOREN — — — PWRTE MCLRE
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase
bit 13 DEBUG: Debugger Enable bit(2)

1 = OFF Background debugger disabled; ICSPCLK and ICSPDAT are general purpose I/O pins
0 = ON Background debugger enabled; ICSPCLK and ICSPDAT are dedicated to the debugger
bit 12 STVREN: Stack Overflow/Underflow Reset Enable bit

1 = ON Stack Overflow or Underflow will cause a Reset
0 = OFF Stack Overflow or Underflow will not cause a Reset
bit 11 PPS1WAY: PPSLOCKED One-Way Set Enable bit

1 = ON The PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle
0 = OFF The PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
bit 10 ZCDDIS: Zero-Cross Detect Disable bit

1 = ON ZCD disabled. ZCD can be enabled by setting the EN bit of the ZCDxCON register
0 = OFF ZCD always enabled (EN bit is ignored)
bit 9 BORV: Brown-out Reset Voltage Selection bit(1)

1 = LOW Brown-out Reset voltage (VBOR) set to lower trip point level
0 = HIGH Brown-out Reset voltage (VBOR) set to higher trip point level
The higher voltage setting is recommended for operation at or above 16 MHz.
bit 7-6 BOREN<1:0>: Brown-out Reset Enable bits

When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit
11 = ON Brown-out Reset is enabled; SBOREN bit is ignored
10 = SLEEP Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored
01 = SBOREN Brown-out Reset is enabled according to SBOREN
00 = OFF Brown-out Reset is disabled
bit 5 LPBOREN: Low-Power BOR Enable bit

1 = LPBOR disabled
0 = LPBOR enabled
bit 1 PWRTE: Power-up Timer Enable bit

1 = OFF PWRT is disabled
0 = ON PWRT is enabled
bit 0 MCLRE: Master Clear (MCLR) Enable bit

If LVP = 1:
RE3 pin function is MCLR.
If LVP = 0:
1 = ON MCLR pin is MCLR.
0 = OFF MCLR pin function is port-defined function.
Note 1: See VBOR parameter for specific trip point voltages.

2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers.
For normal device operation, this bit should be maintained as a ‘1’.

PIC16(L)F18857/77
REGISTER 4-3: CONFIG3: CONFIGURATION WORD 3: WINDOWED WATCHDOG

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
WDTCCS<2:0> WDTCWS<2:0>
bit 13 bit 8
U-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

WDTE<1:0> WDTCPS<4:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit x = Bit is unknown U = Unimplemented bit, read
as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set W = Writable bit n = Value when blank or after
Bulk Erase
bit 13-11 WDTCCS<2:0>: WDT Input Clock Selector bits

111 = Software Control
110 = Reserved
.
.
.
010 = Reserved
001 = WDT reference clock is the MFINTOSC/16 output (31.25 kHz)
000 = WDT reference clock is the 31.0 kHz LFINTOSC (default value)
bit 10-8 WDTCWS<2:0>: WDT Window Select bits
WDTWS at POR
Software Keyed
WDTCWS Window control of access
Window delay
Value opening WDTWS? required?
Percent of time
Percent of time
111 111 n/a 100 Yes No
110 111 n/a 100
101 101 25 75
100 100 37.5 62.5
011 011 50 50 No Yes
010 010 62.5 37.5
001 001 75 25
000 000 87.5 12.5

bit 6-5 WDTE<1:0>: WDT Operating mode:
11 = WDT enabled regardless of Sleep; SWDTEN is ignored
10 = WDT enabled while Sleep = 0, suspended when Sleep = 1; SWDTEN ignored
01 = WDT enabled/disabled by SWDTEN bit in WDTCON0
00 = WDT disabled, SWDTEN is ignored

PIC16(L)F18857/77
REGISTER 4-3: CONFIG3: CONFIGURATION WORD 3: WINDOWED WATCHDOG (CONTINUED)
bit 4-0 WDTCPS<4:0>: WDT Period Select bits
WDTPS at POR
Software control
WDTCPS Typical time out
Value Divider Ratio of WDTPS?
(FIN = 31 kHz)
11111 01011 1:65536 216 2s Yes
11110 11110
... ... 1:32 25 1 ms No
10011 10011
10010 10010 1:8388608 223 256 s
22
10001 10001 1:4194304 2 128 s
21
10000 10000 1:2097152 2 64 s
01111 01111 1:1048576 220 32 s
19
01110 01110 1:524299 2 16 s
18
01101 01101 1:262144 2 8s
17
01100 01100 1:131072 2 4s
01011 01011 1:65536 216 2s
15
01010 01010 1:32768 2 1s
14
01001 01001 1:16384 2 512 ms No
13
01000 01000 1:8192 2 256 ms
00111 00111 1:4096 212 128 ms
11
00110 00110 1:2048 2 64 ms
10
00101 00101 1:1024 2 32 ms
9
00100 00100 1:512 2 16 ms
00011 00011 1:256 28 8 ms
7
00010 00010 1:128 2 4 ms
6
00001 00001 1:64 2 2 ms
5
00000 00000 1:32 2 1 ms

PIC16(L)F18857/77
REGISTER 4-4: CONFIG4: CONFIGURATION WORD 4: MEMORY

R/P-1 R/P-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1
LVP SCANE — — — — — — — — — — WRT<1:0>
bit 13 bit 0
Legend:
R = Readable bit P = Programmable bit x = Bit is U = Unimplemented bit, read as ‘1’
unknown
‘0’ = Bit is cleared ‘1’ = Bit is set W = Writable bit n = Value when blank or after Bulk Erase
bit 13 LVP: Low-Voltage Programming Enable bit

1 = Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is
ignored.
0 = High voltage (meeting VIHH level) on MCLR/VPP must be used for programming.
The LVP bit cannot be written (to zero) while operating from the LVP programming interface. This prevents
accidental lockout from low-voltage programming while using low-voltage programming. High voltage
programming is always available, regardless of the LVP Configuration bit value.
bit 12 SCANE: Scanner Enable bit
1 = Scanner module is available for use, SCANMD bit enables the module.
0 = Scanner module is NOT available for use, SCANMD bit is ignored.
bit 1-0 WRT<1:0>: Program Flash Self-Write Erase Protection bits
11 = Write protection off
10 = 0000h to 01FFh write-protected, 0200h to 7FFFh may be modified by EECON control
01 = 0000h to 3FFFh write-protected, 4000h to 7FFFh may be modified by EECON control
00 = 0000h to 7FFFh write-protected, no addresses may be modified by EECON control

PIC16(L)F18857/77
REGISTER 4-5: CONFIG5: CONFIGURATION WORD 5: CODE PROTECTION

U-1 U-1 U-1 U-1 U-1 U-1
— — — — — —
bit 13 bit 8
U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1

— — — — — — CPD CP
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit x = Bit is unknown U = Unimplemented bit, read
as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set W = Writable bit n = Value when blank or after
Bulk Erase

bit 1 CPD: Data NVM (EEPROM) Memory Code Protection bit
1 = EEPROM code protection disabled
0 = EEPROM code protection enabled
bit 0 CP: Program Flash Memory Code Protection bit
1 = Program Flash Memory code protection disabled
0 = Program Flash Memory code protection enabled

PIC16(L)F18857/77
4.3 Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data memory are controlled independently. Internal
access to the program memory is unaffected by any
code protection setting.
4.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Self-writing the
program memory is dependent upon the write
protection setting. See Section 4.4 “Write
Protection” for more information.
4.3.2 DATA MEMORY PROTECTION

The entire data EEPROM memory space is protected
from external reads and writes by the CPD bit in the
Configuration Words. When CPD = 0, external reads
and writes of EEPROM memory are inhibited and a
read will return all ‘0’s. The CPU can continue to read
EEPROM memory, regardless of the protection bit
settings.
4.4 Write Protection

Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
4.5 User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4.7 “NVMREG Data EEPROM Memory,
User ID, Device ID and Configuration Word
Access” for more information on accessing these
memory locations. For more information on checksum
calculation, see the “PIC16(L)F188XX Memory
Programming Specification” (DS40001753).

PIC16(L)F18857/77
4.6 Device ID and Revision ID
The 14-bit device ID word is located at 8006h and the
14-bit revision ID is located at 8005h. These locations
are read-only and cannot be erased or modified.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID,
Revision ID and Configuration Words. These locations
can also be read from the NVMCON register.
4.7 Register Definitions: Device and Revision
REGISTER 4-6: DEVID: DEVICE ID REGISTER

R R R R R R
DEV<13:8>
bit 13 bit 8
R R R R R R R R
DEV<7:0>
bit 7 bit 0
Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 13-0 DEV<13:0>: Device ID bits
Device DEVID<13:0> Values

PIC16F18857 11 0000 0111 0100 (3074h)
PIC16LF18857 11 0000 0111 0110 (3076h)
PIC16F18877 11 0000 0111 0101 (3075h)
PIC16LF18877 11 0000 0111 0111 (3077h)
REGISTER 4-7: REVISIONID: REVISION ID REGISTER

R R R R R R R R R R R R R R
1 0 MJRREV<5:0> MNRREV<5:0>
bit 13 bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown
bit 13-12 Fixed Value: Read-only bits

These bits are fixed with value ‘10’ for all devices included in this data sheet.
bit 11-6 MJRREV<5:0>: Major Revision ID bits
These bits are used to identify a major revision. A major revision is indicated by an all layer revision (B0,
C0, etc.)
bit 5-0 MNRREV<5:0>: Minor Revision ID bits
These bits are used to identify a minor revision.

PIC16(L)F18857/77
5.0 RESETS
There are multiple ways to reset this device:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
• MCLR Reset
• WDT Reset
• RESET instruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional Power-up timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Rev. 10-000 006D
1/22/201 4
ICSP™ Programming Mode Exit

RESET Instruction
Stack Underflow
Stack Overflow
VPP /MCLR MCLRE

Sleep
WDT
Time-out WDT Device
Window Reset
Violation
Power-on
Reset
VDD BOR Active(1)
R
Brown-out Power-up
Reset Timer
LFINTOSC PWRTE
LPBOR
Reset
Note 1: See Table 5-1 for BOR active conditions.

PIC16(L)F18857/77
5.1 Power-On Reset (POR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
5.2 Brown-Out Reset (BOR)

The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in
Configuration Words. The four operating modes are:
• BOR is always on
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
Refer to Table 5-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.
A VDD noise rejection filter prevents the BOR from
triggering on small events. If VDD falls below VBOR for
a duration greater than parameter TBORDC, the device
will reset. See Figure 5-2 for more information.
TABLE 5-1: BOR OPERATING MODES

Instruction Execution upon:
BOREN<1:0> SBOREN Device Mode BOR Mode
Release of POR or Wake-up from Sleep
11 X X Active Wait for release of BOR(1) (BORRDY = 1)

Awake Active Waits for release of BOR (BORRDY = 1)
10 X
Sleep Disabled Waits for BOR Reset release
1 X Active Waits for BOR Reset release (BORRDY = 1)

01
0 X Disabled
Begins immediately (BORRDY = x)
00 X X Disabled
Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
5.2.1 BOR IS ALWAYS ON 5.2.2 BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Words are When the BOREN bits of Configuration Words are
programmed to ‘11’, the BOR is always on. The device programmed to ‘10’, the BOR is on, except in Sleep.
start-up will be delayed until the BOR is ready and VDD The device start-up will be delayed until the BOR is
is higher than the BOR threshold. ready and VDD is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does BOR protection is not active during Sleep. The device
not delay wake-up from Sleep. wake-up will be delayed until the BOR is ready.

PIC16(L)F18857/77
5.2.3 BOR CONTROLLED BY SOFTWARE 5.2.4 BOR IS ALWAYS OFF
When the BOREN bits of Configuration Words are When the BOREN bits of the Configuration Words are
programmed to ‘01’, the BOR is controlled by the programmed to ‘00’, the BOR is off at all times. The
SBOREN bit of the BORCON register. The device device start-up is not delayed by the BOR ready
start-up is not delayed by the BOR ready condition or condition or the VDD level.
the VDD level.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.
FIGURE 5-2: BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset TPWRT(1)
VDD
VBOR
Internal < TPWRT

Reset TPWRT(1)
VDD
VBOR
Internal
Reset TPWRT(1)
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

PIC16(L)F18857/77
5.3 Register Definitions: Brown-out Reset Control
REGISTER 5-1: BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u
SBOREN(1) — — — — — — BORRDY
bit 7 bit 0
Legend:
bit 7 SBOREN: Software Brown-out Reset Enable bit(1)

If BOREN <1:0> in Configuration Words  01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Words = 01:
1 = BOR Enabled
0 = BOR Disabled
bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
Note 1: BOREN<1:0> bits are located in Configuration Words.
5.4 MCLR 5.5 Windowed Watchdog Timer

The MCLR is an optional external input that can reset
(WWDT) Reset
the device. The MCLR function is controlled by the The Watchdog Timer generates a Reset if the firmware
MCLRE bit of Configuration Words and the LVP bit of does not issue a CLRWDT instruction within the time-out
Configuration Words (Table 5-2). period and the window is open. The TO and PD bits in
the STATUS register and the WDT bit in PCON are
changed to indicate a WDT Reset caused by the timer
TABLE 5-2: MCLR CONFIGURATION
overflowing, and WDTWV bit in the PCON register is
MCLRE LVP MCLR changed to indicate a WDT Reset caused by a window
0 0 Disabled violation. See Section 9.0 “Windowed Watchdog
Timer (WWDT)” for more information.
1 0 Enabled
x 1 Enabled
5.4.1 MCLR ENABLED

When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
Note: A Reset does not drive the MCLR pin low.
5.4.2 MCLR DISABLED

When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 12.1 “I/O Priorities” for
more information.

PIC16(L)F18857/77
5.6 RESET Instruction 5.10 Start-up Sequence
A RESET instruction will cause a device Reset. The RI Upon the release of a POR or BOR, the following must
bit in the PCON register will be set to ‘0’. See Table 5-4 occur before the device will begin executing:
for default conditions after a RESET instruction has 1. Power-up Timer runs to completion (if enabled).
occurred.
2. Oscillator start-up timer runs to completion (if
required for oscillator source).
5.7 Stack Overflow/Underflow Reset
3. MCLR must be released (if enabled).
The device can reset when the Stack Overflows or The total time-out will vary based on oscillator
Underflows. The STKOVF or STKUNF bits of the PCON configuration and Power-up Timer Configuration. See
register indicate the Reset condition. These Resets are Section 6.0 “Oscillator Module (with Fail-Safe
enabled by setting the STVREN bit in Configuration Clock Monitor)” for more information.
Words. See Section 3.4.2 “Overflow/Underflow
Reset” for more information. The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer and oscillator
5.8 Programming Mode Exit start-up timer will expire. Upon bringing MCLR high, the
Upon exit of In-Circuit Serial Programming (ICSP) device will begin execution after 10 FOSC cycles (see
mode, the device will behave as if a POR had just Figure 5-3). This is useful for testing purposes or to
occurred (the device does not reset upon run time synchronize more than one device operating in parallel.
self-programming/erase operations).
5.9 Power-Up Timer

The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
The Power-up Timer is controlled by the PWRTE bit of
the Configuration Words.
The Power-up Timer provides a nominal 64 ms time out
on POR or Brown-out Reset. The device is held in
Reset as long as PWRT is active. The PWRT delay
allows additional time for the VDD to rise to an accept-
able level. The Power-up Timer is enabled by clearing
the PWRTE bit in the Configuration Words. The
Power-up Timer starts after the release of the POR and
BOR. For additional information, refer to Application
Note AN607, “Power-up Trouble Shooting” (DS00607).

PIC16(L)F18857/77
FIGURE 5-3: RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC

PIC16(L)F18857/77
5.11 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 5-3 and Table 5-4 show the Reset
conditions of these registers.
TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition
0 0 1 1 1 0 x 1 1 Power-on Reset
0 0 1 1 1 0 x 0 x Illegal, TO is set on POR
0 0 1 1 1 0 x x 0 Illegal, PD is set on POR
0 0 u 1 1 u 0 1 1 Brown-out Reset
u u 0 u u u u 0 u WDT Reset
u u u u u u u 0 0 WDT Wake-up from Sleep
u u u u u u u 1 0 Interrupt Wake-up from Sleep
u u u 0 u u u u u MCLR Reset during normal operation
u u u 0 u u u 1 0 MCLR Reset during Sleep
u u u u 0 u u u u RESET Instruction Executed
1 u u u u u u u u Stack Overflow Reset (STVREN = 1)
u 1 u u u u u u u Stack Underflow Reset (STVREN = 1)
TABLE 5-4: RESET CONDITION FOR SPECIAL REGISTERS

Program STATUS PCON0
Condition
Counter Register Register
Power-on Reset 0000h ---1 1000 00-- 110x
MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu
MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu
WDT Reset 0000h ---0 uuuu uu-0 uuuu
WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-u uuuu
WDT Window Violation 0000h ---0 uuuu uu00 uuuu
Brown-out Reset 0000h ---1 1000 00-1 11u0
(1)
Interrupt Wake-up from Sleep PC + 1 ---1 0uuu uu-u uuuu
RESET Instruction Executed 0000h ---u uuuu uu-u u0uu
Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-u uuuu
Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

PIC16(L)F18857/77
5.12 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Reset Instruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Watchdog Timer Window Violation Reset
(WDTWV)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON0 register bits are shown in Register 5-2.
Hardware will change the corresponding register bit
during the Reset process; if the Reset was not caused
by the condition, the bit remains unchanged
(Table 5-4).
Software should reset the bit to the inactive state after
the restart (hardware will not reset the bit).
Software may also set any PCON bit to the active state,
so that user code may be tested, but no reset action will
be generated.

PIC16(L)F18857/77
5.13 Register Definitions: Power Control
REGISTER 5-2: PCON0: POWER CONTROL REGISTER 0

R/W/HS-0/q R/W/HS-0/q R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR
bit 7 bit 0
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware
bit 6 STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware
bit 5 WDTWV: WDT Window Violation Flag bit
1 = A WDT Window Violation Reset has not occurred or set by firmware
0 = A WDT Window Violation Reset has occurred (a CLRWDT instruction was executed either without
arming the window or outside the window (cleared by hardware)
bit 4 RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3 RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2 RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BORCON SBOREN — — — — — — BORRDY 103
PCON0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 108
STATUS — — — TO PD Z DC C 38
WDTCON0 — — WDTPS<4:0> SWDTEN 165
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

PIC16(L)F18857/77
6.0 OSCILLATOR MODULE (WITH If an external clock source is selected, the FEXTOSC
bits of Configuration Word 1 must be used in
FAIL-SAFE CLOCK MONITOR)
conjunction with the RSTOSC bits to select the external
clock mode.
6.1 Overview
The external oscillator module can be configured in one
The oscillator module has a wide variety of clock of the following clock modes, by setting the
sources and selection features that allow it to be used FEXTOSC<2:0> bits of Configuration Word 1:
in a wide range of applications while maximizing 1. ECL – External Clock Low-Power mode
performance and minimizing power consumption. (below 500 kHz)
Figure 6-1 illustrates a block diagram of the oscillator
2. ECM – External Clock Medium Power mode
module.
(500 kHz to 8 MHz)
Clock sources can be supplied from external oscillators, 3. ECH – External Clock High-Power mode
quartz-crystal resonators and ceramic resonators. In (above 8 MHz)
addition, the system clock source can be supplied from
4. LP – 32 kHz Low-Power Crystal mode.
one of two internal oscillators and PLL circuits, with a
choice of speeds selectable via software. Additional 5. XT – Medium Gain Crystal or Ceramic Resonator
clock features include: Oscillator mode (between 100 kHz and 4 MHz)
6. HS – High Gain Crystal or Ceramic Resonator
• Selectable system clock source between external
mode (above 4 MHz)
or internal sources via software.
• Fail-Safe Clock Monitor (FSCM) designed to The ECH, ECM, and ECL clock modes rely on an
detect a failure of the external clock source (LP, external logic level signal as the device clock source.
XT, HS, ECH, ECM, ECL) and switch The LP, XT, and HS clock modes require an external
automatically to the internal oscillator. crystal or resonator to be connected to the device.
Each mode is optimized for a different frequency range.
• Oscillator Start-up Timer (OST) ensures stability
The INTOSC internal oscillator block produces low and
of crystal oscillator sources.
high-frequency clock sources, designated LFINTOSC
The RSTOSC bits of Configuration Word 1 determine and HFINTOSC. (see Internal Oscillator Block,
the type of oscillator that will be used when the device Figure 6-1). A wide selection of device clock
reset, including when it is first powered up. frequencies may be derived from these clock sources.
The internal clock modes, LFINTOSC, HFINTOSC (set
at 1 MHz), or HFINTOSC (set at 32 MHz) can be set
through the RSTOSC bits.

FIGURE 6-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
PIC16(L)F18857/77
Rev. 10-000208J
12/13/2016
CLKIN
External
Oscillator
(EXTOSC)
CLKOUT
CDIV<4:0>
4x PLL Mode
COSC<2:0>
SOSCIN/SOSCI
Secondary PLLBlock 512

Oscillator 1001
256
(SOSC) 111 1000
128 Sleep
001 0111
9-bit Postscaler Divider

2x PLL Mode System Clock
SOSCO
64
010 0110
LFINTOSC 32
100 0101
31kHz 16
101 0100 SYSCMD Peripheral Clock
Oscillator
8
110 0011
4
Reserved 000 0010 Sleep
2
011 0001 Idle
1
0000
HFINTOSC
HFFRQ<2:0>
1 – 32 MHz
MFINTOSC FSCM
Oscillator
To Peripherals
To Peripherals
500 kHz
DS40001825F-page 110
To Peripherals
31.25 kHz
To Peripherals
To Peripherals
PIC16(L)F18857/77
6.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up
External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully
clock source to function. Examples are: oscillator static, stopping the external clock input will have the
modules (ECH, ECM, ECL mode), quartz crystal effect of halting the device while leaving all data intact.
resonators or ceramic resonators (LP, XT and HS Upon restarting the external clock, the device will
modes). resume operation as if no time had elapsed.
Internal clock sources are contained within the
oscillator module. The internal oscillator block has two FIGURE 6-2: EXTERNAL CLOCK (EC)
internal oscillators and a dedicated Phase Lock Loop MODE OPERATION
(PLL) that are used to generate internal system clock
sources. The High-Frequency Internal Oscillator OSC1/CLKIN
Clock from
(HFINTOSC) can produce a range from 1 to 32 MHz. Ext. System
The Low-Frequency Internal Oscillator (LFINTOSC) PIC® MCU
generates a 31 kHz frequency. The external oscillator
block can also be used with the PLL. See OSC2/CLKOUT
FOSC/4 or I/O(1)
Section 6.2.1.4 “4x PLL” for more details.
The system clock can be selected between external or
Note 1: Output depends upon CLKOUTEN bit of the
internal clock sources via the NOSC bits in the
Configuration Words.
OSCCON1 register. See Section 6.3 “Clock
Switching” for additional information.
6.2.1.2 LP, XT, HS Modes
6.2.1 EXTERNAL CLOCK SOURCES
The LP, XT and HS modes support the use of quartz
An external clock source can be used as the device crystal resonators or ceramic resonators connected to
system clock by performing one of the following OSC1 and OSC2 (Figure 6-3). The three modes select
actions: a low, medium or high gain setting of the internal
• Program the RSTOSC<2:0> bits in the inverter-amplifier to support various resonator types
Configuration Words to select an external clock and speed.
source that will be used as the default system LP Oscillator mode selects the lowest gain setting of the
clock upon a device Reset internal inverter-amplifier. LP mode current consumption
• Write the NOSC<2:0> and NDIV<4:0> bits in the is the least of the three modes. This mode is designed to
OSCCON1 register to switch the system clock drive only 32.768 kHz tuning-fork type crystals (watch
source crystals).
See Section 6.3 “Clock Switching”for more XT Oscillator mode selects the intermediate gain
information. setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
6.2.1.1 EC Mode This mode is best suited to drive resonators with a
The External Clock (EC) mode allows an externally medium drive level specification.
generated logic level signal to be the system clock HS Oscillator mode selects the highest gain setting of the
source. When operating in this mode, an external clock internal inverter-amplifier. HS mode current consumption
source is connected to the OSC1 input. is the highest of the three modes. This mode is best
OSC2/CLKOUT is available for general purpose I/O or suited for resonators that require a high drive setting.
CLKOUT. Figure 6-2 shows the pin connections for EC Figure 6-3 and Figure 6-4 show typical circuits for
mode. quartz crystal and ceramic resonators, respectively.
EC mode has three power modes to select from through
Configuration Words:
• ECH – High power, 4-32 MHz
• ECM – Medium power, 0.1-4 MHz
• ECL – Low power, 0-0.1 MHz

PIC16(L)F18857/77
FIGURE 6-3: QUARTZ CRYSTAL FIGURE 6-4: CERAMIC RESONATOR
OPERATION (LP, XT OR OPERATION
HS MODE) (XT OR HS MODE)
PIC® MCU PIC® MCU
OSC1/CLKIN OSC1/CLKIN
C1 To Internal C1 To Internal
Logic Logic
Quartz
RF(2) Sleep RP(3)
Crystal RF(2) Sleep
OSC2/CLKOUT
C2 RS(1) OSC2/CLKOUT
C2 Ceramic RS(1)
Resonator
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M. 2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator
according to type, package and operation.
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application. 6.2.1.3 Oscillator Start-up Timer (OST)
2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS
the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts
expected for the application. 1024 oscillations from OSC1. This occurs following a
3: For oscillator design assistance, reference Power-on Reset (POR), or a wake-up from Sleep. The
the following Microchip Application Notes: OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
• AN826, “Crystal Oscillator Basics and is providing a stable system clock to the oscillator
Crystal Selection for rfPIC® and PIC® module.
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)

PIC16(L)F18857/77
6.2.1.4 4x PLL
Note 1: Quartz crystal characteristics vary
The oscillator module contains a PLL that can be used according to type, package and
with external clock sources to provide a system clock manufacturer. The user should consult the
source. The input frequency for the PLL must fall within manufacturer data sheets for specifications
specifications. See the PLL Clock Timing and recommended application.
Specifications in Table 37-9.
2: Always verify oscillator performance over
The PLL may be enabled for use by one of two the VDD and temperature range that is
methods: expected for the application.
1. Program the RSTOSC bits in the Configuration 3: For oscillator design assistance, reference
Word 1 to enable the EXTOSC with 4x PLL. the following Microchip Application Notes:
2. Write the NOSC bits in the OSCCON1 register • AN826, “Crystal Oscillator Basics and
to enable the EXTOSC with 4x PLL. Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
6.2.1.5 Secondary Oscillator
• AN849, “Basic PIC® Oscillator Design”
The secondary oscillator is a separate oscillator block (DS00849)
that can be used as an alternate system clock source. • AN943, “Practical PIC® Oscillator
The secondary oscillator is optimized for 31 kHz, and Analysis and Design” (DS00943)
can be used with an external crystal oscillator con-
• AN949, “Making Your Oscillator Work”
nected to the SOSCI and SOSCO device pins, or an
(DS00949)
external clock source connected to the SOSCIN pin.
The secondary oscillator can be selected during • TB097, “Interfacing a Micro Crystal
run-time using clock switching. Refer to Section 6.3 MS1V-T1K 32.768 kHz Tuning Fork
“Clock Switching” for more information. Crystal to a PIC16F690/SS” (DS91097)
• AN1288, “Design Practices for
FIGURE 6-5: QUARTZ CRYSTAL Low-Power External Oscillators”
OPERATION (DS01288)
(SECONDARY
OSCILLATOR)
PIC® MCU
SOSCI
C1 To Internal
Logic
32.768 kHz
Quartz
Crystal
C2 SOSCO

PIC16(L)F18857/77
6.2.2 INTERNAL CLOCK SOURCES 6.2.2.1 HFINTOSC
The device may be configured to use the internal The High-Frequency Internal Oscillator (HFINTOSC) is
oscillator block as the system clock by performing one a precision digitally-controlled internal clock source
of the following actions: that produces a stable clock up to 32 MHz. The
• Program the RSTOSC<2:0> bits in Configuration HFINTOSC can be enabled through one of the
Words to select the INTOSC clock source, which following methods:
will be used as the default system clock upon a • Programming the RSTOSC<2:0> bits in
device Reset. Configuration Word 1 to ‘110’ (1 MHz) or ‘000’
• Write the NOSC<2:0> bits in the OSCCON1 (32 MHz) to set the oscillator upon device
register to switch the system clock source to the Power-up or Reset.
internal oscillator during run-time. See • Write to the NOSC<2:0> bits of the OSCCON1
Section 6.3 “Clock Switching” for more register during run-time.
information. The HFINTOSC frequency can be selected by setting
In INTOSC mode, OSC1/CLKIN is available for general the HFFRQ<2:0> bits of the OSCFRQ register.
purpose I/O. OSC2/CLKOUT is available for general The NDIV<3:0> bits of the OSCCON1 register allow for
purpose I/O or CLKOUT. division of the HFINTOSC output from a range between
The function of the OSC2/CLKOUT pin is determined 1:1 and 1:512.
by the CLKOUTEN bit in Configuration Words.
The internal oscillator block has two independent
oscillators that can produce two internal system clock
sources.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates up
to 32 MHz. The frequency of HFINTOSC can be
selected through the OSCFRQ Frequency
Selection register, and fine-tuning can be done
via the OSCTUNE register.
2. The LFINTOSC (Low-Frequency Internal
Oscillator) is factory-calibrated and operates at
31 kHz.

PIC16(L)F18857/77
6.2.2.2 Internal Oscillator Frequency 6.2.2.4 MFINTOSC
Adjustment In addition to the two independent internal oscillators,
The internal oscillator is factory-calibrated. This the internal oscillator block also contains a divider block
internal oscillator can be adjusted in software by writing called MFINTOSC, to supply certain specific frequen-
to the OSCTUNE register (Register 6-7). cies to other modules on the device. The MFINTOSC
module takes the undivided HFINTOSC clock as an
The default value of the OSCTUNE register is 00h. The
input and outputs two clocks, a 500 kHz clock
value is a 6-bit two’s complement number. A value of
(MFINTOSC) and a 31.25 kHz clock (MFINTOSC/16).
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to The MFINTOSC is enabled through one of the follow-
the minimum frequency. ing methods:
When the OSCTUNE register is modified, the oscillator • Setting the MFOEN bit of OSCEN (see
frequency will begin shifting to the new frequency. Code Section 6.2.2.5 “Oscillator Status and Manual
execution continues during this shift. There is no Enable”)
indication that the shift has occurred. • Selecting MFINTOSC or MFINTOSC/16 as an input
OSCTUNE does not affect the LFINTOSC frequency. clock for one of the peripherals that uses the clock.
Operation of features that depend on the LFINTOSC Peripherals that use the MFINTOSC output (500 kHz)
clock source frequency, such as the Power-up Timer are:
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
• TMR1
Monitor (FSCM) and peripherals, are not affected by the
change in frequency. • TMR3
• TMR5
6.2.2.3 LFINTOSC
• SMT1
The Low-Frequency Internal Oscillator (LFINTOSC) is
a factory calibrated 31 kHz internal clock source. • SMT2
The LFINTOSC is the frequency for the Power-up Timer • CLKREF
(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Peripherals that use the MFINTOSC/16 output
Monitor (FSCM). (31.25 kHz) are:
The LFINTOSC is enabled through one of the following • WDT
methods:
• TMR2
• Programming the RSTOSC<2:0> bits of
• TMR4
Configuration Word 1 to enable LFINTOSC.
• Write to the NOSC<2:0> bits of the OSCCON1 • TMR6
register. • SMT1
Peripherals that use the LFINTOSC are: • SMT2
• Power-up Timer (PWRT) • CLKREF
• Watchdog Timer (WDT)
• TMR1
Note: Enabling the MFINTOSC will also enable
• TMR0 the HFINTOSC.
• TMR2
• SMT1 6.2.2.5 Oscillator Status and Manual Enable
• SMT2 The ‘ready’ status of each oscillator is displayed in the
• CLKREF OSCSTAT register (Register 6-4). The oscillators can
• CLC also be manually enabled through the OSCEN register
(Register 6-7). Manual enabling makes it possible to
verify the operation of the EXTOSC or SOSC crystal
oscillators. This can be achieved by enabling the
selected oscillator, then watching the corresponding
‘ready’ state of the oscillator in the OSCSTAT register.

PIC16(L)F18857/77
6.3 Clock Switching Changing the clock post-divider without changing the
clock source (i.e., changing FOSC from 1 MHz to 2
The system clock source can be switched between MHz) is handled in the same manner as a clock source
external and internal clock sources via software using change, as described previously. The clock source will
the New Oscillator Source (NOSC) and New Divider already be active, so the switch is relatively quick.
selection request (NDIV) bits of the OSCCON1 register. CSWHOLD must be clear (CSWHOLD = 0) for the
The following clock sources can be selected using the switch to complete.
following:
The current COSC and CDIV are indicated in the
• External oscillator OSCCON2 register up to the moment when the switch
• Internal Oscillator Block (INTOSC) actually occurs, at which time OSCCON2 is updated
and ORDY is set. NOSCR is cleared by hardware to
6.3.1 NEW OSCILLATOR SOURCE indicate that the switch is complete.
(NOSC) AND NEW DIVIDER
SELECTION REQUEST (NDIV) BITS 6.3.2 PLL INPUT SWITCH
The New Oscillator Source (NOSC) and New Divider Switching between the PLL and any non-PLL source is
selection request (NDIV) bits of the OSCCON1 register managed as described above. The input to the PLL is
select the system clock source that is used for the CPU established when NOSC selects the PLL, and main-
and peripherals. tained by the COSC setting.
When new values of NOSC and NDIV are written to When NOSC and COSC select the PLL with different
OSCCON1, the current oscillator selection will input sources, the system continues to run using the
continue to operate while waiting for the new clock COSC setting, and the new source is enabled per
source to indicate that it is stable and ready. In some NOSC. When the new oscillator is ready (and
cases, the newly requested source may already be in CSWHOLD = 0), system operation is suspended while
use, and is ready immediately. In the case of a the PLL input is switched and the PLL acquires lock.
divider-only change, the new and old sources are the
same, so the old source will be ready immediately. The
device may enter Sleep while waiting for the switch as Note: If the PLL fails to lock, the FSCM will
described in Section 6.3.3, Clock Switch and Sleep. trigger.
When the new oscillator is ready, the New Oscillator is
6.3.3 CLOCK SWITCH AND SLEEP
Ready (NOSCR) bit of OSCCON3 and the Clock
Switch Interrupt Flag (CSWIF) bit of PIR1 become set If OSCCON1 is written with a new value and the device
(CSWIF = 1). If Clock Switch Interrupts are enabled is put to Sleep before the switch completes, the switch
(CLKSIE = 1), an interrupt will be generated at that will not take place and the device will enter Sleep
time. The Oscillator Ready (ORDY) bit of OSCCON3 mode.
can also be polled to determine when the oscillator is When the device wakes from Sleep and the
ready in lieu of an interrupt. CSWHOLD bit is clear, the device will wake with the
If the Clock Switch Hold (CSWHOLD) bit of OSCCON3 ‘new’ clock active, and the clock switch interrupt flag bit
is clear, the oscillator switch will occur when the New (CSWIF) will be set.
Oscillator is ready bit (NOSCR) is set, and the interrupt
When the device wakes from Sleep and the
(if enabled) will be serviced at the new oscillator
CSWHOLD bit is set, the device will wake with the ‘old’
setting.
clock active and the new clock will be requested again.
If CSWHOLD is set, the oscillator switch is suspended,
while execution continues using the current (old) clock
source. When the NOSCR bit is set, software should:
• Set CSWHOLD = 0 so the switch can complete,
or
• Copy COSC into NOSC to abandon the switch.
If DOZE is in effect, the switch occurs on the next clock
cycle, whether or not the CPU is operating during that
cycle.

PIC16(L)F18857/77
FIGURE 6-6: CLOCK SWITCH (CSWHOLD = 0)
OSCCON1
WRITTEN
OSC #1 OSC #2
ORDY
NOTE 2
NOSCR
NOTE 1
CSWIF
USER
CSWHOLD CLEAR
Note 1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.
2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.
FIGURE 6-7: CLOCK SWITCH (CSWHOLD = 1)

OSCCON1
WRITTEN
OSC #1 OSC #2
ORDY
NOSCR
NOTE 1
CSWIF
USER
CSWHOLD CLEAR
Note 1: CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.

PIC16(L)F18857/77
FIGURE 6-8: CLOCK SWITCH ABANDONED
OSCCON1 OSCCON1
WRITTEN WRITTEN
OSC #1
ORDY NOTE 2
NOSCR
NOTE 1
CSWIF
CSWHOLD
Note 1: CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared.
2: ORDY = 0 if OSCCON1 does not match OSCCON2; a new switch will begin.

PIC16(L)F18857/77
6.4 Fail-Safe Clock Monitor 6.4.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset,
to continue operating should the external oscillator fail. executing a SLEEP instruction or changing the NOSC
The FSCM is enabled by setting the FCMEN bit in the and NDIV bits of the OSCCON1 register. When
Configuration Words. The FSCM is applicable to all switching to the external oscillator or PLL, the OST is
external Oscillator modes (LP, XT, HS, EC and restarted. While the OST is running, the device
Secondary Oscillator). continues to operate from the INTOSC selected in
OSCCON1. When the OST times out, the Fail-Safe
condition is cleared after successfully switching to the
FIGURE 6-9: FSCM BLOCK DIAGRAM
external clock source. The OSFIF bit should be cleared
Clock Monitor prior to switching to the external clock source. If the
Latch Fail-Safe condition still exists, the OSFIF flag will again
External become set by hardware.
S Q
Clock
LFINTOSC
÷ 64 R Q
Oscillator
31 kHz 488 Hz
(~32 s) (~2 ms)
Sample Clock Clock

Failure
Detected
6.4.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 6-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
6.4.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the
device clock to the HFINTOSC at 1 MHz clock
frequency and sets the bit flag OSFIF of the PIR1
register. Setting this flag will generate an interrupt if the
OSFIE bit of the PIE1 register is also set. The device
firmware can then take steps to mitigate the problems
that may arise from a failed clock. The system clock will
continue to be sourced from the internal clock source
until the device firmware successfully restarts the
external oscillator and switches back to external
operation, by writing to the NOSC and NDIV bits of the
OSCCON1 register.

PIC16(L)F18857/77
6.4.4 RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC
Clock modes so that the FSCM will be active as soon
as the Reset or wake-up has completed. Therefore, the
device will always be executing code while the OST is
operating.
FIGURE 6-10: FSCM TIMING DIAGRAM
Sample Clock
System Oscillator
Clock Failure
Output
Clock Monitor Output

(Q)
Failure
Detected
OSCFIF
Test Test Test
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.

PIC16(L)F18857/77
6.5 Register Definitions: Oscillator Control
REGISTER 6-1: OSCCON1: OSCILLATOR CONTROL REGISTER1

U-0 R/W-f/f(1) R/W-f/f(1) R/W-f/f(1) R/W-q/q R/W-q/q R/W-q/q R/W-q/q
(2,3)
— NOSC<2:0> NDIV<3:0>(2,3,4)
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared f = determined by fuse setting

bit 6-4 NOSC<2:0>: New Oscillator Source Request bits
The setting requests a source oscillator and PLL combination per Table 6-1.
POR value = RSTOSC (Register 4-1).
bit 3-0 NDIV<3:0>: New Divider Selection Request bits
The setting determines the new postscaler division ratio per Table 6-1.
Note 1: The default value (f/f) is set equal to the RSTOSC Configuration bits.
2: If NOSC is written with a reserved value (Table 6-1), the operation is ignored and neither NOSC nor NDIV
is written.
3: When CSWEN = 0, this register is read-only and cannot be changed from the POR value.
4: When NOSC = 110 (HFINTOSC 4 MHz), the NDIV bits will default to ‘0010’ upon Reset; for all other
NOSC settings the NDIV bits will default to ‘0000’ upon Reset.
REGISTER 6-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2

U-0 R-n/n(2) R-n/n(2) R-n/n(2) R-n/n(2) R-n/n(2) R-n/n(2) R-n/n(2)
— COSC<2:0> CDIV<3:0>
bit 7 bit 0
Legend:

bit 6-4 COSC<2:0>: Current Oscillator Source Select bits (read-only)
Indicates the current source oscillator and PLL combination per Table 6-1.
bit 3-0 CDIV<3:0>: Current Divider Select bits (read-only)
Indicates the current postscaler division ratio per Table 6-1.
Note 1: The POR value is the value present when user code execution begins.
2: The reset value (n/n) is the same as the NOSC/NDIV bits.

PIC16(L)F18857/77
TABLE 6-1: NOSC/COSC BIT SETTINGS TABLE 6-2: NDIV/CDIV BIT SETTINGS
NOSC<2:0>/ NDIV<3:0>/
Clock Source Clock divider
COSC<2:0> CDIV<3:0>
111 EXTOSC(1) 1111-1010 Reserved
110 HFINTOSC(2) 1001 512
101 LFINTOSC 1000 256
100 SOSC 0111 128
011 Reserved (it operates like 0110 64
NOSC = 110) 0101 32
010 EXTOSC with 4x PLL(1) 0100 16
001 HFINTOSC with 2x PLL(2) 0011 8
000 Reserved (it operates like 0010 4
NOSC = 110)
0001 2
Note 1: EXTOSC configured by the FEXTOSC bits of
0000 1
Configuration Word 1 (Register 4-1).
2: HFINTOSC settings are configured with the
HFFRQ bits of the OSCFRQ register
(Register 6-6).
REGISTER 6-3: OSCCON3: OSCILLATOR CONTROL REGISTER 3

R/W/HC-0/0 R/W-0/0 U-0 R-0/0 R-0/0 U-0 U-0 U-0
CSWHOLD SOSCPWR — ORDY NOSCR — — —
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
bit 7 CSWHOLD: Clock Switch Hold bit

1 = Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready
0 = Clock switch may proceed when the oscillator selected by NOSC is ready; if this bit
is clear at the time that NOSCR becomes ‘1’, the switch will occur
bit 6 SOSCPWR: Secondary Oscillator Power Mode Select bit
1 = Secondary oscillator operating in High-power mode
0 = Secondary oscillator operating in Low-power mode
bit 5 Unimplemented: Read as ‘0’.
bit 4 ORDY: Oscillator Ready bit (read-only)
1 = OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC
0 = A clock switch is in progress
bit 3 NOSCR: New Oscillator is Ready bit (read-only)
1 = A clock switch is in progress and the oscillator selected by NOSC indicates a “ready” condition
0 = A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready

PIC16(L)F18857/77
REGISTER 6-4: OSCSTAT: OSCILLATOR STATUS REGISTER 1
R-q/q R-0/q R-0/q R-0/q R-q/q R-q/q U-0 R-q/q
EXTOR HFOR MFOR LFOR SOR ADOR — PLLR
bit 7 bit 0
Legend:
bit 7 EXTOR: EXTOSC (external) Oscillator Ready bit

1 = The oscillator is ready to be used
0 = The oscillator is not enabled, or is not yet ready to be used.
bit 6 HFOR: HFINTOSC Oscillator Ready bit
bit 5 MFOR: MFINTOSC Oscillator Ready bit
0 = The oscillator is not enabled, or is not yet ready to be used
bit 4 LFOR: LFINTOSC Oscillator Ready bit
bit 3 SOR: Secondary (Timer1) Oscillator Ready bit
bit 2 ADOR: FRC Oscillator Ready bit
0 = The oscillator is not enabled, or is not yet ready to be used
bit 0 PLLR: PLL is Ready bit
1 = The PLL is ready to be used
0 = The PLL is not enabled, the required input source is not ready, or the PLL is not locked.

PIC16(L)F18857/77
REGISTER 6-5: OSCEN: OSCILLATOR MANUAL ENABLE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0
EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN — —
bit 7 bit 0
Legend:
bit 7 EXTOEN: External Oscillator Manual Request Enable bit(1)

1 = EXTOSC is explicitly enabled, operating as specified by FEXTOSC
0 = EXTOSC could be enabled by another module
bit 6 HFOEN: HFINTOSC Oscillator Manual Request Enable bit
1 = HFINTOSC is explicitly enabled, operating as specified by OSCFRQ
0 = HFINTOSC could be enabled by another module
bit 5 MFOEN: MFINTOSC Oscillator Manual Request Enable bit
1 = MFINTOSC is explicitly enabled
0 = MFINTOSC could be enabled by another module
bit 4 LFOEN: LFINTOSC (31 kHz) Oscillator Manual Request Enable bit
1 = LFINTOSC is explicitly enabled
0 = LFINTOSC could be enabled by another module
bit 3 SOSCEN: Secondary (Timer1) Oscillator Manual Request bit
1 = Secondary oscillator is explicitly enabled, operating as specified by SOSCPWR
0 = Secondary oscillator could be enabled by another module
bit 2 ADOEN: FRC Oscillator Manual Request Enable bit
1 = FRC is explicitly enabled
0 = FRC could be enabled by another module

PIC16(L)F18857/77
REGISTER 6-6: OSCFRQ: HFINTOSC FREQUENCY SELECTION REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-q/q R/W-q/q R/W-q/q
— — — — — HFFRQ<2:0>(1)
bit 7 bit 0
Legend:

bit 2-0 HFFRQ<2:0>: HFINTOSC Frequency Selection bits
Nominal Freq (MHz) (NOSC = 110):
111 = Reserved
110 = 32
101 = 16
100 = 12
011 = 8
010 = 4
001 = 2
000 = 1
Note 1: When RSTOSC=110 (HFINTOSC 1 MHz), the HFFRQ bits will default to ‘010’ upon Reset; when RSTOSC = 000
(HFINTOSC 32 MHz), the HFFRQ bits will default to ‘110’ upon Reset.

PIC16(L)F18857/77
REGISTER 6-7: OSCTUNE: HFINTOSC TUNING REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — HFTUN<5:0>
bit 7 bit 0
Legend:
bit 7-6 Unimplemented: Read as ‘0’.

bit 5-0 HFTUN<5:0>: HFINTOSC Frequency Tuning bits
10 0000 = Minimum frequency
•
•
•
10 0001
00 0000 = Center frequency. Oscillator module is running at the calibrated frequency (default value).
01 1111
•
•
•
01 1111 = Maximum frequency

PIC16(L)F18857/77
TABLE 6-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Register
on Page
OSCCON1 — NOSC<2:0> NDIV<3:0> 121

OSCCON2 — COSC<2:0> CDIV<3:0> 121
OSCCON3 CWSHOLD SOSCPWR — ORDY NOSCR — — — 122
OSCFRQ — — — — — HFFRQ<2:0> 125
OSCSTAT EXTOR HFOR MFOR LFOR SOR ADOR — PLLR 123
OSCTUNE — — HFTUN<5:0> 126
OSCEN EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN — — 124
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 6-4: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page
13:8 — — FCMEN — CSWEN — — CLKOUTEN

CONFIG1 92
7:0 — RSTOSC<2:0> — FEXTOSC<2:0>

PIC16(L)F18857/77
7.0 INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.
FIGURE 7-1: INTERRUPT LOGIC

Rev. 10-000010A
1/13/2014
TMR0IF Wake-up
TMR0IE (If in Sleep mode)
INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF
(TMR1IE) PIE1<0> Interrupt
IOCIE to CPU
PEIE
PIRn<7>
GIE
PIEn<7>

PIC16(L)F18857/77
7.1 Operation 7.2 Interrupt Latency
Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the
are enabled by setting the following bits: interrupt event occurs to the time code execution at the
• GIE bit of the INTCON register interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
• Interrupt Enable bit(s) for the specific interrupt
asynchronous interrupts, the latency is three to five
event(s)
instruction cycles, depending on when the interrupt
• PEIE bit of the INTCON register (if the Interrupt occurs. See Figure 7-2 and Figure 7-3 for more details.
Enable bit of the interrupt event is contained in the
PIEx registers)
The PIR1, PIR2, PIR3 and PIR4 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See “Section 7.5 “Automatic
Context Saving”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.

PIC16(L)F18857/77
FIGURE 7-2: INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR Interrupt Sampled

during Q1
Interrupt
GIE
PC PC-1 PC PC+1 0004h 0005h
Execute 1 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)
Interrupt
GIE
PC+1/FSR New PC/

PC PC-1 PC 0004h 0005h
ADDR PC+1
Execute 2 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)
Interrupt
GIE
PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h
Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h)
Interrupt
GIE
PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h
Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h)

PIC16(L)F18857/77
FIGURE 7-3: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1) (2)
INTF (5) Interrupt Latency
GIE
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Instruction Inst (0004h)

Inst (PC – 1) Inst (PC) Forced NOP Forced NOP
Executed
Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT not available in all oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 37.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.

PIC16(L)F18857/77
7.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 8.0
“Power-Saving Operation Modes” for more details.
7.4 INT Pin

The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the PIE0 register. The INTEDG bit
of the INTCON register determines on which edge the
interrupt will occur. When the INTEDG bit is set, the
rising edge will cause the interrupt. When the INTEDG
bit is clear, the falling edge will cause the interrupt. The
INTF bit of the PIR0 register will be set when a valid
edge appears on the INT pin. If the GIE and INTE bits
are also set, the processor will redirect program
execution to the interrupt vector.
7.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these
registers are automatically restored. Any modifications
to these registers during the ISR will be lost. If
modifications to any of these registers are desired, the
corresponding shadow register should be modified and
the value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.

PIC16(L)F18857/77
7.6 Register Definitions: Interrupt Control
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 U-0 R/W-1/1
GIE PEIE — — — — — INTEDG
bit 7 bit 0
Legend:
bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 0 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.

PIC16(L)F18857/77
REGISTER 7-2: PIE0: PERIPHERAL INTERRUPT ENABLE REGISTER 0

U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
— — TMR0IE IOCIE — — — INTE
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 IOCIE: Interrupt-on-Change Interrupt Enable bit
1 = Enables the IOC change interrupt
0 = Disables the IOC change interrupt
bit 0 INTE: INT External Interrupt Flag bit(1)
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
Note 1: The External Interrupt GPIO pin is selected by INTPPS (Register 13-1).
Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt
controlled by PIE1-PIE8. Interrupt sources
controlled by the PIE0 register do not
require PEIE to be set in order to allow
interrupt vectoring (when GIE is set).

PIC16(L)F18857/77
R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
OSFIE CSWIE — — — — ADTIE ADIE
bit 7 bit 0
Legend:
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail Interrupt
0 = Disables the Oscillator Fail Interrupt
bit 6 CSWIE: Clock Switch Complete Interrupt Enable bit
1 = The clock switch module interrupt is enabled
0 = The clock switch module interrupt is disabled
bit 1 ADTIE: Analog-to-Digital Converter (ADC) Threshold Compare Interrupt Enable bit
1 = Enables the ADC threshold compare interrupt
0 = Disables the ADC threshold compare interrupt
bit 0 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers
PIE1-PIE8.

PIC16(L)F18857/77

U-0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— ZCDIE — — — — C2IE C1IE
bit 7 bit 0
Legend:

bit 6 ZCDIE: Zero-Cross Detection (ZCD) Interrupt Enable bit
1 = Enables the ZCD interrupt
0 = Disables the ZCD interrupt
bit 1 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 0 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt

controlled by registers PIE1-PIE8.

PIC16(L)F18857/77

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — RCIE TXIE BCL2IE SSP2IE BCL1IE SSP1IE
bit 7 bit 0
Legend:

bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Enables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 BCL2IE: MSSP2 Bus Collision Interrupt Enable bit
1 = MSSP bus Collision interrupt enabled
0 = MSSP bus Collision interrupt disabled
bit 2 SSP2IE: Synchronous Serial Port (MSSP2) Interrupt Enable bit
1 = MSSP bus collision Interrupt
0 = Disables the MSSP Interrupt
bit 1 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit
1 = MSSP bus collision interrupt enabled
0 = MSSP bus collision interrupt disabled
bit 0 SSP1IE: Synchronous Serial Port (MSSP1) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt

controlled by PIE1-PIE8.

PIC16(L)F18857/77

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE
bit 7 bit 0
Legend:

bit 5 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the Timer6 to PR6 match interrupt
0 = Disables the Timer6 to PR6 match interrupt
bit 4 TMR5IE: Timer5 Overflow Interrupt Enable bit
1 = Enables the Timer5 overflow interrupt
0 = Disables the Timer5 overflow interrupt
bit 2 TMR3IE: TMR3 Overflow Interrupt Enable bit
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit


PIC16(L)F18857/77

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
CLC4IE CLC3IE CLC2IE CLC1IE — TMR5GIE TMR3GIE TMR1GIE
bit 7 bit 0
Legend:
bit 7 CLC4IE: CLC4 Interrupt Enable bit

1 = CLC4 interrupt enabled
0 = CLC4 interrupt disabled
bit 2 TMR5GIE: Timer5 Gate Interrupt Enable bit
1 = Enables the Timer5 gate acquisition interrupt
0 = Disables the Timer5 gate acquisition interrupt


PIC16(L)F18857/77

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — CCP5IE CCP4IE CCP3IE CCP2IE CCP1IE
bit 7 bit 0
Legend:

bit 4 CCP5IE: CCP5 Interrupt Enable bit
1 = CCP5 interrupt is enabled
0 = CCP5 interrupt is disabled


PIC16(L)F18857/77

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
SCANIE CRCIE NVMIE NCO1IE — CWG3IE CWG2IE CWG1IE
bit 7 bit 0
Legend:
bit 7 SCANIE: Scanner Interrupt Enable bit

1 = Enables the scanner interrupt
0 = Disables the scanner interrupt
bit 6 CRCIE: CRC Interrupt Enable bit
1 = Enables the CRC interrupt
0 = Disables the CRC interrupt
bit 5 NVMIE: NVM Interrupt Enable bit
1 = NVM task complete interrupt enabled
0 = NVM interrupt not enabled
bit 4 NCO1IE: NCO Interrupt Enable bit
1 = NCO rollover interrupt enabled
0 = NCO rollover interrupt disabled
bit 3 Unimplemented: Read as ‘0’.
bit 2 CWG3IE: Complementary Waveform Generator (CWG) 3 Interrupt Enable bit
1 = CWG3 interrupt enabled
0 = CWG3 interrupt disabled
1 = CWG2 interrupt is enabled
1 = CWG1 interrupt is enabled


PIC16(L)F18857/77

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE
bit 7 bit 0
Legend:

bit 6 SMT2PWAIE: SMT2 Pulse-Width Acquisition Interrupt Enable bit
1 = Enables the SMT acquisition interrupt
0 = Disables the SMT acquisition interrupt
bit 5 SMT2PRAIE: SMT2 Period Acquisition Interrupt Enable bit
bit 4 SMT2IE: SMT2 Overflow Interrupt Enable bit
1 = Enables the SMT overflow interrupt
0 = Disables the SMT overflow interrupt
bit 2 SMT1PWAIE: SMT1 Pulse-Width Acquisition Interrupt Enable bit
bit 1 SMT1PRAIE: SMT1 Period Acquisition Interrupt Enable bit
bit 0 SMT1IE: SMT1 Overflow Interrupt Enable bit
1 = Enables the SMT overflow interrupt
0 = Disables the SMT overflow interrupt


PIC16(L)F18857/77
REGISTER 7-11: PIR0: PERIPHERAL INTERRUPT STATUS REGISTER 0

U-0 U-0 R/W/HS-0/0 R-0 U-0 U-0 U-0 R/W/HS-0/0
— — TMR0IF IOCIF — — — INTF(1)
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS= Hardware Set

bit 5 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 4 IOCIF: Interrupt-on-Change Interrupt Flag bit (read-only)(2)
1 = One or more of the IOCAF-IOCEF register bits are currently set, indicating an enabled edge was
detected by the IOC module.
0 = None of the IOCAF-IOCEF register bits are currently set
bit 0 INTF: INT External Interrupt Flag bit(1)
1 = The INT external interrupt occurred (must be cleared in software)
0 = The INT external interrupt did not occur
Note 1: The External Interrupt GPIO pin is selected by INTPPS (Register 13-1).
2: The IOCIF bits are the logical OR of all the IOCAF-IOCEF flags. Therefore, to clear the IOCIF flag,
application firmware should clear all of the lower level IOCAF-IOCEF register bits.


PIC16(L)F18857/77
REGISTER 7-12: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0
OSFIF CSWIF — — — — ADTIF ADIF
bit 7 bit 0
Legend:
bit 7 OSFIF: Oscillator Fail-Safe Interrupt Flag bit

1 = Oscillator fail-safe interrupt has occurred (must be cleared in software)
0 = No oscillator fail-safe interrupt
bit 6 CSWIF: Clock Switch Complete Interrupt Flag bit
1 = The clock switch module indicates an interrupt condition (must be cleared in software)
0 = The clock switch does not indicate an interrupt condition
bit 1 ADTIF: Analog-to-Digital Converter (ADC) Threshold Compare Interrupt Flag bit
1 = An A/D measurement was beyond the configured threshold (must be cleared in software)
0 = A/D measurements have been within the configured threshold
bit 0 ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit
1 = An A/D conversion or complex operation has completed (must be cleared in software)
0 = An A/D conversion or complex operation is not complete


PIC16(L)F18857/77
U-0 R/W/HS-0/0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0
— ZCDIF — — — — C2IF C1IF
bit 7 bit 0
Legend:

bit 6 ZCDIF: Zero-Cross Detect (ZCD) Interrupt Flag bit
1 = An enabled rising and/or falling ZCD event has been detected (must be cleared in software)
0 = No ZCD event has occurred
bit 1 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator 2 interrupt asserted (must be cleared in software)
0 = Comparator 2 interrupt not asserted
bit 0 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator 1 interrupt asserted (must be cleared in software)
0 = Comparator 1 interrupt not asserted


PIC16(L)F18857/77
U-0 U-0 R-0 R-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — RCIF TXIF BCL2IF SSP2IF BCL1IF SSP1IF
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware clearable

bit 5 RCIF: EUSART Receive Interrupt Flag (read-only) bit (1)
1 = The EUSART receive buffer is not empty (contains at least one byte)
0 = The EUSART receive buffer is empty
bit 4 TXIF: EUSART Transmit Interrupt Flag (read-only) bit(2)
1 = The EUSART transmit buffer contains at least one unoccupied space
0 = The EUSART transmit buffer is currently full. The application firmware should not write to TXREG
again, until more room becomes available in the transmit buffer.
bit 3 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1 = A bus collision was detected (must be cleared in software)
0 = No bus collision was detected
bit 2 SSP2IF: Synchronous Serial Port (MSSP2) Interrupt Flag bit
1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 = Waiting for the Transmission/Reception/Bus Condition in progress
bit 1 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit
1 = A bus collision was detected (must be cleared in software)
0 = No bus collision was detected
bit 0 SSP1IF: Synchronous Serial Port (MSSP1) Interrupt Flag bit
1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 = Waiting for the Transmission/Reception/Bus Condition in progress
Note 1: The RCIF flag is a read-only bit. To clear the RCIF flag, the firmware must read from RCREG enough
times to remove all bytes from the receive buffer.
2: The TXIF flag is a read-only bit, indicating if there is room in the transmit buffer. To clear the TXIF flag, the
firmware must write enough data to TXREG to completely fill all available bytes in the buffer. The TXIF flag
does not indicate transmit completion (use TRMT for this purpose instead).


PIC16(L)F18857/77
U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF
bit 7 bit 0
Legend:

bit 5 TRM6IF: Timer6 Interrupt Flag bit
1 = The TMR6 postscaler overflowed, or in 1:1 mode, a TMR6 to PR6 match occurred (must be cleared
in software)
0 = No TMR6 event has occurred
bit 4 TRM5IF: Timer5 Overflow Interrupt Flag bit
1 = TMR5 overflow occurred (must be cleared in software)
0 = No TMR5 overflow occurred
in software)
in software)

PIC16(L)F18857/77

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
CLC4IF CLC3IF CLC2IF CLC1IF — TMR5GIF TMR3GIF TMR1GIF
bit 7 bit 0
Legend:
bit 7 CLC4IF: CLC4 Interrupt Flag bit

1 = A CLC4OUT interrupt condition has occurred (must be cleared in software)
0 = No CLC4 interrupt event has occurred
bit 2 TMR5GIF: Timer5 Gate Interrupt Flag bit
1 = The Timer5 Gate has gone inactive (the gate is closed)
0 = The Timer5 Gate has not gone inactive


PIC16(L)F18857/77

U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — — CCP5IF CCP4IF CCP3IF CCP2IF CCP1IF
bit 7 bit 0
Legend:

bit 4 CCP5IF: CCP5 Interrupt Flag bit
CCPM Mode
Value
Capture Compare PWM
Capture occurred Compare match occurred Output trailing edge occurred
1
(must be cleared in software) (must be cleared in software) (must be cleared in software)
0 Capture did not occur Compare match did not occur Output trailing edge did not occur

CCPM Mode
Value
Capture Compare PWM
1

CCPM Mode
Value
Capture Compare PWM
1

CCPM Mode
Value
Capture Compare PWM
1

CCPM Mode
Value
Capture Compare PWM
1


PIC16(L)F18857/77

U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — — CCP5IF CCP4IF CCP3IF CCP2IF CCP1IF
bit 7 bit 0
Legend:

CCP5IF = 1:
Capture mode: Capture occurred (must be cleared in software)
Compare mode: Compare match occurred (must be cleared in software)
PWM mode: Output trailing edge occurred (must be cleared in software)
CCP5IF = 0:
Capture mode: Capture did not occur
Compare mode: Compare match did not occur
PWM mode: Output trailing edge did not occur
CCP4IF = 1:
CCP4IF = 0:
CCP3IF = 1:
CCP3IF = 0:
CCP2IF = 1:
CCP2IF = 0:
CCP1IF = 1:
CCP1IF = 0:

PIC16(L)F18857/77

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
SCANIF CRCIF NVMIF NCO1IF — CWG3IF CWG2IF CWG1IF
bit 7 bit 0
Legend:
bit 7 SCANIF: Program Memory Scanner Interrupt Flag bit

1 = The operation has completed (a SCANGO 1 to 0 transition has occurred)
0 = No operation is pending or the operation is still in progress
bit 6 CRCIF: CRC Interrupt Flag bit
1 = The operation has completed (a BUSY 1 to 0 transition has occurred)
0 = No operation is pending or the operation is still in progress
bit 5 NVMIF: Non-Volatile Memory (NVM) Interrupt Flag bit
1 = The requested NVM operation has completed
0 = NVM interrupt not asserted
bit 4 NCO1IF: Numerically Controlled Oscillator (NCO) Interrupt Flag bit
1 = The NCO has rolled over
bit 2 CWG3IF: CWG3 Interrupt Flag bit
1 = CWG3 has gone into shutdown
0 = CWG3 is operating normally, or interrupt cleared


PIC16(L)F18857/77

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — SMT2PWAIF SMT2PRAIF SMT2IF SMT1PWAIF SMT1PRAIF SMT1IF
bit 7 bit 0
Legend:

bit 5 SMT2PWAIF: SMT2 Pulse Width Acquisition Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 SMT2PRAIF: SMT2 Period Acquisition Interrupt Flag bit
bit 3 SMT2IF: SMT2 Overflow Interrupt Flag bit
1 = An SMT overflow event has occurred (must be cleared in software)
0 = No overflow event detected
bit 2 SMT1PWAIF: SMT1 Pulse Width Acquisition Interrupt Flag bit
bit 1 SMT1PRAIF: SMT1 Period Acquisition Interrupt Flag bit
bit 0 SMT1IF: SMT1 Overflow Interrupt Flag bit
1 = An SMT overflow event has occurred (must be cleared in software)
0 = No overflow event detected


PIC16(L)F18857/77
TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
on Page
INTCON GIE PEIE — — — — — INTEDG 133

PIE0 — — TMR0IE IOCIE — — — INTE 134
PIE1 OSFIE CSWIE — — — — ADTIE ADIE 135
PIE2 — ZCDIE — — — — C2IE C1IE 136
PIE3 — — RCIE TXIE BCL2IE SSP2IE BCL1IE SSP1IE 137
PIE4 — — TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE 138
PIE5 CLC4IE CLC3IE CLC2IE CLC1IE — TMR5GIE TMR3GIE TMR1GIE 139
PIE6 — — — CCP5IE CCP4IE CCP3IE CCP2IE CCP1IE 140
PIE7 SCANIE CRCIE NVMIE NCO1IE — CWG3IE CWG2IE CWG1IE 141
PIE8 — — SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE 142
PIR0 — — TMR0IF IOCIF — — — INTF 143
PIR1 OSFIF CSWIF — — — — ADTIF ADIF 144
PIR2 — ZCDIF — — — — C2IF C1IF 145
PIR3 — — RCIF TXIF BCL2IF SSP2IF BCL1IF SSP1IF 146
PIR4 — — TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF 147
PIR5 CLC4IF CLC3IF CLC2IF CLC1IF — TMR5GIF TMR3GIF TMR1GIF 148
PIR6 — — — CCP5IF CCP4IF CCP3IF CCP2IF CCP1IF 149
PIR7 SCANIF CRCIF NVMIF NCO1IF — CWG3IF CWG2IF CWG1IF 151
PIR8 — — SMT2PWAIF SMT2PRAIF SMT2IF SMT1PWAIF SMT1PRAIF SMT1IF 152
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.

PIC16(L)F18857/77
8.0 POWER-SAVING OPERATION operate, while only the CPU and PFM are affected. The
reduced execution saves power by eliminating
MODES
unnecessary operations within the CPU and memory.
The purpose of the Power-Down modes is to reduce When the Doze Enable (DOZEN) bit is set (DOZEN =
power consumption. There are two Power-Down 1), the CPU executes only one instruction cycle out of
modes: DOZE mode and Sleep mode. every N cycles as defined by the DOZE<2:0> bits of the
CPUDOZE register. For example, if DOZE<2:0> = 100,
8.1 DOZE Mode the instruction cycle ratio is 1:32. The CPU and
memory execute for one instruction cycle and then lay
DOZE mode allows for power saving by reducing CPU
idle for 31 instruction cycles. During the unused cycles,
operation and program memory (PFM) access, without
the peripherals continue to operate at the system clock
affecting peripheral operation. DOZE mode differs from
speed.
Sleep mode because the system oscillators continue to
FIGURE 8-1: DOZE MODE OPERATION EXAMPLE

System
Clock
1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
/ŶƐƚƌƵĐƚŝŽŶ
WĞƌŝŽĚ 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4 4
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
CPU Clock
PFM Op’s Fetch Fetch Push 0004h Fetch Fetch
CPU Op’s Exec Exec Exec(1,2) NOP Exec Exec Exec
Interrupt
Here
(ROI = 1)
Note 1: Multi-cycle instructions are executed to completion before fetching 0004h.
2: If the pre-fetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed.
8.1.1 DOZE OPERATION

The Doze operation is illustrated in Figure 8-1. For this
example:
• Doze enable (DOZEN) bit set (DOZEN = 1)
• DOZE<2:0> = 001 (1:4) ratio
• Recover-on-Interrupt (ROI) bit set (ROI = 1)
As with normal operation, the PFM fetches for the next
instruction cycle. The Q-clocks to the peripherals
continue throughout.

PIC16(L)F18857/77
8.1.2 INTERRUPTS DURING DOZE To minimize current consumption, the following
conditions should be considered:
If an interrupt occurs and the Recover-On-Interrupt bit
is clear (ROI = 0) at the time of the interrupt, the - I/O pins should not be floating
Interrupt Service Routine (ISR) continues to execute at - External circuitry sinking current from I/O pins
the rate selected by DOZE<2:0>. Interrupt latency is - Internal circuitry sourcing current from I/O
extended by the DOZE<2:0> ratio. pins
- Current draw from pins with internal weak
If an interrupt occurs and the ROI bit is set (ROI = 1) at
pull-ups
the time of the interrupt, the DOZEN bit is cleared and
- Modules using any oscillator
the CPU executes at full speed. The prefetched instruc-
tion is executed and then the interrupt vector sequence I/O pins that are high-impedance inputs should be
is executed. In Figure 8-1, the interrupt occurs during pulled to VDD or VSS externally to avoid switching
the 2nd instruction cycle of the Doze period, and imme- currents caused by floating inputs.
diately brings the CPU out of Doze. If the Doze-On-Exit Examples of internal circuitry that might be sourcing
(DOE) bit is set (DOE = 1) when the RETFIE operation current include modules such as the DAC and FVR
is executed, DOZEN is set, and the CPU executes at modules. See Section 25.0 “5-Bit Digital-to-Analog
the reduced rate based on the DOZE<2:0> ratio. Converter (DAC1) Module” and 16.0 “Fixed Voltage
Reference (FVR)” for more information on these
8.2 Sleep Mode modules.
Sleep mode is entered by executing the SLEEP 8.2.1 WAKE-UP FROM SLEEP
instruction, while the Idle Enable (IDLEN) bit of the
CPUDOZE register is clear (IDLEN = 0). If the SLEEP The device can wake-up from Sleep through one of the
instruction is executed while the IDLEN bit is set following events:
(IDLEN = 1), the CPU will enter the IDLE mode 1. External Reset input on MCLR pin, if enabled.
(Section 8.2.3 “Low-Power Sleep Mode”). 2. BOR Reset, if enabled.
Upon entering Sleep mode, the following conditions 3. POR Reset.
exist: 4. Watchdog Timer, if enabled.
1. WDT will be cleared but keeps running if 5. Any external interrupt.
enabled for operation during Sleep 6. Interrupts by peripherals capable of running
2. The PD bit of the STATUS register is cleared during Sleep (see individual peripheral for more
3. The TO bit of the STATUS register is set information).
4. The CPU clock is disabled The first three events will cause a device Reset. The
5. 31 kHz LFINTOSC, HFINTOSC and SOSC are last three events are considered a continuation of
unaffected and peripherals using them may program execution. To determine whether a device
continue operation in Sleep. Reset or wake-up event occurred, refer to Section 5.11
6. Timer1 and peripherals that use it continue to “Determining the Cause of a Reset”.
operate in Sleep when the Timer1 clock source When the SLEEP instruction is being executed, the next
selected is: instruction (PC + 1) is prefetched. For the device to
• LFINTOSC wake-up through an interrupt event, the corresponding
• T1CKI interrupt enable bit must be enabled. Wake-up will
• Secondary Oscillator occur regardless of the state of the GIE bit. If the GIE
7. ADC is unaffected if the dedicated FRC bit is disabled, the device continues execution at the
oscillator is selected instruction after the SLEEP instruction. If the GIE bit is
8. I/O ports maintain the status they had before enabled, the device executes the instruction after the
Sleep was executed (driving high, low, or SLEEP instruction, the device will then call the Interrupt
high-impedance) Service Routine. In cases where the execution of the
9. Resets other than WDT are not affected by instruction following SLEEP is not desirable, the user
Sleep mode should have a NOP after the SLEEP instruction.
Refer to individual chapters for more details on The WDT is cleared when the device wakes-up from
peripheral operation during Sleep. Sleep, regardless of the source of wake-up.

PIC16(L)F18857/77
8.2.2 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the
execution of a SLEEP instruction
When global interrupts are disabled (GIE cleared) and
any interrupt source, with the exception of the clock - SLEEP instruction will be completely
switch interrupt, has both its interrupt enable bit and executed
interrupt flag bit set, one of the following will occur: - Device will immediately wake-up from Sleep
• If the interrupt occurs before the execution of a - WDT and WDT prescaler will be cleared
SLEEP instruction - TO bit of the STATUS register will be set
- SLEEP instruction will execute as a NOP - PD bit of the STATUS register will be cleared
- WDT and WDT prescaler will not be cleared Even if the flag bits were checked before executing a
- TO bit of the STATUS register will not be set SLEEP instruction, it may be possible for flag bits to
- PD bit of the STATUS register will not be become set before the SLEEP instruction completes. To
cleared determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
FIGURE 8-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2) TOST(3)
Interrupt flag Interrupt Latency (4)
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)
Note 1: External clock. High, Medium, Low mode assumed.

2: CLKOUT is shown here for timing reference.
3: TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes.
4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
8.2.3 LOW-POWER SLEEP MODE 8.2.3.1 Sleep Current vs. Wake-up Time
The PIC16F18857/77 device contains an internal Low In the default operating mode, the LDO and reference
Dropout (LDO) voltage regulator, which allows the circuitry remain in the normal configuration while in
device I/O pins to operate at voltages up to 5.5V while Sleep. The device is able to exit Sleep mode quickly
the internal device logic operates at a lower voltage. since all circuits remain active. In Low-Power Sleep
The LDO and its associated reference circuitry must mode, when waking-up from Sleep, an extra delay time
remain active when the device is in Sleep mode. is required for these circuits to return to the normal
The PIC16F18857/77 allows the user to optimize the configuration and stabilize.
operating current in Sleep, depending on the The Low-Power Sleep mode is beneficial for
application requirements. applications that stay in Sleep mode for long periods of
time. The Normal mode is beneficial for applications
Low-Power Sleep mode can be selected by setting the
that need to wake from Sleep quickly and frequently.
VREGPM bit of the VREGCON register. Depending on
the configuration of these bits, the LDO and reference
circuitry are placed in a low-power state when the
device is in Sleep.

PIC16(L)F18857/77
8.2.3.2 Peripheral Usage in Sleep 8.2.4.2 Idle and WDT
Some peripherals that can operate in Sleep mode will When in Idle, the WDT Reset is blocked and will
not operate properly with the Low-Power Sleep mode instead wake the device. The WDT wake-up is not an
selected. The Low-Power Sleep mode is intended for interrupt, therefore ROI does not apply.
use with these peripherals:
• Brown-out Reset (BOR)
Note: The WDT can bring the device out of Idle,
• Watchdog Timer (WDT)
in the same way it brings the device out of
• External interrupt pin/interrupt-on-change pins
Sleep. The DOZEN bit is not affected.
• Timer1 (with external clock source)
It is the responsibility of the end user to determine what
is acceptable for their application when setting the
VREGPM settings in order to ensure operation in
Sleep.
Note: The PIC16LF18857/77 does not have a

configurable Low-Power Sleep mode.
PIC16LF18857/77 is an unregulated
device and is always in the lowest power
state when in Sleep, with no wake-up time
penalty. This device has a lower maximum
VDD and I/O voltage than the
PIC16F18857/77. See Section 37.0
“Electrical Specifications” for more
information.
8.2.4 IDLE MODE

When the Idle Enable (IDLEN) bit is clear (IDLEN = 0),
the SLEEP instruction will put the device into full Sleep
mode (see Section 8.2 “Sleep Mode”). When IDLEN
is set (IDLEN = 1), the SLEEP instruction will put the
device into IDLE mode. In IDLE mode, the CPU and
memory operations are halted, but the peripheral
clocks continue to run. This mode is similar to DOZE
mode, except that in IDLE both the CPU and PFM are
shut off.
Note: Peripherals using FOSC will continue

running while in Idle (but not in Sleep).
Peripherals using HFINTOSC,
LFINTOSC, or SOSC will continue
running in both Idle and Sleep.
Note: If CLKOUT is enabled (CLKOUT = 0,

Configuration Word 1), the output will
continue operating while in Idle.
8.2.4.1 Idle and Interrupts

IDLE mode ends when an interrupt occurs (even if GIE
= 0), but IDLEN is not changed. The device can
re-enter IDLE by executing the SLEEP instruction.
If Recover-on-Interrupt is enabled (ROI = 1), the
interrupt that brings the device out of Idle also restores
full-speed CPU execution when doze is also enabled.

PIC16(L)F18857/77
8.3 Register Definitions: Voltage Regulator and DOZE Control
REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER (1)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1
— — — — — — VREGPM Reserved
bit 7 bit 0
Legend:

bit 1 VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0 Reserved: Read as ‘1’. Maintain this bit set.
Note 1: PIC16F18857/77 only.

2: See Section 37.0 “Electrical Specifications”.

PIC16(L)F18857/77
REGISTER 8-2: CPUDOZE: DOZE AND IDLE REGISTER
R/W-0/u R/W/HC/HS-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
IDLEN DOZEN(1,2) ROI DOE — DOZE<2:0>
bit 7 bit 0
Legend:
bit 7 IDLEN: Idle Enable bit

1 = A SLEEP instruction inhibits the CPU clock, but not the peripheral clock(s)
0 = A SLEEP instruction places the device into full Sleep mode
bit 6 DOZEN: Doze Enable bit(1,2)
1 = The CPU executes instruction cycles according to DOZE setting
0 = The CPU executes all instruction cycles (fastest, highest power operation)
bit 5 ROI: Recover-on-Interrupt bit
1 = Entering the Interrupt Service Routine (ISR) makes DOZEN = 0 bit, bringing the CPU to full-speed operation.
0 = Interrupt entry does not change DOZEN
bit 4 DOE: Doze on Exit bit
1 = Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation.
0 = RETFIE does not change DOZEN
bit 2-0 DOZE<2:0>: Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles
111 = 1:256
110 = 1:128
101 = 1:64
100 = 1:32
011 = 1:16
010 = 1:8
001 = 1:4
000 = 1:2
Note 1: When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.
2: Entering ICD overrides DOZEN, returning the CPU to full execution speed; this bit is not affected.

PIC16(L)F18857/77
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Register
on Page
PIR0 — — TMR0IF IOCIF — — — INTF 143
IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 253
IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 253
IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 253
IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 255
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 254
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 254
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 254
IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 255
IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 255
IOCEP — — — — IOCEP3 — — — 256
IOCEN — — — — IOCEN3 — — — 256
IOCEF — — — — IOCEF3 — — — 257
VREGCON — — — — — — VREGPM Reserved 158
CPUDOZE IDLEN DOZEN ROI DOE — DOZE<2:0> 159
WDTCON0 — — WDTPS<4:0> SWDTEN 165
IOCEP — — — — IOCEP3 — — — 256
IOCEN — — — — IOCEN3 — — — 256
IOCEF — — — — IOCEF3 — — — 257
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.

PIC16(L)F18857/77
9.0 WINDOWED WATCHDOG
TIMER (WWDT)
The Watchdog Timer (WDT) is a system timer that
generates a Reset if the firmware does not issue a
CLRWDT instruction within the time-out period. The
Watchdog Timer is typically used to recover the system
from unexpected events. The Windowed Watchdog
Timer (WDT) differs in that CLRWDT instructions are
only accepted when they are performed within a
specific window during the time-out period.
The WDT has the following features:
• Selectable clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Configurable window size from 12.5 to 100
percent of the time-out period
• Multiple Reset conditions
• Operation during Sleep

PIC16(L)F18857/77
FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM
Rev. 10-000162B
8/21/2015
WWDT
Armed
WDT
Window
Violation
Window Closed
Window
Comparator
CLRWDT Sizes
WDTWS
RESET
Reserved 111
Reserved 110
Reserved 101
R
Reserved 100 18-bit Prescale
Reserved 011 Counter
E
Reserved 010
MFINTOSC/16 001
LFINTOSC 000
WDTCS
WDTPS
R
5-bit Overflow
WDT Time-out
WDT Counter Latch
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
WDTE<1:0> = 10
Sleep

PIC16(L)F18857/77
9.1 Independent Clock Source 9.4 Watchdog Window
The WDT can derive its time base from either the 31 The Watchdog Timer has an optional Windowed mode
kHz LFINTOSC or 31.25 kHz MFINTOSC/16 internal that is controlled by the WDTCWS<2:0> Configuration
oscillators, depending on the value of either the bits and WINDOW<2:0> bits of the WDTCON1 register.
WDTCCS<2:0> Configuration bits or the WDTCS<2:0> In the Windowed mode, the CLRWDT instruction must
bits of WDTCON1. Time intervals in this chapter are occur within the allowed window of the WDT period.
based on a minimum nominal interval of 1 ms. See Any CLRWDT instruction that occurs outside of this win-
Section 37.0 “Electrical Specifications” for dow will trigger a window violation and will cause a
LFINTOSC and MFINTOSC tolerances. WDT Reset, similar to a WDT time out. See Figure 9-2
for an example.
9.2 WDT Operating Modes The window size is controlled by the WDTCWS<2:0>
Configuration bits, or the WINDOW<2:0> bits of
The Watchdog Timer module has four operating modes
WDTCON1, if WDTCWS<2:0> = 111.
controlled by the WDTE<1:0> bits in Configuration
Words. See Table 9-1. In the event of a window violation, a Reset will be
generated and the WDTWV bit of the PCON register
9.2.1 WDT IS ALWAYS ON will be cleared. This bit is set by a POR or can be set in
When the WDTE bits of Configuration Words are set to firmware.
‘11’, the WDT is always on.
9.5 Clearing the WDT
WDT protection is active during Sleep.
The WDT is cleared when any of the following
9.2.2 WDT IS OFF IN SLEEP conditions occur:
When the WDTE bits of Configuration Words are set to • Any Reset
‘10’, the WDT is on, except in Sleep. • Valid CLRWDT instruction is executed
WDT protection is not active during Sleep. • Device enters Sleep
• Device wakes up from Sleep
9.2.3 WDT CONTROLLED BY SOFTWARE
• WDT is disabled
When the WDTE bits of Configuration Words are set to
• Oscillator Start-up Timer (OST) is running
‘01’, the WDT is controlled by the SEN bit of the
WDTCON0 register. • Any write to the WDTCON0 or WDTCON1 registers
WDT protection is unchanged by Sleep. See Table 9-1 9.5.1 CLRWDT CONSIDERATIONS
for more details. (WINDOWED MODE)
TABLE 9-1: WDT OPERATING MODES When in Windowed mode, the WDT must be armed
before a CLRWDT instruction will clear the timer. This is
Device WDT performed by reading the WDTCON0 register. Execut-
WDTE<1:0> SEN
Mode Mode ing a CLRWDT instruction without performing such an
arming action will trigger a window violation.
11 X X Active
See Table 9-2 for more information.
Awake Active
10 X
Sleep Disabled 9.6 Operation During Sleep
1 X Active When the device enters Sleep, the WDT is cleared. If
01 the WDT is enabled during Sleep, the WDT resumes
0 X Disabled
counting. When the device exits Sleep, the WDT is
00 X X Disabled cleared again.
The WDT remains clear until the OST, if enabled, com-
9.3 Time-Out Period pletes. See Section 6.0 “Oscillator Module (with Fail-
Safe Clock Monitor)” for more information on the OST.
The WDTPS bits of the WDTCON0 register set the
time-out period from 1 ms to 256 seconds (nominal). When a WDT time-out occurs while the device is in
After a Reset, the default time-out period is two Sleep, no Reset is generated. Instead, the device
seconds. wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. The RWDT bit in the PCON register can also be
used. See Section 3.0 “Memory Organization” for
more information.

PIC16(L)F18857/77
TABLE 9-2: WDT CLEARING CONDITIONS

Conditions WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SEN = 0
WDTE<1:0> = 10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK
Change INTOSC divider (IRCF bits) Unaffected
FIGURE 9-2: WINDOW PERIOD AND DELAY
Rev. 10-000163A
8/15/2016
CLRWDT Instruction
(or other WDT Reset)
Window Period
Window Closed Window Open
Time-out Event
Window Delay
(window violation can occur)

PIC16(L)F18857/77
9.7 Register Definitions: Windowed Watchdog Timer Control
REGISTER 9-1: WDTCON0: WATCHDOG TIMER CONTROL REGISTER 0

U-0 U-0 R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W-0/0
— — WDTPS<4:0>(1) SEN
bit 7 bit 0
Legend:

bit 5-1 WDTPS<4:0>: Watchdog Timer Prescale Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)
10010 = 1:8388608 (223) (Interval 256s nominal)

01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
bit 0 SEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 1x:
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 00:
Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

2: When WDTCPS <4:0> in CONFIG3 = 11111, the Reset value of WDTPS<4:0> is 01011. Otherwise, the
Reset value of WDTPS<4:0> is equal to WDTCPS<4:0> in CONFIG3.
3: When WDTCPS <4:0> in CONFIG3 ≠ 11111, these bits are read-only.

PIC16(L)F18857/77
REGISTER 9-2: WDTCON1: WATCHDOG TIMER CONTROL REGISTER 1

U-0 R/W(3)-q/q(1) R/W(3)-q/q(1) R/W(3)-q/q(1) U-0 R/W(4)-q/q(2) R/W(4)-q/q(2) R/W(4)-q/q(2)
— WDTCS<2:0> — WINDOW<2:0>
bit 7 bit 0
Legend:

bit 6-4 WDTCS<2:0>: Watchdog Timer Clock Select bits
111 = Reserved
•
•
•
010 = Reserved
001 = MFINTOSC/16 (31.25 kHz)
000 = LFINTOSC (31 kHz)
bit 2-0 WINDOW<2:0>: Watchdog Timer Window Select bits
Window delay Window opening

WINDOW<2:0>
Percent of time Percent of time
111 N/A 100
110 12.5 87.5
101 25 75
100 37.5 62.5
011 50 50
010 62.5 37.5
001 75 25
000 87.5 12.5
Note 1: If WDTCCS <2:0> in CONFIG3 = 111, the Reset value of WDTCS<2:0> is 000.
2: The Reset value of WINDOW<2:0> is determined by the value of WDTCWS<2:0> in the CONFIG3 register.
3: If WDTCCS<2:0> in CONFIG3 ≠ 111, these bits are read-only.
4: If WDTCWS<2:0> in CONFIG3 ≠ 111, these bits are read-only.

PIC16(L)F18857/77
REGISTER 9-3: WDTPSL: WDT PRESCALE SELECT LOW BYTE REGISTER (READ-ONLY)
R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
PSCNT<7:0>(1)
bit 7 bit 0
Legend:
bit 7-0 PSCNT<7:0>: Prescale Select Low Byte bits(1)
Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR
registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation.
REGISTER 9-4: WDTPSH: WDT PRESCALE SELECT HIGH BYTE REGISTER (READ-ONLY)
R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
PSCNT<15:8>(1)
bit 7 bit 0
Legend:
bit 7-0 PSCNT<15:8>: Prescale Select High Byte bits(1)
REGISTER 9-5: WDTTMR: WDT TIMER REGISTER (READ-ONLY)

U-0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
— WDTTMR<3:0> STATE PSCNT<17:16>(1)
bit 7 bit 0
Legend:

bit 6-3 WDTTMR<3:0>: Watchdog Timer Value bits
bit 2 STATE: WDT Armed Status bit
1 = WDT is armed
0 = WDT is not armed
bit 1-0 PSCNT<17:16>: Prescale Select Upper Byte bits(1)

PIC16(L)F18857/77
TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
on Page
OSCCON1 — NOSC<2:0> NDIV<3:0> 121
OSCCON2 — COSC<2:0> CDIV<3:0> 121
OSCCON3 CSWHOLD SOSCPWR — ORDY NOSCR — — — 122
PCON0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 108
WDTCON0 — — WDTPS<4:0> SEN 165
WDTCON1 — WDTCS<2:0> — WINDOW<2:0> 165
WDTPSL PSCNT<7:0> 165
WDTPSH PSCNT<15:8> 165
WDTTMR — WDTTMR<4:0> STATE PSCNT<17:16> 165
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register
on Page
13:8 — — FCMEN — CSWEN — — CLKOUTEN

CONFIG1 92
7:0 — RSTOSC<2:0> — FEXTOSC<2:0>

PIC16(L)F18857/77
10.0 NONVOLATILE MEMORY It is important to understand the PFM memory structure
for erase and programming operations. PFM is
(NVM) CONTROL
arranged in rows. A row consists of 32 14-bit program
NVM is separated into two types: Program Flash memory words. A row is the minimum size that can be
Memory (PFM) and Data EEPROM Memory. erased by user software.
NVM is accessible by using both the FSR and INDF After a row has been erased, all or a portion of this row
registers, or through the NVMREG register interface. can be programmed. Data to be written into the
program memory row is written to 14-bit wide data write
The write time is controlled by an on-chip timer. The
latches. These latches are not directly accessible, but
write/erase voltages are generated by an on-chip
may be loaded via sequential writes to the
charge pump rated to operate over the operating
NVMDATH:NVMDATL register pair.
voltage range of the device.
NVM can be protected in two ways; by either code
protection or write protection. Note: To modify only a portion of a previously
programmed row, then the contents of the
Code protection (CP and CPD bits in Configuration
entire row must be read and saved in
Word 5) disables access, reading and writing, to both
RAM prior to the erase. Then, the new
the PFM and EEPROM via external device program-
data and retained data can be written into
mers. Code protection does not affect the self-write and
the write latches to reprogram the row of
erase functionality. Code protection can only be Reset
PFM. However, any unprogrammed
by a device programmer performing a Bulk Erase to the
locations can be written without first
device, clearing all nonvolatile memory, Configuration
erasing the row. In this case, it is not
bits, and User IDs.
necessary to save and rewrite the other
Write protection prohibits self-write and erase to a previously programmed locations
portion or all of the PFM, as defined by the WRT<1:0>
bits of Configuration Word 4. Write protection does not 10.1.1 PROGRAM MEMORY VOLTAGES
affect a device programmer’s ability to read, write, or
erase the device. The PFM is readable and writable during normal
operation over the full VDD range.
10.1 Program Flash Memory (PFM) 10.1.1.1 Programming Externally
PFM consists of an array of 14-bit words as user The program memory cell and control logic support
memory, with additional words for User ID information, write and Bulk Erase operations down to the minimum
Configuration words, and interrupt vectors. PFM device operating voltage. Special BOR operation is
provides storage locations for: enabled during Bulk Erase (Section 5.2.4 “BOR is
• User program instructions always OFF”).
• User defined data
10.1.1.2 Self-programming
PFM data can be read and/or written to through:
The program memory cell and control logic will support
• CPU instruction fetch (read-only)
write and row erase operations across the entire VDD
• FSR/INDF indirect access (read-only)
range. Bulk Erase is not supported when self-
(Section 10.3 “FSR and INDF Access”)
programming.
• NVMREG access (Section 10.4 “NVMREG
Access”
• In-Circuit Serial Programming™ (ICSP™)
Read operations return a single word of memory. When
write and erase operations are done on a row basis, the
row size is defined in Table 10-1. PFM will erase to a
logic ‘1’ and program to a logic ‘0’.
TABLE 10-1: FLASH MEMORY

ORGANIZATION BY DEVICE
Total
Write
Row Erase Program
Device Latches
(words) Flash
(words)
(words)
PIC16(L)F18857
32 32 32768
PIC16(L)F18877

PIC16(L)F18857/77
10.2 Data EEPROM Memory 10.4 NVMREG Access
Data EEPROM Memory consists of 256 bytes of user The NVMREG interface allows read/write access to all
data memory. The EEPROM provides storage the locations accessible by FSRs, and also read/write
locations for 8-bit user defined data. access to the User ID locations, and read-only access
EEPROM can be read and/or written through: to the device identification, revision, and Configuration
data.
• FSR/INDF indirect access (Section 10.3 “FSR
and INDF Access”) Reading, writing, or erasing of NVM via the NVMREG
• NVMREG access (Section 10.4 “NVMREG interface is prevented when the device is code-
Access”) protected.
• In-Circuit Serial Programming (ICSP)
10.4.1 NVMREG READ OPERATION
Unlike PFM, which must be written to by row, EEPROM
can be written to word by word. To read a NVM location using the NVMREG interface,
the user must:
10.3 FSR and INDF Access 1. Clear the NVMREGS bit of the NVMCON1
register if the user intends to access PFM
The FSR and INDF registers allow indirect access to locations, or set NMVREGS if the user intends
the PFM or EEPROM. to access User ID, Configuration, or EEPROM
locations.
10.3.1 FSR READ
2. Write the desired address into the
With the intended address loaded into an FSR register NVMADRH:NVMADRL register pair (Table 10-
a MOVIW instruction or read of INDF will read data from 2).
the PFM or EEPROM. 3. Set the RD bit of the NVMCON1 register to
Reading from NVM requires one instruction cycle. The initiate the read.
CPU operation is suspended during the read, and Once the read control bit is set, the CPU operation is
resumes immediately after. Read operations return a suspended during the read, and resumes immediately
single word of memory. after. The data is available in the very next cycle, in the
NVMDATH:NVMDATL register pair; therefore, it can be
10.3.2 FSR WRITE read as two bytes in the following instructions.
Writing/erasing the NVM through the FSR registers (ex. NVMDATH:NVMDATL register pair will hold this value
MOVWI instruction) is not supported in the until another read or until it is written to by the user.
PIC16(L)F18857/77 devices.

PIC16(L)F18857/77
Upon completion, the RD bit is cleared by hardware.
FIGURE 10-1: FLASH PROGRAM

MEMORY READ
FLOWCHART
Rev. 10-000046C
8/21/2015
Start
Read Operation
Select Memory:
PFM, EEPROM, Config Words, User
ID (NVMREGS)
Select
Word Address
(NVMADRH:NVMADRL)
Data read now in

NVMDATH:NVMDATL
End
Read Operation
EXAMPLE 10-1: PFM PROGRAM MEMORY READ

* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
* data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL NVMADRL ; Select Bank for NVMCON registers

MOVLW PROG_ADDR_LO ;
MOVWF NVMADRL ; Store LSB of address
MOVLW PROG_ADDR_HI ;
MOVWF NVMADRH ; Store MSB of address
BCF NVMCON1,NVMREGS ; Do not select Configuration Space

BSF NVMCON1,RD ; Initiate read
MOVF NVMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF NVMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

PIC16(L)F18857/77
10.4.2 NVM UNLOCK SEQUENCE FIGURE 10-2: NVM UNLOCK
The unlock sequence is a mechanism that protects the SEQUENCE FLOWCHART
NVM from unintended self-write programming or
erasing. The sequence must be executed and Rev. 10-000047B
completed without interruption to successfully

8/24/2015
complete any of the following operations:

• PFM Row Erase Start
• Load of PFM write latches Unlock Sequence
• Write of PFM write latches to PFM memory
• Write of PFM write latches to User IDs
• Write to EEPROM
Write 0x55 to
The unlock sequence consists of the following steps NVMCON2
and must be completed in order:
• Write 55h to NVMCON2
• Write AAh to NMVCON2
• Set the WR bit of NVMCON1 Write 0xAA to
NVMCON2
Once the WR bit is set, the processor will stall internal
operations until the operation is complete and then
resume with the next instruction.
Initiate
Write or Erase operation
(WR = 1)
Note: The two NOP instructions after setting the
WR bit that were required in previous
devices are not required for
End
PIC16(L)F18857/77 devices. See Unlock Sequence
Figure 10-2.
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
EXAMPLE 10-2: NVM UNLOCK SEQUENCE

BCF INTCON, GIE ; Recommended so sequence is not interrupted
BANKSEL NVMCON1 ;
BSF NVMCON1, WREN ; Enable write/erase
MOVLW 55h ; Load 55h
MOVWF NVMCON2 ; Step 1: Load 55h into NVMCON2

MOVLW AAh ; Step 2: Load W with AAh
MOVWF NVMCON2 ; Step 3: Load AAH into NVMCON2
BSF NVMCON1, WR ; Step 4: Set WR bit to begin write/erase
BSF INTCON, GIE ; Re-enable interrupts
Note 1: Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order shown.
2: Opcodes shown are illustrative; any instruction that has the indicated effect may be used.

PIC16(L)F18857/77
10.4.3 NVMREG WRITE TO EEPROM FIGURE 10-3: NVM ERASE
Writing to the EEPROM is accomplished by the FLOWCHART
following steps: Rev. 10-000048B
8/24/2015
1. Set the NVMREGS and WREN bits of the

NVMCON1 register. Start
2. Write the desired address (address + F000h) Erase Operation
into the NVMADRH:NVMADRL register pair
(Table 10-2).
3. Perform the unlock sequence as described in Select Memory:
Section 10.4.2 “NVM Unlock Sequence”. PFM, Config Words, User ID
(NVMREGS)
A single EEPROM word is written with NVMDATA. The
operation includes an implicit erase cycle for that word
(it is not necessary to set the FREE bit), and requires
many instruction cycles to finish. CPU execution Select Word Address
(NVMADRH:NVMADRL)
continues in parallel and, when complete, WR is
cleared by hardware, NVMIF is set, and an interrupt will
occur if NVMIE is also set. Software must poll the WR
bit to determine when writing is complete, or wait for the Select Erase Operation
interrupt to occur. WREN will remain unchanged. (FREE=1)
Once the EEPROM write operation begins, clearing the
WR bit will have no effect; the operation will continue to
run to completion.
Enable Write/Erase Operation
(WREN=1)
10.4.4 NVMREG ERASE OF PFM
Before writing to PFM, the word(s) to be written must
be erased or previously unwritten. PFM can only be
erased one row at a time. No automatic erase occurs Disable Interrupts
upon the initiation of the write to PFM. (GIE=0)
To erase a PFM row:

1. Clear the NVMREGS bit of the NVMCON1
register to erase PFM locations, or set the Unlock Sequence
(See Note 1)
NMVREGS bit to erase User ID locations.
2. Write the desired address into the
NVMADRH:NVMADRL register pair (Table 10-
2). CPU stalls while
Erase operation completes
3. Set the FREE and WREN bits of the NVMCON1 (2 ms typical)
register.
4. Perform the unlock sequence as described in
Section 10.4.2 “NVM Unlock Sequence”.
If the PFM address is write-protected, the WR bit will be Disable Write/Erase Operation
(WREN = 0)
cleared and the erase operation will not take place.
While erasing PFM, CPU operation is suspended, and
resumes when the operation is complete. Upon
completion, the NVMIF is set, and an interrupt will Re-enable Interrupts
occur if the NVMIE bit is also set. (GIE = 1)
Write latch data is not affected by erase operations,

and WREN will remain unchanged.
End
Erase Operation
Note 1: See Figure 10-2.

PIC16(L)F18857/77
EXAMPLE 10-3: ERASING ONE ROW OF PROGRAM FLASH MEMORY (PFM)
; This sample row erase routine assumes the following:
; 1.A valid address within the erase row is loaded in variables ADDRH:ADDRL
; 2.ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
BANKSEL NVMADRL
MOVF ADDRL,W
MOVWF NVMADRL ; Load lower 8 bits of erase address boundary
MOVF ADDRH,W
MOVWF NVMADRH ; Load upper 6 bits of erase address boundary
BCF NVMCON1,NVMREGS ; Choose PFM memory area
BSF NVMCON1,FREE ; Specify an erase operation
BSF NVMCON1,WREN ; Enable writes
BCF INTCON,GIE ; Disable interrupts during unlock sequence
; -------------------------------REQUIRED UNLOCK SEQUENCE:------------------------------
MOVLW 55h ; Load 55h to get ready for unlock sequence

MOVWF NVMCON2 ; First step is to load 55h into NVMCON2
MOVLW AAh ; Second step is to load AAh into W
MOVWF NVMCON2 ; Third step is to load AAh into NVMCON2
BSF NVMCON1,WR ; Final step is to set WR bit
; --------------------------------------------------------------------------------------
BSF INTCON,GIE ; Re-enable interrupts, erase is complete

BCF NVMCON1,WREN ; Disable writes
TABLE 10-2: NVM ORGANIZATION AND ACCESS INFORMATION

Primary Values NVMREG Access FSR Access
NVMREGS FSR
Memory ICSP™ Memory NVMADR Allowed FSR
bit Programming
Function Address Type <15:0> Operations Address
(NVMCON1) Address
Reset Vector 0000h 0 8000h 8000h
User Memory 0001h 0 8001h 8001h
0003h 8003h Read 8003h
PFM Read-Only
INT Vector 0004h 0 8004h Write 8004h
User Memory 0005h 0 8005h 8005h
07FFh 87FFh 87FFh
User ID 8000h PFM 1 8000h Read
8003h 8003h Write
Reserved 8004h — — 8004h —
Rev ID 8005h 1 8005h Read
Device ID 8006h 1 8006h Write
CONFIG1 8007h 1 8007h No Access
PFM
CONFIG2 8008h 1 8008h
CONFIG3 8009h 1 8009h Read-Only
CONFIG4 800Ah 1 800Ah
CONFIG5 800Bh 1 800Bh
User Memory F000h EEPROM 1 F000h Read 7000h Read-Only
F0FFh F0FFh Write 70FFh

PIC16(L)F18857/77
10.4.5 NVMREG WRITE TO PFM The following steps should be completed to load the
write latches and program a row of program memory.
Program memory is programmed using the following
These steps are divided into two parts. First, each write
steps:
latch is loaded with data from the
1. Load the address of the row to be programmed NVMDATH:NVMDATL using the unlock sequence with
into NVMADRH:NVMADRL. LWLO = 1. When the last word to be loaded into the
2. Load each write latch with data. write latch is ready, the LWLO bit is cleared and the
3. Initiate a programming operation. unlock sequence executed. This initiates the
4. Repeat steps 1 through 3 until all data is written. programming operation, writing all the latches into
Flash program memory.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten. Note: The special unlock sequence is required
Program memory can only be erased one row at a time. to load a write latch with data or initiate a
No automatic erase occurs upon the initiation of the Flash programming operation. If the
write. unlock sequence is interrupted, writing to
the latches or program memory will not be
Program memory can be written one or more words at
initiated.
a time. The maximum number of words written at one
time is equal to the number of write latches. See 1. Set the WREN bit of the NVMCON1 register.
Figure 10-4 (row writes to program memory with 32 2. Clear the NVMREGS bit of the NVMCON1
write latches) for more details. register.
The write latches are aligned to the Flash row address 3. Set the LWLO bit of the NVMCON1 register.
boundary defined by the upper ten bits of When the LWLO bit of the NVMCON1 register is
NVMADRH:NVMADRL, (NVMADRH<6:0>:NVMADRL<7:5>) ‘1’, the write sequence will only load the write
with the lower five bits of NVMADRL, (NVMADRL<4:0>) latches and will not initiate the write to Flash
determining the write latch being loaded. Write opera- program memory.
tions do not cross these boundaries. At the completion 4. Load the NVMADRH:NVMADRL register pair
of a program memory write operation, the data in the with the address of the location to be written.
write latches is reset to contain 0x3FFF. 5. Load the NVMDATH:NVMDATL register pair
with the program memory data to be written.
6. Execute the unlock sequence (Section
10.4.2 “NVM Unlock Sequence”). The write
latch is now loaded.
7. Increment the NVMADRH:NVMADRL register
pair to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the NVMCON1 register.
When the LWLO bit of the NVMCON1 register is
‘0’, the write sequence will initiate the write to
10. Load the NVMDATH:NVMDATL register pair
with the program memory data to be written.
11. Execute the unlock sequence (Section
10.4.2 “NVM Unlock Sequence”). The entire
program memory latch content is now written to
Note: The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 10-4. The initial address is loaded into the
NVMADRH:NVMADRL register pair; the data is loaded
using indirect addressing.

FIGURE 10-4: BLOCK WRITES TO PROGRAM FLASH MEMORY (PFM) WITH 32 WRITE LATCHES
PIC16(L)F18857/77
Rev. 10-000004E
7 6 0 7 4 3 0 7 5 0 7 0 8/14/2015
NVMADRH NVMADRL - - NVMDATH NVMDATL

- rA r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c3 c2 c1 c0 6 8
14
Program Memory Write Latches

11 4
14 14 14 14
Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31
00h 01h 1Eh 1Fh
NVMADRL<3:0>
14 14 14 14
Row Addr Addr Addr Addr
000h 0000h 0001h 001Eh 001Fh

001h 0010h 0011h 003Eh 003Fh
002h 0020h 0021h 005Eh 005Fh
NVMREGS=0
1FEh 1FE0h 1FE1h 1FDEh 1FDFh

Row 1FFh 1FF0h 1FF1h 1FFEh 1FFFh
Address
NVMADRH<6:0> Decode Flash Program Memory
NVMADRL<7:4>
DS40001825F-page 176
800h 8000h - 8003h 8004h 8005h 8006h 8007h – 800Bh 800Ch - 801Fh
MASK/ DEVICE ID Configuration
USER ID 0 - 3 reserved reserved
NVMREGS = 1 REV ID Words
Configuration Memory
PIC16(L)F18857/77
FIGURE 10-5: PROGRAM FLASH MEMORY (PFM) WRITE FLOWCHART
Rev. 10-000 049E
7/17/202 0
Start
Write O peration
Determine number of
words to be written into Loa d the value to write
PFM. The number of NVMDA T
words can not exceed th e
numbe r of wo rds per row
(word_cnt)
Update the word counter

Write L atches to PFM
(word_cnt--)
Sele ct access to PFM

locations u sin g
NVMRE G<1:0> bits
Disa ble In terr upts
(GIE = 0)
Last word to Yes
write ?
Sele ct Row Addr ess
NVMADR
No
Unlock Se quence
(See no te 1)
Disa ble In terr upts

Sele ct Wri te Ope rati on (GIE = 0)
(FRE E = 0)
CPU stalls while Write
ope rati on comple tes
(2 ms typi cal)
Unlock Se quence
Loa d Write Latch es Onl y (See no te 1)
Ena ble Wr ite/Era se

No delay whe n writing to Re-ena ble Interru pts
Ope ration (WREN = 1)
PFM La tches (GIE = 1)
Disa ble Write/Era se

Ope ration (WREN = 0)
Re-ena ble Interru pts

(GIE = 1)
End
Write O peration
Incr ement Ad dress

NVMADR++

PIC16(L)F18857/77
EXAMPLE 10-4: WRITING TO PROGRAM FLASH MEMORY (PFM)
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
; 5. NVM interrupts are not taken into account
BANKSEL NVMADRH
MOVF ADDRH,W
MOVWF NVMADRH ; Load initial address
MOVF ADDRL,W
MOVWF NVMADRL
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L
MOVLW HIGH DATA_ADDR
MOVWF FSR0H
BCF NVMCON1,NVMREGS ; Set Program Flash Memory as write location
BSF NVMCON1,LWLO ; Load only write latches
LOOP
MOVIW FSR0++
MOVWF NVMDATL ; Load first data byte
MOVIW FSR0++
MOVWF NVMDATH ; Load second data byte
MOVF NVMADRL,W
XORLW 0x1F ; Check if lower bits of address are 00000
ANDLW 0x1F ; and if on last of 32 addresses
BTFSC STATUS,Z ; Last of 32 words?
GOTO START_WRITE ; If so, go write latches into memory
CALL UNLOCK_SEQ ; If not, go load latch
INCF NVMADRL,F ; Increment address
GOTO LOOP
START_WRITE
BCF NVMCON1,LWLO ; Latch writes complete, now write memory
CALL UNLOCK_SEQ ; Perform required unlock sequence
UNLOCK_SEQ
MOVLW 55h
BCF INTCON,GIE ; Disable interrupts
MOVWF NVMCON2 ; Begin unlock sequence
MOVLW AAh
MOVWF NVMCON2
BSF NVMCON1,WR
BSF INTCON,GIE ; Unlock sequence complete, re-enable interrupts
return

PIC16(L)F18857/77
10.4.6 MODIFYING FLASH PROGRAM FIGURE 10-6: FLASH PROGRAM
MEMORY MEMORY MODIFY
When modifying existing data in a program memory FLOWCHART
row, and data within that row must be preserved, it must Rev. 10-000050B
8/21/2015
first be read and saved in a RAM image. Program

memory is modified using the following steps:
Start
1. Load the starting address of the row to be Modify Operation
modified.
2. Read the existing data from the row into a RAM
image.
Read Operation
3. Modify the RAM image to contain the new data (See Note 1)
to be written into program memory.
4. Load the starting address of the row to be
rewritten.
An image of the entire row
5. Erase the program memory row.
read must be stored in RAM
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(See Note 2)
Write Operation
Use RAM image
(See Note 3)
End
Modify Operation

2: See Figure 10-3.
3: See Figure 10-5.

PIC16(L)F18857/77
10.4.7 NVMREG DATA EEPROM MEMORY, FIGURE 10-7: FLASH PROGRAM
USER ID, DEVICE ID AND MEMORY MODIFY
CONFIGURATION WORD ACCESS FLOWCHART
Instead of accessing Program Flash Memory (PFM), Rev. 10-000051C
8/21/2015
the Data EEPROM Memory, the User ID’s, Device ID/

Revision ID and Configuration Words can be accessed
when NVMREGS = 1 in the NVMCON1 register. This is
Start
the region that would be pointed to by PC<15> = 1, but
Verify Operation
not all addresses are accessible. Different access may
exist for reads and writes. Refer to Table 10-3.
When read access is initiated on an address outside
This routine assumes that the last
the parameters listed in Table 10-3, the NVMDATH: row of data written was from an
NVMDATL register pair is cleared, reading back ‘0’s. image saved on RAM. This image
will be used to verify the data
currently stored in Flash Program
Memory
Read Operation
(See Note 1)
PMDAT = No
RAM image ?
Yes
Fail
Verify Operation
No
Last word ?
Yes
End
Verify Operation
TABLE 10-3: EEPROM, USER ID, DEV/REV ID AND CONFIGURATION WORD ACCESS
(NVMREGS = 1)
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8005h-8006h Device ID/Revision ID Yes No
8007h-800Bh Configuration Words 1-5 Yes No
F000h-F0FFh EEPROM Yes Yes

PIC16(L)F18857/77
EXAMPLE 10-5: DEVICE ID ACCESS
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
; 5. NVM interrupts are not taken into account
BANKSEL NVMADRH
MOVF ADDRH,W
MOVWF NVMADRH ; Load initial address
MOVF ADDRL,W
MOVWF NVMADRL
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L
MOVLW HIGH DATA_ADDR
MOVWF FSR0H
BCF NVMCON1,NVMREGS ; Set PFM as write location
BSF NVMCON1,LWLO ; Load only write latches
LOOP
MOVIW FSR0++
MOVWF NVMDATL ; Load first data byte
MOVIW FSR0++
MOVWF NVMDATH ; Load second data byte
MOVF NVMADRL,W
XORLW 0x1F ; Check if lower bits of address are 00000
ANDLW 0x1F ; and if on last of 32 addresses
BTFSC STATUS,Z ; Last of 32 words?
GOTO START_WRITE ; If so, go write latches into memory
CALL UNLOCK_SEQ ; If not, go load latch
INCF NVMADRL,F ; Increment address
GOTO LOOP
START_WRITE
BCF NVMCON1,LWLO ; Latch writes complete, now write memory
CALL UNLOCK_SEQ ; Perform required unlock sequence
UNLOCK_SEQ
MOVLW 55h
BCF INTCON,GIE ; Disable interrupts
MOVWF NVMCON2 ; Begin unlock sequence
MOVLW AAh
MOVWF NVMCON2
BSF NVMCON1,WR
BSF INTCON,GIE ; Unlock sequence complete, re-enable interrupts
return

PIC16(L)F18857/77
10.4.8 WRITE VERIFY
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 10-8: FLASH PROGRAM

MEMORY VERIFY
FLOWCHART
Start
Verify Operation
This routine assumes that the last row

of data written was from an image
saved in RAM. This image will be used
to verify the data currently stored in
Flash Program Memory.
Read Operation
(Figure10-1
Figure x.x)
NVMDAT = No
RAM image
?
Yes Fail
Verify Operation
No Last
Word ?
Yes
End
Verify Operation

PIC16(L)F18857/77
10.4.9 WRERR BIT
The WRERR bit can be used to determine if a write
error occurred.
WRERR will be set if one of the following conditions
occurs:
• If WR is set while the NVMADRH:NMVADRL
points to a write-protected address
• A Reset occurs while a self-write operation was in
progress
• An unlock sequence was interrupted
The WRERR bit is normally set by hardware, but can
be set by the user for test purposes. Once set, WRERR
must be cleared in software.
TABLE 10-4: ACTIONS FOR PFM WHEN WR = 1

Free LWLO Actions for PFM when WR = 1 Comments
1 x Erase the 32-word row of NVMADRH:NVMADRL • If WP is enabled, WR is cleared and
location. See Section 10.4.3 “NVMREG Write WRERR is set
to EEPROM” • All 32 words are erased
• NVMDATH:NVMDATL is ignored
0 1 Copy NVMDATH:NVMDATL to the write latch • Write protection is ignored
corresponding to NVMADR LSBs. See Section • No memory access occurs
10.4.4 “NVMREG Erase of PFM”
0 0 Write the write-latch data to PFM row. See Sec- • If WP is enabled, WR is cleared and
tion 10.4.4 “NVMREG Erase of PFM” WRERR is set
• Write latches are reset to 3FFh
• NVMDATH:NVMDATL is ignored

PIC16(L)F18857/77
10.5 Register Definitions: Flash Program Memory Control
REGISTER 10-1: NVMDATL: NONVOLATILE MEMORY DATA LOW BYTE REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
NVMDAT<7:0>
bit 7 bit 0
Legend:
bit 7-0 NVMDAT<7:0>: Read/write value for Least Significant bits of program memory
REGISTER 10-2: NVMDATH: NONVOLATILE MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — NVMDAT<13:8>
bit 7 bit 0
Legend:

bit 5-0 NVMDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 10-3: NVMADRL: NONVOLATILE MEMORY ADDRESS LOW BYTE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
NVMADR<7:0>
bit 7 bit 0
Legend:
bit 7-0 NVMADR<7:0>: Specifies the Least Significant bits for program memory address
REGISTER 10-4: NVMADRH: NONVOLATILE MEMORY ADDRESS HIGH BYTE REGISTER

U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—(1) NVMADR<14:8>
bit 7 bit 0
Legend:

bit 6-0 NVMADR<14:8>: Specifies the Most Significant bits for program memory address
Note 1: Bit is undefined while WR = 1 (during the EEPROM write operation it may be ‘0’ or ‘1’).

PIC16(L)F18857/77
REGISTER 10-5: NVMCON1: NONVOLATILE MEMORY CONTROL 1 REGISTER

U-0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0
— NVMREGS LWLO FREE WRERR(1,2,3) WREN WR(4,5,6) RD(7)
bit 7 bit 0
Legend:
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

bit 6 NVMREGS: Configuration Select bit
1 = Access EEPROM, Configuration, User ID and Device ID Registers
0 = Access PFM
bit 5 LWLO: Load Write Latches Only bit
When FREE = 0:
1 = The next WR command updates the write latch for this word within the row; no memory operation is initiated.
0 = The next WR command writes data or erases
Otherwise: The bit is ignored
bit 4 FREE: PFM Erase Enable bit
When NVMREGS:NVMADR points to a PFM location:
1 = Performs an erase operation with the next WR command; the 32-word pseudo-row containing the indicated
address is erased (to all 1s) to prepare for writing.
0 = All write operations have completed normally
bit 3 WRERR: Program/Erase Error Flag bit(1,2,3)
This bit is normally set by hardware.
1 = A write operation was interrupted by a Reset, interrupted unlock sequence, or WR was written to one while
NVMADR points to a write-protected address.
0 = The program or erase operation completed normally
bit 2 WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1 WR: Write Control bit(4,5,6)
When NVMREG:NVMADR points to a EEPROM location:
1 = Initiates an erase/program cycle at the corresponding EEPROM location
0 = NVM program/erase operation is complete and inactive
When NVMREG:NVMADR points to a PFM location:
1 = Initiates the operation indicated by Table 10-4
0 = NVM program/erase operation is complete and inactive
Otherwise: This bit is ignored
bit 0 RD: Read Control bit(7)
1 = Initiates a read at address = NVMADR1, and loads data to NVMDAT Read takes one instruction cycle and the
bit is cleared when the operation is complete. The bit can only be set (not cleared) in software.
0 = NVM read operation is complete and inactive
Note 1: Bit is undefined while WR = 1 (during the EEPROM write operation it may be ‘0’ or ‘1’).
2: Bit must be cleared by software; hardware will not clear this bit.
3: Bit may be written to ‘1’ by software in order to implement test sequences.
4: This bit can only be set by following the unlock sequence of Section 10.4.2 “NVM Unlock Sequence”.
5: Operations are self-timed, and the WR bit is cleared by hardware when complete.
6: Once a write operation is initiated, setting this bit to zero will have no effect.
7: Reading from EEPROM loads only NVMDATL<7:0> (Register 10-1).

PIC16(L)F18857/77
REGISTER 10-6: NVMCON2: NONVOLATILE MEMORY CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0
NVMCON2<7:0>
bit 7 bit 0
Legend:
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 NVMCON2<7:0>: Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
NVMCON1 register. The value written to this register is used to unlock the writes.
TABLE 10-5: SUMMARY OF REGISTERS ASSOCIATED WITH NONVOLATILE MEMORY (NVM)

Register
on Page
PIE7 SCANIE CRCIE NVMIE NCO1IE — CWG3IE CWG2IE CWG1IE 136
PIR7 SCANIF CRCIF NVMIF NCO1IF — CWG3IF CWG2IF CWG1IF 145
NVMCON1 — NVMREGS LWLO FREE WRERR WREN WR RD 185
NVMCON2 NVMCON2<7:0> 186
NVMADRL NVMADR<7:0> 184
NVMADRH —(1) NVMADR<14:8> 184
NVMDATL NVMDAT<7:0> 184
NVMDATH — — NVMDAT<13:8> 184
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by NVM.
Note 1: Unimplemented, read as ‘1’.

PIC16(L)F18857/77
11.0 CYCLIC REDUNDANCY CHECK EXAMPLE 11-1: BASIC CRC OPERATION
(CRC) MODULE EXAMPLE
The Cyclic Redundancy Check (CRC) module provides CRC-16-ANSI

a software-configurable hardware-implemented CRC 16
x + x15 + x2 + 1 (17 bits)
checksum generator. This module includes the following
features: Standard 16-bit representation = 0x8005
CRCXORH = 0b10000000
• Any standard CRC up to 16 bits can be used (1)
CRCXORL = 0b0000010-
• Configurable Polynomial
Data Sequence:
• Any seed value up to 16 bits can be used 0x55, 0x66, 0x77, 0x88
• Standard and reversed bit order available DLEN = 0b0111
• Augmented zeros can be added automatically or PLEN = 0b1111
by the user Data entered into the CRC:
• Memory scanner for fast CRC calculations on SHIFTM = 0:
01010101 01100110 01110111 10001000
program memory user data
• Software loadable data registers for calculating SHIFTM = 1:
CRC values not from the memory scanner 10101010 01100110 11101110 00010001
Check Value (ACCM = 1):

11.1 CRC Module Overview
SHIFTM = 0: 0x32D6
The CRC module provides a means for calculating a CRCACCH = 0b00110010
check value of program memory. The CRC module is CRCACCL = 0b11010110
coupled with a memory scanner for faster CRC
calculations. The memory scanner can automatically SHIFTM = 1: 0x6BA2
provide data to the CRC module. The CRC module can CRCACCH = 0b01101011
also be operated by directly writing data to SFRs, CRCACCL = 0b10100010
without using the scanner.
Note 1: Bit 0 is unimplemented. The LSb of any CRC
11.2 CRC Functional Overview polynomial is always ‘1’ and will always be
treated as a ‘1’ by the CRC for calculating the
The CRC module can be used to detect bit errors in the CRC check value. This bit will be read in soft-
Flash memory using the built-in memory scanner or ware as a ‘0’.
through user input RAM memory. The CRC module can
accept up to a 16-bit polynomial with up to a 16-bit seed
value. A CRC calculated check value (or checksum) 11.3 CRC Polynomial Implementation
will then be generated into the CRCACC<15:0> regis-
ters for user storage. The CRC module uses an XOR Any standard polynomial up to 17 bits can be used. The
shift register implementation to perform the polynomial PLEN<3:0> bits are used to specify how long the
division required for the CRC calculation. polynomial used will be. For an xn polynomial, PLEN =
n-2. In an n-bit polynomial the xn bit and the LSb will be
used as a ‘1’ in the CRC calculation because the MSb
and LSb must always be a ‘1’ for a CRC polynomial.
For example, if using CRC-16-ANSI, the polynomial will
look like 0x8005. This will be implemented into the
CRCXOR<15:1> registers, as shown in Example 11-1.

PIC16(L)F18857/77
FIGURE 11-1: CRC LFSR EXAMPLE
Rev. 10-000207A
Linear Feedback Shift Register for CRC-16-ANSI 5/27/2014
x16 + x15 + x2 + 1
Data in
Augmentation Mode ON
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Data in
Augmentation Mode OFF
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
11.4 CRC Data Sources 11.5 CRC Check Value

Data can be input to the CRC module in two ways: The CRC check value will be located in the CRCACC
- User data using the CRCDAT registers registers after the CRC calculation has finished. The
check value will depend on two mode settings of the
- Flash using the Program Memory Scanner
CRCCON: ACCM and SHIFTM.
To set the number of bits of data, up to 16 bits, the
If the ACCM bit is set, the CRC module will augment
DLEN bits of CRCCON1 must be set accordingly. Only
the data with a number of zeros equal to the length of
data bits in CRCDATA registers up to DLEN will be
the polynomial to find the final check value. If the
used, other data bits in CRCDATA registers will be
ACCM bit is not set, the CRC will stop at the end of the
ignored.
data. A number of zeros equal to the length of the poly-
Data is moved into the CRCSHIFT as an intermediate nomial can then be entered to find the same check
to calculate the check value located in the CRCACC value as augmented mode, alternatively the expected
registers. check value can be entered at this point to make the
The SHIFTM bit is used to determine the bit order of the final result equal to 0.
data being shifted into the accumulator. If SHIFTM is A final XOR value may be needed with the check value
not set, the data will be shifted in MSb first. The value to find the desired CRC result
of DLEN will determine the MSb. If SHIFTM bit is set,
the data will be shifted into the accumulator in reversed 11.6 CRC Interrupt
order, LSb first.
The CRC will generate an interrupt when the BUSY bit
The CRC module can be seeded with an initial value by
transitions from ‘1’ to ‘0’. The CRCIF interrupt flag bit of
setting the CRCACC<15:0> registers to the
the PIR6 register is set every time the BUSY bit transi-
appropriate value before beginning the CRC.
tions, regardless of whether or not the CRC interrupt is
11.4.1 CRC FROM USER DATA enabled. The CRCIF bit can only be cleared in soft-
ware. The CRC interrupt enable is the CRCIE bit of the
To use the CRC module on data input from the user, the PIE6 register.
user must write the data to the CRCDAT registers. The
data from the CRCDAT registers will be latched into the
shift registers on any write to the CRCDATL register.
11.4.2 CRC FROM FLASH

To use the CRC module on data located in Flash
memory, the user can initialize the Program Memory
Scanner as defined in Section 11.8, Program Mem-
ory Scan Configuration.

PIC16(L)F18857/77
11.7 Configuring the CRC 11.8 Program Memory Scan
The following steps illustrate how to properly configure
Configuration
the CRC. If desired, the Program Memory Scan module may be
1. Determine if the automatic Program Memory used in conjunction with the CRC module to perform a
scan will be used with the scanner or manual CRC calculation over a range of program memory
calculation through the SFR interface and per- addresses. In order to set up the Scanner to work with
form the actions specified in Section 11.4 “CRC the CRC you need to perform the following steps:
Data Sources”, depending on which decision 1. Set the EN bit to enable the module. This can be
was made. performed at any point preceding the setting of
2. If desired, seed a starting CRC value into the the SCANGO bit, but if it gets disabled, all
CRCACCH/L registers. internal states of the Scanner are reset
3. Program the CRCXORH/L registers with the (registers are unaffected).
desired generator polynomial. 2. Choose which memory access mode is to be
4. Program the DLEN<3:0> bits of the CRCCON1 used (see Section 11.10 “Scanning Modes”)
register with the length of the data word – 1 and set the MODE bits of the SCANCON0
(refer to Example 11-1). This determines how register appropriately.
many times the shifter will shift into the accumu- 3. Based on the memory access mode, set the
lator for each data word. INTM bits of the SCANCON0 register to the
5. Program the PLEN<3:0> bits of the CRCCON1 appropriate interrupt mode (see Section
register with the length of the polynomial – 2 11.10.5 “Interrupt Interaction”)
(refer to Example 11-1). 4. Set the SCANLADRL/H and SCANHADRL/H
6. Determine whether shifting in trailing zeros is registers with the beginning and ending
desired and set the ACCM bit of CRCCON0 locations in memory that are to be scanned.
register appropriately. 5. Begin the scan by setting the SCANGO bit in the
7. Likewise, determine whether the MSb or LSb SCANCON0 register. The scanner will wait
should be shifted first and write the SHIFTM bit (CRCGO must be set) for the signal from the
of CRCCON0 register appropriately. CRC that it is ready for the first Flash memory
8. Write the CRCGO bit of the CRCCON0 register location, then begin loading data into the CRC.
to begin the shifting process. It will continue to do so until it either hits the
configured end address or an address that is
9a. If manual SFR entry is used, monitor the FULL bit
unimplemented on the device, at which point the
of CRCCON0 register. When FULL = 0, another
SCANGO bit will clear, Scanner functions will
word of data can be written to the CRCDATH/L
cease, and the SCANIF interrupt will be
registers, keeping in mind that CRCDATH should
triggered. Alternately, the SCANGO bit can be
be written first if the data has >8 bits, as the
cleared in software if desired.
shifter will begin upon the CRCDATL register
being written.
11.9 Scanner Interrupt
9b. If the scanner is used, the scanner will
automatically stuff words into the CRCDATH/L The scanner will trigger an interrupt when the
registers as needed, as long as the SCANGO bit SCANGO bit transitions from ‘1’ to ‘0’. The SCANIF
is set. interrupt flag of PIR7 is set when the last memory
10a.If using the Flash memory scanner, monitor the location is reached and the data is entered into the
SCANIF (or the SCANGO bit) for the scanner to CRCDATA registers. The SCANIF bit can only be
finish pushing information into the CRCDATA cleared in software. The SCAN interrupt enable is the
registers. After the scanner is completed, moni- SCANIE bit of the PIE7 register.
tor the CRCIF (or the BUSY bit) to determine
that the CRC has been completed and the check 11.10 Scanning Modes
value can be read from the CRCACC registers.
If both the interrupt flags are set (or both BUSY The memory scanner can scan in four modes: Burst,
and SCANGO bits are cleared), the completed Peek, Concurrent, and Triggered. These modes are
CRC calculation can be read from the controlled by the MODE bits of the SCANCON0
CRCACCH/L registers. register. The four modes are summarized in Table 11-1.
10b.If manual entry is used, monitor the CRCIF (or
BUSY bit) to determine when the CRCACC
registers will hold the check value.

PIC16(L)F18857/77
11.10.1 BURST MODE 11.10.3 TRIGGERED MODE
When MODE = 01, the scanner is in Burst mode. In When MODE = 11, the scanner is in Triggered mode.
Burst mode, CPU operation is stalled beginning with the Triggered mode behaves identically to Concurrent
operation after the one that sets the SCANGO bit, and mode, except instead of beginning the scan
the scan begins, using the instruction clock to execute. immediately upon the SCANGO bit being set, it waits
The CPU is held until the scan stops. Note that because for a rising edge from a separate trigger clock, the
the CPU is not executing instructions, the SCANGO bit source of which is determined by the SCANTRIG
cannot be cleared in software, so the CPU will remain register.
stalled until one of the hardware end-conditions occurs.
Burst mode has the highest throughput for the scanner, 11.10.4 PEEK MODE
but has the cost of stalling other execution while it When MODE = 10, the scanner is in Peek mode. Peek
occurs. mode waits for an instruction cycle in which the CPU
does not need to access the NVM (such as a branch
11.10.2 CONCURRENT MODE instruction) and uses that cycle to do its own NVM
When MODE = 00, the scanner is in Concurrent mode. access. This results in the lowest throughput for the NVM
Concurrent mode, like Burst mode, stalls the CPU access (and can take a much longer time to complete a
while performing accesses of memory. However, while scan than the other modes), but does so without any
Burst mode stalls until all accesses are complete, impact on execution times, unlike the other modes.
Concurrent mode allows the CPU to execute in
between access cycles.
TABLE 11-1: SUMMARY OF SCANNER MODES

Description
MODE<1:0>
First Scan Access CPU Operation
As soon as possible CPU resumes execution following
11 Triggered Stalled during NVM access
following a trigger each access
CPU continues execution following
10 Peek At the first dead cycle Timing is unaffected
each access
CPU suspended until scan
01 Burst
completes
As soon as possible Stalled during NVM access
CPU resumes execution following
00 Concurrent
each access
11.10.5 INTERRUPT INTERACTION

The INTM bit of the SCANCON0 register controls the
scanner’s response to interrupts depending on which
mode the NVM scanner is in, as described in
Table 11-2.
TABLE 11-2: SCAN INTERRUPT MODES

MODE<1:0>
INTM
MODE == Burst MODE != Burst
Interrupt overrides SCANGO to pause the burst
Scanner suspended during interrupt response;
and the interrupt handler executes at full speed;
1 interrupt executes at full speed and scan
Scanner Burst resumes when interrupt
resumes when the interrupt is complete.
completes.
Interrupts do not override SCANGO, and the
Scanner accesses NVM during interrupt
scan (burst) operation will continue; interrupt
0 response. If MODE != Peak the interrupt handler
response will be delayed until scan completes
execution speed will be affected.
(latency will be increased).

PIC16(L)F18857/77
In general, if INTM = 0, the scanner will take 11.10.7 IN-CIRCUIT DEBUG (ICD)
precedence over the interrupt, resulting in decreased INTERACTION
interrupt processing speed and/or increased interrupt
The scanner freezes when an ICD halt occurs, and
response latency. If INTM = 1, the interrupt will take
remains frozen until user-mode operation resumes.
precedence and have a better speed, delaying the
The debugger may inspect the SCANCON0 and
memory scan.
SCANLADR registers to determine the state of the
11.10.6 WDT INTERACTION scan.
Operation of the WDT is not affected by scanner The ICD interaction with each operating mode is
activity. Hence, it is possible that long scans, summarized in Table 11-3.
particularly in Burst mode, may exceed the WDT time-
out period and result in an undesired device Reset.
This should be considered when performing memory
scans with an application that also utilizes WDT.
TABLE 11-3: ICD AND SCANNER INTERACTIONS

Scanner Operating Mode
ICD Halt Concurrent
Peek Burst
Triggered
If external halt is asserted during the
BSF(SCANCON.GO), ICD entry
If external halt is asserted during a occurs, and the burst is delayed until
scan cycle, the instruction (delayed ICD exit.
by scan) may or may not execute
before ICD entry, depending on Otherwise, the current NVM-access
External Halt external halt timing. cycle will complete, and then the
scanner will be interrupted for ICD
entry.
cycle immediately prior to the scan
burst, the burst is suspended and will
cycle, both scan and instruction
resume with ICD exit.
execution happen after the ICD exits.
Scan cycle occurs before ICD entry
PC If Scanner would peek an instruction
and instruction execution happens
Breakpoint that is not executed (because of ICD
after the ICD exits. If PCPB (or single step) is on
entry), the peek will occur after ICD
exit, when the instruction executes. The instruction with the dataBP BSF(SCANCON.GO), the ICD is
executes and ICD entry occurs entered before execution; execution
Data
immediately after. If scan is of the burst will occur at ICD exit, and
Breakpoint
requested during that cycle, the scan the burst will run to completion.
cycle is postponed until the ICD exits.
If a scan cycle is ready after the Note that the burst can be interrupted
debug instruction is executed, the by an external halt.
Single Step
scan will read PFM and then the ICD
is re-entered.
If SWBP replaces
BSF(SCANCON.GO), the ICD will be
SWBP and If scan would stall a SWBP, the scan entered; instruction execution will
ICDINST cycle occurs and the ICD is entered. occur at ICD exit (from ICDINSTR
register), and the burst will run to
completion.

PIC16(L)F18857/77
11.11 Register Definitions: CRC and Scanner Control
REGISTER 11-1: CRCCON0: CRC CONTROL REGISTER 0

R/W-0/0 R/W-0/0 R-0 R/W-0/0 U-0 U-0 R/W-0/0 R-0
EN CRCGO BUSY ACCM — — SHIFTM FULL
bit 7 bit 0
Legend:
bit 7 EN: CRC Enable bit

1 = CRC module is released from Reset
0 = CRC is disabled and consumes no operating current
bit 6 CRCGO: CRC Start bit
1 = Start CRC serial shifter
0 = CRC serial shifter turned off
bit 5 BUSY: CRC Busy bit
1 = Shifting in progress or pending
0 = All valid bits in shifter have been shifted into accumulator and EMPTY = 1
bit 4 ACCM: Accumulator Mode bit
1 = Data is augmented with zeros
0 = Data is not augmented with zeros
bit 1 SHIFTM: Shift Mode bit
1 = Shift right (LSb)
0 = Shift left (MSb)
bit 0 FULL: Data Path Full Indicator bit
1 = CRCDATH/L registers are full
0 = CRCDATH/L registers have shifted their data into the shifter
REGISTER 11-2: CRCCON1: CRC CONTROL REGISTER 1

DLEN<3:0> PLEN<3:0>
bit 7 bit 0
Legend:
bit 7-4 DLEN<3:0>: Data Length bits

Denotes the length of the data word -1 (See Example 11-1)
bit 3-0 PLEN<3:0>: Polynomial Length bits
Denotes the length of the polynomial -1 (See Example 11-1)

PIC16(L)F18857/77
REGISTER 11-3: CRCDATH: CRC DATA HIGH BYTE REGISTER

R/W-xx R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x
DAT<15:8>
bit 7 bit 0
Legend:
bit 7-0 DAT<15:8>: CRC Input/Output Data bits
REGISTER 11-4: CRCDATL: CRC DATA LOW BYTE REGISTER

R/W-xx R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x
DAT<7:0>
bit 7 bit 0
Legend:
bit 7-0 DAT<7:0>: CRC Input/Output Data bits

Writing to this register fills the shifter.
REGISTER 11-5: CRCACCH: CRC ACCUMULATOR HIGH BYTE REGISTER

ACC<15:8>
bit 7 bit 0
Legend:
bit 7-0 ACC<15:8>: CRC Accumulator Register bits

Writing to this register writes to the CRC accumulator register. Reading from this register reads the CRC accumulator.
REGISTER 11-6: CRCACCL: CRC ACCUMULATOR LOW BYTE REGISTER

ACC<7:0>
bit 7 bit 0
Legend:
bit 7-0 ACC<7:0>: CRC Accumulator Register bits

Writing to this register writes to the CRC accumulator register through the CRC write bus. Reading from this register
reads the CRC accumulator.

PIC16(L)F18857/77
REGISTER 11-7: CRCSHIFTH: CRC SHIFT HIGH BYTE REGISTER

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
SHIFT<15:8>
bit 7 bit 0
Legend:
bit 7-0 SHIFT<15:8>: CRC Shifter Register bits

Reading from this register reads the CRC Shifter.
REGISTER 11-8: CRCSHIFTL: CRC SHIFT LOW BYTE REGISTER

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
SHIFT<7:0>
bit 7 bit 0
Legend:
bit 7-0 SHIFT<7:0>: CRC Shifter Register bits

Reading from this register reads the CRC Shifter.
REGISTER 11-9: CRCXORH: CRC XOR HIGH BYTE REGISTER

R/W R/W R/W R/W R/W R/W R/W R/W
X<15:8>
bit 7 bit 0
Legend:
bit 7-0 X<15:8>: XOR of Polynomial Term XN Enable bits
REGISTER 11-10: CRCXORL: CRC XOR LOW BYTE REGISTER

R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x U-1
X<7:1> —
bit 7 bit 0
Legend:
bit 7-1 XOR<7:1>: XOR of Polynomial Term XN Enable bits


PIC16(L)F18857/77
REGISTER 11-11: SCANCON0: SCANNER ACCESS CONTROL REGISTER 0

R/W-0/0 R/W/HC-0/0 R-0 R-0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
EN(1) SCANGO (2, 3)
BUSY (4)
INVALID INTM — MODE<1:0>(5)
bit 7 bit 0
Legend:
bit 7 EN: Scanner Enable bit(1)

1 = Scanner is enabled
0 = Scanner is disabled, internal states are reset
bit 6 SCANGO: Scanner GO bit(2, 3)
1 = When the CRC sends a ready signal, NVM will be accessed according to MDx and data passed
to the client peripheral.
0 = Scanner operations will not occur
bit 5 BUSY: Scanner Busy Indicator bit(4)
1 = Scanner cycle is in process
0 = Scanner cycle is complete (or never started)
bit 4 INVALID: Scanner Abort signal bit
1 = SCANLADRL/H has incremented or contains an invalid address(6)
0 = SCANLADRL/H points to a valid address
bit 3 INTM: NVM Scanner Interrupt Management Mode Select bit
If MODE = 10:
This bit is ignored
If MODE = 01 (CPU is stalled until all data is transferred):
1 = SCANGO is overridden (to zero) during interrupt operation; scanner resumes after returning from
interrupt
0 = SCANGO is not affected by interrupts, the interrupt response will be affected
If MODE = 00 or 11:
1 = SCANGO is overridden (to zero) during interrupt operation; scan operations resume after returning
from interrupt
0 = Interrupts do not prevent NVM access
bit 1-0 MODE<1:0>: Memory Access Mode bits(5)
11 = Triggered mode
10 = Peek mode
01 = Burst mode
00 = Concurrent mode
Note 1: Setting EN = 0 (SCANCON0 register) does not affect any other register content.
2: This bit is cleared when LADR > HADR (and a data cycle is not occurring).
3: If INTM = 1, this bit is overridden (to zero, but not cleared) during an interrupt response.
4: BUSY = 1 when the NVM is being accessed, or when the CRC sends a ready signal.
5: See Table 11-1 for more detailed information.
6: An invalid address happens when the entire range of the PFM is scanned and completed, i.e., device
memory is 0x4000 and SCANHADR = 0x3FFF, after the last scan SCANLADR increments to 0x4000, the
address is invalid.

PIC16(L)F18857/77
REGISTER 11-12: SCANLADRH: SCAN LOW ADDRESS HIGH BYTE REGISTER

LADR<15:8>(1,2)
bit 7 bit 0
Legend:
bit 7-0 LADR<15:8>: Scan Start/Current Address bits(1,2)

Most Significant bits of the current address to be fetched from, value increments on each fetch of
memory.
Note 1: Registers SCANLADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access;
registers should only be read or written while SCANGO = 0 (SCANCON0 register).
2: While SCANGO = 1 (SCANCON0 register), writing to this register is ignored.
REGISTER 11-13: SCANLADRL: SCAN LOW ADDRESS LOW BYTE REGISTER

LADR<7:0>(1,2)
bit 7 bit 0
Legend:
bit 7-0 LADR<7:0>: Scan Start/Current Address bits(1,2)

Least Significant bits of the current address to be fetched from, value increments on each fetch of
memory
Note 1: Registers SCANLADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access;

PIC16(L)F18857/77
REGISTER 11-14: SCANHADRH: SCAN HIGH ADDRESS HIGH BYTE REGISTER

HADR<15:8>(1,2)
bit 7 bit 0
Legend:
bit 7-0 HADR<15:8>: Scan End Address bits(1,2)

Most Significant bits of the address at the end of the designated scan
Note 1: Registers SCANHADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access;
REGISTER 11-15: SCANHADRL: SCAN HIGH ADDRESS LOW BYTE REGISTER

HADR<7:0>(1,2)
bit 7 bit 0
Legend:
bit 7-0 HADR<7:0>: Scan End Address bits(1,2)

Least Significant bits of the address at the end of the designated scan
Note 1: Registers SCANHADRH/L form a 16-bit value, but are not guarded for atomic or asynchronous access;

PIC16(L)F18857/77
REGISTER 11-16: SCANTRIG: SCAN TRIGGER SELECTION REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0

— — — — TSEL<3:0>
bit 7 bit 0
Legend:

bit 3-0 TSEL<3:0>: Scanner Data Trigger Input Selection bits
1111-1010 = Reserved
1001 = SMT2_Match
1000 = SMT1_Match
0111 = TMR5_Overflow
0110 = TMR4_postscaled
0001 = CLKR
0000 = LFINTOSC
TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH CRC

Register
on Page
CRCACCH ACC<15:8> 193
CRCACCL ACC<7:0> 193
CRCCON0 EN CRCGO BUSY ACCM — — SHIFTM FULL 192
CRCCON1 DLEN<3:0> PLEN<3:0> 192
CRCDATH DAT<15:8> 193
CRCDATL DAT<7:0> 193
CRCSHIFTH SHIFT<15:8> 194
CRCSHIFTL SHIFT<7:0> 194
CRCXORH XOR<15:8> 194
CRCXORL XOR<7:1> — 194
SCANCON0 EN SCANGO BUSY INVALID INTM — MODE<1:0> 195
SCANHADRH HADR<15:8> 197
SCANHADRL HADR<7:0> 197
SCANLADRH LADR<15:8> 196
SCANLADRL LADR<7:0> 196
SCANTRIG — — — — TSEL<3:0> 198
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the CRC module.
* Page provides register information.

PIC16(L)F18857/77
12.0 I/O PORTS Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
TABLE 12-1: PORT AVAILABILITY PER
simplified model of a generic I/O port, without the
DEVICE
interfaces to other peripherals, is shown in Figure 12-1.
PORTA
PORTB
PORTC
PORTD
PORTE
Device FIGURE 12-1: GENERIC I/O PORT
OPERATION
PIC16(L)F18857 ● ● ● ●
PIC16(L)F18877 ● ● ● ● ●
Each port has ten standard registers for its operation. Read LATx
TRISx
These registers are:
• PORTx registers (reads the levels on the pins of D Q
the device) Write LATx

Write PORTx
• LATx registers (output latch) CK VDD
• TRISx registers (data direction) Data Register
• ANSELx registers (analog select)
• WPUx registers (weak pull-up) Data Bus
• INLVLx (input level control) I/O pin

Read PORTx
• SLRCONx registers (slew rate)
To digital peripherals
• ODCONx registers (open-drain) VSS
ANSELx
Most port pins share functions with device peripherals, To analog peripherals
both analog and digital. In general, when a peripheral
is enabled on a port pin, that pin cannot be used as a
general purpose output; however, the pin can still be 12.1 I/O Priorities
read.
Each pin defaults to the PORT data latch after Reset.
The Data Latch (LATx registers) is useful for Other functions are selected with the peripheral pin
read-modify-write operations on the value that the I/O select logic. See Section 13.0 “Peripheral Pin Select
pins are driving. (PPS) Module” for more information.
A write operation to the LATx register has the same Analog input functions, such as ADC and comparator
effect as a write to the corresponding PORTx register. inputs, are not shown in the peripheral pin select lists.
A read of the LATx register reads of the values held in These inputs are active when the I/O pin is set for
the I/O PORT latches, while a read of the PORTx Analog mode using the ANSELx register. Digital output
register reads the actual I/O pin value. functions may continue to control the pin when it is in
Ports that support analog inputs have an associated Analog mode.
ANSELx register. When an ANSEL bit is set, the digital Analog outputs, when enabled, take priority over the
input buffer associated with that bit is disabled. digital outputs and force the digital output driver to the
high-impedance state.

PIC16(L)F18857/77
12.2 PORTA Registers 12.2.3 OPEN-DRAIN CONTROL
The ODCONA register (Register 12-6) controls the
12.2.1 DATA REGISTER open-drain feature of the port. Open-drain operation is
PORTA is an 8-bit wide, bidirectional port. The independently selected for each pin. When an
corresponding data direction register is TRISA ODCONA bit is set, the corresponding port output
(Register 12-2). Setting a TRISA bit (= 1) will make the becomes an open-drain driver capable of sinking
corresponding PORTA pin an input (i.e., disable the current only. When an ODCONA bit is cleared, the
output driver). Clearing a TRISA bit (= 0) will make the corresponding port output pin is the standard push-pull
corresponding PORTA pin an output (i.e., enables drive capable of sourcing and sinking current.
output driver and puts the contents of the output latch
on the selected pin). Example 12.2.8 shows how to
initialize PORTA. Note: It is not necessary to set open-drain
control when using the pin for I2C; the I2C
Reading the PORTA register (Register 12-1) reads the
module controls the pin and makes the pin
status of the pins, whereas writing to it will write to the
open-drain.
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then 12.2.4 SLEW RATE CONTROL
written to the PORT data latch (LATA). The SLRCONA register (Register 12-7) controls the
The PORT data latch LATA (Register 12-3) holds the slew rate option for each port pin. Slew rate control is
output port data, and contains the latest value of a independently selectable for each port pin. When an
LATA or PORTA write. SLRCONA bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONA bit is cleared,
EXAMPLE 12-1: INITIALIZING PORTA The corresponding port pin drive slews at the maximum
; This code example illustrates
rate possible.
; initializing the PORTA register. The
; other ports are initialized in the same
; manner.
BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
BANKSEL LATA ;Data Latch
CLRF LATA ;
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW B'00111000' ;Set RA<5:3> as inputs
MOVWF TRISA ;and set RA<2:0> as
;outputs
12.2.2 DIRECTION CONTROL

The TRISA register (Register 12-2) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
inputs always read ‘0’.

PIC16(L)F18857/77
12.2.5 INPUT THRESHOLD CONTROL
The INLVLA register (Register 12-8) controls the input
voltage threshold for each of the available PORTA input
pins. A selection between the Schmitt Trigger CMOS or
the TTL Compatible thresholds is available. The input
threshold is important in determining the value of a read
of the PORTA register and also the level at which an
interrupt-on-change occurs, if that feature is enabled.
See Table 37-4 for more information on threshold
levels.
Note: Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
12.2.6 ANALOG CONTROL

The ANSELA register (Register 12-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with its TRIS bit clear and its
ANSEL bit set will still operate as a digital output, but
the Input mode will be analog. This can cause
unexpected behavior when executing
read-modify-write instructions on the affected port.
Note: The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
12.2.7 WEAK PULL-UP CONTROL

The WPUA register (Register 12-5) controls the
individual weak pull-ups for each PORT pin.
12.2.8 PORTA FUNCTIONS AND OUTPUT

PRIORITIES
Each PORTA pin is multiplexed with other functions.
Each pin defaults to the PORT latch data after Reset.
Other output functions are selected with the peripheral
pin select logic or by enabling an analog output, such
as the DAC. See Section 13.0 “Peripheral Pin Select
(PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs are not shown in the peripheral pin select lists.
Digital output functions may continue to control the pin
when it is in Analog mode.

PIC16(L)F18857/77
12.3 Register Definitions: PORTA
REGISTER 12-1: PORTA: PORTA REGISTER

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
bit 7-0 RA<7:0>: PORTA I/O Value bits(1)

1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-2: TRISA: PORTA TRI-STATE REGISTER

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output

PIC16(L)F18857/77
REGISTER 12-3: LATA: PORTA DATA LATCH REGISTER

LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0
bit 7 bit 0
Legend:
bit 7-0 LATA<7:0>: RA<7:0> Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-4: ANSELA: PORTA ANALOG SELECT REGISTER

ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0
bit 7 bit 0
Legend:
bit 7-0 ANSA<7:0>: Analog Select between Analog or Digital Function on pins RA<7:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.

PIC16(L)F18857/77
REGISTER 12-5: WPUA: WEAK PULL-UP PORTA REGISTER

WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0
bit 7 bit 0
Legend:
bit 7-0 WPUA<7:0>: Weak Pull-up Register bits(1)

1 = Pull-up enabled
0 = Pull-up disabled
Note 1: The weak pull-up device is automatically disabled if the pin is configured as an output.
REGISTER 12-6: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER

ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0
bit 7 bit 0
Legend:
bit 7-0 ODCA<7:0>: PORTA Open-Drain Enable bits

For RA<7:0> pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)

PIC16(L)F18857/77
REGISTER 12-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER

SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0
bit 7 bit 0
Legend:
bit 7-0 SLRA<7:0>: PORTA Slew Rate Enable bits

1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
REGISTER 12-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER

INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
bit 7 bit 0
Legend:
bit 7-0 INLVLA<7:0>: PORTA Input Level Select bits

1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change

PIC16(L)F18857/77
TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Register
on Page
PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 202
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 202
LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 203
ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 203
WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 204
ODCONA ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 204
SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 205
INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 205
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTA.

PIC16(L)F18857/77
12.4 PORTB Registers 12.4.3 OPEN-DRAIN CONTROL
The ODCONB register (Register 12-14) controls the
PORTB is an 8-bit wide, bidirectional port. The independently selected for each pin. When an
corresponding data direction register is TRISB ODCONB bit is set, the corresponding port output
(Register 12-10). Setting a TRISB bit (= 1) will make becomes an open-drain driver capable of sinking
the corresponding PORTB pin an input (i.e., disable the current only. When an ODCONB bit is cleared, the
output driver). Clearing a TRISB bit (= 0) will make the corresponding port output pin is the standard push-pull
corresponding PORTB pin an output (i.e., enables drive capable of sourcing and sinking current.
on the selected pin). Example 12.2.8 shows how to
initialize PORTB. Note: It is not necessary to set open-drain
Reading the PORTB register (Register 12-9) reads the
open-drain.
port pins are read, this value is modified and then 12.4.4 SLEW RATE CONTROL
written to the PORT data latch (LATB). The SLRCONB register (Register 12-15) controls the
The PORT data latch LATB (Register 12-11) holds the slew rate option for each port pin. Slew rate control is
output port data, and contains the latest value of a independently selectable for each port pin. When an
LATB or PORTB write. SLRCONB bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONB bit is cleared,
EXAMPLE 12-2: INITIALIZING PORTA The corresponding port pin drive slews at the maximum
; This code example illustrates
rate possible.
; initializing the PORTA register. The
; other ports are initialized in the same
; manner.
BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
BANKSEL LATA ;Data Latch
CLRF LATA ;
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW B'00111000' ;Set RA<5:3> as inputs
MOVWF TRISA ;and set RA<2:0> as
;outputs

The TRISB register (Register 12-10) controls the
PORTB pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISB register are maintained set when using
them as analog inputs. I/O pins configured as analog
inputs always read ‘0’.

PIC16(L)F18857/77
The INLVLB register (Register 12-8) controls the input
voltage threshold for each of the available PORTB input
pins. A selection between the Schmitt Trigger CMOS or
the TTL Compatible thresholds is available. The input
threshold is important in determining the value of a read
of the PORTB register and also the level at which an
interrupt-on-change occurs, if that feature is enabled.
See Table 37-4 for more information on threshold
levels.
that pin.
12.4.6 ANALOG CONTROL

The ANSELB register (Register 12-4) is used to
Setting the appropriate ANSELA bit high will cause all
The state of the ANSELB bits has no effect on digital
output functions. A pin with its TRIS bit clear and its
ANSEL bit set will still operate as a digital output, but
the Input mode will be analog. This can cause
unexpected behavior when executing
read-modify-write instructions on the affected port.
Note: The ANSELB bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits

The WPUB register (Register 12-5) controls the
individual weak pull-ups for each PORT pin.
12.4.8 PORTA FUNCTIONS AND OUTPUT

PRIORITIES
Each PORTB pin is multiplexed with other functions.
pin select logic or by enabling an analog output, such
as the DAC. See Section 13.0 “Peripheral Pin Select
(PPS) Module” for more information.
inputs are not shown in the peripheral pin select lists.

PIC16(L)F18857/77
12.5 Register Definitions: PORTB
REGISTER 12-9: PORTB: PORTB REGISTER

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
bit 7 bit 0
Legend:
bit 7-0 RB<7:0>: PORTB I/O Value bits(1)

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
REGISTER 12-10: TRISB: PORTB TRI-STATE REGISTER

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
bit 7 bit 0
Legend:
bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit

1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output

PIC16(L)F18857/77
REGISTER 12-11: LATB: PORTB DATA LATCH REGISTER

LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
bit 7 bit 0
Legend:
bit 7-0 LATB<7:0>: RB<7:0> Output Latch Value bits(1)
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
REGISTER 12-12: ANSELB: PORTB ANALOG SELECT REGISTER

ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0
bit 7 bit 0
Legend:
bit 7-0 ANSB<7:0>: Analog Select between Analog or Digital Function on pins RB<7:0>, respectively

PIC16(L)F18857/77
REGISTER 12-13: WPUB: WEAK PULL-UP PORTB REGISTER

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
Legend:
bit 7-0 WPUB<7:0>: Weak Pull-up Register bits(1)

1 = Pull-up enabled
REGISTER 12-14: ODCONB: PORTB OPEN-DRAIN CONTROL REGISTER

ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0
bit 7 bit 0
Legend:
bit 7-0 ODCB<7:0>: PORTB Open-Drain Enable bits

For RB<7:0> pins, respectively

PIC16(L)F18857/77
REGISTER 12-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER

SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0
bit 7 bit 0
Legend:
bit 7-0 SLRB<7:0>: PORTB Slew Rate Enable bits

REGISTER 12-16: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER

INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0
bit 7 bit 0
Legend:
bit 7-0 INLVLB<7:0>: PORTB Input Level Select bits


PIC16(L)F18857/77
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Register
on Page
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 209
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 209
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 210
ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 210
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 211
ODCONB ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 211
SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 212
INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 212
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTB.

PIC16(L)F18857/77
12.6 PORTC Registers 12.6.4 OPEN-DRAIN CONTROL
The ODCONC register (Register 12-22) controls the
PORTC is an 8-bit wide bidirectional port. The independently selected for each pin. When an
corresponding data direction register is TRISC ODCONC bit is set, the corresponding port output
(Register 12-18). Setting a TRISC bit (= 1) will make the becomes an open-drain driver capable of sinking
corresponding PORTC pin an input (i.e., put the current only. When an ODCONC bit is cleared, the
corresponding output driver in a High-Impedance mode). corresponding port output pin is the standard push-pull
Clearing a TRISC bit (= 0) will make the corresponding drive capable of sourcing and sinking current.
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12.2.8 shows how to initialize an I/O port. Note: It is not necessary to set open-drain
Reading the PORTC register (Register 12-17) reads the
open-drain.
port pins are read, this value is modified and then written 12.6.5 SLEW RATE CONTROL
to the PORT data latch (LATC). The SLRCONC register (Register 12-23) controls the
The PORT data latch LATC (Register 12-19) holds the slew rate option for each port pin. Slew rate control is
output port data, and contains the latest value of a LATC independently selectable for each port pin. When an
or PORTC write. SLRCONC bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONC bit is cleared,
12.6.2 DIRECTION CONTROL The corresponding port pin drive slews at the maximum
rate possible.
The TRISC register (Register 12-18) controls the
PORTC pin output drivers, even when they are being 12.6.6 ANALOG CONTROL
used as analog inputs. The user should ensure the bits in
the TRISC register are maintained set when using them The ANSELC register (Register 12-20) is used to
as analog inputs. I/O pins configured as analog inputs configure the Input mode of an I/O pin to analog.
always read ‘0’. Setting the appropriate ANSELC bit high will cause all
12.6.3 INPUT THRESHOLD CONTROL analog functions on the pin to operate correctly.
The INLVLC register (Register 12-24) controls the input The state of the ANSELC bits has no effect on digital out-
voltage threshold for each of the available PORTC put functions. A pin with TRIS clear and ANSELC set will
input pins. A selection between the Schmitt Trigger still operate as a digital output, but the Input mode will be
CMOS or the TTL Compatible thresholds is available. analog. This can cause unexpected behavior when exe-
The input threshold is important in determining the cuting read-modify-write instructions on the affected
value of a read of the PORTC register and also the port.
level at which an interrupt-on-change occurs, if that Note: The ANSELC bits default to the Analog
feature is enabled. See Table 37-4 for more information mode after Reset. To use any pins as
on threshold levels. digital general purpose or peripheral
Note: Changing the input threshold selection inputs, the corresponding ANSEL bits
should be performed while all peripheral must be initialized to ‘0’ by user software.
threshold level during the time a module is 12.6.7 WEAK PULL-UP CONTROL
active may inadvertently generate a The WPUC register (Register 12-21) controls the
transition associated with an input pin, individual weak pull-ups for each port pin.
that pin. 12.6.8 PORTC FUNCTIONS AND OUTPUT
PRIORITIES
pin select logic. See Section 13.0 “Peripheral Pin
Select (PPS) Module” for more information.
inputs, are not shown in the peripheral pin select lists.

PIC16(L)F18857/77
12.7 Register Definitions: PORTC
REGISTER 12-17: PORTC: PORTC REGISTER

RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits(1)

Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
REGISTER 12-18: TRISC: PORTC TRI-STATE REGISTER

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
REGISTER 12-19: LATC: PORTC DATA LATCH REGISTER

LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
bit 7 bit 0
Legend:
bit 7-0 LATC<7:0>: PORTC Output Latch Value bits

PIC16(L)F18857/77
REGISTER 12-20: ANSELC: PORTC ANALOG SELECT REGISTER

ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0
bit 7 bit 0
Legend:
bit 7-0 ANSC<7:0>: Analog Select between Analog or Digital Function on Pins RC<7:0>, respectively(1)
REGISTER 12-21: WPUC: WEAK PULL-UP PORTC REGISTER

WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0
bit 7 bit 0
Legend:
bit 7-0 WPUC<7:0>: Weak Pull-up Register bits(1)

1 = Pull-up enabled

PIC16(L)F18857/77
REGISTER 12-22: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER

ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0
bit 7 bit 0
Legend:
bit 7-0 ODCC<7:0>: PORTC Open-Drain Enable bits

For RC<7:0> pins, respectively
REGISTER 12-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER

SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0
bit 7 bit 0
Legend:
bit 7-0 SLRC<7:0>: PORTC Slew Rate Enable bits

REGISTER 12-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER

INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
bit 7 bit 0
Legend:
bit 7-0 INLVLC<7:0>: PORTC Input Level Select bits


PIC16(L)F18857/77
TABLE 12-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Register
on Page
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 215
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 215
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 215
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 216
WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 216
ODCONC ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 217
SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 217
INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 217
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

PIC16(L)F18857/77
12.8 PORTD Registers 12.8.4 OPEN-DRAIN CONTROL
(PIC16(L)F18877 only) The ODCOND register (Register 12-30) controls the
open-drain feature of the port. Open-drain operation is
12.8.1 DATA REGISTER CONTROL independently selected for each pin. When an
PORTD is an 8-bit wide bidirectional port. The ODCOND bit is set, the corresponding port output
corresponding data direction register is TRISD becomes an open-drain driver capable of sinking
(Register 12-26). Setting a TRISD bit (= 1) will make the current only. When an ODCOND bit is cleared, the
corresponding PORTC pin an input (i.e., put the corresponding port output pin is the standard push-pull
corresponding output driver in a High-Impedance mode). drive capable of sourcing and sinking current.
Clearing a TRISD bit (= 0) will make the corresponding
PORTD pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin). Note: It is not necessary to set open-drain
Example 12.2.8 shows how to initialize an I/O port. control when using the pin for I2C; the I2C
Reading the PORTD register (Register 12-25) reads the open-drain.
12.8.5 SLEW RATE CONTROL
port pins are read, this value is modified and then written The SLRCOND register (Register 12-31) controls the
to the PORT data latch (LATD). slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
The PORT data latch LATD (Register 12-27) holds the
SLRCOND bit is set, the corresponding port pin drive is
output port data, and contains the latest value of a LATD
slew rate limited. When an SLRCOND bit is cleared,
or PORTD write.
The corresponding port pin drive slews at the maximum
rate possible.
The TRISD register (Register 12-26) controls the 12.8.6 ANALOG CONTROL
PORTD pin output drivers, even when they are being
The ANSELD register (Register 12-28) is used to
the TRISD register are maintained set when using them
Setting the appropriate ANSELD bit high will cause all
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
12.8.3 INPUT THRESHOLD CONTROL The state of the ANSELD bits has no effect on digital out-
put functions. A pin with TRIS clear and ANSELD set will
The INLVLD register (Register 12-32) controls the input
still operate as a digital output, but the Input mode will be
voltage threshold for each of the available PORTD
analog. This can cause unexpected behavior when exe-
input pins. A selection between the Schmitt Trigger
cuting read-modify-write instructions on the affected
CMOS or the TTL Compatible thresholds is available.
port.
The input threshold is important in determining the
value of a read of the PORTD register and also the Note: The ANSELD bits default to the Analog
level at which an interrupt-on-change occurs, if that mode after Reset. To use any pins as
feature is enabled. See Table 37-4 for more information digital general purpose or peripheral
on threshold levels. inputs, the corresponding ANSEL bits
threshold level during the time a module is The WPUD register (Register 12-29) controls the
active may inadvertently generate a individual weak pull-ups for each port pin.
12.8.8 PORTD FUNCTIONS AND OUTPUT
that pin. PRIORITIES

PIC16(L)F18857/77
12.9 Register Definitions: PORTD
REGISTER 12-25: PORTD: PORTD REGISTER

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
bit 7 bit 0
Legend:
bit 7-0 RD<7:0>: PORTD I/O Value bits(1)

Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is
REGISTER 12-26: TRISD: PORTD TRI-STATE REGISTER

TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
bit 7 bit 0
Legend:
bit 7-0 TRISD<7:0>: TRISD Tri-State Control bits

1 = PORTD pin configured as an input (tri-stated)
0 = PORTD pin configured as an output

PIC16(L)F18857/77
REGISTER 12-27: LATD: PORTD TRI-STATE REGISTER

LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0
bit 7 bit 0
Legend:
bit 7-0 LATD<7:0>: LATD Output Latch Value bits
REGISTER 12-28: ANSELD: PORTD TRI-STATE REGISTER

ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0
bit 7 bit 0
Legend:
bit 7-0 ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RC<7:0>, respectively
allow external control of the voltage on the pin.0

PIC16(L)F18857/77
REGISTER 12-29: WPUD: WEAK PULL-UP PORTD REGISTER

WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0
bit 7 bit 0
Legend:
bit 7-0 WPUD<7:0>: Weak Pull-up Register

1 = Pull-up enabled
REGISTER 12-30: ODCOND: PORTD OPEN-DRAIN CONTROL REGISTER

ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0
bit 7 bit 0
Legend:
bit 7-0 ODCD<7:0>: PORTD Open-Drain Enable bits

For RD<7:0> pins, respectively

PIC16(L)F18857/77
REGISTER 12-31: SLRCOND: PORTD SLEW RATE CONTROL REGISTER

SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0
bit 7 bit 0
Legend:
bit 7-0 SLRD<7:0>: PORTD Slew Rate Enable bits

REGISTER 12-32: INLVLD: PORTD INPUT LEVEL CONTROL REGISTER

INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0
bit 7 bit 0
Legend:
bit 7-0 INLVLD<7:0>: PORTD Input Level Select bits

TABLE 12-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1)

Register
on Page
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 220
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 220
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 221
ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 221
WPUD WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 222
ODCOND ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 222
SLRCOND SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 223
INLVLD INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 223
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.
Note 1: PIC16(L)F18877 only.

PIC16(L)F18857/77
12.10 PORTE Registers
(PIC16(L)F18857)
12.10.1 DATA REGISTER
PORTE is a 1-bit wide, input-only port.
Reading the PORTE register (Register 12-33) reads
the status of the pins, whereas writing to it will write to
the PORT latch. All write operations are
read-modify-write operations. Since RE3 is input-only,
writes to the PORTE register on this device will have no
effect.

The INLVLE register (Register 12-35) controls the input
voltage threshold for each of the available PORTE
The input threshold is important in determining the
value of a read of the PORTE register and also the level
at which an interrupt-on-change occurs, if that feature
is enabled. See Table 37-4 for more information on
threshold levels.
that pin.

The WPUE register (Register 12-34) controls the
individual weak pull-ups for each port pin.
12.10.4 PORTE FUNCTIONS AND OUTPUT

PRIORITIES

PIC16(L)F18857/77
12.11 Register Definitions: PORTE (PIC16(L)F18857)
REGISTER 12-33: PORTE: PORTE REGISTER

U-0 U-0 U-0 U-0 R-x/u U-0 U-0 U-0
— — — — RE3 — — —
bit 7 bit 0
Legend:

bit 3 RE<3>: PORTE Input Pin bit
REGISTER 12-34: WPUE: WEAK PULL-UP PORTE REGISTER

U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0
— — — — WPUE3 — — —
bit 7 bit 0
Legend:

bit 3 WPUE3: Weak Pull-up Register bit(1)
1 = Pull-up enabled

PIC16(L)F18857/77
REGISTER 12-35: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER

U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0
— — — — INLVLE3 — — —
bit 7 bit 0
Legend:

bit 3 INLVLE3: PORTE Input Level Select bits
For RE3 pin,
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Register
on Page
PORTE — — — — RE3 — — — 225

WPUE — — — — WPUE3 — — — 225
INLVLE — — — — INLVLE3 — — — 226
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
TABLE 12-7: SUMMARY OF CONFIGURATION WORD WITH PORTE

Register
on Page
13:8 — — DEBUG STVREN PPS1WAY ZCDDIS BORV —
CONFIG2 92
7:0 BOREN<1:0> LPBOREN — — — PWRTE MCLRE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTE.

PIC16(L)F18857/77
12.12 PORTE Registers 12.12.4 OPEN-DRAIN CONTROL
(PIC16(L)F18877) The ODCONE register (Register 12-41) controls the
open-drain feature of the port. Open-drain operation is
12.12.1 DATA REGISTER independently selected for each pin. When an
PORTE is a 4-bit wide, bidirectional port. The ODCONE bit is set, the corresponding port output
corresponding data direction register is TRISE becomes an open-drain driver capable of sinking
(Register 12-37). Setting a TRISE bit (= 1) will make current only. When an ODCONE bit is cleared, the
the corresponding PORTE pin an input (i.e., disable the corresponding port output pin is the standard push-pull
output driver). Clearing a TRISE bit (= 0) will make the drive capable of sourcing and sinking current.
corresponding PORTE pin an output (i.e., enables
on the selected pin). Example 12.2.8 shows how to Note: It is not necessary to set open-drain
initialize PORTE. control when using the pin for I2C; the I2C
Reading the PORTE register (Register 12-36) reads open-drain.
the status of the pins, whereas writing to it will write to
the PORT latch. All write operations are
12.12.5 SLEW RATE CONTROL
read-modify-write operations. Therefore, a write to a
port implies that the port pins are read, this value is The SLRCONE register (Register 12-42) controls the
modified and then written to the PORT data latch slew rate option for each port pin. Slew rate control is
(LATE). independently selectable for each port pin. When an
SLRCONE bit is set, the corresponding port pin drive is
The PORT data latch LATE (Register 12-38) holds the
slew rate limited. When an SLRCONE bit is cleared,
output port data, and contains the latest value of a
The corresponding port pin drive slews at the maximum
LATE or PORTE write.
rate possible.
12.12.2 DIRECTION CONTROL 12.12.6 ANALOG CONTROL
The TRISE register (Register 12-37) controls the
The ANSELE register (Register 12-39) is used to
PORTE pin output drivers, even when they are being
Setting the appropriate ANSELE bit high will cause all
the TRISE register are maintained set when using them
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
The state of the ANSELE bits has no effect on digital out-
12.12.3 INPUT THRESHOLD CONTROL put functions. A pin with TRIS clear and ANSELE set will
still operate as a digital output, but the Input mode will be
The INLVLE register (Register 12-43) controls the input
analog. This can cause unexpected behavior when exe-
voltage threshold for each of the available PORTE
cuting read-modify-write instructions on the affected
port.
The input threshold is important in determining the Note: The ANSELC bits default to the Analog
value of a read of the PORTE register and also the level mode after Reset. To use any pins as
at which an interrupt-on-change occurs, if that feature digital general purpose or peripheral
is enabled. See Table 37-4 for more information on inputs, the corresponding ANSEL bits
threshold levels. must be initialized to ‘0’ by user software.
modules are disabled. Changing the The WPUE register (Register 12-40) controls the
threshold level during the time a module is individual weak pull-ups for each port pin.
regardless of the actual voltage level on PRIORITIES
that pin. Each pin defaults to the PORT latch data after Reset.

PIC16(L)F18857/77
PRIORITIES

PIC16(L)F18857/77
12.13 Register Definitions: PORTE (PIC16(L)F18877)
REGISTER 12-36: PORTE: PORTE REGISTER

U-0 U-0 U-0 U-0 R-x/u R/W-x/u R/W-x/u R/W-x/u
— — — — RE3 RE2 RE1 RE0
bit 7 bit 0
Legend:

bit 3-0 RE<3:0>: PORTE Input Pin bit
Note 1: Writes to RE<2:0> are actually written to the corresponding LATE register. Reads from the PORTE regis-
ter is the return of actual I/O pin values.
REGISTER 12-37: TRISE: PORTE TRI-STATE REGISTER

U-0 U-0 U-0 U-0 U-1(1) R/W-1/1 R/W-1/1 R/W-1/1
— — — — — TRISE2 TRISE1 TRISE0
bit 7 bit 0
Legend:
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

bit 2-0 TRISE<2:0>: PORTE Tri-State Control bits
1 = PORTE pin configured as an input
0 = PORTE pin configured as an output

PIC16(L)F18857/77
REGISTER 12-38: LATE: PORTE DATA LATCH REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u
— — — — — LATE2 LATE1 LATE0
bit 7 bit 0
Legend:

bit 2-0 LATE<2:0>: PORTE Output Latch Value bits(1)
Note 1: Writes to PORTE are actually written to the corresponding LATE register. Reads from the PORTE register
is return of actual I/O pin values.
REGISTER 12-39: ANSELE: PORTE ANALOG SELECT REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — — — — ANSE2 ANSE1 ANSE0
bit 7 bit 0
Legend:

bit 2-0 ANSE<2:0>: Analog Select between Analog or Digital Function on pins RE<2:0>, respectively

PIC16(L)F18857/77
REGISTER 12-40: WPUE: WEAK PULL-UP PORTE REGISTER

U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — — — WPUE3 WPUE2 WPUE1 WPUE0
bit 7 bit 0
Legend:

bit 3-0 WPUE<3:0> Weak Pull-up Register bit(1)
1 = Pull-up enabled
REGISTER 12-41: ODCONE: PORTE OPEN-DRAIN CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — ODCE2 ODCE1 ODCE0
bit 7 bit 0
Legend:

bit 2-0 ODCE<2:0>: PORTE Open-Drain Enable bits
For RE<2:0> pins, respectively

PIC16(L)F18857/77
REGISTER 12-42: SLRCONE: PORTE SLEW RATE CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — — — — SLRE2 SLRE1 SLRE0
bit 7 bit 0
Legend:

bit 2-0 SLRE<2:0>: PORTE Slew Rate Enable bits
REGISTER 12-43: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER

U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — — — INLVLE3 INLVLE2 INLVLE1 INLVLE0
bit 7 bit 0
Legend:

bit 3-0 INLVLE<3:0>: PORTE Input Level Select bits

PIC16(L)F18857/77
TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE(1)

Register
on Page
PORTE — — — — RE3 RE2 RE1 RE0 220

TRISE — — — — —(1) TRISE2 TRISE1 TRISE0 220
LATE — — — — — LATE2 LATE1 LATE0 221
ANSELE — — — — — ANSE2 ANSE1 ANSE0 221
WPUE — — — — WPUE3 WPUE2 WPUE1 WPUE0 222
ODCONE — — — — — ODCE2 ODCE1 ODCE0 222
SLRCONE — — — — — SLRE2 SLRE1 SLRE0 223
INLVLE — — — — INLVLE3 INLVLE2 INLVLE1 INLVLE0 223
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
TABLE 12-9: SUMMARY OF CONFIGURATION WORD WITH PORTE

Register
on Page
13:8 — — DEBUG STVREN PPS1WAY ZCDDIS BORV —
CONFIG2 92
7:0 BOREN<1:0> LPBOREN — — — PWRTE MCLRE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTE.

PIC16(L)F18857/77
13.0 PERIPHERAL PIN SELECT
(PPS) MODULE
The Peripheral Pin Select (PPS) module connects
peripheral inputs and outputs to the device I/O pins.
Only digital signals are included in the selections. All
analog inputs and outputs remain fixed to their
assigned pins. Input and output selections are
independent as shown in the simplified block diagram
Figure 13-1.
TABLE 13-1: PPS INPUT SIGNAL ROUTING OPTIONS

Remappable to Pins of PORTx
Default
Input Signal Input Register
Location PIC16F18857 PIC16F18877
Name Name
at POR
PORTA PORTB PORTC PORTA PORTB PORTC PORTD PORTE
INT INTPPS RB0    
T0CKI T0CKIPPS RA4    
T1CKI T1CKIPPS RC0    
T1G T1GPPS RB5    
T3G T3GPPS RC0    
T5G T5GPPS RB4    
T2IN T2AINPPS RC3    
T4IN T4AINPPS RC5    
T6IN T6AINPPS RB7    
CCP1 CCP1PPS RC2    
CCP2 CCP2PPS RC1    
CCP3 CCP3PPS RB5    
CCP4 CCP4PPS RB0    
CCP5 CCP5PPS RA4    
SMTWIN1 SMT1WINPPS RC0   
SMTSIG1 SMT1SIGPPS RC1   
SMTWIN2 SMT2WINPPS RB4    
SMTSIG2 SMT2SIGPPS RB5    
CWG1IN CWG1PPS RB0    
MDCARL MDCARLPPS RA3    
MDCARH MDCARHPPS RA4    
MDMSRC MDSRCPPS RA5    
CLCIN0 CLCIN0PPS RA0    
CLCIN1 CLCIN1PPS RA1    
CLCIN2 CLCIN2PPS RB6    

PIC16(L)F18857/77
TABLE 13-1: PPS INPUT SIGNAL ROUTING OPTIONS (CONTINUED)
Input Signal Input Register Default
Location PIC16F18857 PIC16F18877
Name Name
at POR
CLCIN3 CLCIN3PPS RB7    
ADCACT ADCACTPPS RB4    
SCK1/SCL1 SSP1CLKPPS RC3    
SDI1/SDA1 SSP1DATPPS RC4    
SS1 SSP1SSPPS RA5    
SCK2/SCL2 SSP2CLKPPS RB1    
SDI2/SDA2 SSP2DATPPS RB2    
SS2 SSP2SSPPS RB0    
RX/DT RXPPS RC7    
CK TXPPS RC6    

PIC16(L)F18857/77
TABLE 13-2: PPS INPUT REGISTER VALUES

Desired Input Pin Value to Write to Register(1)
RA0 0x00
RA1 0x01
RA2 0x02
RA3 0x03
RA4 0x04
RA5 0x05
RA6 0x06
RA7 0x07
RB0 0x08
RB1 0x09
RB2 0x0A
RB3 0x0B
RB4 0x0C
RB5 0x0D
RB6 0x0E
RB7 0x0F
RC0 0x10
RC1 0x11
RC2 0x12
RC3 0x13
RC4 0x14
RC5 0x15
RC6 0x16
RC7 0x17
RD0 0x18
RD1 0x19
RD2 0x1A
RD3 0x1B
RD4 0x1C
RD5 0x1D
RD6 0x1E
RD7 0x1F
RE0 0x20
RE1 0x21
RE2 0x22
RE3 0x23
Note 1: Only a few of the values in this column are valid for any given
signal. For example, since the INT signal can only be
mapped to PORTA or PORTB pins, only the register values
0x00-0x0F (corresponding to RA<7:0> and RB<7:0>) are
valid values to write to the INTPPS register.

PIC16(L)F18857/77
13.1 PPS Inputs 13.2 PPS Outputs
Each peripheral has a PPS register with which the Each I/O pin has a PPS register with which the pin
inputs to the peripheral are selected. Inputs include the output source is selected. With few exceptions, the port
device pins. TRIS control associated with that pin retains control
Although every peripheral has its own PPS input over the pin output driver. Peripherals that control the
selection register, the selections are identical for every pin output driver as part of the peripheral operation will
peripheral as shown in Register 13-1.. override the TRIS control as needed. These
peripherals include:
Note: The notation “xxx” in the register name is
• EUSART (synchronous operation)
a place holder for the peripheral identifier.
For example, CLC1PPS. • MSSP (I2C)
Although every pin has its own PPS peripheral
selection register, the selections are identical for every
pin as shown in Register 13-2.
Note: The notation “Rxy” is a place holder for the
pin port and bit identifiers. For example, x
and y for PORTA bit 0 would be A and 0,
respectively, resulting in the pin PPS
output selection register RA0PPS.
FIGURE 13-1: SIMPLIFIED PPS BLOCK DIAGRAM

PPS Outputs
RA0PPS
PPS Inputs
abcPPS RA0
RA0
Peripheral abc
RxyPPS
Rxy
Peripheral xyz
RE2(1) R E2PPS(1)
xyzPPS RE2(1)
Note 1: RD<7:0> and RE<2:0> are only implemented on the 40/44-pin devices.
RE3 is PPS input capable only (when MLCR is disabled).

PIC16(L)F18857/77
13.3 Bidirectional Pins 13.5 PPS Permanent Lock
PPS selections for peripherals with bidirectional The PPS can be permanently locked by setting the
signals on a single pin must be made so that the PPS PPS1WAY Configuration bit. When this bit is set, the
input and PPS output select the same pin. Peripherals PPSLOCKED bit can only be cleared and set one time
that have bidirectional signals include: after a device Reset. This allows for clearing the
• EUSART (synchronous operation) PPSLOCKED bit so that the input and output selections
can be made during initialization. When the
• MSSP (I2C)
PPSLOCKED bit is set after all selections have been
made, it will remain set and cannot be cleared until after
the next device Reset event.
Note: The I2C SCLx and SDAx functions can be
remapped through PPS. However, only
the RB1, RB2, RC3 and RC4 pins have 13.6 Operation During Sleep
the I2C and SMBus specific input buffers PPS input and output selections are unaffected by
implemented (which have different Sleep.
thresholds compared to the normal
ST/TTL input levels of the other general
purpose I/O pins). If the SCLx or SDAx
13.7 Effects of a Reset
functions are mapped to some other pin A device Power-On-Reset (POR) clears all PPS input
(other than RB1, RB2, RC3 or RC4), the and output selections to their default values. All other
general purpose TTL or ST input buffers Resets leave the selections unchanged. Default input
(as configured based on INLVL register selections are shown in pin allocation Table 13-1 and
setting) will be used instead. In most Table 13-2.
applications, it is therefore recommended
only to map the SCLx and SDAx pin
functions to the RB1, RB2, RC3 or RC4
pins.
13.4 PPS Lock

The PPS includes a mode in which all input and output
selections can be locked to prevent inadvertent
changes. PPS selections are locked by setting the
PPSLOCKED bit of the PPSLOCK register. Setting and
clearing this bit requires a special sequence as an extra
precaution against inadvertent changes. Examples of
setting and clearing the PPSLOCKED bit are shown in
Example 13-1.
EXAMPLE 13-1: PPS LOCK/UNLOCK

SEQUENCE
; suspend interrupts
BCF INTCON,GIE
; BANKSEL PPSLOCK ; set bank
; required sequence, next 5 instructions
MOVLW 0x55
MOVWF PPSLOCK
MOVLW 0xAA
MOVWF PPSLOCK
; Set PPSLOCKED bit to disable writes or
; Clear PPSLOCKED bit to enable writes
BSF PPSLOCK,PPSLOCKED
; restore interrupts
BSF INTCON,GIE

PIC16(L)F18857/77
TABLE 13-3: PPS OUTPUT SIGNAL ROUTING OPTIONS

Output Signal RxyPPS Register PIC16F18857 PIC16F18877

Name Value
ADGRDG 0x25    
ADGRDA 0x24    
CWG3D 0x23    
CWG3C 0x22    
CWG3B 0x21    
CWG3A 0x20    
CWG2D 0x1F    
CWG2C 0x1E    
CWG2B 0x1D    
CWG2A 0x1C    
DSM 0x1B    
CLKR 0x1A    
NCO 0x19    
TMR0 0x18    
SDO2/SDA2 0x17    
SCK2/SCL2 0x16    
SD01/SDA1 0x15    
SCK1/SCL1 0x14    
C2OUT 0x13    
C1OUT 0x12    
DT 0x11    
TX/CK 0x10    
PWM7OUT 0x0F    
PWM6OUT 0x0E    
CCP5 0x0D    
CCP4 0x0C    
CCP3 0x0B    
CCP2 0x0A    
CCP1 0x09    
CWG1D 0x08    
CWG1C 0x07    
CWG1B 0x06    
CWG1A 0x05    
CLC4OUT 0x04    
CLC3OUT 0x03    
CLC2OUT 0x02    
CLC1OUT 0x01    
Note: When RxyPPS = 0x00, port pin Rxy output value is controlled by the respective LATxy bit.

PIC16(L)F18857/77
13.8 Register Definitions: PPS Input Selection
REGISTER 13-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION(1)
U-0 U-0 R/W-q/u R/W-q/u R/W/q/u R/W-q/u R/W-q/u R/W-q/u
— — xxxPPS<5:0>
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral

bit 5-0 xxxPPS<5:0>: Peripheral xxx Input Selection bits
See Table 13-2.
Note 1: The “xxx” in the register name “xxxPPS” represents the input signal function name, such as “INT”,
“T0CKI”, “RX”, etc. This register summary shown here is only a prototype of the array of actual registers,
as each input function has its own dedicated SFR (ex: INTPPS, T0CKIPPS, RXPPS, etc.).
2: Each specific input signal may only be mapped to a subset of these I/O pins, as shown in Table 13-2.
Attempting to map an input signal to a non-supported I/O pin will result in undefined behavior. For
example, the “INT” signal map be mapped to any PORTA or PORTB pin. Therefore, the INTPPS register
may be written with values from 0x00-0x0F (corresponding to RA0-RB7). Attempting to write 0x10 or
higher to the INTPPS register is not supported and will result in undefined behavior.

PIC16(L)F18857/77
REGISTER 13-2: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER

U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u
— — RxyPPS<5:0>
bit 7 bit 0
Legend:

bit 5-0 RxyPPS<5:0>: Pin Rxy Output Source Selection bits
See Table 13-3.
Note 1: TRIS control is overridden by the peripheral as required.
REGISTER 13-3: PPSLOCK: PPS LOCK REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
— — — — — — — PPSLOCKED
bit 7 bit 0
Legend:

bit 0 PPSLOCKED: PPS Locked bit
1= PPS is locked. PPS selections can not be changed.
0= PPS is not locked. PPS selections can be changed.

PIC16(L)F18857/77
TABLE 13-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE

Register
on page
PPSLOCK — — — — — — — PPSLOCKED 241

INTPPS — — — — INTPPS<3:0> 240
T0CKIPPS — — — — T0CKIPPS<3:0> 240
T1CKIPPS — — — T1CKIPPS<4:0> 240
T1GPPS — — — T1GPPS<4:0> 240
T3GPPS — — — T3GPPS<4:0> 240
T5GPPS — — — T5GPPS<4:0> 240
T5GPPS — — — T5GPPS<4:0> 240
T2AINPPS T2AINPPS<4:0> 240
CCP1PPS — — — CCP1PPS<4:0> 240
CWG1PPS — — — CWG1PPS<4:0> 240
MDCARLPPS — — — MDCARLPPS<4:0> 240
MDCARHPPS — — — MDCARHPPS<4:0> 240
MDSRCPPS — — — MDSRCPPS<4:0> 240
SSP1CLKPPS — — — SSP1CLKPPS<4:0> 240
SSP1DATPPS — — — SSP1DATPPS<4:0> 240
SSP1SSPPS — — — SSP1SSPPS<4:0> 240
RXPPS — — — RXPPS<4:0> 241
TXPPS — — — TXPPS<4:0> 240
CLCIN0PPS — — — CLCIN0PPS<4:0> 240
SMT1WINPPS — — — SMT1WINPPS<4:0> 240
SMT1SIGPPS — — — SMT1SIGPPS<4:0> 240
SMT2WINPPS — — — SMT2WINPPS<4:0> 240
SMT2SIGPPS — — — SMT2SIGPPS<4:0> 240
ADCACTPPS — — — ADCACTPPS<4:0> 240
RA0PPS — — RA0PPS<5:0> 241
RA1PPS — — RA1PPS<5:0> 241
RA2PPS — — RA2PPS<5:0> 241
RA3PPS — — RA3PPS<5:0> 241
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.
Note 1: PIC16F18877 only.

PIC16(L)F18857/77
TABLE 13-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED)
Register
on page
RA4PPS — — RA4PPS<5:0> 241

RA5PPS — — RA5PPS<5:0> 241
RA6PPS — — RA6PPS<5:0> 241
RA7PPS — — RA7PPS<5:0> 241
RB0PPS — — RB0PPS<5:0> 241
RB1PPS — — RB1PPS<5:0> 241
RB2PPS — — RB2PPS<5:0> 241
RB3PPS — — RB3PPS<5:0> 241
RB4PPS — — RB4PPS<5:0> 241
RB5PPS — — RB5PPS<5:0> 241
RB6PPS — — RB6PPS<5:0> 241
RB7PPS — — RB7PPS<5:0> 241
RC0PPS — — RC0PPS<5:0> 241
RC1PPS — — RC1PPS<5:0> 241
RC2PPS — — RC2PPS<5:0> 241
RC3PPS — — RC3PPS<5:0> 241
RC4PPS — — RC4PPS<5:0> 241
RC5PPS — — RC5PPS<5:0> 241
RC6PPS — — RC6PPS<5:0> 241
RC7PPS — — RC7PPS<5:0> 241
RD0PPS(1) — — RD0PPS<5:0> 241
RD1PPS(1) — — RD1PPS<5:0> 241
RD2PPS(1) — — RD2PPS<5:0> 241
RD3PPS(1) — — RD3PPS<5:0> 241
RD4PPS(1) — — RD4PPS<5:0> 241
RD5PPS(1) — — RD5PPS<5:0> 241
RD6PPS(1) — — RD6PPS<5:0> 241
RD7PPS(1) — — RD7PPS<5:0> 241
RE0PPS(1) — — RE0PPS<5:0> 241
RE1PPS(1) — — RE1PPS<5:0> 241
RE2PPS(1) — — RE2PPS<5:0> 241
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.
Note 1: PIC16F18877 only.

PIC16(L)F18857/77
14.0 PERIPHERAL MODULE 14.2 Enabling a module
DISABLE When the register bit is cleared, the module is re-
The PIC16F18857/77 provides the ability to disable enabled and will be in its Reset state; SFR data will
selected modules, placing them into the lowest reflect the POR Reset values.
possible Power mode. Depending on the module, it may take up to one full
For legacy reasons, all modules are ON by default instruction cycle for the module to become active.
following any Reset. There should be no interaction with the module
(e.g., writing to registers) for at least one instruction
after it has been re-enabled.
14.1 Disabling a Module
Disabling a module has the following effects: 14.3 Disabling a Module
• All clock and control inputs to the module are When a module is disabled, any and all associated
suspended; there are no logic transitions, and the input selection registers (ISMs) are also disabled.
module will not function.
• The module is held in Reset. 14.4 System Clock Disable
• Any SFRs become “unimplemented”
Setting SYSCMD (PMD0, Register 14-1) disables the
- Writing is disabled
system clock (FOSC) distribution network to the
- Reading returns 00h
peripherals. Not all peripherals make use of SYSCLK,
• Module outputs are disabled; I/O goes to the next so not all peripherals are affected. Refer to the specific
module according to pin priority peripheral description to see if it will be affected by this
bit.

PIC16(L)F18857/77
REGISTER 14-1: PMD0: PMD CONTROL REGISTER 0
R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
SYSCMD FVRMD — CRCMD SCANMD NVMMD CLKRMD IOCMD
7 0
Legend:
bit 7 SYSCMD: Disable Peripheral System Clock Network bit

See description in Section 14.4 “System Clock Disable”.
1 = System clock network disabled (a.k.a. FOSC)
0 = System clock network enabled
bit 6 FVRMD: Disable Fixed Voltage Reference (FVR) bit
1 = FVR module disabled
0 = FVR module enabled
bit 4 CRCMD: CRC module disable bit
1 = CRC module disabled
0 = CRC module enabled
bit 3 SCANMD: Program Memory Scanner Module Disable bit
1 = Scanner module disabled
0 = Scanner module enabled
bit 2 NVMMD: NVM Module Disable bit(1)
1 = User memory and EEPROM reading and writing is disabled; NVMCON registers cannot be written;
FSR access to these locations returns zero.
0 = NVM module enabled
bit 1 CLKRMD: Disable Clock Reference CLKR bit
1 = CLKR module disabled
0 = CLKR module enabled
bit 0 IOCMD: Disable Interrupt-on-Change bit, All Ports
1 = IOC module(s) disabled
0 = IOC module(s) enabled
Note 1: When enabling NVM, a delay of up to 1 µs may be required before accessing data.

PIC16(L)F18857/77
NCOMD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD
bit 7 bit 0
Legend:
bit 7 NCOMD: Disable Numerically Control Oscillator bit

1 = NCO1 module disabled
0 = NCO1 module enabled
bit 6 TMR6MD: Disable Timer TMR6
1 = TMR6 module disabled
0 = TMR6 module enabled

PIC16(L)F18857/77
U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— DACMD ADCMD — — CMP2MD CMP1MD ZCDMD
bit 7 bit 0
Legend:

bit 6 DACMD: Disable DAC bit
1 = DAC module disabled
0 = DAC module enabled
bit 5 ADCMD: Disable ADC bit
1 = ADC module disabled
0 = ADC module enabled
bit 2 CMP2MD: Disable Comparator CMP2 bit(1)
1 = CMP2 module disabled
0 = CMP2 module enabled
bit 1 CMP1MD: Disable Comparator CMP1 bit
1 = CMP1 module disabled
0 = CMP1 module enabled
bit 0 ZCDMD: Disable ZCD
1 = ZCD module disabled
0 = ZCD module enabled

PIC16(L)F18857/77
— PWM7MD PWM6MD CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD
bit 7 bit 0
Legend:

bit 6 PWM7MD: Disable Pulse-Width Modulator PWM7 bit
1 = PWM7 module disabled
0 = PWM7 module enabled
bit 5 PWM6MD: Disable Pulse-Width Modulator PWM6 bit
1 = PWM6 module disabled
0 = PWM6 module enabled
bit 4 CCP5MD: Disable Pulse-Width Modulator CCP5 bit
1 = CCP5 module disabled
0 = CCP5 module enabled

PIC16(L)F18857/77
U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— UART1MD MSSP2MD MSSP1MD — CWG3MD CWG2MD CWG1MD
bit 7 bit 0
Legend:

bit 6 UART1MD: Disable EUSART bit
1 = EUSART module disabled
0 = EUSART module enabled
bit 5 MSSP2MD: Disable MSSP2 bit
1 = MSSP2 module disabled
0 = MSSP2 module enabled
bit 4 MSSP1MD: Disable MSSP1 bit
1 = MSSP1 module disabled
0 = MSSP1 module enabled
bit 2 CWG3MD: Disable CWG3 bit
1 = CWG3 module disabled
0 = CWG3 module enabled

PIC16(L)F18857/77
REGISTER 14-6: PMD5 – PMD CONTROL REGISTER 5
R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
SMT2MD SMT1MD — CLC4MD CLC3MD CLC2MD CLC1MD DSMMD
bit 7 bit 0
Legend:
bit 7 SMT2MD: Disable Signal Measurement Timer2 bit

1 = SMT2 module disabled
0 = SMT2 module enabled
bit 6 SMT1MD: Disable Signal Measurement Timer1 bit
1 = SMT1 module disabled
0 = SMT1 module enabled
bit 4 CLC4MD: Disable CLC4 bit
1 = CLC4 module disabled
0 = CLC4 module enabled
bit 1 CLC1MD: Disable CLC bit
bit 0 DSMMD: Disable Data Signal Modulator bit
1 = DSM module disabled
0 = DSM module enabled

PIC16(L)F18857/77
15.0 INTERRUPT-ON-CHANGE 15.3 Interrupt Flags
All the pins of PORTA, PORTB, PORTC, and pin RE3 of The bits located in the IOCxF registers are status flags
PORTE can be configured to operate as that correspond to the interrupt-on-change pins of each
interrupt-on-change (IOC) pins on PIC16(L)F18857/77 port. If an expected edge is detected on an appropriately
family devices. An interrupt can be generated by enabled pin, then the status flag for that pin will be set,
detecting a signal that has either a rising edge or a falling and an interrupt will be generated if the IOCIE bit is set.
edge. Any individual pin, or combination of pins, can be The IOCIF bit of the PIR0 register reflects the status of
configured to generate an interrupt. The all IOCxF bits.
interrupt-on-change module has the following features:
• Interrupt-on-Change enable (Main Switch) 15.4 Clearing Interrupt Flags
• Individual pin configuration The individual status flags, (IOCxF register bits), can be
• Rising and falling edge detection cleared by resetting them to zero. If another edge is
• Individual pin interrupt flags detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
Figure 15-1 is a block diagram of the IOC module.
regardless of the value actually being written.
15.1 Enabling the Module In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
To allow individual pins to generate an interrupt, the changed bits should be performed. The following
IOCIE bit of the PIE0 register must be set. If the IOCIE sequence is an example of what should be performed.
bit is disabled, the edge detection on the pin will still
occur, but an interrupt will not be generated. EXAMPLE 15-1: CLEARING INTERRUPT
FLAGS
15.2 Individual Pin Configuration (PORTA EXAMPLE)
For each pin, a rising edge detector and a falling edge MOVLW 0xff
detector are present. To enable a pin to detect a rising XORWF IOCAF, W
edge, the associated bit of the IOCxP register is set. To ANDWF IOCAF, F
enable a pin to detect a falling edge, the associated bit
of the IOCxN register is set.
15.5 Operation in Sleep
A pin can be configured to detect rising and falling
edges simultaneously by setting the associated bits in The interrupt-on-change interrupt sequence will wake
both of the IOCxP and IOCxN registers. the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the affected
IOCxF register will be updated prior to the first instruction
executed out of Sleep.

PIC16(L)F18857/77
FIGURE 15-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
Rev. 10-000 037A
6/2/201 4
IOCANx D Q
R Q4Q1
edge
detect
RAx
to data bus
data bus = S
IOCAFx
IOCAPx D Q
0 or 1
D Q
R
write IOCAFx
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
FOSC
Q1 Q1 Q1
Q2 Q2 Q2
Q3 Q3 Q3
Q4 Q4 Q4
Q4Q1 Q4Q1 Q4Q1 Q4Q1

PIC16(L)F18857/77
15.6 Register Definitions: Interrupt-on-Change Control
REGISTER 15-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER

IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
bit 7 bit 0
Legend:
bit 7-0 IOCAP<7:0>: Interrupt-on-Change PORTA Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive-going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 15-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER

IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
bit 7 bit 0
Legend:
bit 7-0 IOCAN<7:0>: Interrupt-on-Change PORTA Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative-going edge. IOCAFx bit and IOCIF flag will
REGISTER 15-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
bit 7-0 IOCAF<7:0>: Interrupt-on-Change PORTA Flag bits

1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling
edge was detected on RAx.
0 = No change was detected, or the user cleared the detected change.

PIC16(L)F18857/77
REGISTER 15-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER

IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0
bit 7 bit 0
Legend:
bit 7-0 IOCBP<7:0>: Interrupt-on-Change PORTB Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive-going edge. IOCBFx bit and IOCIF flag will
REGISTER 15-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER

IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0
bit 7 bit 0
Legend:
bit 7-0 IOCBN<7:0>: Interrupt-on-Change PORTB Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative-going edge. IOCBFx bit and IOCIF flag will
REGISTER 15-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER

IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0
bit 7 bit 0
Legend:
bit 7-0 IOCBF<7:0>: Interrupt-on-Change PORTB Flag bits

1 = An enabled change was detected on the associated pin.
Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling
edge was detected on RBx.
0 = No change was detected, or the user cleared the detected change.

PIC16(L)F18857/77
REGISTER 15-7: IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER

IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0
bit 7 bit 0
Legend:
bit 7-0 IOCCP<7:0>: Interrupt-on-Change PORTC Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive-going edge. IOCCFx bit and IOCIF flag will
0 = Interrupt-on-Change disabled for the associated pin
REGISTER 15-8: IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER

IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0
bit 7 bit 0
Legend:
bit 7-0 IOCCN<7:0>: Interrupt-on-Change PORTC Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative-going edge. IOCCFx bit and IOCIF flag will
REGISTER 15-9: IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER

IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0
bit 7 bit 0
Legend:
bit 7-0 IOCCF<7:0>: Interrupt-on-Change PORTC Flag bits

1 = An enabled change was detected on the associated pin
Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling
edge was detected on RCx.
0 = No change was detected, or the user cleared the detected change

PIC16(L)F18857/77
REGISTER 15-10: IOCEP: INTERRUPT-ON-CHANGE PORTE POSITIVE EDGE REGISTER

U-0 U-0 U-0 U-0 R/W/HS-0/0 U-0 U-0 U-0
— — — — IOCEP3 — — —
bit 7 bit 0
Legend:

bit 3 IOCEP3: Interrupt-on-Change PORTE Positive Edge Enable bit
1 = Interrupt-on-Change enabled on the pin for a positive-going edge. IOCCFx bit and IOCIF flag will
REGISTER 15-11: IOCEN: INTERRUPT-ON-CHANGE PORTE NEGATIVE EDGE REGISTER

U-0 U-0 U-0 U-0 R/W/HS-0/0 U-0 U-0 U-0
— — — — IOCEN3 — — —
bit 7 bit 0
Legend:

bit 3 IOCEN3: Interrupt-on-Change PORTE Negative Edge Enable bit
1 = Interrupt-on-Change enabled on the pin for a negative-going edge. IOCCFx bit and IOCIF flag will

PIC16(L)F18857/77
REGISTER 15-12: IOCEF: INTERRUPT-ON-CHANGE PORTE FLAG REGISTER

U-0 U-0 U-0 U-0 R/W/HS-0/0 U-0 U-0 U-0
— — — — IOCEF3 — — —
bit 7 bit 0
Legend:

bit 3 IOCEF3: Interrupt-on-Change PORTE Flag bit
1 = An enabled change was detected on the associated pin
Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling
edge was detected on RCx.
0 = No change was detected, or the user cleared the detected change

PIC16(L)F18857/77
TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
on Page
IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 253
IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 253
IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 253
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 254
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 254
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 254
IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 255
IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 255
IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 255
IOCEP — — — — IOCEP3 — — — 256
IOCEN — — — — IOCEN3 — — — 256
IOCEF — — — — IOCEF3 — — — 257
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.

PIC16(L)F18857/77
16.0 FIXED VOLTAGE REFERENCE 16.1 Independent Gain Amplifiers
(FVR) The output of the FVR, which is connected to the ADC,
The Fixed Voltage Reference, or FVR, is a stable comparators, and DAC, is routed through two
voltage reference, independent of VDD, with 1.024V, independent programmable gain amplifiers. Each
2.048V or 4.096V selectable output levels. The output amplifier can be programmed for a gain of 1x, 2x or 4x,
of the FVR can be configured to supply a reference to produce the three possible voltage levels.
voltage to the following: The ADFVR<1:0> bits of the FVRCON register are
• ADC input channel used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module.
• ADC positive reference
Reference Section 23.0 “Analog-to-Digital Con-
• Comparator positive input verter With Computation (ADC2) Module” for addi-
• Digital-to-Analog Converter (DAC) tional information.
The FVR can be enabled by setting the FVREN bit of The CDAFVR<1:0> bits of the FVRCON register are
the FVRCON register. used to enable and configure the gain amplifier settings
for the reference supplied to the DAC and comparator
module. Reference Section 25.0 “5-Bit Digi-
Note: Fixed Voltage Reference output cannot tal-to-Analog Converter (DAC1) Module” and
exceed VDD. Section 18.0 “Comparator Module” for additional
information.
16.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set.
FIGURE 16-1: VOLTAGE REFERENCE BLOCK DIAGRAM

Rev. 10-000 053C
12/9/201 3
2
ADFVR<1:0>
1x
FVR_buffer1
2x
4x (To ADC Module)
2
CDAFVR<1:0>
1x FVR_buffer2
2x (To Comparators
4x and DAC)
FVREN
+
_ FVRRDY
Note 1

PIC16(L)F18857/77
16.3 Register Definitions: FVR Control
REGISTER 16-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
(1) (3) (3)
FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0>
bit 7 bit 0
Legend:
bit 7 FVREN: Fixed Voltage Reference Enable bit

1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5 TSEN: Temperature Indicator Enable bit(3)
1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
1 = VOUT = VDD - 4VT (High Range)
0 = VOUT = VDD - 2VT (Low Range)
bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits
11 = Comparator FVR Buffer Gain is 4x, (4.096V)(2)
10 = Comparator FVR Buffer Gain is 2x, (2.048V)(2)
01 = Comparator FVR Buffer Gain is 1x, (1.024V)
00 = Comparator FVR Buffer is off
bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit
11 = ADC FVR Buffer Gain is 4x, (4.096V)(2)
10 = ADC FVR Buffer Gain is 2x, (2.048V)(2)
01 = ADC FVR Buffer Gain is 1x, (1.024V)
00 = ADC FVR Buffer is off
Note 1: FVRRDY is always ‘1’ for PIC16F18857/77 devices only.

2: Fixed Voltage Reference output cannot exceed VDD.
3: See Section 17.0 “Temperature Indicator Module” for additional information.

PIC16(L)F18857/77
TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Register
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 260
ADREF ADNREF ADPREF<1:0> 353
ADPCH ADPCH<5:0> 354
CM1CON1 — — — — — — INTP INTN 271
CM1NSEL — — — — — NCH<2:0> 272
CM1PSEL — — — — — PCH<2:0> 272
CM2CON1 — — — — — — INTP INTN 271
CM2NSEL — — — — — NCH<2:0> 272
CM2PSEL — — — — — PCH<2:0> 272
DAC1CON0 DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS 379
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used with the Fixed Voltage Reference.

PIC16(L)F18857/77
17.0 TEMPERATURE INDICATOR FIGURE 17-1: TEMPERATURE CIRCUIT
MODULE DIAGRAM
This family of devices is equipped with a temperature

Rev. 10-000069A
circuit designed to measure the operating temperature VDD

7/31/2013
of the silicon die. The circuit’s range of operating

temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device TSEN
temperature. The output of the temperature indicator is
internally connected to the device ADC.
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
TSRNG
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal VOUT
To ADC
Temperature Indicator” (DS01333) for more details Temp. Indicator
regarding the calibration process.
17.1 Circuit Operation

Figure 17-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is 17.2 Minimum Operating VDD
achieved by measuring the forward voltage drop across
multiple silicon junctions. When the temperature circuit is operated in low range,
Equation 17-1 describes the output characteristics of the device may be operated at any operating voltage
the temperature indicator. that is within specifications.
When the temperature circuit is operated in high range,
EQUATION 17-1: VOUT RANGES the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is
correctly biased.
High Range: VOUT = VDD - 4VT
Table 17-1 shows the recommended minimum VDD vs.
Low Range: VOUT = VDD - 2VT range setting.
TABLE 17-1: RECOMMENDED VDD VS.

The temperature sense circuit is integrated with the RANGE
Fixed Voltage Reference (FVR) module. See 16.0
Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0
“Fixed Voltage Reference (FVR)” for more
information. 3.6V 1.8V
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no 17.3 Temperature Output
current.
The output of the circuit is measured using the internal
The circuit operates in either high or low range. The high Analog-to-Digital Converter. A channel is reserved for
range, selected by setting the TSRNG bit of the the temperature circuit output. Refer to Section 23.0
FVRCON register, provides a wider output voltage. This “Analog-to-Digital Converter With Computation
provides more resolution over the temperature range, (ADC2) Module” for detailed information.
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.

PIC16(L)F18857/77
17.4 ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between consecutive
conversions of the temperature indicator output.
TABLE 17-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR

Register
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDFVR<1:0> ADFVR<1:0> 260
Legend: Shaded cells are unused by the Temperature Indicator module.

PIC16(L)F18857/77
18.0 COMPARATOR MODULE FIGURE 18-1: SINGLE COMPARATOR
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and VIN+ +
providing a digital indication of their relative magnitudes. Output
VIN- –
Comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
• Programmable input selection VIN-
VIN+
• Programmable output polarity
• Rising/falling output edge interrupts
• Wake-up from Sleep
• Programmable Speed/Power optimization
Output
• CWG1 Auto-shutdown source
• Selectable voltage reference
18.1 Comparator Overview Note: The black areas of the output of the
comparator represents the uncertainty
A single comparator is shown in Figure 18-1 along with due to input offsets and response time.
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparators available are shown in Table 18-1.
TABLE 18-1: AVAILABLE COMPARATORS

Device C1 C2
PIC16(L)F18857/77 ● ●

PIC16(L)F18857/77
FIGURE 18-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
Rev. 10-000027K
11/20/2015
3 (1)
CxNCH<2:0> CxON
Interrupt CxINTP
Rising
Edge set bit
CxIN0- 000 CxIF
Interrupt CxINTN
CxIN1- 001
Falling
CxIN2- 010 CxON(1) Edge
CxIN3- 011 CxVN

- D Q
CxOUT
Reserved 100
Cx MCxOUT
Reserved 101 CxVP
FVR_buffer2 110
+ Q1
111 CxSP CxHYS CxPOL
CxOUT_sync to
peripherals
CxSYNC
CxIN0+ 000
TRIS bit
CxIN1+ 001 0
Reserved 010 PPS CxOUT

D Q 1
Reserved 011
Reserved 100 RxyPPS
(From Timer1 Module) T1CLK
DAC_output 101
FVR_buffer2 110
111
CxPCH<2:0> CxON(1)
2
Note 1: When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.

PIC16(L)F18857/77
18.2 Comparator Control 18.2.3 COMPARATOR OUTPUT POLARITY
Each comparator has two control registers: CMxCON0 Inverting the output of the comparator is functionally
and CMxCON1. equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
The CMxCON0 register (see Register 18-1) contains setting the CxPOL bit of the CMxCON0 register.
Control and Status bits for the following: Clearing the CxPOL bit results in a non-inverted output.
• Enable Table 18-2 shows the output state versus input
• Output conditions, including polarity control.
• Output polarity
• Hysteresis enable
TABLE 18-2: COMPARATOR OUTPUT
• Timer1 output synchronization STATE VS. INPUT
The CMxCON1 register (see Register 18-2) contains CONDITIONS
Control bits for the following:
Input Condition CxPOL CxOUT
• Interrupt on positive/negative edge enables
CxVN > CxVP 0 0
18.2.1 COMPARATOR ENABLE CxVN < CxVP 0 1
Setting the CxON bit of the CMxCON0 register enables CxVN > CxVP 1 1
the comparator for operation. Clearing the CxON bit CxVN < CxVP 1 0
disables the comparator resulting in minimum current
consumption.
18.2.2 COMPARATOR OUTPUT

The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register.
The comparator output can also be routed to an
external pin through the RxyPPS register
(Register 13-2). The corresponding TRIS bit must be
clear to enable the pin as an output.
Note 1: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external out-
puts are not latched.

PIC16(L)F18857/77
18.3 Comparator Hysteresis The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
A selectable amount of separation voltage can be detected while this flag is being cleared, the flag will still
added to the input pins of each comparator to provide a be set at the end of the sequence.
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0 Note: Although a comparator is disabled, an
register. interrupt can be generated by changing
the output polarity with the CxPOL bit of
See Comparator Specifications in Table 37-14 for more
the CMxCON0 register, or by switching
information.
the comparator on or off with the CxON bit
of the CMxCON0 register.
18.4 Timer1 Gate Operation
The output resulting from a comparator operation can 18.6 Comparator Positive Input
be used as a source for gate control of Timer1. See Selection
Section 28.7 “Timer Gate” for more information. This
feature is useful for timing the duration or interval of an Configuring the CxPCH<2:0> bits of the CMxCON1
analog event. register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
It is recommended that the comparator output be
synchronized to Timer1. This ensures that Timer1 does • CxIN0+ analog pin
not increment while a change in the comparator is • DAC output
occurring. • FVR (Fixed Voltage Reference)
• VSS (Ground)
18.4.1 COMPARATOR OUTPUT
SYNCHRONIZATION See Section 16.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
The output from a comparator can be synchronized module.
with Timer1 by setting the CxSYNC bit of the
CMxCON0 register. See Section 25.0 “5-Bit Digital-to-Analog Converter
(DAC1) Module” for more information on the DAC
Once enabled, the comparator output is latched on the input signal.
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after Any time the comparator is disabled (CxON = 0), all
the prescaling function. To prevent a race condition, the comparator inputs are disabled.
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the 18.7 Comparator Negative Input
rising edge of its clock source. See the Comparator Selection
Block Diagram (Figure 18-2) and the Timer1 Block
Diagram (Figure 28-1) for more information. The CxNCH<2:0> bits of the CMxCON1 register direct
an analog input pin and internal reference voltage or
analog ground to the inverting input of the comparator:
18.5 Comparator Interrupt
• CxIN- pin
An interrupt can be generated upon a change in the
• FVR (Fixed Voltage Reference)
output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are • Analog Ground
present. Some inverting input selections share a pin with the
When either edge detector is triggered and its associ- operational amplifier output function. Enabling both
ated enable bit is set (CxINTP and/or CxINTN bits of functions at the same time will direct the operational
the CMxCON1 register), the Corresponding Interrupt amplifier output to the comparator inverting input.
Flag bit (CxIF bit of the PIR2 register) will be set.
To enable the interrupt, you must set the following bits:
Note: To use CxINy+ and CxINy- pins as analog
• CxON, CxPOL and CxSP bits of the CMxCON0 input, the appropriate bits must be set in
register the ANSEL register and the correspond-
• CxIE bit of the PIE2 register ing TRIS bits must also be set to disable
• CxINTP bit of the CMxCON1 register (for a rising the output drivers.
edge detection)
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register

PIC16(L)F18857/77
18.8 Comparator Response Time 18.9 Analog Input Connection
The comparator output is indeterminate for a period of
Considerations
time after the change of an input source or the selection A simplified circuit for an analog input is shown in
of a new reference voltage. This period is referred to as Figure 18-3. Since the analog input pins share their
the response time. The response time of the comparator connection with a digital input, they have reverse
differs from the settling time of the voltage reference. biased ESD protection diodes to VDD and VSS. The
Therefore, both of these times must be considered when analog input, therefore, must be between VSS and VDD.
determining the total response time to a comparator If the input voltage deviates from this range by more
input change. See the Comparator and Voltage than 0.6V in either direction, one of the diodes is
Reference Specifications in Table 37-14 for more forward biased and a latch-up may occur.
details.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
FIGURE 18-3: ANALOG INPUT MODEL

VDD
Analog
Input
pin VT  0.6V RIC
Rs < 10K
To Comparator
CPIN ILEAKAGE(1)
VA VT  0.6V
5 pF
Vss
Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage
Note 1: See I/O Ports in Table 37-4.

PIC16(L)F18857/77
18.10 CWG1 Auto-shutdown Source
The output of the comparator module can be used as
an auto-shutdown source for the CWG1 module. When
the output of the comparator is active and the
corresponding ASxE is enabled, the CWG operation
will be suspended immediately (see Section 20.10
“Auto-Shutdown”).
18.11 Operation in Sleep Mode

The comparator module can operate during Sleep. The
comparator clock source is based on the Timer1 clock
source. If the Timer1 clock source is either the system
clock (FOSC) or the instruction clock (FOSC/4), Timer1
will not operate during Sleep, and synchronized
comparator outputs will not operate.
A comparator interrupt will wake the device from Sleep.
The CxIE bits of the PIE2 register must be set to enable
comparator interrupts.

PIC16(L)F18857/77
18.12 Register Definitions: Comparator Control
REGISTER 18-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0 R-0/0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
ON OUT — POL — — HYS SYNC
bit 7 bit 0
Legend:
bit 7 ON: Comparator Enable bit

1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6 OUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 4 POL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 1 HYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0 SYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous

PIC16(L)F18857/77
REGISTER 18-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— — — — — — INTP INTN
bit 7 bit 0
Legend:

bit 1 INTP: Comparator Interrupt on Positive-Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive-going edge of the CxOUT bit
bit 0 INTN: Comparator Interrupt on Negative-Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative-going edge of the CxOUT bit

PIC16(L)F18857/77
REGISTER 18-3: CMxNSEL: COMPARATOR Cx NEGATIVE INPUT SELECT REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — NCH<2:0>
bit 7 bit 0
Legend:

bit 2-0 NCH<2:0>: Comparator Negative Input Channel Select bits
111 = CxVN connects to AVSS
110 = CxVN connects to FVR Buffer 2
101 = CxVN unconnected
100 = CxVN unconnected
011 = CxVN connects to CxIN3- pin
REGISTER 18-4: CMxPSEL: COMPARATOR Cx POSITIVE INPUT SELECT REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — PCH<2:0>
bit 7 bit 0
Legend:

bit 2-0 PCH<2:0>: Comparator Positive Input Channel Select bits
111 = CxVP connects to AVSS
110 = CxVP connects to FVR Buffer 2
101 = CxVP connects to DAC output
100 = CxVP unconnected
001 = CxVP connects to CxIN1+ pin
000 = CxVP connects to CxIN0+ pin

PIC16(L)F18857/77
REGISTER 18-5: CMOUT: COMPARATOR OUTPUT REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0
— — — — — — MC2OUT MC1OUT
bit 7 bit 0
Legend:

bit 1 MC2OUT: Mirror Copy of C2OUT bit
bit 0 MC1OUT: Mirror Copy of C1OUT bit
TABLE 18-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Register
on Page
CMxCON0 ON OUT — POL — — HYS SYNC 270
CMxCON1 — — — — — — INTP INTN 271
CMOUT — — — — — — MC2OUT MC1OUT 273
CWG1AS1 — AS6E AS5E AS4E AS3E AS2E AS1E AS0E 301
CWG2AS1 AS6E AS5E AS4E AS3E AS2E AS1E AS0E 301
CWG3AS1 AS6E AS5E AS4E AS3E AS2E AS1E AS0E 301
DAC1CON1 — — — DAC1R<4:0> 379
INTCON GIE PEIE — 133
RxyPPS ― ― RxyPPS<5:0> 241
CLCINxPPS — — — CLCIN0PPS<4:0> 240
MDSRCPPS ― ― ― MDSRCPPS<4:0> 240
T1GPPS ― ― ― T1GPPS<4:0> 240
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 209
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the Comparator module.

PIC16(L)F18857/77
19.0 PULSE-WIDTH MODULATION FIGURE 19-1: PWM OUTPUT
(PWM)
Q1 Q2 Q3 Q4 Rev. 10-000023C
8/26/2015
The PWMx modules generate Pulse-Width Modulated

(PWM) signals of varying frequency and duty cycle.
FOSC
In addition to the CCP modules, the
PIC16(L)F18857/77 devices contain two PWM mod-
Pulse Width
ules (PWM6 and PWM7). These modules are essen- PWM
tially the same as the CCP modules without the TMRx = 0
(1)
Capture or Compare functionality.

(1)
TMRx = PWMxDC
Note: The PWM6 and PWM7 modules are two (1)

TMRx = PRx
instances of the same PWM module
design. Throughout this section, the lower
Note 1: Timer dependent on PWMTMRS register settings.
case ‘x’ in register and bit names is a
generic reference to the PWM module
number (which should be substituted with
6 or 7 during code development). For
example, the control register is generically
described in this chapter as PWMxCON,
but the actual device registers are
PWM6CON and PWM7CON. Similarly,
the PWMxEN bit represents the PWM6EN
and PWM7EN bits.
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the ‘on’ state (pulse width), and the low
portion of the signal is considered the ‘off’ state. The
term duty cycle describes the proportion of the ‘on’ time
to the ‘off’ time and is expressed in percentages, where
0% is fully off and 100% is fully on. A lower duty cycle
corresponds to less power applied and a higher duty
cycle corresponds to more power applied. The PWM
period is defined as the duration of one complete cycle
or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and, in turn, the power that is applied to the
load.
Figure 19-1 shows a typical waveform of the PWM
signal.

PIC16(L)F18857/77
19.1 Standard PWM Mode
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the PWMx pin with up to
ten bits of resolution. The period, duty cycle, and
resolution are controlled by the following registers:
• TMR2 register
• PR2 register
• PWMxCON registers
• PWMxDCH registers
• PWMxDCL registers
Figure 19-2 shows a simplified block diagram of PWM
operation.
If PWMPOL = 0, the default state of the output is ‘0‘. If
PWMPOL = 1, the default state is ‘1’. If PWMEN = ‘0’,
the output will be the default state.
Note: The corresponding TRIS bit must be

cleared to enable the PWM output on the
PWMx pin
FIGURE 19-2: SIMPLIFIED PWM BLOCK DIAGRAM
Rev. 10-000022B
9/24/2014
Duty cycle registers PWMxDCL<7:6>

PWMxDCH
PWMx_out
To Peripherals
10-bit Latch
(Not visible to user)
Comparator R Q
0
PPS PWMx
1
S Q
TMR2 Module
R PWMxPOL RxyPPS TRIS Control
TMR2 (1)
Comparator
T2_match
PR2
Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.

PIC16(L)F18857/77
19.1.1 PWM CLOCK SELECTION The PWMDC register is double-buffered and can be
updated at any time. This double buffering is essential
The PIC16(L)F18857/77 allows each individual CCP
for glitch-free PWM operation. New values take effect
and PWM module to select the timer source that con-
when TMR2 = PR2. Note that PWMDC is left-justified.
trols the module. Each module has an independent
selection. The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two
As there are up to three 8-bit timers with auto-reload
bits of the prescaler, to create the 10-bit time base. The
(Timer2/4/6), PWM mode on the CCP and PWM mod-
system clock is used if the Timer2 prescaler is set to
ules can use any of these timers.
1:1.
The CCPTMRS0 and CCPTMRS1 register are used to
Equation 19-2 is used to calculate the PWM pulse
select which timer is used.
width.
19.1.2 USING THE TMR2/4/6 WITH THE Equation 19-3 is used to calculate the PWM duty cycle
PWM MODULE ratio.
This device has a newer version of the TMR2 module
that has many new modes, which allow for greater cus- EQUATION 19-2: PULSE WIDTH
tomization and control of the PWM signals than on
Pulse Widthൌሺܹܲ‫ܥܦݔܯ‬ሻ ή ܱܶܵ‫ ܥ‬ή
older parts. Refer to Section 29.5, Operation Examples
ሺܶ‫݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯ‬ሻ
for examples of PWM signal generation using the dif-
ferent modes of Timer2. PWM operation requires that
the timer used as the PWM time base has the FOSC/4
clock source selected. EQUATION 19-3: DUTY CYCLE RATIO
ሺܹܲ‫ܥܦݔܯ‬ሻ
19.1.3 PWM PERIOD ‫ ݋݅ݐܴ݈ܽ݁ܿݕܥݕݐݑܦ‬ൌ
Ͷሺܴܲʹ ൅ ͳሻ
Referring to Figure 19-1, the PWM output has a period
and a pulse width. The frequency of the PWM is the
inverse of the period (1/period). 19.1.5 PWM RESOLUTION
The PWM period is specified by writing to the PR2 The resolution determines the number of available duty
register. The PWM period can be calculated using the cycles for a given period. For example, a 10-bit
following formula: resolution will result in 1024 discrete duty cycles,
whereas an 8-bit resolution will result in 256 discrete
duty cycles.
EQUATION 19-1: PWM PERIOD
The maximum PWM resolution is ten bits when PR2 is
ܹܲ‫ ݀݋݅ݎ݁ܲܯ‬ൌ ሾሺܴܲʹሻ ൅ ͳሿ ή Ͷ ή ܱܶܵ‫ܥ‬ 255. The resolution is a function of the PR2 register
ή ሺܶ‫݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯ‬ሻ value as shown by Equation 19-4.
Note 1: TOSC = 1/FOSC EQUATION 19-4: PWM RESOLUTION
When TMR2 is equal to PR2, the following three events log  4  PR2 + 1  
Resolution = ------------------------------------------ bits
occur on the next increment cycle: log  2 
• TMR2 is cleared
• The PWMx pin is set (Exception: If the PWM duty
cycle = 0%, the pin will not be set.) Note: If the pulse width value is greater than the
• The PWM pulse width is latched from PWMxDC. period the assigned PWM pin(s) will
remain unchanged.
Note: If the pulse width value is greater than the
period the assigned PWM pin(s) will 19.1.6 OPERATION IN SLEEP MODE
remain unchanged. In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
19.1.4 PWM DUTY CYCLE PWMx pin is driving a value, it will continue to drive that
The PWM duty cycle is specified by writing a 10-bit value. When the device wakes up, TMR2 will continue
value to the PWMxDC register. The PWMxDCH from its previous state.
contains the eight MSbs and the PWMxDCL<7:6> bits
contain the two LSbs.

PIC16(L)F18857/77
19.1.7 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 6.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.
19.1.8 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the
PWMx registers to their Reset states.
TABLE 19-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6

19.1.9 SETUP FOR PWM OPERATION • Route the signal to the desired pin by
configuring the RxyPPS register.
The following steps should be taken when configuring
the module for using the PWMx outputs: • Enable the PWMx module by setting the
PWMxEN bit of the PWMxCON register.
1. Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s). In order to send a complete duty cycle and period on
the first PWM output, the above steps must be followed
2. Configure the PWM output polarity by
in the order given. If it is not critical to start with a com-
configuring the PWMxPOL bit of the PWMxCON
plete PWM signal, then the PWM module can be
register.
enabled during Step 2 by setting the PWMxEN bit of
3. Load the PR2 register with the PWM period value, the PWMxCON register.
as determined by Equation 19-1.
4. Load the PWMxDCH register and bits <7:6> of
the PWMxDCL register with the PWM duty cycle
value, as determined by Equation 19-2.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the PIR4
register.
• Select the Timer2 prescale value by configuring
the T2CKPS<1:0> bits of the T2CON
register.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6. Wait until the TMR2IF is set.
7. When the TMR2IF flag bit is set:
• Clear the associated TRIS bit(s) to enable the
output driver.

PIC16(L)F18857/77
19.2 Register Definitions: PWM Control
REGISTER 19-1: PWMxCON: PWM CONTROL REGISTER

R/W-0/0 U-0 R-0 R/W-0/0 U-0 U-0 U-0 U-0
PWMxEN — PWMxOUT PWMxPOL — — — —
bit 7 bit 0
Legend:
bit 7 PWMxEN: PWM Module Enable bit

1 = PWM module is enabled
0 = PWM module is disabled
bit 5 PWMxOUT: PWM Module Output Level when Bit is Read
bit 4 PWMxPOL: PWMx Output Polarity Select bit
1 = PWM output is active-low
0 = PWM output is active-high

PIC16(L)F18857/77
REGISTER 19-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS

PWMxDC<9:2>
bit 7 bit 0
Legend:
bit 7-0 PWMxDC<9:2>: PWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle. The two LSbs are found in PWMxDCL Register.
REGISTER 19-3: PWMxDCL: PWM DUTY CYCLE LOW BITS

R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0
PWMxDC<1:0> — — — — — —
bit 7 bit 0
Legend:
bit 7-6 PWMxDC<1:0>: PWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle. The MSbs are found in PWMxDCH Register.

PIC16(L)F18857/77
TABLE 19-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWMx

Register
on Page
PWM6CON PWM6EN — PWM6OUT PWM6POL — — — — 278

PWM6DCH PWM6DC<9:2> 279
PWM6DCL PWM6DC<1:0> — — — — — — 279
PWM7CON PWM7EN — PWM7OUT PWM7POL — — — — 278
PWM7DCH PWM7DC<9:2> 279
PWM7DCL PWM7DC<1:0> — — — — — — 279
T2CON ON CKPS<2:0> OUTPS<3:0> 430
T2TMR Holding Register for the 8-bit TMR2 Register
T2PR TMR2 Period Register
RxyPPS ― ― RxyPPS<5:0> 241
CWG1ISM — — — — IS<3:0> 303
CWG2ISM IS<3:0> 303
CWG3ISM IS<3:0> 303
CLCxSELy — — LCxDyS<5:0> 320
MDSRC — — — MDMS<4:0> 389
MDCARH — — — — MDCHS<3:0> 390
MDCARL — — — — MDCLS<3:0> 391
Legend: - = Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWMx module.

PIC16(L)F18857/77
20.0 COMPLEMENTARY WAVEFORM 20.1 Fundamental Operation
GENERATOR (CWG) MODULE The CWG module can operate in six different modes,
The Complementary Waveform Generator (CWG) pro- as specified by MODE of the CWGxCON0 register:
duces half-bridge, full-bridge, and steering of PWM • Half-Bridge mode (Figure 20-9)
waveforms. It is backwards compatible with previous • Push-Pull mode (Figure 20-2)
ECCP functions. - Full-Bridge mode, Forward (Figure 20-3)
The CWG has the following features: - Full-Bridge mode, Reverse (Figure 20-3)
• Six operating modes: • Steering mode (Figure 20-10)
- Synchronous Steering mode • Synchronous Steering mode (Figure 20-11)
- Asynchronous Steering mode It may be necessary to guard against the possibility of
- Full-Bridge mode, Forward circuit faults or a feedback event arriving too late or not
- Full-Bridge mode, Reverse at all. In this case, the active drive must be terminated
- Half-Bridge mode before the Fault condition causes damage. Thus, all
output modes support auto-shutdown, which is covered
- Push-Pull mode
in 20.10 “Auto-Shutdown”.
• Output polarity control
• Output steering 20.1.1 HALF-BRIDGE MODE
- Synchronized to rising event In Half-Bridge mode, two output signals are generated
- Immediate effect as true and inverted versions of the input as illustrated
• Independent 6-bit rising and falling event dead- in Figure 20-9. A non-overlap (dead-band) time is
band timers inserted between the two outputs to prevent shoot
- Clocked dead band through current in various power supply applications.
Dead-band control is described in Section
- Independent rising and falling dead-band
20.5 “Dead-Band Control”.
enables
• Auto-shutdown control with: The unused outputs CWGxC and CWGxD drive similar
signals, with polarity independently controlled by the
- Selectable shutdown sources
POLC and POLD bits of the CWGxCON1 register,
- Auto-restart enable respectively.
- Auto-shutdown pin override control
The CWG modules available are shown in Table 20-1.
TABLE 20-1: AVAILABLE CWG MODULES

Device CWG1 CWG2 CWG2
PIC16(L)F18857/77 ● ● ●

FIGURE 20-1: SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE)
PIC16(L)F18857/77
Rev. 10-000 166C
7/17/202 0
CWG_data
Rising Deadband Block

See clock CWG_dataA
CWGxISM signal_out
Register signal_in CWG_dataC
D Q
CWGxISM<3:0>
E Q
R
Falling Deadband Block
clock CWG_dataB
signal_out
signal_in CWG_dataD
EN
SHUTDOWN
HFINTOSC 1
FOSC 0
CWGxCLKCON<0>
DS40001825F-page 282
PIC16(L)F18857/77
20.1.2 PUSH-PULL MODE
In Push-Pull mode, two output signals are generated,
alternating copies of the input as illustrated in
Figure 20-2. This alternation creates the push-pull
effect required for driving some transformer-based
power supply designs.
The push-pull sequencer is reset whenever EN = 0 or
if an auto-shutdown event occurs. The sequencer is
clocked by the first input pulse, and the first output
appears on CWGxA.
The unused outputs CWGxC and CWGxD drive copies
of CWGxA and CWGxB, respectively, but with polarity
controlled by the POLC and POLD bits of the
CWGxCON1 register, respectively.
20.1.3 FULL-BRIDGE MODES

In Forward and Reverse Full-Bridge modes, three out-
puts drive static values while the fourth is modulated by
the input data signal. In Forward Full-Bridge mode,
CWGxA is driven to its active state, CWGxB and
CWGxC are driven to their inactive state, and CWGxD
is modulated by the input signal. In Reverse Full-Bridge
mode, CWGxC is driven to its active state, CWGxA and
CWGxD are driven to their inactive states, and CWGxB
is modulated by the input signal. In Full-Bridge mode,
the dead-band period is used when there is a switch
from forward to reverse or vice-versa. This dead-band
control is described in Section 20.5 “Dead-Band Con-
trol”, with additional details in Section 20.6 “Rising
Edge and Reverse Dead Band” and Section
20.7 “Falling Edge and Forward Dead Band”.
The mode selection may be toggled between forward
and reverse toggling the MODE<0> bit of the
CWGxCON0 while keeping MODE<2:1> static, without
disabling the CWG module.

FIGURE 20-2: SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE)
PIC16(L)F18857/77
Rev. 10-000167B
8/29/2014
CWG_data
See
CWGxISM
Register D Q
CWG_dataA
Q CWG_dataC
R
CWG_dataB
D Q
CWG_dataD
CWGxISM<3:0>
E Q
R
EN
SHUTDOWN
DS40001825F-page 284
FIGURE 20-3: SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE MODES)
PIC16(L)F18857/77
Rev. 10-000 165C
7/17/202 0
MODE0 Reverse Deadband Block

clock
signal_out
See signal_in
CWGxISM
Register
CWG_dataA
D Q CWG_dataB
D Q
Q CWG_dataC
CWGxISM<3:0>
E
R
Q CWG_dataD
clock
signal_out
signal_in
Forward Deadband Block
EN CWG_data
SHUTDOWN
HFINTOSC 1
FOSC 0
CWGxCLKCON<0>
DS40001825F-page 285
PIC16(L)F18857/77
20.1.4 STEERING MODES
In Steering modes, the data input can be steered to any
or all of the four CWG output pins. In Synchronous
Steering mode, changes to steering selection registers
take effect on the next rising input.
In Non-Synchronous mode, steering takes effect on the
next instruction cycle. Additional details are provided in
Section 20.9 “CWG Steering Mode”.
FIGURE 20-4: SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES)

Rev. 10-000164B
8/26/2015
See
CWGxISM CWG_dataA
Register
CWG_dataB
CWG_data
CWG_dataC
CWG_dataD
D Q
CWGxISM <3:0>
E Q
R
EN
SHUTDOWN
20.2 Clock Source

The CWG module allows the following clock sources to
be selected:
• Fosc (system clock)
• HFINTOSC (16 MHz only)
The clock sources are selected using the CS bit of the
CWGxCLKCON register.

PIC16(L)F18857/77
20.3 Selectable Input Sources 20.4 Output Control
The CWG generates the output waveforms from the 20.4.1 OUTPUT ENABLES
input sources in Table 20-2.
Each CWG output pin has individual output enable con-
trol. Output enables are selected with the Gx1OEx
TABLE 20-2: SELECTABLE INPUT
<3:0> bits. When an output enable control is cleared,
SOURCES
the module asserts no control over the pin. When an
Source Peripheral Signal Name output enable is set, the override value or active PWM
waveform is applied to the pin per the port priority
CWG input PPS pin CWGxIN PPS
selection. The output pin enables are dependent on the
CCP1 CCP1_out module enable bit, EN of the CWGxCON0 register.
CCP2 CCP2_out When EN is cleared, CWG output enables and CWG
CCP3 CCP3_out drive levels have no effect.
CCP4 CCP4_out 20.4.2 POLARITY CONTROL
CCP5 CCP5_out
The polarity of each CWG output can be selected inde-
PWM6 PWM6_out pendently. When the output polarity bit is set, the corre-
PWM7 PWM7_out sponding output is active-high. Clearing the output
NCO NCO1_out polarity bit configures the corresponding output as
active-low. However, polarity does not affect the over-
Comparator C1 C1OUT_sync ride levels. Output polarity is selected with the POLx
Comparator C2 C2OUT_sync bits of the CWGxCON1. Auto-shutdown and steering
DSM DSM_out options are unaffected by polarity.
CLC1 LC1_out
CLC2 LC2_out
CLC3 LC3_out
CLC4 LC4_out
The input sources are selected using the CWGxISM
register.

PIC16(L)F18857/77
FIGURE 20-5: CWG OUTPUT BLOCK DIAGRAM
Rev. 10-000171B
9/24/2014
LSAC<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataA High Z 01 PPS CWGxA
1 0
POLA 00
OVRA 0
STRA(1)
LSBD<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataB High Z 01 PPS CWGxB
1 0
POLB 00
OVRB 0
STRB(1)
LSAC<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataC High Z 01 PPS CWGxC
1 0
POLC 00
OVRC 0
STRC(1)
LSBD<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataD High Z 01 PPS CWGxD
1 0
POLD 00
OVRD 0
STRD(1)
CWG_shutdown
Note 1: STRx is held to 1 in all modes other than Output Steering Mode.

PIC16(L)F18857/77
20.5 Dead-Band Control 20.7 Falling Edge and Forward Dead
The dead-band control provides non-overlapping PWM
Band
signals to prevent shoot-through current in PWM CWGxDBF controls the dead-band time at the leading
switches. Dead-band operation is employed for Half-
edge of CWGxB (Half-Bridge mode) or the leading
Bridge and Full-Bridge modes. The CWG contains two
edge of CWGxD (Full-Bridge mode). The CWGxDBF
6-bit dead-band counters. One is used for the rising
edge of the input source control in Half-Bridge mode or value is double-buffered. When EN = 0, the
for reverse dead-band Full-Bridge mode. The other is CWGxDBF register is loaded immediately when
used for the falling edge of the input source control in CWGxDBF is written. When EN = 1 then software
Half-Bridge mode or for forward dead band in Full- must set the LD bit of the CWGxCON0 register, and
Bridge mode. the buffer will be loaded at the next falling edge of the
Dead band is timed by counting CWG clock periods CWG input signal. If the input source signal is not
from zero up to the value in the rising or falling dead- present for enough time for the count to be completed,
band counter registers. See CWGxDBR and no output will be seen on the respective output.
CWGxDBF registers, respectively.
Refer to Figure 20.6 and Figure 20-7 for examples.
20.5.1 DEAD-BAND FUNCTIONALITY IN
HALF-BRIDGE MODE
In Half-Bridge mode, the dead-band counters dictate
the delay between the falling edge of the normal output
and the rising edge of the inverted output. This can be
seen in Figure 20-9.
20.5.2 DEAD-BAND FUNCTIONALITY IN

FULL-BRIDGE MODE
In Full-Bridge mode, the dead-band counters are used
when undergoing a direction change. The MODE<0>
bit of the CWGxCON0 register can be set or cleared
while the CWG is running, allowing for changes from
Forward to Reverse mode. The CWGxA and CWGxC
signals will change immediately upon the first rising
input edge following a direction change, but the modu-
lated signals (CWGxB or CWGxD, depending on the
direction of the change) will experience a delay dictated
by the dead-band counters. This is demonstrated in
Figure 20-3.
20.6 Rising Edge and Reverse Dead

Band
CWGxDBR controls the rising edge dead-band time at
the leading edge of CWGxA (Half-Bridge mode) or the
leading edge of CWGxB (Full-Bridge mode). The
CWGxDBR value is double-buffered. When EN = 0,
the CWGxDBR register is loaded immediately when
CWGxDBR is written. When EN = 1, then software
must set the LD bit of the CWGxCON0 register, and the
buffer will be loaded at the next falling edge of the CWG
input signal. If the input source signal is not present for
enough time for the count to be completed, no output
will be seen on the respective output.

FIGURE 20-6: DEAD-BAND OPERATION CWGXDBR = 0X01, CWGXDBF = 0X02
PIC16(L)F18857/77
cwg_clock
Input Source
CWGxA
CWGxB
FIGURE 20-7: DEAD-BAND OPERATION, CWGXDBR = 0X03, CWGXDBF = 0X04, SOURCE SHORTER THAN DEAD BAND
cwg_clock
Input Source
CWGxA
CWGxB
source shorter than dead band

DS40001825F-page 290
PIC16(L)F18857/77
20.8 Dead-Band Uncertainty EQUATION 20-1: DEAD-BAND
UNCERTAINTY
When the rising and falling edges of the input source
are asynchronous to the CWG clock, it creates uncer-
tainty in the dead-band time delay. The maximum 1
TDEADBAND_UNCERTAINTY = -----------------------------
uncertainty is equal to one CWG clock period. Refer to Fcwg_clock
Equation 20-1 for more details.
Example:
FCWG_CLOCK = 16 MHz
Therefore:
1
TDEADBAND_UNCERTAINTY = ----------------------------
-
Fcwg_clock
1 -
= -----------------
16MHz
= 62.5ns
FIGURE 20-8: EXAMPLE OF PWM DIRECTION CHANGE
MODE0
CWGxA
CWGxB
CWGxC
CWGxD
No delay CWGxDBR No delay CWGxDBF

CWGx_data
Note 1:WGPOL{ABCD} = 0
2: The direction bit MODE<0> (Register 20-1) can be written any time during the PWM cycle, and takes effect at the
next rising CWGx_data.
3: When changing directions, CWGxA and CWGxC switch at rising CWGx_data; modulated CWGxB and CWGxD are
held inactive for the dead band duration shown; dead band affects only the first pulse after the direction change.
FIGURE 20-9: CWG HALF-BRIDGE MODE OPERATION
CWGx_clock
CWGxA
CWGxC
Rising Event Dead Band Rising Event D
Falling Event Dead Band Falling Event Dead Band
CWGxB
CWGxD
CWGx_data
Note: CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out

PIC16(L)F18857/77
20.9 CWG Steering Mode 20.9.1 STEERING SYNCHRONIZATION
In Steering mode (MODE = 00x), the CWG allows any Changing the MODE bits allows for two modes of steer-
combination of the CWGxx pins to be the modulated ing, synchronous and asynchronous.
signal. The same signal can be simultaneously avail- When MODE = 000, the steering event is asynchro-
able on multiple pins, or a fixed-value output can be nous and will happen at the end of the instruction that
presented. writes to STRx (that is, immediately). In this case, the
When the respective STRx bit of CWGxOCON0 is ‘0’, output signal at the output pin may be an incomplete
the corresponding pin is held at the level defined. When waveform. This can be useful for immediately removing
the respective STRx bit of CWGxOCON0 is ‘1’, the pin a signal from the pin.
is driven by the input data signal. The user can assign When MODE = 001, the steering update is synchro-
the input data signal to one, two, three, or all four output nous and occurs at the beginning of the next rising
pins. edge of the input data signal. In this case, steering the
The POLx bits of the CWGxCON1 register control the output on/off will always produce a complete waveform.
signal polarity only when STRx = 1. Figure 20-10 and Figure 20-11 illustrate the timing of
The CWG auto-shutdown operation also applies in asynchronous and synchronous steering, respectively.
Steering modes as described in Section 20.10 “Auto-
Shutdown”. An auto-shutdown event will only affect
pins that have STRx = 1.
FIGURE 20-10: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION

(MODE<2:0> = 000)
Rising Event
CWGx_data
(Rising and Falling Source)
STR<D:A>
CWGx<D:A> OVR<D:A> OVR<D:A> Data
follows CWGx_data
FIGURE 20-11: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION

(MODE<2:0> = 001)
CWGx_data
(Rising and Falling Source)
STR<D:A>
CWGx<D:A> OVR<D:A> Data OVR<D:A> Data
follows CWGx_data

PIC16(L)F18857/77
20.10 Auto-Shutdown 20.11 Operation During Sleep
Auto-shutdown is a method to immediately override the The CWG module operates independently from the
CWG output levels with specific overrides that allow for system clock and will continue to run during Sleep,
safe shutdown of the circuit. The shutdown state can be provided that the clock and input sources selected
either cleared automatically or held until cleared by remain active.
software. The auto-shutdown circuit is illustrated in The HFINTOSC remains active during Sleep when all
Figure 20-12. the following conditions are met:
20.10.1 SHUTDOWN • CWG module is enabled
The shutdown state can be entered by either of the • Input source is active
following two methods: • HFINTOSC is selected as the clock source,
regardless of the system clock source selected.
• Software generated
• External Input In other words, if the HFINTOSC is simultaneously
selected as the system clock and the CWG clock
20.10.1.1 Software Generated Shutdown source, when the CWG is enabled and the input source
is active, then the CPU will go idle during Sleep, but the
Setting the SHUTDOWN bit of the CWGxAS0 register HFINTOSC will remain active and the CWG will con-
will force the CWG into the shutdown state. tinue to operate. This will have a direct effect on the
When the auto-restart is disabled, the shutdown state Sleep mode current.
will persist as long as the SHUTDOWN bit is set.
When auto-restart is enabled, the SHUTDOWN bit will
clear automatically and resume operation on the next
rising edge event.
20.10.2 EXTERNAL INPUT SOURCE

External shutdown inputs provide the fastest way to
safely suspend CWG operation in the event of a Fault
condition. When any of the selected shutdown inputs
goes active, the CWG outputs will immediately go to the
selected override levels without software delay. Several
input sources can be selected to cause a shutdown con-
dition. All input sources are active-low. The sources are:
• Comparator C1OUT_sync
• Comparator C2OUT_sync
• Timer2 – TMR2_postscaled
• CWGxIN input pin
Shutdown inputs are selected using the CWGxAS1
register (Register 20-6).
Note: Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state can-
not be cleared, except by disabling auto-
shutdown, as long as the shutdown input
level persists.

FIGURE 20-12: CWG SHUTDOWN BLOCK DIAGRAM
PIC16(L)F18857/77
Write ‘1’ to Rev. 10-000172B
1/21/2015
SHUTDOWN bit
PPS
INAS
CWGINPPS
C1OUT_sync
C1AS
C2OUT_sync
C2AS
TMR2_postscaled SHUTDOWN S
S Q
TMR2AS
D Q CWG_shutdown
TMR4_postscaled
REN FREEZE
R
TMR4AS Write ‘0’ to
SHUTDOWN bit
TMR6_postscaled CWG_data CK
TMR6AS
DS40001825F-page 294
PIC16(L)F18857/77
20.12 Configuring the CWG 20.12.2 AUTO-SHUTDOWN RESTART
The following steps illustrate how to properly configure After an auto-shutdown event has occurred, there are
the CWG. two ways to resume operation:
1. Ensure that the TRIS control bits corresponding • Software controlled

to the desired CWG pins for your application are • Auto-restart
set so that the pins are configured as inputs. The restart method is selected with the REN bit of the
2. Clear the EN bit, if not already cleared. CWGxCON2 register. Waveforms of software controlled
3. Set desired mode of operation with the MODE and automatic restarts are shown in Figure 20-13 and
bits. Figure 20-14.
4. Set desired dead-band times, if applicable to
mode, with the CWGxDBR and CWGxDBF reg- 20.12.2.1 Software Controlled Restart
isters. When the REN bit of the CWGxAS0 register is cleared,
5. Setup the following controls in the CWGxAS0 the CWG must be restarted after an auto-shutdown
and CWGxAS1 registers. event by software. Clearing the shutdown state
requires all selected shutdown inputs to be low, other-
a. Select the desired shutdown source.
wise the SHUTDOWN bit will remain set. The overrides
b. Select both output overrides to the desired will remain in effect until the first rising edge event after
levels (this is necessary even if not using auto- the SHUTDOWN bit is cleared. The CWG will then
shutdown because start-up will be from a shut- resume operation.
down state).
c. Set which pins will be affected by auto-shut- 20.12.2.2 Auto-Restart
down with the CWGxAS1 register. When the REN bit of the CWGxCON2 register is set,
d. Set the SHUTDOWN bit and clear the REN bit. the CWG will restart from the auto-shutdown state
automatically. The SHUTDOWN bit will clear automati-
6. Select the desired input source using the cally when all shutdown sources go low. The overrides
CWGxISM register. will remain in effect until the first rising edge event after
7. Configure the following controls. the SHUTDOWN bit is cleared. The CWG will then
a. Select desired clock source using the resume operation.
CWGxCLKCON register.
b. Select the desired output polarities using the
CWGxCON1 register.
c. Set the output enables for the desired outputs.
8. Set the EN bit.
9. Clear TRIS control bits corresponding to the
desired output pins to configure these pins as
outputs.
10. If auto-restart is to be used, set the REN bit and
the SHUTDOWN bit will be cleared automati-
cally. Otherwise, clear the SHUTDOWN bit to
start the CWG.
20.12.1 PIN OVERRIDE LEVELS

The levels driven to the output pins, while the shutdown
input is true, are controlled by the LSBD and LSAC bits
of the CWGxAS0 register. LSBD<1:0> controls the
CWGxB and D override levels and LSAC<1:0> controls
the CWGxA and C override levels. The control bit logic
level corresponds to the output logic drive level while in
the shutdown state. The polarity control does not affect
the override level.

FIGURE 20-13: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01, LSBD = 01)
PIC16(L)F18857/77
Shutdown Event Ceases REN Cleared by Software
CWG Input
Source
Shutdown Source
SHUTDOWN
CWGxA Tri-State (No Pulse)

CWGxC
CWGxB Tri-State (No Pulse)

CWGxD
No Shutdown
Shutdown Output Resumes
FIGURE 20-14: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01, LSBD = 01)
Shutdown Event Ceases REN auto-cleared by hardware
CWG Input
Source
Shutdown Source
SHUTDOWN
CWGxA Tri-State (No Pulse)

DS40001825F-page 296
CWGxC
CWGxB Tri-State (No Pulse)

CWGxD
No Shutdown
Shutdown Output Resumes
PIC16(L)F18857/77
20.13 Register Definitions: CWG Control
Long bit name prefixes for the CWG peripherals are
shown in Section 1.1 “Register and Bit naming con-
ventions”.
TABLE 20-3: LONG BIT NAMES PREFIXES
FOR CWG PERIPHERALS
Peripheral Bit Name Prefix
CWG1 CWG1
CWG2 CWG2
CWG3 CWG3
REGISTER 20-1: CWGxCON0: CWGx CONTROL REGISTER 0

R/W-0/0 R/W/HC-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
EN LD(1) — — — MODE<2:0>
bit 7 bit 0
Legend:
bit 7 EN: CWGx Enable bit

1 = Module is enabled
0 = Module is disabled
bit 6 LD: CWGx Load Buffer bits(1)
1 = Buffers to be loaded on the next rising/falling event
0 = Buffers not loaded
bit 2-0 MODE<2:0>: CWGx Mode bits
111 = Reserved
110 = Reserved
101 = CWG outputs operate in Push-Pull mode
100 = CWG outputs operate in Half-Bridge mode
011 = CWG outputs operate in Reverse Full-Bridge mode
010 = CWG outputs operate in Forward Full-Bridge mode
001 = CWG outputs operate in Synchronous Steering mode
000 = CWG outputs operate in Steering mode
Note 1: This bit can only be set after EN = 1 and cannot be set in the same instruction that EN is set.

PIC16(L)F18857/77
REGISTER 20-2: CWGxCON1: CWGx CONTROL REGISTER 1

U-0 U-0 R-x U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IN — POLD POLC POLB POLA
bit 7 bit 0
Legend:

bit 5 IN: CWG Input Value
bit 3 POLD: CWGxD Output Polarity bit
1 = Signal output is inverted polarity
0 = Signal output is normal polarity
bit 2 POLC: CWGxC Output Polarity bit
bit 1 POLB: CWGxB Output Polarity bit
bit 0 POLA: CWGxA Output Polarity bit

PIC16(L)F18857/77
REGISTER 20-3: CWGxDBR: CWGx RISING DEAD-BAND COUNTER REGISTER

— — DBR<5:0>
bit 7 bit 0
Legend:

bit 5-0 DBR<5:0>: Rising Event Dead-Band Value for Counter bits
REGISTER 20-4: CWGxDBF: CWGx FALLING DEAD-BAND COUNTER REGISTER

— — DBF<5:0>
bit 7 bit 0
Legend:

bit 5-0 DBF<5:0>: Falling Event Dead-Band Value for Counter bits

PIC16(L)F18857/77
REGISTER 20-5: CWGxAS0: CWGx AUTO-SHUTDOWN CONTROL REGISTER 0

R/W/HS-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 U-0 U-0
SHUTDOWN(1, 2) REN LSBD<1:0> LSAC<1:0> — —
bit 7 bit 0
Legend:
bit 7 SHUTDOWN: Auto-Shutdown Event Status bit(1, 2)

1 = An Auto-Shutdown state is in effect
0 = No Auto-shutdown event has occurred
bit 6 REN: Auto-Restart Enable bit
1 = Auto-restart enabled
0 = Auto-restart disabled
bit 5-4 LSBD<1:0>: CWGxB and CWGxD Auto-Shutdown State Control bits
11 = A logic ‘1’ is placed on CWGxB/D when an auto-shutdown event is present
10 = A logic ‘0’ is placed on CWGxB/D when an auto-shutdown event is present
01 = Pin is tri-stated on CWGxB/D when an auto-shutdown event is present
00 = The inactive state of the pin, including polarity, is placed on CWGxB/D after the required
dead-band interval
bit 3-2 LSAC<1:0>: CWGxA and CWGxC Auto-Shutdown State Control bits
11 = A logic ‘1’ is placed on CWGxA/C when an auto-shutdown event is present
10 = A logic ‘0’ is placed on CWGxA/C when an auto-shutdown event is present
01 = Pin is tri-stated on CWGxA/C when an auto-shutdown event is present
00 = The inactive state of the pin, including polarity, is placed on CWGxA/C after the required
dead-band interval
Note 1: This bit may be written while EN = 0 (CWGxCON0 register) to place the outputs into the shutdown config-
uration.
2: The outputs will remain in auto-shutdown state until the next rising edge of the input signal after this bit is
cleared.

PIC16(L)F18857/77
REGISTER 20-6: CWGxAS1: CWGx AUTO-SHUTDOWN CONTROL REGISTER 1

— AS6E AS5E AS4E AS3E AS2E AS1E AS0E
bit 7 bit 0
Legend:

bit 6 AS6E: CLC2 Output bit
1 = LC2_out shut down is enabled
0 = LC2_out shut down is disabled
bit 5 AS5E: Comparator C2 Output bit
1 = C2 output shut-down is enabled
0 = C2 output shut-down is disabled
bit 4 AS4E: Comparator C1 Output bit
1 = C1 output shut-down is enabled
0 = C1 output shut-down is disabled
bit 3 AS3E: TMR6 Postscale Output bit
1 = TMR6 output shut-down is enabled
0 = TMR6 output shut-down is disabled
1 = TMR4 output shut-down is enabled
0 = TMR4 output shut-down is disabled
1 = TMR2 Postscale shut-down is enabled
0 = TMR2 Postscale shut-down is disabled
bit 0 AS0E: CWGx Input Pin bit
1 = Input pin selected by CWGxPPS shut-down is enabled
0 = Input pin selected by CWGxPPS shut-down is disabled

PIC16(L)F18857/77
REGISTER 20-7: CWGxSTR: CWGx STEERING CONTROL REGISTER(1)

OVRD OVRC OVRB OVRA STRD(2) STRC(2) STRB(2) STRA(2)
bit 7 bit 0
Legend:
bit 7 OVRD: Steering Data D bit

bit 6 OVRC: Steering Data C bit
bit 5 OVRB: Steering Data B bit
bit 4 OVRA: Steering Data A bit
bit 3 STRD: Steering Enable D bit(2)
1 = CWGxD output has the CWGx_data waveform with polarity control from POLD bit
0 = CWGxD output is assigned the value of OVRD bit
bit 2 STRC: Steering Enable C bit(2)
1 = CWGxC output has the CWGx_data waveform with polarity control from POLC bit
0 = CWGxC output is assigned the value of OVRC bit
bit 1 STRB: Steering Enable B bit(2)
1 = CWGxB output has the CWGx_data waveform with polarity control from POLB bit
0 = CWGxB output is assigned the value of OVRB bit
bit 0 STRA: Steering Enable A bit(2)
1 = CWGxA output has the CWGx_data waveform with polarity control from POLA bit
0 = CWGxA output is assigned the value of OVRA bit
Note 1: The bits in this register apply only when MODE<2:0> = 00x.
2: This bit is effectively double-buffered when MODE<2:0> = 001.

PIC16(L)F18857/77
REGISTER 20-8: CWGxCLKCON: CWGx CLOCK SELECTION REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0
— — — — — — — CS
bit 7 bit 0
Legend:

bit 0 CS: CWGx Clock Selection bit
1 = HFINTOSC 16 MHz is selected
0 = FOSC is selected
REGISTER 20-9: CWGxISM: CWGx INPUT SELECTION REGISTER

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — IS<3:0>
bit 7 bit 0
Legend:

bit 3-0 IS<3:0>: CWGx Input Selection bits
1111 = LC4_out
1110 = LC3_out
1101 = LC2_out
1100 = LC1_out
1011 = DSM_out
1010 = C2OUT_sync
1001 = C1OUT_sync
1000 = NCO1_out
0111 = PWM7_out
0110 = PWM6_out
0101 = CCP5_out
0100 = CCP4_out
0011 = CCP3_out
0010 = CCP2_out
0001 = CCP1_out
0000 = CWGxINPPS

PIC16(L)F18857/77
TABLE 20-4: SUMMARY OF REGISTERS ASSOCIATED WITH CWG
Register
on Page
CWG1CLKCON — — — — — — — CS 303
CWG1ISM — — — — IS<3:0> 303
CWG1DBR — — DBR<5:0> 299
CWG1DBF — — DBF<5:0> 299
CWG1CON0 EN LD — — — MODE<2:0> 302
CWG1CON1 — — IN — POLD POLC POLB POLA 298
CWG1AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 300
CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 302
CWG2CLKCON — — — — — — — CS 303
CWG2ISM — — — — IS<3:0> 303
CWG2DBR — — DBR<5:0> 299
CWG2DBF — — DBF<5:0> 299
CWG3CLKCON — — — — — — — CS 303
CWG3ISM — — — — IS<3:0> 303
CWG3DBR — — DBR<5:0> 299
CWG3DBF — — DBF<5:0> 299
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by CWG.

PIC16(L)F18857/77
21.0 ZERO-CROSS DETECTION 21.1 External Resistor Selection
(ZCD) MODULE The ZCD module requires a current limiting resistor in
The ZCD module detects when an A/C signal crosses series with the external voltage source. The impedance
through the ground potential. The actual zero crossing and rating of this resistor depends on the external
threshold is the zero crossing reference voltage, source peak voltage. Select a resistor value that will drop
VCPINV, which is typically 0.75V above ground. all of the peak voltage when the current through the
resistor is nominally 300 A. Refer to Equation 21-1 and
The connection to the signal to be detected is through Figure 21-1. Make sure that the ZCD I/O pin internal
a series current limiting resistor. The module applies a weak pull-up is disabled so it does not interfere with the
current source or sink to the ZCD pin to maintain a current source and sink.
constant voltage on the pin, thereby preventing the pin
voltage from forward biasing the ESD protection
EQUATION 21-1: EXTERNAL RESISTOR
diodes. When the applied voltage is greater than the
reference voltage, the module sinks current. When the
applied voltage is less than the reference voltage, the
module sources current. The current source and sink
action keeps the pin voltage constant over the full V PEAK-
R SERIES = ----------------
range of the applied voltage. The ZCD module is –4
shown in the simplified block diagram Figure 21-2.
3 10
The ZCD module is useful when monitoring an A/C
waveform for, but not limited to, the following purposes:
• A/C period measurement
• Accurate long term time measurement
FIGURE 21-1: EXTERNAL VOLTAGE
• Dimmer phase delayed drive
• Low EMI cycle switching VMAXPEAK
VPEAK VMINPEAK
VCPINV

PIC16(L)F18857/77
FIGURE 21-2: SIMPLIFIED ZCD BLOCK DIAGRAM
VPULLUP Rev. 10-000194B

5/14/2014
optional
VDD RPULLUP
- ZCDxIN RSERIES
External
Zcpinv + RPULLDOWN voltage
source
optional
ZCDx_output
D Q OUT bit
POL
Q1
Interrupt
det
INTP Set
ZCDIF
INTN flag
Interrupt
det

PIC16(L)F18857/77
21.2 ZCD Logic Output 21.5 Correcting for VCPINV offset
The ZCD module includes a Status bit, which can be The actual voltage at which the ZCD switches is the
read to determine whether the current source or sink is reference voltage at the non-inverting input of the ZCD
active. The OUT bit of the ZCDxCON register is set op amp. For external voltage source waveforms other
when the current sink is active, and cleared when the than square waves, this voltage offset from zero
current source is active. The OUT bit is affected by the causes the zero-cross event to occur either too early or
polarity bit. too late.
21.3 ZCD Logic Polarity 21.5.1 CORRECTION BY AC COUPLING

When the external voltage source is sinusoidal, the
The POL bit of the ZCDxCON register inverts the
effects of the ZCPINV offset can be eliminated by
ZCDxOUT bit relative to the current source and sink
isolating the external voltage source from the ZCD pin
output. When the POL bit is set, a OUT high indicates
with a capacitor, in addition to the voltage reducing
that the current source is active, and a low output
resistor. The capacitor will cause a phase shift resulting
indicates that the current sink is active.
in the ZCD output switch in advance of the actual zero
The POL bit affects the ZCD interrupts. See Section crossing event. The phase shift will be the same for
21.4 “ZCD Interrupts”. both rising and falling zero crossings, which can be
compensated for by either delaying the CPU response
21.4 ZCD Interrupts to the ZCD switch by a timer or other means, or
selecting a capacitor value large enough that the phase
An interrupt will be generated upon a change in the shift is negligible.
ZCD logic output when the appropriate interrupt
enables are set. A rising edge detector and a falling To determine the series resistor and capacitor values
edge detector are present in the ZCD for this purpose. for this configuration, start by computing the
impedance, Z, to obtain a peak current of 300 A. Next,
The ZCDIF bit of the PIR2 register will be set when arbitrarily select a suitably large non-polar capacitor
either edge detector is triggered and its associated and compute its reactance, Xc, at the external voltage
enable bit is set. The INTP enables rising edge inter- source frequency. Finally, compute the series resistor,
rupts and the INTN bit enables falling edge interrupts. capacitor peak voltage, and phase shift by the formulas
Both are located in the ZCDxCON register. shown in Equation 21-2.
To fully enable the interrupt, the following bits must be set: When this technique is used and the input signal is not
• ZCDIE bit of the PIE2 register present, the ZCD will tend to oscillate. To avoid this
• INTP bit of the ZCDxCON register oscillation, connect the ZCD pin to VDD or GND with a
(for a rising edge detection) high-impedance resistor such as 200K.
• INTN bit of the ZCDxCON register
(for a falling edge detection)
• PEIE and GIE bits of the INTCON register
Changing the POL bit will cause an interrupt, regard-
less of the level of the EN bit.
The ZCDIF bit of the PIR2 register must be cleared in
software as part of the interrupt service. If another edge
is detected while this flag is being cleared, the flag will
still be set at the end of the sequence.

PIC16(L)F18857/77
EQUATION 21-2: R-C CALCULATIONS 21.5.2 CORRECTION BY OFFSET
VPEAK = External voltage source peak voltage
CURRENT
f = External voltage source frequency When the waveform is varying relative to VSS, then the
C = Series capacitor zero cross is detected too early as the waveform falls
R = Series resistor and too late as the waveform rises. When the
VC = Peak capacitor voltage
waveform is varying relative to VDD, then the zero cross
is detected too late as the waveform rises and too early
Φ = Capacitor induced zero crossing phase advance in
radians
as the waveform falls. The actual offset time can be
determined for sinusoidal waveforms with the
TΦ = Time ZC event occurs before actual zero crossing
corresponding equations shown in Equation 21-3.
V PEAK-
Z = -------------------
3  10
–4 EQUATION 21-3: ZCD EVENT OFFSET
1 -
X C = ------------ When External Voltage Source is relative to Vss:
2fC
Vcpinv
R =
2
Z – XC
2 asin  ------------------
V PEAK
T OFFSET = ----------------------------------
–4 2  Freq
V C = X C  3  10 
When External Voltage Source is relative to VDD:
–1 X C
 = Tan  -------
 R
V DD – Vcpinv
- asin  --------------------------------
T = --------
2f  V PEAK 
T OFFSET = -------------------------------------------------
2  Freq
EXAMPLE 21-1: R-C CALCULATIONS
This offset time can be compensated for by adding a
VRMS = 120
pull-up or pull-down biasing resistor to the ZCD pin. A
VPEAK = VRMS *= 169.7
pull-up resistor is used when the external voltage
f = 60 Hz
source is varying relative to VSS. A pull-down resistor is
C = 0.1 µF used when the voltage is varying relative to VDD. The
resistor adds a bias to the ZCD pin so that the target
169.7 -
V PEAK- = -------------------
Z = ------------------- = 565.7k  external voltage source must go to zero to pull the pin
–4 –4
3  10 3  10 voltage to the VCPINV switching voltage. The pull-up or
pull-down value can be determined with the equations
1 1
X C = ------------- = -------------------------------------------------- = 26.53k  shown in Equation 21-4.
2fC  2  60  1  10 
–7
EQUATION 21-4: ZCD PULL-UP/DOWN

2 2
R =  Z  X C  = 565.1k   computed 
R = 560k  used  When External Signal is relative to Vss:
R SERIES  V PULLUP – V cpinv 

ZR =
2 2
R + X C = 560.6k   u sin g actual resistor 
R PULLUP = ------------------------------------------------------------------------
V cpinv
I PEAK = V PEAK –6 When External Signal is relative to VDD:

- = 302.7  10
-----------------
ZR
R SERIES  V cpinv 
V C = X C  Ipeak = 8.0V R PULLDOWN = --------------------------------------------
 V DD – V cpinv 
–1 X C
 = Tan  ------- = 0.047 radians
 R
 - = 125.6s
T = --------
2f

PIC16(L)F18857/77
21.6 Handling VPEAK variations
If the peak amplitude of the external voltage is
expected to vary, the series resistor must be selected
to keep the ZCD current source and sink below the
design maximum range of ± 600 A and above a
reasonable minimum range. A general rule of thumb is
that the maximum peak voltage can be no more than
six times the minimum peak voltage. To ensure that the
maximum current does not exceed ± 600 A and the
minimum is at least ± 100 A, compute the series
resistance as shown in Equation 21-5. The
compensating pull-up for this series resistance can be
determined with Equation 21-4 because the pull-up
value is independent from the peak voltage.
EQUATION 21-5: SERIES R FOR V RANGE
R SERIES = V MAXPEAK + V MINPEAK

---------------------------------------------------------
–4
7 10
21.7 Operation During Sleep

The ZCD current sources and interrupts are unaffected
by Sleep.

The ZCD circuit can be configured to default to the active
or inactive state on Power-On-Reset (POR). When the
ZCDDIS Configuration bit is cleared, the ZCD circuit will
be active at POR. When the ZCD Configuration bit is set,
the EN bit of the ZCDxCON register must be set to
enable the ZCD module.
21.9 Disabling the ZCD Module

The ZCD module can be disabled in two ways:
1. Configuration Word 2H has the ZCD bit, which
disables the ZCD module when set, but it can be
enabled using the EN bit of the ZCDCON
register (Register 21-1). If the ZCD bit is clear,
the ZCD is always enabled.
2. The ZCD can also be disabled using the
ZCDMD bit of the PMD2 register (Register 14-3)
this is subject to the status of the ZCD bit.

PIC16(L)F18857/77
21.10 Register Definitions: ZCD Control
REGISTER 21-1: ZCDCON: ZERO-CROSS DETECTION CONTROL REGISTER

R/W-q/q U-0 R-x/x R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
EN — OUT POL — — INTP INTN
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
bit 7 EN: Zero-Cross Detection Enable bit

1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current.
0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls.
bit 5 OUT: Zero-Cross Detection Logic Level bit
POL bit = 1:
1 = ZCD pin is sourcing current
0 = ZCD pin is sinking current
POL bit = 0:
1 = ZCD pin is sinking current
0 = ZCD pin is sourcing current
bit 4 POL: Zero-Cross Detection Logic Output Polarity bit
1 = ZCD logic output is inverted
0 = ZCD logic output is not inverted
bit 1 INTP: Zero-Cross Positive Edge Interrupt Enable bit
1 = ZCDIF bit is set on low-to-high ZCDx_output transition
0 = ZCDIF bit is unaffected by low-to-high ZCDx_output transition
bit 0 INTN: Zero-Cross Negative Edge Interrupt Enable bit
1 = ZCDIF bit is set on high-to-low ZCDx_output transition
0 = ZCDIF bit is unaffected by high-to-low ZCDx_output transition
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE

Register
on page
ZCDxCON EN — OUT POL — — INTP INTN 310
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module.
TABLE 21-2: SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE

Register
on Page
CONFIG2 13:8 DEBUG STVREN PPS1WAY ZCDDIS BORV — BOREN<1:0> 93

7:0 LPBOREN — — — PWRTE MCLRE WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module.

PIC16(L)F18857/77
22.0 CONFIGURABLE LOGIC CELL Refer to Figure 22-1 for a simplified diagram showing
signal flow through the CLCx.
(CLC)
Possible configurations include:
The Configurable Logic Cell (CLCx) module provides
programmable logic that operates outside the speed • Combinatorial Logic
limitations of software execution. The logic cell takes up - AND
to 32 input signals and, through the use of configurable - NAND
gates, reduces the 32 inputs to four logic lines that drive - AND-OR
one of eight selectable single-output logic functions. - AND-OR-INVERT
Input sources are a combination of the following: - OR-XOR
• I/O pins - OR-XNOR
• Internal clocks • Latches
• Peripherals - S-R
• Register bits - Clocked D with Set and Reset
The output can be directed internally to peripherals and - Transparent D with Set and Reset
to an output pin. - Clocked J-K with Reset
The CLC modules available are shown in Table 22-1.
TABLE 22-1: AVAILABLE CLC MODULES

Device CLC1 CLC2 CLC3 CLC4
PIC16(L)F18857/77 ● ● ● ●
Note: The CLC1, CLC2, CLC3 and CLC4 are

four separate module instances of the
same CLC module design. Throughout
this section, the lower case ‘x’ in register
and bit names is a generic reference to
the CLC number (which should be substi-
tuted with 1, 2, 3, or 4 during code devel-
opment). For example, the control register
is generically described in this chapter as
CLCxCON, but the actual device registers
are CLC1CON, CLC2CON, CLC3CON
and CLC4CON. Similarly, the LCxEN bit
represents the LC1EN, LC2EN, LC3EN
and LC4EN bits.

PIC16(L)F18857/77
FIGURE 22-1: CLCx SIMPLIFIED BLOCK DIAGRAM
Rev. 10-000025F
8/14/2015
OUT
D Q
&LCxOUT
Q1
LCx_in[0]
LCx_in[1] LCx_out
to Peripherals
LCx_in[2]
Input Data Selection Gates(1)
. lcxg1
EN
CLCxPPS
. lcxg2
lcxg3
Logic
Function
(2)
lcxq
PPS CLCx
. lcxg4
POL TRIS
LCx_in[45] MODE<2:0> Interrupt

LCx_in[46] det
LCx_in[47]
INTP
set bit
INTN CLCxIF
Interrupt
det
Note 1: See Figure 22-2: Input Data Selection and Gating

2: See Figure 22-3: Programmable Logic Functions.

PIC16(L)F18857/77
22.1 CLCx Setup TABLE 22-2: CLCx DATA INPUT SELECTION
Programming the CLCx module is performed by LCxDyS<4:0>
CLCx Input Source
Value
configuring the four stages in the logic signal flow. The
four stages are: 110000 to 111111 [48+] Reserved
101111 [47] CWG3B output
• Data selection
101110 [46] CWG3A output
• Data gating
101101 [45] CWG2B output
• Logic function selection 101100 [44] CWG2A output
• Output polarity 101011 [43] CWG1B output
Each stage is setup at run time by writing to the corre- 101010 [42] CWG1A output
sponding CLCx Special Function Registers. This has 101001 [41] MSSP2 SCK/SCL output
the added advantage of permitting logic reconfiguration 101000 [40] MSSP2 SDO/SDA output
on-the-fly during program execution. 100111 [39] MSSP1 SCK/SCL output
100110 [38] MSSP1 SDO/SDA output
22.1.1 DATA SELECTION
100101 [37] EUSART (TX/CK) output
There are 32 signals available as inputs to the 100100 [36] EUSART (DT) output
configurable logic. Four 32-input multiplexers are used 100011 [35] CLC4 output
to select the inputs to pass on to the next stage.
100010 [34] CLC3 output
Data selection is through four multiplexers as indicated 100001 [33] CLC2 output
on the left side of Figure 22-2. Data inputs in the figure 100000 [32] CLC1 output
are identified by a generic numbered input name. 011111 [31] DSM output
Table 22-2 correlates the generic input name to the 011110 [30] IOCIF
actual signal for each CLC module. The column labeled 011101 [29] ZCD output
‘LCxDyS<4:0> Value’ indicates the MUX selection code 011100 [28] Comparator 2 output
for the selected data input. LCxDyS is an abbreviation 011011 [27] Comparator 1 output
for the MUX select input codes: LCxD1S<4:0> through
011010 [26] NCO1 output
LCxD4S<4:0>.
011001 [25] PWM7 output
Data inputs are selected with CLCxSEL0 through 011000 [24] PWM6 output
CLCxSEL3 registers (Register 22-3 through 010111 [23] CCP5 output
Register 22-6).
010110 [22] CCP4 output
Note: Data selections are undefined at power-up. 010101 [21] CCP3 output
010100 [20] CCP2 output
010011 [19] CCP1 output
010010 [18] SMT2 output
010001 [17] SMT1 output
010000 [16] TMR6 to PR6 match
001111 [15] TMR5 overflow
001001 [9] CLKR output
001000 [8] FRC
000111 [7] SOSC
000110 [6] LFINTOSC
000101 [5] HFINTOSC
000100 [4] FOSC
000011 [3] CLCIN3PPS

PIC16(L)F18857/77
22.1.2 DATA GATING Data gating is indicated in the right side of Figure 22-2.
Only one gate is shown in detail. The remaining three
Outputs from the input multiplexers are directed to the
gates are configured identically with the exception that
desired logic function input through the data gating
the data enables correspond to the enables for that
stage. Each data gate can direct any combination of the
gate.
four selected inputs.
Note: Data gating is undefined at power-up. 22.1.3 LOGIC FUNCTION
The gate stage is more than just signal direction. The There are eight available logic functions including:
gate can be configured to direct each input signal as • AND-OR
inverted or non-inverted data. Directed signals are • OR-XOR
ANDed together in each gate. The output of each gate
• AND
can be inverted before going on to the logic function
stage. • S-R Latch
• D Flip-Flop with Set and Reset
The gating is in essence a 1-to-4 input
AND/NAND/OR/NOR gate. When every input is • D Flip-Flop with Reset
inverted and the output is inverted, the gate is an OR of • J-K Flip-Flop with Reset
all enabled data inputs. When the inputs and output are • Transparent Latch with Set and Reset
not inverted, the gate is an AND or all enabled inputs. Logic functions are shown in Figure 22-2. Each logic
Table 22-3 summarizes the basic logic that can be function has four inputs and one output. The four inputs
obtained in gate 1 by using the gate logic select bits. are the four data gate outputs of the previous stage.
The table shows the logic of four input variables, but The output is fed to the inversion stage and from there
to other peripherals, an output pin, and back to the
each gate can be configured to use less than four. If
CLCx itself.
no inputs are selected, the output will be zero or one,
depending on the gate output polarity bit. 22.1.4 OUTPUT POLARITY
TABLE 22-3: DATA GATING LOGIC The last stage in the Configurable Logic Cell is the
output polarity. Setting the LCxPOL bit of the CLCxPOL
CLCxGLSy LCxGyPOL Gate Logic register inverts the output signal from the logic stage.
0x55 1 AND Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
0x55 0 NAND
0xAA 1 NOR
0xAA 0 OR
0x00 0 Logic 0
0x00 1 Logic 1
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select
registers as follows:
• Gate 1: CLCxGLS0 (Register 22-7)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.

PIC16(L)F18857/77
22.2 CLCx Interrupts 22.6 CLCx Setup Steps
An interrupt will be generated upon a change in the The following steps should be followed when setting up
output value of the CLCx when the appropriate interrupt the CLCx:
enables are set. A rising edge detector and a falling • Disable CLCx by clearing the LCxEN bit.
edge detector are present in each CLC for this purpose.
• Select desired inputs using CLCxSEL0 through
The CLCxIF bit of the associated PIR5 register will be CLCxSEL3 registers (See Table 22-2).
set when either edge detector is triggered and its asso- • Clear any associated ANSEL bits.
ciated enable bit is set. The LCxINTP enables rising • Set all TRIS bits associated with inputs.
edge interrupts and the LCxINTN bit enables falling
• Clear all TRIS bits associated with outputs.
edge interrupts. Both are located in the CLCxCON
register. • Enable the chosen inputs through the four gates
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
To fully enable the interrupt, set the following bits: CLCxGLS3 registers.
• CLCxIE bit of the PIE5 register • Select the gate output polarities with the
• LCxINTP bit of the CLCxCON register (for a rising LCxGyPOL bits of the CLCxPOL register.
edge detection) • Select the desired logic function with the
• LCxINTN bit of the CLCxCON register (for a LCxMODE<2:0> bits of the CLCxCON register.
falling edge detection) • Select the desired polarity of the logic output with
• PEIE and GIE bits of the INTCON register the LCxPOL bit of the CLCxPOL register. (This
The CLCxIF bit of the PIR5 register, must be cleared in step may be combined with the previous gate out-
software as part of the interrupt service. If another edge put polarity step).
is detected while this flag is being cleared, the flag will • If driving a device pin, set the desired pin PPS
still be set at the end of the sequence. control register and also clear the TRIS bit
corresponding to that output.
22.3 Output Mirror Copies • If interrupts are desired, configure the following
bits:
Mirror copies of all LCxCON output bits are contained - Set the LCxINTP bit in the CLCxCON register
in the CLCxDATA register. Reading this register reads for rising event.
the outputs of all CLCs simultaneously. This prevents
- Set the LCxINTN bit in the CLCxCON
any reading skew introduced by testing or reading the
register for falling event.
LCxOUT bits in the individual CLCxCON registers.
- Set the CLCxIE bit of the PIE5 register.
22.4 Effects of a Reset - Set the GIE and PEIE bits of the INTCON
register.
The CLCxCON register is cleared to zero as the result • Enable the CLCx by setting the LCxEN bit of the
of a Reset. All other selection and gating values remain CLCxCON register.
unchanged.

The CLC module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
The HFINTOSC remains active during Sleep when the
CLC module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLC input
source, when the CLC is enabled, the CPU will go idle
during Sleep, but the CLC will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.

PIC16(L)F18857/77
FIGURE 22-2: INPUT DATA SELECTION AND GATING
Data Selection
LCx_in[0] 00000
Data GATE 1
lcxd1T LCxD1G1T
lcxd1N LCxD1G1N
LCx_in[46] 11111
LCxD2G1T
LCxD1S<5:0>
LCxD2G1N lcxg1
LCx_in[0] 00000
LCxD3G1T
LCxG1POL
lcxd2T
LCxD3G1N
lcxd2N
LCxD4G1T
LCx_in[46] 11111
LCxD2S<5:0> LCxD4G1N
LCx_in[0] 00000
Data GATE 2
lcxg2
lcxd3T
(Same as Data GATE 1)
lcxd3N
Data GATE 3
LCx_in[46] 11111
lcxg3
LCxD3S<5:0>
(Same as Data GATE 1)
LCx_in[0] 00000 Data GATE 4

lcxg4
lcxd4T (Same as Data GATE 1)
lcxd4N
LCx_in[46] 11111
LCxD4S<5:0>
Note: All controls are undefined at power-up.

PIC16(L)F18857/77
FIGURE 22-3: PROGRAMMABLE LOGIC FUNCTIONS
Rev. 10-000122A
5/18/2016
AND-OR OR-XOR
lcxg1 lcxg1
lcxg2 lcxg2
lcxq lcxq
lcxg3 lcxg3
lcxg4 lcxg4
LCxMODE<2:0> = 000 LCxMODE<2:0> = 001

4-input AND S-R Latch
lcxg1 lcxg1
S Q lcxq
lcxg2
lcxg2
lcxq
lcxg3
lcxg3
R
lcxg4 lcxg4
LCxMODE<2:0> = 010 LCxMODE<2:0> = 011

1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R
lcxg4
S
lcxg4
lcxg2 D Q lcxq D Q lcxq
lcxg2
lcxg1 R
lcxg1 R
lcxg3 lcxg3
LCxMODE<2:0> = 100 LCxMODE<2:0> = 101

J-K Flip-Flop with R 1-Input Transparent Latch with S and R
lcxg4
lcxg2 J Q lcxq S
lcxg2 D Q lcxq
lcxg1
lcxg4 K
R
lcxg3 LE
R
lcxg3
lcxg1
LCxMODE<2:0> = 110 LCxMODE<2:0> = 111

PIC16(L)F18857/77
22.7 Register Definitions: CLC Control
REGISTER 22-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER

R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
LCxEN — LCxOUT LCxINTP LCxINTN LCxMODE<2:0>
bit 7 bit 0
Legend:
bit 7 LCxEN: Configurable Logic Cell Enable bit

1 = Configurable logic cell is enabled and mixing input signals
0 = Configurable logic cell is disabled and has logic zero output
bit 5 LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCPOL; sampled from CLCxOUT
bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a rising edge occurs on CLCxOUT
0 = CLCxIF will not be set
bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a falling edge occurs on CLCxOUT
0 = CLCxIF will not be set
bit 2-0 LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits
111 = Cell is 1-input transparent latch with S and R
110 = Cell is J-K flip-flop with R
101 = Cell is 2-input D flip-flop with R
100 = Cell is 1-input D flip-flop with S and R
011 = Cell is S-R latch
010 = Cell is 4-input AND
001 = Cell is OR-XOR
000 = Cell is AND-OR

PIC16(L)F18857/77
REGISTER 22-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER

R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL
bit 7 bit 0
Legend:
bit 7 LCxPOL: CLCxOUT Output Polarity Control bit

1 = The output of the logic cell is inverted
0 = The output of the logic cell is not inverted
bit 3 LCxG4POL: Gate 3 Output Polarity Control bit
1 = The output of gate 3 is inverted when applied to the logic cell
0 = The output of gate 3 is not inverted

PIC16(L)F18857/77
REGISTER 22-3: CLCxSEL0: GENERIC CLCx DATA 0 SELECT REGISTER

— — LCxD1S<5:0>
bit 7 bit 0
Legend:

bit 5-0 LCxD1S<5:0>: CLCx Data1 Input Selection bits
See Table 22-2.

— — LCxD2S<5:0>
bit 7 bit 0
Legend:

bit 5-0 LCxD2S<5:0>: CLCx Data 2 Input Selection bits
See Table 22-2.

— — LCxD3S<5:0>
bit 7 bit 0
Legend:

See Table 22-2.

— — LCxD4S<5:0>
bit 7 bit 0
Legend:

See Table 22-2.

PIC16(L)F18857/77
REGISTER 22-7: CLCxGLS0: GATE 0 LOGIC SELECT REGISTER

LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N
bit 7 bit 0
Legend:
bit 7 LCxG1D4T: Gate 0 Data 4 True (non-inverted) bit

1 = CLCIN3 (true) is gated into CLCx Gate 0
0 = CLCIN3 (true) is not gated into CLCx Gate 0
bit 6 LCxG1D4N: Gate 0 Data 4 Negated (inverted) bit
1 = CLCIN3 (inverted) is gated into CLCx Gate 0
0 = CLCIN3 (inverted) is not gated into CLCx Gate 0
0 = CLCIN1 (true) is not gated into l CLCx Gate 0

PIC16(L)F18857/77

bit 7 bit 0
Legend:

0 = CLCIN0 (true) is not gated into CLCx Gate1

PIC16(L)F18857/77

bit 7 bit 0
Legend:


PIC16(L)F18857/77

bit 7 bit 0
Legend:


PIC16(L)F18857/77
REGISTER 22-11: CLCDATA: CLC DATA OUTPUT

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT
bit 7 bit 0
Legend:

bit 3 MLC4OUT: Mirror copy of LC4OUT bit

PIC16(L)F18857/77
TABLE 22-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx
Register
on Page
INTCON GIE PEIE ― ― ― ― ― INTEDG 133
PIR5 CLC4IF CLC3IF CLC2IF CLC1IF — TMR5GIF TMR3GIF TMR1GIF 148
PIE5 CLC4IE CLC4IE CLC2IE CLC1IE — TMR5GIE TMR3GIE TMR1GIE 139
CLC1CON LC1EN ― LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 318
CLC1POL LC1POL ― ― ― LC1G4POL LC1G3POL LC1G2POL LC1G1POL 319
CLC1SEL0 ― ― LC1D1S<5:0> 320
CLC1SEL1 ― ― LC1D2S<5:0> 320
CLC1SEL2 ― ― LC1D3S<5:0> 320
CLC1SEL3 ― ― LC1D4S<5:0> 320
CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 321
CLC2SEL0 ― ― LC2D1S<5:0> 320
CLC2SEL1 ― ― LC2D2S<5:0> 320
CLC2SEL2 ― ― LC2D3S<5:0> 320
CLC2SEL3 ― ― LC2D4S<5:0> 320
CLC3SEL0 ― ― LC3D1S<5:0> 320
CLC3SEL1 ― ― LC3D2S<5:0> 320
CLC3SEL2 ― ― LC3D3S<5:0> 320
CLC3SEL3 ― ― LC3D4S<5:0> 320
CLC4SEL0 ― ― LC4D1S<5:0> 320
CLC4SEL1 ― ― LC4D2S<5:0> 320
CLC4SEL2 ― ― LC4D3S<5:0> 320
CLC4SEL3 ― ― LC4D4S<5:0> 320
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.

PIC16(L)F18857/77
TABLE 22-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx (continued)
Register
on Page
CLCDATA ― ― ― ― MLC4OUT MLC3OUT MLC2OUT MLC1OUT 325
CLCIN0PPS ― ― ― CLCIN0PPS<4:0> 240

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.

PIC16(L)F18857/77
23.0 ANALOG-TO-DIGITAL
CONVERTER WITH
COMPUTATION (ADC2)
MODULE
The Analog-to-Digital Converter with Computation
(ADC2) allows conversion of an analog input signal to
a 10-bit binary representation of that signal. This device
uses analog inputs, which are multiplexed into a single
sample and hold circuit. The output of the sample and
hold is connected to the input of the converter. The
converter generates a 10-bit binary result via
successive approximation and stores the conversion
result into the ADC result registers (ADRESH:ADRESL
register pair).
Additionally, the following features are provided within
the ADC module:
• 8-bit Acquisition Timer
• Hardware Capacitive Voltage Divider (CVD)
support:
- 8-bit Precharge Timer
- Adjustable sample and hold capacitor array
- Guard ring digital output drive
• Automatic repeat and sequencing:
- Automated double sample conversion for
CVD
- Two sets of result registers (Result and
Previous result)
- Auto-conversion trigger
- Internal retrigger
• Computation features:
- Averaging and Low-Pass Filter functions
- Reference Comparison
- 2-level Threshold Comparison
- Selectable Interrupts
Figure 23-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
The ADC can generate an interrupt upon completion of
a conversion and upon threshold comparison. These
interrupts can be used to wake-up the device from
Sleep.

PIC16(L)F18857/77
FIGURE 23-1: ADC2 BLOCK DIAGRAM
ADPREF<1:0> Rev. 10-000034B
10/13/2015
VREF+ pin FVR_buffer1 11 Positive

Reference
10 Select
Reserved 01
00
ADNREF
VDD
1
VREF- pin
0
VSS ADCS<2:0>
AN0
ANa Vref- Vref+
External .
Channel . FOSC/n Fosc
. Divider FOSC
Inputs ADC
ANz ADC_clk
sampled Clock
VSS input Select FRC
FRC
Temp Indicator
Internal
Channel DACx_output ADC CLOCK SOURCE
Inputs
FVR_buffer1 ADC
Sample Circuit
CHS<4:0>
ADFM
set bit ADIF
10
complete 10-bit Result
Write to bit
GO/DONE
GO/DONE Q1 16
start
Q4
ADRESH ADRESL
Q2 Enable
Trigger Select
TRIGSEL<3:0> ADON
. . . VSS
Trigger Sources
AUTO CONVERSION
TRIGGER

PIC16(L)F18857/77
23.1 ADC Configuration
When configuring and using the ADC the following Note: It is recommended that when switching
functions must be considered: from an ADC channel of a higher voltage
to a channel of a lower voltage, the soft-
• Port configuration
ware selects the VSS channel before
• Channel selection switching to the channel of the lower volt-
• ADC voltage reference selection age. If the ADC does not have a dedicated
• ADC conversion clock source VSS input channel, the VSS selection
• Interrupt control (DAC1R<4:0> = b'00000') through the
DAC output channel can be used. If the
• Result formatting
DAC is in use, a free input channel can be
• Conversion Trigger Selection connected to VSS, and can be used in
• ADC Acquisition Time place of the DAC.
• ADC Precharge Time
• Additional Sample and Hold Capacitor 23.1.3 ADC VOLTAGE REFERENCE
• Single/Double Sample Conversion The ADPREF bits of the ADREF register provides
• Guard Ring Outputs control of the positive voltage reference. The positive
voltage reference can be:
23.1.1 PORT CONFIGURATION • VREF+ pin
The ADC can be used to convert both analog and • VDD
digital signals. When converting analog signals, the I/O • FVR 1.024V
pin should be configured for analog by setting the • FVR 2.048V
associated TRIS and ANSEL bits. Refer to • FVR 4.096V
Section 12.0 “I/O Ports” for more information. The ADNREF bit of the ADREF register provides
Note: Analog voltages on any pin that is defined control of the negative voltage reference. The negative
as a digital input may cause the input voltage reference can be:
buffer to conduct excess current. • VREF- pin
• VSS
23.1.2 CHANNEL SELECTION
See Section 16.0 “Fixed Voltage Reference (FVR)”
There are several channel selections available: for more details on the Fixed Voltage Reference.
• Eight PORTA pins (RA<7:0>)
23.1.4 CONVERSION CLOCK
• Eight PORTB pins (RB<7:0>)
• Eight PORTC pins (RC<7:0>) The source of the conversion clock is software
selectable via the ADCLK register and the ADCS bit of
• Eight PORTD pins (RD<7:0>, PIC16(L)F18877
the ADCON0 register. There are two possible clock
only)
sources:
• Three PORTE pins (RE<2:0>, PIC16(L)F18877
only) • FOSC/(2*(n+1)) (where n is from 0 to 63),
• FRC (dedicated RC oscillator)
• Temperature Indicator
• DAC output The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD peri-
• Fixed Voltage Reference (FVR)
ods as shown in Figure 23-2.
• AVSS (ground)
For correct conversion, the appropriate TAD specification
The ADPCH register determines which channel is must be met. Refer to Table 37-13 for more information.
connected to the sample and hold circuit. Table 23-1 gives examples of appropriate ADC clock
When changing channels, a delay is required before selections.
starting the next conversion. Refer to Section 23.2
Note 1: Unless using the FRC, any changes in
“ADC Operation” for more information.
the system clock frequency will change
the ADC clock frequency, which may
adversely affect the ADC result.
2: The internal control logic of the ADC runs
off of the clock selected by the ADCS bit of
ADCON0. What this can mean is when the
ADCS bit of ADCON0 is set to 1 (ADC runs
on FRC), there may be unexpected delays
in operation when setting ADC control bits.

PIC16(L)F18857/77
TABLE 23-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC
ADCCS<5:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Clock Source
FOSC/2 000000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
FOSC/4 000001 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s
FOSC/6 000010 187.5 ns(2) 300 ns(2) 375 ns(2) 750 ns(2) 1.5 s 6.0 s
(2) (2) (2)
FOSC/8 000011 250 s 400 ns 500 s 1.0 s 2.0 s 8.0 s(3)
... ... ... ... ... ... ... ...
FOSC/16 000111 500 ns(2) 800 ns(2) 1.0 s 2.0 s 4.0 s 16.0 s(2)
... ... ... ... ... ... ... ...
FOSC/128 111111 4.0 s 6.4 s 8.0 s 16.0 s(3) 32.0 s(2) 128.0 s(2)
FRC ADCS(ADCON0 1.0-6.0 s(1) 1.0-6.0 s(1) 1.0-6.0 s(1) 1.0-6.0 s(1) 1.0-6.0 s(1) 1.0-6.0 s(1)
<4>)=1
Legend: Shaded cells are outside of recommended range.
Note 1: See TAD parameter for FRC source typical TAD value.
2: These values violate the required TAD time.
3: Outside the recommended TAD time.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 23-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES (ADSC = 0)

Rev. 10-000035B
11/3/2016
Precharge Acquisition/ Conversion Time
Time Sharing Time (Traditional Timing of ADC Conversion)
1-255 TCY 1-255 TCY
(TPRE) (TACQ) TCY TCY-TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 2 TCY
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
External and Internal External and Internal Conversion starts

Channels are Channels share
charged/discharged charge Holding capacitor CHOLD is disconnected from analog input (typically 100ns)
If ADPRE 0 If ADACQ 0 If ADPRE = 0

If ADACQ = 0 On the following cycle:
(Traditional Operation Start) ADRESH:ADRESL is loaded,
GO bit is cleared,
Set GO bit ADIF bit is set,

PIC16(L)F18857/77
23.1.5 INTERRUPTS Figure 23-3 shows the two output formats.
The ADC module allows for the ability to generate an Software writes to the ADRES register pair are always
interrupt upon completion of an Analog-to-Digital right justified regardless of the selected format mode.
conversion. The ADC Interrupt Flag is the ADIF bit in Therefore, data read after writing to ADRES when
the PIR1 register. The ADC Interrupt Enable is the ADFRM0 = 0 will be shifted left six places. For exam-
ADIE bit in the PIE1 register. The ADIF bit must be ple, writing 0xFF to ADRESL will be read as 0xC0 in
cleared in software. ADRESL and 0x3F logical OR’d with whatever was in
the two MSbits in ADRESH.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the ADIE bit of the PIE1 register and the
PEIE bit of the INTCON register must both be set and
the GIE bit of the INTCON register must be cleared. If
all three of these bits are set, the execution will switch
to the Interrupt Service Routine.
23.1.6 RESULT FORMATTING

The 10-bit ADC conversion result can be supplied in
two formats, left justified or right justified. The ADFRM0
bit of the ADCON0 register controls the output format.
FIGURE 23-3: 10-BIT ADC CONVERSION RESULT FORMAT
ADRESH ADRESL
(ADFRM0 = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit ADC Result Unimplemented: Read as ‘0’
(ADFRM0 = 1) MSB LSB

bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’ 10-bit ADC Result

PIC16(L)F18857/77
23.2 ADC Operation 23.2.3 TERMINATING A CONVERSION
If a conversion must be terminated before completion,
23.2.1 STARTING A CONVERSION the ADGO bit can be cleared in software. The ADRESH
To enable the ADC module, the ADON bit of the and ADRESL registers will be updated with the partially
ADCON0 register must be set to a ‘1’. A conversion complete Analog-to-Digital conversion sample.
may be started by any of the following: Incomplete bits will match the last bit converted. In this
• Software setting the ADGO bit of ADCON0 to ‘1’ case, filter and/or threshold occur.
• An external trigger (selected by Register 23-3) Note: A device Reset forces all registers to their
• A continuous-mode retrigger (see section Reset state. Thus, the ADC module is
Section 23.5.8 “Continuous Sampling Mode”) turned off and any pending conversion is
. terminated.
Note: The ADGO bit should not be set in the

same instruction that turns on the ADC.
Refer to Section 23.2.7 “ADC Conver-
sion Procedure (Basic Mode)”.
23.2.2 COMPLETION OF A CONVERSION

When any individual conversion is complete, the value
already in ADRES is written into ADPREV (if
ADPSIS=1) and the new conversion results appear in
ADRES. When the conversion completes, the ADC
module will:
• Clear the ADGO bit (Unless the ADCONT bit of
ADCON0 is set)
• Set the ADIF Interrupt Flag bit
• Set the ADMATH bit
• Update ADACC
When ADDSEN=0 then after every conversion, or
when ADDSEN=1 then after every other conversion,
the following events occur:
• ADERR is calculated
• ADTIF is set if ADERR calculation meets thresh-
old requirements
In addition, on the completion of every conversion if
ADDSEN=0, or every other conversion if ADDSEN=1:
• ADSTPE is calculated
• Depending on ADSTPE, the threshold compari-
son may set ADTIF
Importantly, filter and threshold computations occur
after the conversion itself is complete. As such,
interrupt handlers responding to ADIF should check
ADTIF before reading filter and threshold results.

PIC16(L)F18857/77
23.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC oscillator source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
23.2.5 EXTERNAL TRIGGER DURING

SLEEP
If the external trigger is received during sleep while
ADC clock source is set to the FRC, then the ADC
module will perform the conversion and set the ADIF bit
upon completion.
If an external trigger is received when the ADC clock
source is something other than FRC, then the trigger
will be recorded, but the conversion will not begin until
the device exits Sleep.
23.2.6 AUTO-CONVERSION TRIGGER

The Auto-conversion Trigger allows periodic ADC mea-
surements without software intervention. When a rising
edge of the selected source occurs, the ADGO bit is set
by hardware.
The Auto-conversion Trigger source is selected with
the ADACT<4:0> bits of the ADACT register.

PIC16(L)F18857/77
Using the Auto-conversion Trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met. See
Table 23-2 for auto-conversion sources.
TABLE 23-2: ADC AUTO-CONVERSION TABLE
ADACT Value Source Peripheral Description
0x00 Disabled External Trigger Disabled
0x01 ADACTPPS Pin selected by ADACTPPS
0x02 TMR0 Timer0 overflow condition
0x04 TMR2 Match between Timer2
postscaled value and PR2
0x09 SMT1 Match between SMT1 and
SMT1PR
0x0A SMT2 Match between SMT2 and
SMT2PR
0x0B CCP1 CCP1 output
0x0C CCP2 CCP2 output
0x0D CCP3 CCP3 output
0x0E CCP4 CCP4 output
0x0F CCP5 CCP5 output
0x10 PWM6 PWM6 output
0x11 PWM7 PWM7 output
0x12 C1 Comparator C1 output
0x13 C2 Comparator C2 output
0x14 IOC Interrupt-on-change interrupt
trigger
0x15 CLC1 CLC1 output
0x19-0x1B Reserved Reserved, do not use
0x1C ADERR Read of ADERR register
0x1D ADRESH Read of ADRESH register
0x1E Reserved Reserved, do not use
0x1F ADPCH Read of ADPCH register

PIC16(L)F18857/77
23.2.7 ADC CONVERSION PROCEDURE EXAMPLE 23-1: ADC CONVERSION
(BASIC MODE) ;This code block configures the ADC
This is an example procedure for using the ADC to ;for polling, VDD and VSS references, FRC
perform an Analog-to-Digital conversion: ;oscillator and AN0 input.
;
1. Configure Port: ;Conversion start & polling for completion
• Disable pin output driver (Refer to the TRISx ;are included.
register) ;
BANKSEL ADCON1 ;
• Configure pin as analog (Refer to the
MOVLW B’11110000’ ;Right justify,
ANSELx register)
FRC
2. Configure the ADC module: ;oscillator
• Select ADC conversion clock MOVWF ADCON1 ;Vdd and Vss Vref
• Configure voltage reference BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
• Select ADC input channel BANKSEL ANSEL ;
(precharge+acquisition) BSF ANSEL,0 ;Set RA0 to analog
• Turn on ADC module BANKSEL ADCON0 ;
3. Configure ADC interrupt (optional): MOVLW B’00000001’ ;Select channel AN0
MOVWF ADCON0 ;Turn ADC On
• Clear ADC interrupt flag CALL SampleTime ;Acquisiton delay
• Enable ADC interrupt BSF ADCON0,ADGO ;Start conversion
• Enable peripheral interrupt (PEIE bit) BTFSC ADCON0,ADGO ;Is conversion done?
GOTO $-1 ;No, test again
• Enable global interrupt (GIE bit)(1) BANKSEL ADRESH ;
4. If ADACQ=0, software must wait the required MOVF ADRESH,W ;Read upper 2 bits
acquisition time (2). MOVWF RESULTHI ;store in GPR space
5. Start conversion by setting the ADGO bit. BANKSEL ADRESL ;
MOVF ADRESL,W ;Read lower 8 bits
6. Wait for ADC conversion to complete by one of
the following:
• Polling the ADGO bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 23.3 “ADC Acquisi-
tion Requirements”.

PIC16(L)F18857/77
23.3 ADC Acquisition Requirements source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
For the ADC to meet its specified accuracy, the charge selected (or changed), an ADC acquisition must be
holding capacitor (CHOLD) must be allowed to fully completed before the conversion can be started. To
charge to the input channel voltage level. The Analog calculate the minimum acquisition time, Equation 23-1
Input model is shown in Figure 23-4. The source may be used. This equation assumes that 1/2 LSb error
impedance (RS) and the internal sampling switch (RSS) is used (1,024 steps for the ADC). The 1/2 LSb error is
impedance directly affect the time required to charge the maximum error allowed for the ADC to meet its
the capacitor CHOLD. The sampling switch (RSS) specified resolution.
impedance varies over the device voltage (VDD), refer
to Figure 23-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 23-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50°C and external impedance of 10k  5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
1
V APPLIED  1 – -------------------------- = V CHOLD ;[1] VCHOLD charged to within 1/2 lsb
n+1
2 –1
–T C
 ----------
RC
V APPLIED  1 – e  = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
 
– Tc
 ---------
1
V APPLIED  1 – e  = V APPLIED  1 – -------------------------- ;combining [1] and [2]
RC
   n+1 
2 –1
Note: Where n = number of bits of the ADC.
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 10pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.37 µs
Therefore:
T ACQ = 2µs + 892ns +   50°C- 25°C   0.05 µs/°C  
= 4.62µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

PIC16(L)F18857/77
FIGURE 23-4: ANALOG INPUT MODEL
VDD
Analog Sampling
Input Switch
VT  0.6V
pin RIC  1k SS Rss
Rs
VA CPIN I LEAKAGE(1)
VT  0.6V CHOLD = 10 pF
5 pF
Ref-
6V
5V RSS
Legend: CHOLD = Sample/Hold Capacitance VDD 4V
3V
CPIN = Input Capacitance 2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 10 11
RIC = Interconnect Resistance
Sampling Switch
RSS = Resistance of Sampling Switch (k)
SS = Sampling Switch
VT = Threshold Voltage
Note 1: Refer to Table 37-4 (parameter D060).
FIGURE 23-5: ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB
REF- Zero-Scale
Transition Full-Scale
Transition REF+

PIC16(L)F18857/77
23.4 Capacitive Voltage Divider (CVD)
Features
The ADC module contains several features that allow
the user to perform a relative capacitance
measurement on any ADC channel using the internal
ADC sample and hold capacitance as a reference. This
relative capacitance measurement can be used to
implement capacitive touch or proximity sensing
applications. Figure 23-6 shows the basic block
diagram of the CVD portion of the ADC module.
FIGURE 23-6: HARDWARE CAPACITIVE VOLTAGE DIVIDER BLOCK DIAGRAM
VDD
ADPPOL = 1
ANx ADC Conversion Bus
ANx Pads
ADPPOL = 0
VGND
ADCAP<2:0>
Additional
Sample and
Hold Cap
VGND VGND VGND

PIC16(L)F18857/77
23.4.1 CVD OPERATION
A CVD operation begins with the ADC’s internal
sample and hold capacitor (CHOLD) being
disconnected from the path which connects it to the
external capacitive sensor node. While disconnected,
CHOLD is precharged to VDD or VSS, while the path to
the sensor node is also discharged to VDD or VSS.
Typically, this node is discharged to the level opposite
that of CHOLD. When the precharge phase is complete,
the VDD/VSS bias paths for the two nodes are shut off
and CHOLD and the path to the external sensor node
are reconnected, at which time the acquisition phase of
the CVD operation begins. During acquisition, a
capacitive voltage divider is formed between the
precharged CHOLD and sensor nodes, which results in
a final voltage level setting on CHOLD, which is
determined by the capacitances and precharge levels
of the two nodes. After acquisition, the ADC converts
the voltage level on CHOLD. This process is then
repeated with the selected precharge levels for both
the CHOLD and the inverted sensor nodes. Figure 23-7
shows the waveform for two inverted CVD
measurements, which is known as differential CVD
measurement.
FIGURE 23-7: DIFFERENTIAL CVD MEASUREMENT WAVEFORM
Precharge Acquisition Conversion Precharge Acquisition Conversion

VDD
ADC Sample and Hold Capacitor
Voltage
External Capacitive Sensor
VSS
First Sample Second Sample
Time

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23.4.2 PRECHARGE CONTROL 23.4.4 GUARD RING OUTPUTS
The precharge stage is an optional period of time that The purpose of the guard ring is to generate a signal in
brings the external channel and internal sample and phase with the CVD sensing signal to minimize the
hold capacitor to known voltage levels. Precharge is effects of the parasitic capacitance on sensing elec-
enabled by writing a non-zero value to the ADPRE reg- trodes. It also can be used as a mutual drive for mutual
ister. This stage is initiated when an ADC conversion capacitive sensing. For more information about active
begins, either from setting the ADGO bit, a special guard and mutual drive, see Application Note AN1478,
event trigger, or a conversion restart from the computa- “mTouchTM Sensing Solution Acquisition Methods
tion functionality. If the ADPRE register is cleared when Capacitive Voltage Divider” (DS01478).
an ADC conversion begins, this stage is skipped. Figure 23-8 shows a typical guard ring circuit. CGUARD
During the precharge time, CHOLD is disconnected from represents the capacitance of the guard ring trace
the outer portion of the sample path that leads to the placed on the PCB board. The user selects values for
external capacitive sensor and is connected to either RA and RB that will create a voltage profile on CGUARD,
VDD or VSS, depending on the value of the ADPPOL bit which will match the selected acquisition channel.
of ADCON1. At the same time, the port pin logic of the The ADC has two guard ring drive outputs, ADGRDA
selected analog channel is overridden to drive a digital and ADGRDB. These outputs can be routed through
high or low out, in order to precharge the outer portion PPS controls to I/O pins (see Section 13.0 “Periph-
of the ADC’s sample path, which includes the external eral Pin Select (PPS) Module” for details). The polar-
sensor. The output polarity of this override is also deter- ity of these outputs are controlled by the ADGPOL and
mined by the ADPPOL bit of ADCON1. The amount of ADIPEN bits of ADCON1.
time that this charging needs is controlled by the
ADPRE register. At the start of the first precharge stage, both outputs
are set to match the ADGPOL bit of ADCON1. Once
the acquisition stage begins, ADGRDA changes
Note: The external charging overrides the TRIS polarity, while ADGRDB remains unchanged. When
setting of the respective I/O pin. If there is performing a double sample conversion, setting the
a device attached to this pin, precharge ADIPEN bit of ADCON1 causes both guard ring
should not be used. outputs to transition to the opposite polarity of
ADGPOL at the start of the second precharge stage,
23.4.3 ACQUISITION CONTROL and ADGRDA toggles again for the second acquisition.
For more information on the timing of the guard ring
The Acquisition stage is an optional time for the voltage output, refer to Figure 23-8 and Figure 23-9.
on the internal sample and hold capacitor to charge or
discharge from the selected analog channel.This
FIGURE 23-8: GUARD RING CIRCUIT
acquisition time is controlled by the ADACQ register.
When ADPRE=0, acquisition starts at the beginning of
conversion. When ADPRE=1, the acquisition stage
begins when precharge ends. ADGRDA
RA
At the start of the acquisition stage, the port pin logic of
the selected analog channel is overridden to turn off the
digital high/low output drivers so they do not affect the
final result of the charge averaging. Also, the selected
ADC channel is connected to CHOLD. This allows RB CGUARD
charge averaging to proceed between the precharged
channel and the CHOLD capacitor. ADGRDB
Note: When ADPRE!=0, acquisition time cannot

be ‘0’. In this case, setting ADACQ to ‘0’
will set a maximum acquisition time (256
ADC clock cycles). When precharge is
disabled, setting ADACQ to ‘0’ will disable
hardware acquisition time control.

PIC16(L)F18857/77
FIGURE 23-9: DIFFERENTIAL CVD WITH GUARD RING OUTPUT WAVEFORM
VDD
Voltage
External Capacitive Sensor
Guard Ring Output
VSS
First Sample Second Sample
Time

PIC16(L)F18857/77
23.4.5 ADDITIONAL SAMPLE AND HOLD 23.5 Computation Operation
CAPACITANCE
The ADC module hardware is equipped with post
Additional capacitance can be added in parallel with the conversion computation features. These features
internal sample and hold capacitor (CHOLD) by means provide data post-processing functions that can be
of the ADCAP register. This register selects a digitally operated on the ADC conversion result, including
programmable capacitance which is added to the ADC digital filtering/averaging and threshold comparison
conversion bus, increasing the effective internal capac- functions.
itance of the sample and hold capacitor in the ADC
module. This is used to improve the match between
internal and external capacitance for a better sensing
performance. The additional capacitance does not
affect analog performance of the ADC because it is not
connected during conversion. See Figure 23-10.
FIGURE 23-10: COMPUTATIONAL FEATURES SIMPLIFIED BLOCK DIAGRAM

Rev. 10-000260A
7/28/2015
ADCALC<2:0>
ADTMOD<2:0>
ADRES
ADFILT
Set
Error Threshold
Interrupt
Average/ Calculation ADERR Logic
1 Flag
Filter ADPREV
0
ADSTPT
ADUTHR ADLTHR
ADPSIS
The operation of the ADC computational features is • Low-Pass Filter (LPF): With each trigger, the ADC
controlled by the ADMD <2:0> bits in the ADCON2 conversion result is sent through a filter. When ADRPT
register. samples have occurred, a threshold test is performed.
The module can be operated in one of five modes: Every trigger after that the ADC conversion result is
sent through the filter and another threshold test is
• Basic: This is a legacy mode. In this mode, ADC performed.
conversion occurs on single (ADDSEN=0) or double
(ADDSEN=1) samples. ADIF is set after each The five modes are summarized in Table 23-3 below.
conversion completes.
• Accumulate: With each trigger, the ADC conversion
result is added to accumulator and ADCNT increments.
ADIF is set after each conversion. ADTIF is set accord-
ing to the Calculation mode.
• Average: With each trigger, the ADC conversion
result is added to the accumulator. When the ADRPT
number of samples have been accumulated, a
threshold test is performed. Upon the next trigger, the
counter is reset to ‘1’ and the accumulator is replaced
with the first ADC conversion cleared. For the
subsequent threshold tests, additional ADRPT
samples are required to be accumulated.
• Burst Average: At the trigger, the accumulator and
counter are cleared. The ADC conversion results are
then collected repetitively until ADRPT samples are
accumulated and finally the threshold is tested.

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TABLE 23-3: COMPUTATION MODES
Clear Conditions Value after Trigger completion Threshold Operations Value at ADTIF interrupt
Mode ADMD ADACC and ADCNT ADACC ADCNT Retrigger Threshold Interrupt ADAOV ADFLTR ADCNT
Test
Basic 0 ADACLR = 1 Unchanged Unchanged No Every If thresh- N/A N/A count
Sample old=true
Accumulate 1 ADACLR = 1 S + ADACC If (ADCNT=FF): ADCNT, No Every If thresh- ADACC Overflow ADACC/2ADCRS count
or otherwise: ADCNT+1 Sample old=true
(S2-S1) + ADACC
Average 2 ADACLR = 1 or S + ADACC If (ADCNT>=ADRPT):1, No If If thresh- ADACC Overflow ADACC/2ADCRS count
ADCNT>=ADRPT at ADGO or otherwise: ADCNT+1 ADCNT>= old=true
or retrigger (S2-S1) + ADACC ADRPT
Burst 3 ADACLR = 1 or ADGO set or Each repetition: same as Reset and count up until Repeat while If If thresh- ADACC Overflow ADACC/2ADCRS ADRPT
Average retrigger Average ADCNT=ADRPT ADCNT<ADRPT ADCNT>= old=true
End with sum of all ADRPT
samples
Lowpass 4 ADACLR = 1 S+ADACC-ADACC/ If (ADCNT=FF): ADCNT, No If If thresh- ADACC Overflow Filtered Value count
Filter 2ADCRS otherwise: ADCNT+1 ADCNT>= old=true
or ADRPT
(S2-S1)+ADACC-ADACC/
2 ADCRS
Note 1: S, S1, and S2 are abbreviations for ADRES, ADRES(n), and ADRES(n+1), respectively. When ADDSEN = 0: S = ADRES. When ADDSEN = 1:
S1 = ADPREV, and S2 = ADRES.
2: All results of divisions using the ADCRS bits are truncated, not rounded.
DS40001825F-page 344
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23.5.1 DIGITAL FILTER/AVERAGE The ADAOV (accumulator overflow) bit in the ADSTAT
register, ADACC, and ADCNT registers will be cleared
The digital filter/average module consists of an accu-
any time the ADACLR bit in the ADCON2 register is
mulator with data feedback options, and control logic to
set.
determine when threshold tests need to be applied.
The accumulator is a 16-bit wide signed register
(15 bits + 1 sign bit), which can be accessed through
Note: When ADC is operating from FRC, 5 FRC
the ADACCH:ADACCL register pair.
clock cycles are required to execute the
Upon each trigger event (the ADGO bit set or external ADACC clearing operation.
event trigger), the ADC conversion result is added to
the accumulator. If the value exceeds The ADCRS <2:0> bits in the ADCON2 register control
‘1111111111111111’, then the overflow bit ADAOV in the data shift on the accumulator result, which
the ADSTAT register is set. effectively divides the value in the accumulator
(ADACCH:ADACCL) register pair. For the Accumulate
The number of samples to be accumulated is mode of the digital filter, the shift provides a simple
determined by the ADRPT (A/D Repeat Setting) scaling operation. For the Average/Burst Average
register. Each time a sample is added to the mode, the shift bits are used to determine number of
accumulator, the ADCNT register is incremented. In samples for averaging. For the Lowpass Filter mode,
Average and Burst Average modes the ADCNT and the shift is an integral part of the filter, and determines
ADACC registers are cleared automatically when a the cut-off frequency of the filter. Table 23-4 shows the
trigger causes the ADCNT value to exceed the ADRPT -3 dB cut-off frequency in ωT (radians) and the highest
value to ‘1’ and replace the ADACC contents with the signal attenuation obtained by this filter at nyquist
conversion result. frequency (ωT = π).
TABLE 23-4: LOWPASS FILTER -3 dB CUT-OFF FREQUENCY

ADCRS ωT (radians) @ -3 dB Frequency dB @ Fnyquist=1/(2T)
1 0.72 -9.5
2 0.284 -16.9
3 0.134 -23.5
4 0.065 -29.8
5 0.032 -36.0
23.5.2 BASIC MODE 23.5.4 AVERAGE MODE

Basic mode (ADMD = 000) disables all additional In Average Mode (ADMD = 010), the ADACC registers
computation features. In this mode, no accumulation accumulate with each ADC sample, much as in
occurs. Double sampling, Continuous mode, all CVD Accumulate mode, and the ADCNT register increments
features, and threshold error detection are still with each sample. However, in Average mode, the
available, but no features involving the digital threshold comparison is performed upon ADCNT being
filter/average features are used. greater than or equal to a user-defined ADRPT value.
The ADCRS bits still right-shift the final result, but in
23.5.3 ACCUMULATE MODE: this mode when ADCRS= log(ADRPT)/log(2) then the
In Accumulate mode (ADMD = 001), the ADC final accumulated value will be divided by number of
conversion result is added to the ADACC registers. The samples, allowing for a threshold comparison operation
Formatting mode does not affect the right-justification on the average of all gathered samples.
of the ADACC value. Upon each sample, ADCNT is
incremented, indicating the number of samples
accumulated. After each sample and accumulation, the
ADFLTR register is updated with the value of ADACC
right shifted by the ADCRS value, a threshold
comparison is performed (see Section 23.5.7
“Threshold Comparison”) and the ADTIF interrupt
may trigger.

PIC16(L)F18857/77
23.5.5 BURST AVERAGE MODE 23.5.7 THRESHOLD COMPARISON
The Burst Average mode (ADMD = ‘011’) acts the At the end of each computation:
same as the Average mode in most respects. The one • The conversion results are latched and held
way it differs is that it continuously retriggers ADC stable at the end-of-conversion.
sampling until the ADCNT value is greater than or • The difference value is calculated based on a
equal to ADRPT, even if Continuous Sampling mode difference calculation which is selected by the
(see Section 23.5.8 “Continuous Sampling Mode”) ADCALC<2:0> bits in the ADCON3 register. The
is not enabled. This allows for a threshold comparison value can be one of the following calculations
on the average of a short burst of ADC samples. (see Register 23-4 for more details):
- The first derivative of single measurements
23.5.6 LOWPASS FILTER MODE
- The CVD result in CVD mode
The Lowpass Filter mode (ADMD = ‘100’) acts similarly - The current result vs. a setpoint
to the Average mode in how it handles samples - The current result vs. the filtered/average
(accumulates samples until ADCNT value greater than result
or equal to ADRPT, then triggers threshold - The first derivative of the filtered/average
comparison), but instead of a simple average, it value
performs a lowpass filter operation on all of the - Filtered/average value vs. a setpoint
samples, reducing the effect of high-frequency noise • The result of the calculation (ADERR) is
on the average, then performs a threshold comparison compared to the upper and lower thresholds,
on the results. (see Table 23-3 for a more detailed ADUTH<ADUTHH:ADUTHL> and
description of the mathematical operation). In this ADLTH<ADLTHH:ADLTHL> registers, to set the
mode, the ADCRS bits determine the cut-off frequency ADUTHR and ADLTHR flag bits. The threshold
of the lowpass filter (as demonstrated by Table 23-4). logic is selected by ADTMD<2:0> bits in the
ADCON3 register. The threshold trigger option
can be one of the following
- Never interrupt
- Error is less than lower threshold
- Error is greater than or equal to lower
threshold
- Error is between thresholds (inclusive)
- Error is outside of thresholds
- Error is less than or equal to upper threshold
- Error is greater than upper threshold
- Always interrupt regardless of threshold test
results
• The threshold interrupt flag ADTIF is set when the
threshold condition is met.
Note 1: The threshold tests are signed

operations.
2: If ADAOV is set, a threshold interrupt is
signaled.

PIC16(L)F18857/77
23.5.8 CONTINUOUS SAMPLING MODE
Setting the ADCONT bit in the ADCON0 register
automatically retriggers a new conversion cycle after
updating the ADACC register. That means the ADGO
bit is set to generate automatic retriggering, until the
device Reset occurs or the A/D Stop-on-interrupt bit
(ADSOI in the ADCON3 register) is set (correct logic).
23.5.9 DOUBLE SAMPLE CONVERSION

Double sampling is enabled by setting the ADDSEN bit
of the ADCON1 register. When this bit is set, two
conversions are required before the module will
calculate threshold error (each conversion must still be
triggered separately). The first conversion will set the
ADMATH bit of the ADSTAT register and update
ADACC, but will not calculate ADERR or trigger ADTIF.
When the second conversion completes, the first value
is transferred to ADPREV (depending on the setting of
ADPSIS) and the value of the second conversion is
placed into ADRES. Only upon the completion of the
second conversion is ADERR calculated and ADTIF
triggered (depending on the value of ADCALC).

PIC16(L)F18857/77
23.6 Register Definitions: ADC Control
REGISTER 23-1: ADCON0: ADC CONTROL REGISTER 0

R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 R/W-0/0 U-0 R/W/HC-0
ADON ADCONT — ADCS — ADFRM0 — ADGO
bit 7 bit 0
Legend:
bit 7 ADON: ADC Enable bit

1 = ADC is enabled
0 = ADC is disabled
bit 6 ADCONT: ADC Continuous Operation Enable bit
1 = ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI is
set) or until ADGO is cleared (regardless of the value of ADSOI)
0 = ADGO is cleared upon completion of each conversion trigger
bit 4 ADCS: ADC Clock Selection bit
1 = Clock supplied from FRC dedicated oscillator
0 = Clock supplied by FOSC, divided according to ADCLK register
bit 2 ADFRM0: ADC results Format/alignment Selection
1 = ADRES and ADPREV data are right-justified
0 = ADRES and ADPREV data are left-justified, zero-filled
bit 0 ADGO: ADC Conversion Status bit
1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is
cleared by hardware as determined by the ADCONT bit
0 = ADC conversion completed/not in progress

PIC16(L)F18857/77
R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0
ADPPOL ADIPEN ADGPOL — — — — ADDSEN
bit 7 bit 0
Legend:
bit 7 ADDPOL: Precharge Polarity bit

If ADPRE>0x00:
Action During 1st Precharge Stage

ADPPOL
External (selected analog I/O pin) Internal (AD sampling capacitor)
1 Shorted to AVDD CHOLD shorted to VSS
0 Shorted to VSS CHOLD shorted to AVDD
Otherwise
The bit is ignored
bit 6 ADIPEN: A/D Inverted Precharge Enable bit
If ADDSEN = 1:
1 = The precharge and guard signals in the second conversion cycle are the opposite polarity of the
first cycle
0 = Both Conversion cycles use the precharge and guards specified by ADPPOL and ADGPOL
Otherwise:
The bit is ignored
bit 5 ADGPOL: Guard Ring Polarity Selection bit
1 = ADC guard ring outputs start as digital high during precharge stage
0 = ADC guard ring outputs start as digital low during precharge stage
bit 0 ADDSEN: Double-Sample Enable bit
1 = See Table 23-5.
0 = One conversion is performed for each trigger
TABLE 23-5: EXAMPLE OF REGISTER VALUES FOR ACCUMULATE AND AVERAGE MODES
Trigger ADPREV
ADCONT Sample ADPSIS
ADRES ADACC
n
0 1 0 1
T1 T1 1 S(n) S(n-1) ADFLTR(n-1) ADACC(n-1)-S(n-1)

T2 — 2 S(n) S(n-1) ADFLTR(n-2) ADACC(n-1)+S(n-1)

PIC16(L)F18857/77

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0 R/W-0/0 R/W-0/0 R/W-0/0
ADPSIS ADCRS<2:0> ADACLR ADMD<2:0>
bit 7 bit 0
Legend:
bit 7 ADPSIS: ADC Previous Sample Input Select bits

1 = ADFLTR is transferred to ADPREV at start-of-conversion
0 = ADRES is transferred to ADPREV at start-of-conversion
bit 6-4 ADCRS<2:0>: ADC Accumulated Calculation Right Shift Select bits
111 = Reserved
110 = Reserved
101 through 000:
If ADMD = 100:
Low-pass filter time constant is 2ADCRS, filter gain is 1:1
If ADMD = 001, 010 or 011:
The accumulated value is right-shifted by ADCRS (divided by 2ADCRS)(2)
Otherwise:
Bits are ignored
bit 3 ADACLR: ADC Accumulator Clear Command bit
1 = Initial clear of ADACC, ADAOV, and the sample counter. Bit is cleared by hardware.
0 = Clearing action is complete (or not started)
bit 2-0 ADMD<2:0>: ADC Operating Mode Selection bits(1)
111 = Reserved
•
•
•
101 = Reserved
100 = Low-pass Filter mode
011 = Burst Average mode
010 = Average mode
001 = Accumulate mode
000 = Basic (Legacy) mode
Note 1: See Table 23-3 for Full mode descriptions.

2: All results of divisions using the ADCRS bits are truncated, not rounded.

PIC16(L)F18857/77
REGISTER 23-4: ADCON3: ADC THRESHOLD REGISTER

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0 R/W-0/0 R/W-0/0 R/W-0/0
— ADCALC<2:0> ADSOI ADTMD<2:0>
bit 7 bit 0
Legend:

bit 6-4 ADCAL<2:0>: ADC Error Calculation Mode Select bits
Action During 1st Precharge Stage

ADCALC ADDSEN = 0 ADDSEN = 1 CVD Application
Single-Sample Mode Double-Sample Mode(1)
111 Reserved Reserved Reserved
101 ADFLTR-ADSTPT ADFLTR-ADSTPT Average/filtered value vs.
setpoint
100 ADPREV-ADFLTR ADPREV-ADFLTR First derivative of filtered
value(3) (negative)
010 ADRES-ADFLTR (ADRES-ADPREV)-ADFLTR Actual result vs.
averaged/filtered value
001 ADRES-ADSTPT (ADRES-ADPREV)-ADSTPT Actual result vs.setpoint
000 ADRES-ADPREV ADRES-ADPREV First derivative of single
measurement(2)
Actual CVD result in CVD
mode(2)
bit 3 ADSOI: ADC Stop-on-Interrupt bit

If ADCONT = 1:
1 = ADGO is cleared when the threshold conditions are met, otherwise the conversion is retriggered
0 = ADGO is not cleared by hardware, must be cleared by software to stop retriggers
If ADCONT = 0 bit is ignored.
bit 2-0 ADTMD<2:0>: Threshold Interrupt Mode Select bits
111 = Always set ADTIF at end of calculation
110 = Set ADTIF if ADERR>ADUTH
101 = Set ADTIF if ADERRADUTH
100 = Set ADTIF if ADERRADLTH or ADERR>ADUTH
011 = Set ADTIF if ADERR>ADLTH and ADERR<ADUTH
010 = Set ADTIF if ADERR≥ADLTH
001 = Set ADTIF if ADERR<ADLTH
000 = ADTIF is disabled
Note 1: When ADPSIS = 0, the value of (ADRES-ADPREV) is the value of (S2-S1) from Table 23-3.
2: When ADPSIS = 0
3: When ADPSIS = 1.

PIC16(L)F18857/77
REGISTER 23-5: ADSTAT: ADC THRESHOLD REGISTER

R-0/0 R-0/0 R-0/0 R/C/HS-0/0 U-0 R-0/0 R-0/0 R-0/0
ADAOV ADUTHR ADLTHR ADMATH — ADSTAT<2:0>
bit 7 bit 0
Legend:
bit 7 ADAOV: ADC Computation Overflow bit

1 = ADC accumulator or ADERR calculation have overflowed
0 = ADC accumulator and ADERR calculation have not overflowed
bit 6 ADUTHR: ADC Module Greater-than Upper Threshold Flag bit
1 = ADERR >ADUTH
0 = ADERRADUTH
bit 5 ADLTHR: ADC Module Less-than Lower Threshold Flag bit
1 = ADERR<ADLTH
0 = ADERR≥ADLTH
bit 4 ADMATH: ADC Module Computation Status bit
1 = Registers ADACC, ADFLTR, ADUTH, ADLTH and the ADAOV bit are updating or have already
updated
0 = Associated registers/bits have not changed since this bit was last cleared
bit 2-0 ADSTAT<0:2>: ADC Module Cycle Multistage Status bits(1)
111 = ADC module is in 2nd conversion stage
110 = ADC module is in 2nd acquisition stage
101 = ADC module is in 2nd precharge stage
100 = Not used
011 = ADC module is in 1st conversion stage
010 = ADC module is in 1st acquisition stage
001 = ADC module is in 1st precharge stage
000 = ADC module is not converting
Note 1: If ADOSC=1, and FOSC<FRC, these bits may be invalid.

PIC16(L)F18857/77
REGISTER 23-6: ADCLK: ADC CLOCK SELECTION REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — ADCCS<5:0>
bit 7 bit 0
Legend:

bit 5-0 ADCCS<5:0>: ADC Conversion Clock Select bits
111111 = FOSC/128
111110 = FOSC/126
111101 = FOSC/124
•
•
•
000000 = FOSC/2
REGISTER 23-7: ADREF: ADC REFERENCE SELECTION REGISTER

U-0 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
— — — ADNREF — — ADPREF<1:0>
bit 7 bit 0
Legend:

bit 4 ADNREF: ADC Negative Voltage Reference Selection bit
1 = VREF- is connected to VREF- pin
0 = VREF- is connected to AVSS
bit 1-0 ADPREF: ADC Positive Voltage Reference Selection bits
11 = VREF+ is connected to FVR_buffer 1
10 = VREF+ is connected to VREF+ pin
01 = Reserved
00 = VREF+ is connected to VDD

PIC16(L)F18857/77
REGISTER 23-8: ADPCH: ADC POSITIVE CHANNEL SELECTION REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — ADPCH<5:0>
bit 7 bit 0
Legend:

bit 5-0 ADPCH<5:0>: ADC Positive Input Channel Selection bits
111111 = Fixed Voltage Reference (FVR)(2)
111110 = DAC1 output(1)
111101 = Temperature Indicator(3)
111100 = AVSS (Analog Ground)
111011 = Reserved. No channel connected.
•
•
•
100010 = ANE2(4)
100001 = ANE1(4)
100000 = ANE0(4)
011111 = AND7(4)
011110 = AND6(4)
011101 = AND5(4)
011100 = AND4(4)
011011 = AND3(4)
011010 = AND2(4)
011001 = AND1(4)
011000 = AND0(4)
010111 = ANC7
010110 = ANC6
010101 = ANC5
010100 = ANC4
010011 = ANC3
010010 = ANC2
010001 = ANC1
010000 = ANC0
001111 = ANB7
001110 = ANB6
001101 = ANB5
001100 = ANB4
001011 = ANB3
001010 = ANB2
001001 = ANB1
001000 = ANB0
000111 = ANA7
000110 = ANA6
000101 = ANA5
000100 = ANA4
000011 = ANA3
000010 = ANA2
000001 = ANA1
000000 = ANA0
Note 1: See Section 25.0 “5-Bit Digital-to-Analog Converter (DAC1) Module” for more information.
2: See Section 16.0 “Fixed Voltage Reference (FVR)” for more information.
3: See Section 17.0 “Temperature Indicator Module” for more information.
4: PIC16(L)F18877 only.

PIC16(L)F18857/77
REGISTER 23-9: ADPRE: ADC PRECHARGE TIME CONTROL REGISTER

ADPRE<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADPRE<7:0>: Precharge Time Select bits(1)

11111111 = Precharge time is 255 clocks of the selected ADC clock
11111110 = Precharge time is 254 clocks of the selected ADC clock
•
•
•
00000001 = Precharge time is 1 clock of the selected ADC clock
00000000 = Precharge time is not included in the data conversion cycle
Note 1: When FOSC is selected as the ADC clock (ADCS bit of ADCON0 = 0), both ADPRE and ADACQ are
calculated using undivided FOSC, regardless of the value of the ADCLK register.
REGISTER 23-10: ADACQ: ADC ACQUISITION TIME CONTROL REGISTER

ADACQ<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADACQ<7:0>: Acquisition (charge share time) Select bits(1)

11111111= Acquisition time is 255 clocks of the selected ADC clock
11111110= Acquisition time is 254 clocks of the selected ADC clock
•
•
•
00000001= Acquisition time is 1 clock of the selected ADC clock
00000000= Acquisition time is not included in the data conversion cycle(2)
Note 1: When FOSC is selected as the ADC clock (ADCS bit of ADCON0 = 0), both ADPRE and ADACQ are
calculated using undivided FOSC, regardless of the value of the ADCLK register.
2: If ADPRE! = 0, ADAQC = 0 will instead set an Acquisition time of 256 clocks of the selected ADC clock.

PIC16(L)F18857/77
REGISTER 23-11: ADCAP: ADC ADDITIONAL SAMPLE CAPACITOR SELECTION REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — ADCAP<4:0>
bit 7 bit 0
Legend:

bit 4-0 ADCAP<4:0>: ADC Additional Sample Capacitor Selection bits
11111 = 31 pF
11110 = 30 pF
11101 = 29 pF
•
•
•
00011 = 3 pF
00010 = 2 pF
00001 = 1 pF
00000 = No additional capacitance
REGISTER 23-12: ADRPT: ADC REPEAT SETTING REGISTER

ADRPT<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADRPT<7:0>: ADC Repeat Threshold bits

Counts the number of times that the ADC has been triggered. Used in conjunction along with ADCNT
to determine when the error threshold is checked for Low-pass Filter, Burst Average, and Average
modes.

PIC16(L)F18857/77
REGISTER 23-13: ADCNT: ADC CONVERSION COUNTER REGISTER

ADCNT<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADCNT<7:0>: ADC Conversion Counter

Counts the number of times that the ADC is triggered. Determines when the threshold is checked for
the Low-Pass Filter, Burst Average, and Average Computation modes. Count saturates at 0xFF and
does not roll-over to 0x00.
REGISTER 23-14: ADFLTRH: ADC FILTER HIGH BYTE REGISTER

R-x R-x R-x R-x R-x R-x R-x R-x
ADFLTR<15:8>
bit 7 bit 0
Legend:
bit 7-0 ADFLTR<15:8>: ADC Filter Output Most Significant bits and Sign bit
In Accumulate, Average, and Burst Average mode, this is equal to ADACC right shifted by the ADCRS
bits of ADCON2. In LPF mode, this is the output of the Lowpass Filter.
REGISTER 23-15: ADFLTRL: ADC FILTER LOW BYTE REGISTER

ADFLTR<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADFLTR<7:0>: ADC Filter Output Least Significant bits

In Accumulate, Average, and Burst Average mode, this is equal to ADACC right shifted by the ADCRS
bits of ADCON2. In LPF mode, this is the output of the Lowpass Filter.

PIC16(L)F18857/77
REGISTER 23-16: ADRESH: ADC RESULT REGISTER HIGH, ADFRM=0

ADRES<9:2>
bit 7 bit 0
Legend:
bit 7-0 ADRES<9:2>: ADC Result Register bits

Most Significant eight bits of 10-bit conversion result.
REGISTER 23-17: ADRESL: ADC RESULT REGISTER LOW, ADFRM=0

ADRES<1:0> — — — — — —
bit 7 bit 0
Legend:
bit 7-6 ADRES<1:0>: ADC Result Register bits. Least Significant two bits of 10-bit conversion result.
bit 5-0 Reserved: Do not use.
REGISTER 23-18: ADRESH: ADC RESULT REGISTER HIGH, ADFRM=1

— — — — — — ADRES<9:8>
bit 7 bit 0
Legend:
bit 7-2 Reserved: Do not use.

bit 1-0 ADRES<9:8>: ADC Sample Result bits. Most Significant two bits of 10-bit conversion result.

PIC16(L)F18857/77
REGISTER 23-19: ADRESL: ADC RESULT REGISTER LOW, ADFRM=1

ADRES<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADRES<7:0>: ADC Result Register bits. Least Significant eight bits of 10-bit conversion result.
REGISTER 23-20: ADPREVH: ADC PREVIOUS RESULT REGISTER

ADPREV<15:8>
bit 7 bit 0
Legend:
bit 7-0 ADPREV<15:8>: Previous ADC Results Most Significant Byte

If ADPSIS = 1:
Most Significant Byte of ADFLTR at the start of current ADC conversion
If ADPSIS = 0:
Most Significant bits of ADRES at the start of current ADC conversion(1)
Note 1: If ADPSIS = 0, ADPREVH and ADPREVL are formatted the same way as ADRES is, depending on the
ADFRM bit.

PIC16(L)F18857/77
REGISTER 23-21: ADPREVL: ADC PREVIOUS RESULT REGISTER

ADPREV<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADPREV<7:0>: Previous ADC Results Least Significant Byte

If ADPSIS = 1:
Least Significant Byte of ADFLTR at the start of current ADC conversion
If ADPSIS = 0:
Least Significant bits of ADRES at the start of current ADC conversion(1)
Note 1: If ADPSIS = 0, ADPREVH and ADPREVL are formatted the same way as ADRES is, depending on the
ADFRM bit.
REGISTER 23-22: ADACCH: ADC ACCUMULATOR REGISTER HIGH

ADACC<15:8>
bit 7 bit 0
Legend:
bit 7-0 ADACC<15:8>: ADC Accumulator MSB. Most Significant seven bits of accumulator value and sign bit.
REGISTER 23-23: ADACCL: ADC ACCUMULATOR REGISTER LOW

ADACC<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADACC<7:0>: ADC Accumulator LSB. Least Significant eight bits of accumulator value.

PIC16(L)F18857/77
REGISTER 23-24: ADSTPTH: ADC THRESHOLD SETPOINT REGISTER HIGH

ADSTPT<15:8>
bit 7 bit 0
Legend:
bit 7-0 ADSTPT<15:8>: ADC Threshold Setpoint MSB. Most Significant Byte of ADC threshold setpoint,
depending on ADCALC, may be used to determine ADERR, see Register 21-1 for more details.
\
REGISTER 23-25: ADSTPTL: ADC THRESHOLD SETPOINT REGISTER LOW
R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x
ADSTPT<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADSTPT<7:0>: ADC Threshold Setpoint LSB. Least Significant Byte of ADC threshold setpoint,
depending on ADCALC, may be used to determine ADERR, see Register 21-1 for more details.
REGISTER 23-26: ADERRH: ADC CALCULATION ERROR REGISTER HIGH

ADERR<15:8>
bit 7 bit 0
Legend:
bit 7-0 ADERR<15:8>: ADC Calculation Error MSB. Most Significant Byte of ADC Calculation Error.
Calculation is determined by ADCALC bits of ADCON3, see Register 21-1 for more details.

PIC16(L)F18857/77
REGISTER 23-27: ADERRL: ADC CALCULATION ERROR LOW BYTE REGISTER

ADERR<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADERR<7:0>: ADC Calculation Error LSB. Least Significant Byte of ADC Calculation Error. Calcula-
tion is determined by ADCALC bits of ADCON3, see Register 21-1 for more details.
REGISTER 23-28: ADLTHH: ADC LOWER THRESHOLD HIGH BYTE REGISTER

ADLTH<15:8>
bit 7 bit 0
Legend:
bit 7-0 ADLTH<15:8>: ADC Lower Threshold MSB. ADLTH and ADUTH are compared with ADERR to set
the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be
triggered by the results of this comparison.
REGISTER 23-29: ADLTHL: ADC LOWER THRESHOLD LOW BYTE REGISTER

ADLTH<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADLTH<7:0>: ADC Lower Threshold LSB. ADLTH and ADUTH are compared with ADERR to set the
ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be

PIC16(L)F18857/77
REGISTER 23-30: ADUTHH: ADC UPPER THRESHOLD HIGH BYTE REGISTER

ADUTH<15:8>
bit 7 bit 0
Legend:
bit 7-0 ADUTH<15:8>: ADC Upper Threshold MSB. ADLTH and ADUTH are compared with ADERR to set
the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be
REGISTER 23-31: ADUTHL: ADC UPPER THRESHOLD LOW BYTE REGISTER

ADUTH<7:0>
bit 7 bit 0
Legend:
bit 7-0 ADUTH<7:0>: ADC Upper Threshold LSB. ADLTH and ADUTH are compared with ADERR to set the
ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be

PIC16(L)F18857/77
REGISTER 23-32: ADACT: ADC AUTO CONVERSION TRIGGER CONTROL REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — ADACT<4:0>
bit 7 bit 0
Legend:

bit 4-0 ADACT<4:0>: Auto-Conversion Trigger Select Bits
See Table 23-2.

PIC16(L)F18857/77
TABLE 23-6: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
on Page
ADCON0 ADON ADCONT — ADCS — ADFRM0 — ADGO 348

ADCON1 ADPPOL ADIPEN ADGPOL — — — — ADDSEN 349
ADCON2 ADPSIS ADCRS<2:0> ADACLR ADMD<2:0> 350
ADCON3 — ADCALC<2:0> ADSOI ADTMD<2:0> 351
ADACT — — — ADACT<4:0> 350
ADACCH ADACCH 360
ADACCL ADACCL 360
ADPREVH ADPREVH 359
ADPREVL ADPREVL 360
ADRESH ADRESH 358
ADRESL ADRESL 358
ADSTAT ADAOV ADUTHR ADLTHR ADMATH — ADSTAT<2:0> 352
ADCLK — — ADCCS<5:0> 353
ADREF — — — ADNREF — — ADPREF<1:0> 353
ADCAP — — — ADCAP<4:0> 356
ADPRE ADPRE<7:0> 355
ADACQ ADACQ<7:0> 355
ADPCH — — ADPCH<5:0> 354
ADCNT ADCNT<7:0> 357
ADRPT ADRPT<7:0> 356
ADLTHL ADLTH<7:0> 362
ADLTHH ADLTH<15:8> 362
ADUTHL ADUTH<7:0> 363
ADUTHH ADUTH<15:8> 363
ADSTPTL ADSTPT<7:0> 361
ADSTPTH ADSTPT<15:8> 361
ADFLTRL ADFLTR<7:0> 357
ADFLTRH ADFLTR<15:8> 357
ADERRL ADERR<7:0> 362
ADERRH ADERR<15:8> 361
ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 221
ANSELE — — — — ANSE3 ANSE2(1) ANSE1(1) ANSE0(1) 230
DAC1CON1 — — — DAC1R<4:0> 379
OSCSTAT EXTOR HFOR MFOR LFOR SOR ADOR — PLLR 123
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for the ADC module.
Note 1: PIC16(L)F18877 only.

PIC16(L)F18857/77
24.0 NUMERICALLY CONTROLLED
OSCILLATOR (NCO) MODULE
The Numerically Controlled Oscillator (NCO) module is
a timer that uses overflow from the addition of an
increment value to divide the input frequency. The
advantage of the addition method over simple counter
driven timer is that the output frequency resolution
does not vary with the divider value. The NCO is most
useful for application that requires frequency accuracy
and fine resolution at a fixed duty cycle.
Features of the NCO include:
• 20-bit Increment Function
• Fixed Duty Cycle mode (FDC) mode
• Pulse Frequency (PF) mode
• Output Pulse Width Control
• Multiple Clock Input Sources
• Output Polarity Control
• Interrupt Capability
Figure 24-1 is a simplified block diagram of the NCO
module.

FIGURE 24-1: DIRECT DIGITAL SYNTHESIS MODULE SIMPLIFIED BLOCK DIAGRAM
PIC16(L)F18857/77
NCOxINCU NCOxINCH NCOxINCL Rev. 10-000028C
2/2/2015
20
(1)
INCBUFU INCBUFH INCBUFL
20
20
reserved 111
reserved 110
NCO_overflow Adder
CLC4_out 101
20
CLC3_out 100 NCOx_clk
NCOxACCU NCOxACCH NCOxACCL
CLC2_out 011 20
CLC1_out 010
HFINTOSC 001 NCO_interrupt set bit
NCOxIF
FOSC 000 Fixed Duty
Cycle Mode
Circuitry
NxCKS<2:0> D Q D Q 0 TRIS bit
3
NCOxOUT
_ 1
Q
NxPFM NxPOL
NCOx_out
To Peripherals
EN S Q
_ D Q NxOUT
Ripple
R Q
Counter
Pulse Q1
DS40001825F-page 367
R Frequency
3 Mode Circuitry
NxPWS<2:0>
Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO module. The full increment value is loaded into the buffer registers on the
second rising edge of the NCOx_clk signal that occurs immediately after a write to NCOxINCL register. The buffers are not user-accessible and are shown here for reference.
PIC16(L)F18857/77
24.1 NCO OPERATION
The NCO operates by repeatedly adding a fixed value to
an accumulator. Additions occur at the input clock rate.
The accumulator will overflow with a carry periodically,
which is the raw NCO output (NCO_overflow). This
effectively reduces the input clock by the ratio of the
addition value to the maximum accumulator value. See
Equation 24-1.
The NCO output can be further modified by stretching
the pulse or toggling a flip-flop. The modified NCO
output is then distributed internally to other peripherals
and can be optionally output to a pin. The accumulator
overflow also generates an interrupt (NCO_overflow).
The NCO period changes in discrete steps to create an
average frequency. This output depends on the ability
of the receiving circuit (i.e., CWG or external resonant
converter circuitry) to average the NCO output to
reduce uncertainty.
EQUATION 24-1: NCO OVERFLOW FREQUENCY
Clock Frequency  Increment Value-

F OVERFLOW = NCO
---------------------------------------------------------------------------------------------------------------
20
2
24.1.1 NCO CLOCK SOURCES 24.1.4 INCREMENT REGISTERS

Clock sources available to the NCO include: The increment value is stored in three registers making
• HFINTOSC up a 20-bit incrementer. In order of LSB to MSB they
• FOSC are:
• LC1_out • NCO1INCL
• LC2_out • NCO1INCH
• LC3_out • NCO1INCU
• LC4_out
When the NCO module is enabled, the NCO1INCU and
The NCO clock source is selected by configuring the NCO1INCH registers should be written first, then the
N1CKS<2:0> bits in the NCO1CLK register. NCO1INCL register. Writing to the NCO1INCL register
initiates the increment buffer registers to be loaded
24.1.2 ACCUMULATOR
simultaneously on the second rising edge of the
The accumulator is a 20-bit register. Read and write NCO_clk signal.
access to the accumulator is available through three
The registers are readable and writable. The increment
registers:
registers are double-buffered to allow value changes to
• NCO1ACCL be made without first disabling the NCO module.
• NCO1ACCH When the NCO module is disabled, the increment
• NCO1ACCU buffers are loaded immediately after a write to the
increment registers.
24.1.3 ADDER
The NCO Adder is a full adder, which operates
independently from the source clock. The addition of Note: The increment buffer registers are not user-
the previous result and the increment value replaces accessible.
the accumulator value on the rising edge of each input
clock.

PIC16(L)F18857/77
24.2 FIXED DUTY CYCLE MODE 24.5 Interrupts
In Fixed Duty Cycle (FDC) mode, every time the When the accumulator overflows (NCO_overflow), the
accumulator overflows (NCO_overflow), the output is NCO Interrupt Flag bit, NCO1IF, of the PIR7 register is
toggled. This provides a 50% duty cycle, provided that set. To enable the interrupt event (NCO_interrupt), the
the increment value remains constant. For more following bits must be set:
information, see Figure 24-2. • N1EN bit of the NCO1CON register
The FDC mode is selected by clearing the N1PFM bit • NCO1IE bit of the PIE7 register
in the NCO1CON register. • PEIE bit of the INTCON register
• GIE bit of the INTCON register
24.3 PULSE FREQUENCY MODE The interrupt must be cleared by software by clearing
the NCO1IF bit in the Interrupt Service Routine.
In Pulse Frequency (PF) mode, every time the
Accumulator overflows, the output becomes active for
one or more clock periods. Once the clock period 24.6 Effects of a Reset
expires, the output returns to an inactive state. This All of the NCO registers are cleared to zero as the
provides a pulsed output. The output becomes active result of a Reset.
on the rising clock edge immediately following the
overflow event. For more information, see Figure 24-2.
24.7 Operation in Sleep
The value of the active and inactive states depends on
the polarity bit, N1POL in the NCO1CON register. The NCO module operates independently from the
system clock and will continue to run during Sleep,
The PF mode is selected by setting the N1PFM bit in
provided that the clock source selected remains active.
the NCO1CON register.
The HFINTOSC remains active during Sleep when the
24.3.1 OUTPUT PULSE WIDTH CONTROL NCO module is enabled and the HFINTOSC is
selected as the clock source, regardless of the system
When operating in PF mode, the active state of the out-
clock source selected.
put can vary in width by multiple clock periods. Various
pulse widths are selected with the N1PWS<2:0> bits in In other words, if the HFINTOSC is simultaneously
the NCO1CLK register. selected as the system clock and the NCO clock
source, when the NCO is enabled, the CPU will go idle
When the selected pulse width is greater than the
during Sleep, but the NCO will continue to operate and
Accumulator overflow time frame, then DDS operation
the HFINTOSC will remain active.
is undefined.
This will have a direct effect on the Sleep mode current.
24.4 OUTPUT POLARITY CONTROL
The last stage in the NCO module is the output polarity.
The N1POL bit in the NCO1CON register selects the
output polarity. Changing the polarity while the
interrupts are enabled will cause an interrupt for the
resulting output transition.
The NCO output signal is available to the following
peripherals:
• CLC
• CWG
• Timer2/4/6
• SMT
• DSM
• Reference Clock Output

FIGURE 24-2: FDC OUTPUT MODE OPERATION DIAGRAM
PIC16(L)F18857/77
Rev. 10-000029A
11/7/2013
NCOx
Clock
Source
NCOx
Increment 4000h 4000h 4000h
Value
NCOx
Accumulator 00000h 04000h 08000h FC000h 00000h 04000h 08000h FC000h 00000h 04000h 08000h
Value
NCO_overflow
NCO_interrupt
NCOx Output
FDC Mode
NCOx Output
DS40001825F-page 370
PF Mode
NCOxPWS =
000
NCOx Output
PF Mode
NCOxPWS =
001
PIC16(L)F18857/77
24.8 NCO Control Registers
REGISTER 24-1: NCO1CON: NCO CONTROL REGISTER

R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
N1EN — N1OUT N1POL — — — N1PFM
bit 7 bit 0
Legend:
bit 7 N1EN: NCO1 Enable bit

1 = NCO1 module is enabled
0 = NCO1 module is disabled
bit 5 N1OUT: NCO1 Output bit
Displays the current output value of the NCO1 module.
bit 4 N1POL: NCO1 Polarity
1 = NCO1 output signal is inverted
0 = NCO1 output signal is not inverted
bit 0 N1PFM: NCO1 Pulse Frequency Mode bit
1 = NCO1 operates in Pulse Frequency mode
0 = NCO1 operates in Fixed Duty Cycle mode, divide by 2

PIC16(L)F18857/77
REGISTER 24-2: NCO1CLK: NCO1 INPUT CLOCK CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
N1PWS<2:0>(1,2) — — N1CKS<2:0>
bit 7 bit 0
Legend:
bit 7-5 N1PWS<2:0>: NCO1 Output Pulse Width Select bits(1,2)

111 = NCO1 output is active for 128 input clock periods
000 = NCO1 output is active for 1 input clock period
bit 2-0 N1CKS<2:0>: NCO1 Clock Source Select bits
110 = Reserved
•
•
•
111 = Reserved
101 = LC4_out
100 = LC3_out
011 = LC2_out
010 = LC1_out
001 = HFINTOSC
000 = FOSC
Note 1: N1PWS applies only when operating in Pulse Frequency mode.

2: If NCO1 pulse width is greater than NCO1 overflow period, operation is undefined.

PIC16(L)F18857/77
REGISTER 24-3: NCO1ACCL: NCO1 ACCUMULATOR REGISTER – LOW BYTE
NCO1ACC<7:0>
bit 7 bit 0
Legend:
bit 7-0 NCO1ACC<7:0>: NCO1 Accumulator, Low Byte
REGISTER 24-4: NCO1ACCH: NCO1 ACCUMULATOR REGISTER – HIGH BYTE

NCO1ACC<15:8>
bit 7 bit 0
Legend:
bit 7-0 NOC1ACC<15:8>: NCO1 Accumulator, High Byte
REGISTER 24-5: NCO1ACCU: NCO1 ACCUMULATOR REGISTER – UPPER BYTE(1)

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — NCO1ACC<19:16>
bit 7 bit 0
Legend:

bit 3-0 NCO1ACC<19:16>: NCO1 Accumulator, Upper Byte
Note 1: The accumulator spans registers NCO1ACCU:NCO1ACCH: NCO1ACCL. The 24 bits are reserved but
not all are used.This register updates in real-time, asynchronously to the CPU; there is no provision to
guarantee atomic access to this 24-bit space using an 8-bit bus. Writing to this register while the module is
operating will produce undefined results.

PIC16(L)F18857/77
REGISTER 24-6: NCO1INCL: NCO1 INCREMENT REGISTER – LOW BYTE(1,2)
NCO1INC<7:0>
bit 7 bit 0
Legend:
bit 7-0 NCO1INC<7:0>: NCO1 Increment, Low Byte
Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.

2: DDSINC is double-buffered as INCBUF; INCBUF is updated on the next falling edge of NCOCLK after
writing to NCO1INCL; NCO1INCU and NCO1INCH should be written prior to writing NCO1INCL.
REGISTER 24-7: NCO1INCH: NCO1 INCREMENT REGISTER – HIGH BYTE(1)

NCO1INC<15:8>
bit 7 bit 0
Legend:
bit 7-0 NCO1INC<15:8>: NCO1 Increment, High Byte
REGISTER 24-8: NCO1INCU: NCO1 INCREMENT REGISTER – UPPER BYTE(1)

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — NCO1INC<19:16>
bit 7 bit 0
Legend:

bit 3-0 NCO1INC<19:16>: NCO1 Increment, Upper Byte

PIC16(L)F18857/77
TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH NCO
Register
on Page
PIR2 ― ZCDIF ― ― ― ― C2IF C1IF 145
PIE2 ― ZCDIE ― ― ― ― C2IE C1IE 136

NCO1CON N1EN ― N1OUT N1POL ― ― ― N1PFM 371
NCO1CLK N1PWS<2:0> ― ― N1CKS<2:0> 372
NCO1ACCL NCO1ACC<7:0> 373
NCO1ACCH NCO1ACC<15:8> 373
NCO1ACCU ― ― ― ― NCO1ACC<19:16> 373
NCO1INCL NCO1INC<7:0> 374
NCO1INCH NCO1INC<15:8> 374
NCO1INCU ― ― ― ― NCO1INC<19:16> 374
RxyPPS ― ― ― RxyPPS<4:0> 241
CWG1ISM ― ― ― ― IS<3:0> 303
MDSRC — — — MDMS<4:0> 389
MDCARH — — — — MDCHS<3:0> 390
MDCARL — — — — MDCLS<3:0> 391
CCP1CAP ― ― ― ― ― CTS<2:0> 443
CCP2CAP ― ― ― ― ― CTS<2:0> 443
CCP3CAP ― ― ― ― ― CTS<2:0> 443
CCP4CAP ― ― ― ― ― CTS<2:0> 443
CCP5CAP ― ― ― ― ― CTS<2:0> 443
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for NCO module.

PIC16(L)F18857/77
25.0 5-BIT DIGITAL-TO-ANALOG 25.1 Output Voltage Selection
CONVERTER (DAC1) MODULE The DAC has 32 voltage level ranges. The 32 levels
The Digital-to-Analog Converter supplies a variable are set with the DAC1R<4:0> bits of the DAC1CON1
voltage reference, ratiometric with the input source, register.
with 32 selectable output levels. The DAC output voltage is determined by Equation 25-1:
The input of the DAC can be connected to:
• External VREF pins
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• ADC input channel
• DAC1OUT pin
The Digital-to-Analog Converter (DAC) is enabled by
setting the DAC1EN bit of the DAC1CON0 register.
EQUATION 25-1: DAC OUTPUT VOLTAGE

 DAC1R  4:0 
V = V  – V   ----------------------------------- +  V 
OUT  SOURCE+ SOURCE- 5  SOURCE-
2
V = V or V REF+ or FVR
SOURCE+ DD
V = V or V REF-
SOURCE- SS
25.2 Ratiometric Output Level

The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Table 37-15.
25.3 DAC Voltage Reference Output

The DAC voltage can be output to the DAC1OUT1/2
pins by setting the DAC1OE1/2 bits of the DAC1CON0
register, respectively. Selecting the DAC reference
voltage for output on the DAC1OUT1/2 pins
automatically overrides the digital output buffer and
digital input threshold detector functions and disables
the weak pull-up. Reading the DAC1OUT1/2 pin when
it has been configured for DAC reference voltage
output will always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage reference output for
external connections to the DAC1OUT1/2 pins.
Figure 25-2 shows an example buffering technique.

PIC16(L)F18857/77
FIGURE 25-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Rev. 10-000026G
12/15/2016
Reserved 11
VSOURCE+ DACR<4:0>
FVR Buffer 10 5
VREF+ 01 R
VDD 00
R
DACPSS
32-to-1 MUX
32 DACx_output
To Peripherals
Steps
DACEN
R
R DACxOUT1(1)
DACOE1
R
DACxOUT2(1)
VREF- 1 VSOURCE- DACOE2

VSS 0
DACNSS
Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s).
FIGURE 25-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
R
Module
+
Voltage DAC1OUT Buffered DAC Output
–
Reference
Output
Impedance

PIC16(L)F18857/77
The DAC continues to function during Sleep. When the
device wakes up from Sleep through an interrupt or a
Watchdog Timer time-out, the contents of the
DAC1CON0 register are not affected.

A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DAC1OUT1/2 pins.
• The DAC1R<4:0> range select bits are cleared.

PIC16(L)F18857/77
25.6 Register Definitions: DAC Control
REGISTER 25-1: DAC1CON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS
bit 7 bit 0
Legend:
bit 7 DAC1EN: DAC1 Enable bit

1 = DAC is enabled
0 = DAC is disabled
bit 5 DAC1OE1: DAC1 Voltage Output 1 Enable bit
1 = DAC voltage level is also an output on the DAC1OUT1 pin
0 = DAC voltage level is disconnected from the DAC1OUT1 pin
bit 4 DAC1OE2: DAC1 Voltage Output 1 Enable bit
1 = DAC voltage level is also an output on the DAC1OUT2 pin
0 = DAC voltage level is disconnected from the DAC1OUT2 pin
bit 3-2 DAC1PSS<1:0>: DAC1 Positive Source Select bits
11 = Reserved, do not use
10 = FVR output
01 = VREF+ pin
00 = VDD
bit 0 DAC1NSS: DAC1 Negative Source Select bits
1 = VREF- pin
0 = VSS
REGISTER 25-2: DAC1CON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — DAC1R<4:0>
bit 7 bit 0
Legend:

bit 4-0 DAC1R<4:0>: DAC1 Voltage Output Select bits
VOUT = (VSRC+ - VSRC-)*(DAC1R<4:0>/32) + VSRC

PIC16(L)F18857/77
TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC1 MODULE
Register
on page
DAC1CON1 — — — DAC1R<4:0> 379
CM1PSEL — — — — — PCH<2:0> 272
CM2PSEL — — — — — PCH<2:0> 272
ADPCH — — ADPCH<5:0> 348
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.

PIC16(L)F18857/77
26.0 DATA SIGNAL MODULATOR
(DSM) MODULE
The Data Signal Modulator (DSM) is a peripheral which
allows the user to mix a data stream, also known as a
modulator signal, with a carrier signal to produce a
modulated output.
Both the carrier and the modulator signals are supplied
to the DSM module either internally, from the output of
a peripheral, or externally through an input pin.
The modulated output signal is generated by
performing a logical “AND” operation of both the carrier
and modulator signals and then provided to the MDOUT
pin.
The carrier signal is comprised of two distinct and
separate signals. A carrier high (CARH) signal and a
carrier low (CARL) signal. During the time in which the
modulator (MOD) signal is in a logic high state, the
DSM mixes the carrier high signal with the modulator
signal. When the modulator signal is in a logic low
state, the DSM mixes the carrier low signal with the
modulator signal.
Using this method, the DSM can generate the following
types of Key Modulation schemes:
• Frequency-Shift Keying (FSK)
• Phase-Shift Keying (PSK)
• On-Off Keying (OOK)
Additionally, the following features are provided within
the DSM module:
• Carrier Synchronization
• Carrier Source Polarity Select
• Carrier Source Pin Disable
• Programmable Modulator Data
• Modulator Source Pin Disable
• Modulated Output Polarity Select
• Slew Rate Control
Figure 26-1 shows a Simplified Block Diagram of the
Data Signal Modulator peripheral.

PIC16(L)F18857/77
FIGURE 26-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
MDCHS<3:0> Rev. 10-000248D

7/28/2015
Data Signal Modulator

0000
See
MDCARH CARH
Register
MDCHPOL D
1111 SYNC
Q
MDSRCS<4:0> 1
0
00000
RxyPPS
MDCHSYNC
See
MOD
MDSRC
PPS
Register
MDOPOL
11111
MDCLS<3:0>
D
SYNC
0000 Q
1
0
See
MDCARL CARL
Register MDCLSYNC
MDCLPOL
1111

PIC16(L)F18857/77
26.1 DSM Operation 26.3 Carrier Signal Sources
The DSM module can be enabled by setting the MDEN The carrier high signal and carrier low signal can be
bit in the MDCON register. Clearing the MDEN bit in the supplied from the following sources:
MDCON register, disables the DSM module by auto- • External Signal on MDCARH/LPPS pins
matically switching the carrier high and carrier low sig-
• FOSC (system clock)
nals to the VSS signal source. The modulator signal
source is also switched to the MDBIT in the MDCON • HFINTOSC
register. This not only assures that the DSM module is • Reference Clock Module Signal
inactive, but that it is also consuming the least amount • CCP1 Signal
of current. • CCP2 Signal
The values used to select the carrier high, carrier low, • CCP3 Signal
and modulator sources held by the Modulation Source, • CCP4 Signal
Modulation High Carrier, and Modulation Low Carrier
• CCP5 Signal
control registers are not affected when the MDEN bit is
cleared and the DSM module is disabled. The values • PWM6 Output
inside these registers remain unchanged while the • PWM7 Output
DSM is inactive. The sources for the carrier high, car- • NCO output
rier low and modulator signals will once again be • CLC1 output
selected when the MDEN bit is set and the DSM • CLC2 output
module is again enabled and active.
• CLC3 output
The modulated output signal can be disabled without • CLC4 output
shutting down the DSM module. The DSM module will
remain active and continue to mix signals, but the out- The carrier high signal is selected by configuring the
put value will not be sent to the DSM pin. During the MDCHS <3:0> bits in the MDCARH register. The
time that the output is disabled, the DSM pin will remain carrier low signal is selected by configuring the MDCLS
low. The modulated output can be disabled by clearing <3:0> bits in the MDCARL register.
the MDEN bit in the MDCON register.
26.4 Carrier Synchronization
26.2 Modulator Signal Sources During the time when the DSM switches between car-
The modulator signal can be supplied from the rier high and carrier low signal sources, the carrier data
following sources: in the modulated output signal can become truncated.
To prevent this, the carrier signal can be synchronized
• External Signal on MDSRCPPS pin to the modulator signal. When synchronization is
• MDBIT bit in the MDCON0 register enabled, the carrier pulse that is being mixed at the
• CCP1 Signal time of the transition is allowed to transition low before
• CCP2 Signal the DSM switches over to the next carrier source.
• CCP3 Signal
• CCP4 Signal Synchronization is enabled separately for the carrier
• CCP5 Signal high and carrier low signal sources. Synchronization for
• PWM6 Signal the carrier high signal is enabled by setting the
• PWM7 Signal MDCHSYNC bit in the MDCON1 register.
• NCO output Synchronization for the carrier low signal is enabled by
• Comparator C1 Signal setting the MDCLSYNC bit in the MDCON1 register.
• Comparator C2 Signal Figure 26-1 through Figure 26-6 show timing diagrams
• CLC1 Output of using various synchronization methods.
• CLC2 Output
• CLC3 Output
• CLC4 Output
• EUSART DT Signal
• EUSART TX/CK Signal
• MSSP1 SDO Signal (SPI Mode Only)
• MSSP2 SDO Signal
The modulator signal is selected by configuring the
MDMS <4:0> bits in the MDSRC register.

PIC16(L)F18857/77
FIGURE 26-2: ON OFF KEYING (OOK) SYNCHRONIZATION
Carrier Low (CARL)
Carrier High (CARH)
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
MDCHSYNC = 1
MDCLSYNC = 1
MDCHSYNC = 0
MDCLSYNC = 0
MDCHSYNC = 0
MDCLSYNC = 1
FIGURE 26-3: NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0)

Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 0
Active Carrier CARH CARL CARH CARL

State
FIGURE 26-4: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0)

Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
Active Carrier CARH both CARL CARH both CARL

State

PIC16(L)F18857/77
FIGURE 26-5: CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 1

State
FIGURE 26-6: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1)

Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD) Falling edges

used to sync
MDCHSYNC = 1
MDCLSYNC = 1

State

PIC16(L)F18857/77
26.5 Carrier Source Polarity Select 26.9 Operation in Sleep Mode
The signal provided from any selected input source for The DSM module is not affected by Sleep mode. The
the carrier high and carrier low signals can be inverted. DSM can still operate during Sleep, if the Carrier and
Inverting the signal for the carrier high source is Modulator input sources are also still operable during
enabled by setting the MDCHPOL bit of the MDCON1 Sleep.
register. Inverting the signal for the carrier low source is
enabled by setting the MDCLPOL bit of the MDCON1 26.10 Effects of a Reset
register.
Upon any device Reset, the DSM module is disabled.
26.6 Programmable Modulator Data The user’s firmware is responsible for initializing the
module before enabling the output. The registers are
The MDBIT of the MDCON0 register can be selected reset to their default values.
as the source for the modulator signal. This gives the
user the ability to program the value used for modula-
tion.
26.7 Modulated Output Polarity

The modulated output signal provided on the DSM pin
can also be inverted. Inverting the modulated output
signal is enabled by setting the MDOPOL bit of the
MDCON0 register.
26.8 Slew Rate Control

The slew rate limitation on the output port pin can be
disabled. The slew rate limitation can be removed by
clearing the SLR bit of the SLRCON register
associated with that pin. For example, clearing the slew
rate limitation for pin RA5 would require clearing the
SLRA5 bit of the SLRCONA register.

PIC16(L)F18857/77
26.11 Register Definitions: Modulation Control
REGISTER 26-1: MDCON0: MODULATION CONTROL REGISTER

R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
MDEN — MDOUT MDOPOL — — — MDBIT(2)
bit 7 bit 0
Legend:
bit 7 MDEN: Modulator Module Enable bit

1 = Modulator module is enabled and mixing input signals
0 = Modulator module is disabled and has no output
bit 5 MDOUT: Modulator Output bit
Displays the current output value of the modulator module.(1)
bit 4 MDOPOL: Modulator Output Polarity Select bit
1 = Modulator output signal is inverted; idle high output
0 = Modulator output signal is not inverted; idle low output
bit 0 MDBIT: Allows software to manually set modulation source input to module(2)
Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit, the bit value may not be valid for higher speed modulator or carrier signals.
2: MDBIT must be selected as the modulation source in the MDSRC register for this operation.

PIC16(L)F18857/77
REGISTER 26-2: MDCON1: MODULATION CONTROL REGISTER 1

U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
— — MDCHPOL MDCHSYNC — — MDCLPOL MDCLSYNC
bit 7 bit 0
Legend:

bit 5 MDCHPOL: Modulator High Carrier Polarity Select bit
1 = Selected high carrier signal is inverted
0 = Selected high carrier signal is not inverted
bit 4 MDCHSYNC: Modulator High Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the
low time carrier
0 = Modulator Output is not synchronized to the high-time carrier signal(1)
bit 1 MDCLPOL: Modulator Low Carrier Polarity Select bit
1 = Selected low carrier signal is inverted
0 = Selected low carrier signal is not inverted
bit 0 MDCLSYNC: Modulator Low Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the
high-time carrier
0 = Modulator Output is not synchronized to the low-time carrier signal(1)
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.

PIC16(L)F18857/77
REGISTER 26-3: MDSRC: MODULATION SOURCE CONTROL REGISTER

U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — MDMS<4:0>
bit 7 bit 0
Legend:

bit 4-0 MDMS<4:0> Modulation Source Selection bits
•
•
•
10011 = MSSP2 SDO
10010 = MSSP1 SDO
10001 = EUSART TX/CK output
10000 = EUSART DT output
01111 = CLC4 output
01110 = CLC3 output
01101 = CLC2 output
01100 = CLC1 output
01011 = C2 (Comparator 2) output
01010 = C1 (Comparator 1) output
01001 = NCO output
01000 = PWM7 output
00111 = PWM6 output
00110 = CCP5 output (PWM Output mode only)
00001 = MDBIT of MDCON0 register is modulation source
00000 = MDSRCPPS

PIC16(L)F18857/77
REGISTER 26-4: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER

U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u
(1)
— — — — MDCHS<3:0>
bit 7 bit 0
Legend:

bit 3-0 MDCHS<3:0> Modulator Data High Carrier Selection bits (1)
1111 = LC4_out
1110 = LC3_out
1101 = LC2_out
1100 = LC1_out
1011 = NCO output
1010 = PWM7_out
1001 = PWM6_out
0011 = Reference clock module signal (CLKR)
0010 = HFINTOSC
0001 = FOSC
0000 = Pin selected by MDCARHPPS

PIC16(L)F18857/77
REGISTER 26-5: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER

U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u
(1)
— — — — MDCLS<3:0>
bit 7 bit 0
Legend:

bit 3-0 MDCLS<3:0> Modulator Data High Carrier Selection bits (1)
1111 = LC4_out
1110 = LC3_out
1101 = LC2_out
1100 = LC1_out
1011 = NCO output
1010 = PWM7_out
1001 = PWM6_out
0011 = Reference clock module signal (CLKR)
0010 = HFINTOSC
0001 = FOSC
0000 = Pin selected by MDCARLPPS

PIC16(L)F18857/77
TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE
Register
on Page
INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 205
INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 217
MDCON0 MDEN — MDOUT MDOPOL — — — MDBIT 387
MDCON1 — — MDCHPOL MDCHSYNC — — MDCLPOL MDCLSYNC 388
MDSRC — — — MDMS<4:0> 389
MDCARH — — — — MDCHS<3:0> 390
MDCARL — — — — MDCLS<3:0> 391
MDCARLPPS — — — MDCARLPPS<4:0> 240
MDCARHPPS — — — MDCARHPPS<4:0> 240
MDSRCPPS — — — MDSRCPPS<4:0> 240
RxyPPS — — — RxyPPS<4:0> 241
SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 205
SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 217
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode.

PIC16(L)F18857/77
27.0 TIMER0 MODULE The value of TMR0L is compared to that of the Period
buffer, a copy of TMR0H, on each clock cycle. When
The Timer0 module is an 8/16-bit timer/counter with the the two values match, the following events happen:
following features:
• TMR0_out goes high for one prescaled clock
• 16-bit timer/counter period
• 8-bit timer/counter with programmable period • TMR0L is reset
• Synchronous or asynchronous operation • The contents of TMR0H are copied to the period
• Selectable clock sources buffer
• Programmable prescaler (independent of
In 8-bit mode, the TMR0L and TMR0H registers are
Watchdog Timer)
both directly readable and writable. The TMR0L
• Programmable postscaler
register is cleared on any device Reset, while the
• Operation during Sleep mode
TMR0H register initializes at FFh.
• Interrupt on match or overflow
• Output on I/O pin (via PPS) or to other peripherals Both the prescaler and postscaler counters are cleared
on the following events:
27.1 Timer0 Operation • A write to the TMR0L register
• A write to either the T0CON0 or T0CON1
Timer0 can operate as either an 8-bit timer/counter or registers
a 16-bit timer/counter. The mode is selected with the • Any device Reset – Power-on Reset (POR),
T016BIT bit of the T0CON register. MCLR Reset, Watchdog Timer Reset (WDTR) or
When used with an internal clock source, the module is • Brown-out Reset (BOR)
a timer and increments on every instruction cycle.
When used with an external clock source, the module 27.1.3 COUNTER MODE
can be used as either a timer or a counter and In Counter mode, the prescaler is normally disabled by
increments on every rising edge of the external source. setting the T0CKPS bits of the T0CON1 register to
‘0000’. Each rising edge of the clock input (or the
27.1.1 16-BIT MODE output of the prescaler if the prescaler is used)
In normal operation, TMR0 increments on the rising increments the counter by ‘1’.
edge of the clock source. A 15-bit prescaler on the
clock input gives several prescale options (see 27.1.4 TIMER MODE
prescaler control bits, T0CKPS<3:0> in the T0CON1 In Timer mode, the Timer0 module will increment every
register). instruction cycle as long as there is a valid clock signal
and the T0CKPS bits of the T0CON1 register
27.1.1.1 Timer0 Reads and Writes in 16-Bit (Register 27-2) are set to ‘0000’. When a prescaler is
Mode added, the timer will increment at the rate based on the
TMR0H is not the actual high byte of Timer0 in 16-bit prescaler value.
mode. It is actually a buffered version of the real high
byte of Timer0, which is neither directly readable nor 27.1.5 ASYNCHRONOUS MODE
writable (see Figure 27-1). TMR0H is updated with the When the T0ASYNC bit of the T0CON1 register is set
contents of the high byte of Timer0 during a read of (T0ASYNC = ‘1’), the counter increments with each
TMR0L. This provides the ability to read all 16 bits of rising edge of the input source (or output of the
Timer0 without having to verify that the read of the high prescaler, if used). Asynchronous mode allows the
and low byte was valid, due to a rollover between counter to continue operation during Sleep mode
successive reads of the high and low byte. provided that the clock also continues to operate during
Similarly, a write to the high byte of Timer0 must also Sleep.
take place through the TMR0H Buffer register. The high
27.1.6 SYNCHRONOUS MODE
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0 When the T0ASYNC bit of the T0CON1 register is clear
to be updated at once. (T0ASYNC = 0), the counter clock is synchronized to
the system oscillator (FOSC/4). When operating in
27.1.2 8-BIT MODE Synchronous mode, the counter clock frequency
In normal operation, TMR0 increments on the rising cannot exceed FOSC/4.
edge of the clock source. A 15-bit prescaler on the
clock input gives several prescale options (see 27.2 Clock Source Selection
prescaler control bits, T0CKPS<3:0> in the T0CON1
The T0CS<2:0> bits of the T0CON1 register are used
register).
to select the clock source for Timer0. Register 27-2
displays the clock source selections.

PIC16(L)F18857/77
27.2.1 INTERNAL CLOCK SOURCE 27.7 Timer0 Output
When the internal clock source is selected, Timer0 The Timer0 output can be routed to any I/O pin via the
operates as a timer and will increment on multiples of RxyPPS output selection register (see Section 13.0
the clock source, as determined by the Timer0 “Peripheral Pin Select (PPS) Module” for additional
prescaler. information). The Timer0 output can also be used by
other peripherals, such as the Auto-conversion Trigger
27.2.2 EXTERNAL CLOCK SOURCE of the Analog-to-Digital Converter. Finally, the Timer0
When an external clock source is selected, Timer0 can output can be monitored through software via the
operate as either a timer or a counter. Timer0 will Timer0 output bit (T0OUT) of the T0CON0 register
increment on multiples of the rising edge of the external (Register 27-1).
clock source, as determined by the Timer0 prescaler. TMR0_out will be one postscaled clock period when a
match occurs between TMR0L and TMR0H in 8-bit
27.3 Programmable Prescaler mode, or when TMR0 rolls over in 16-bit mode. The
Timer0 output is a 50% duty cycle that toggles on each
A software programmable prescaler is available for
TMR0_out rising clock edge.
exclusive use with Timer0. There are 16 prescaler
options for Timer0 ranging in powers of two from 1:1 to
1:32768. The prescaler values are selected using the
T0CKPS<3:0> bits of the T0CON1 register.
The prescaler is not directly readable or writable.
Clearing the prescaler register can be done by writing
to the TMR0L register or the T0CON1 register.
27.4 Programmable Postscaler

A software programmable postscaler (output divider) is
available for exclusive use with Timer0. There are 16
postscaler options for Timer0 ranging from 1:1 to 1:16.
The postscaler values are selected using the
T0OUTPS<3:0> bits of the T0CON0 register.
The postscaler is not directly readable or writable.
Clearing the postscaler register can be done by writing
to the TMR0L register or the T0CON0 register.
27.5 Operation during Sleep

When operating synchronously, Timer0 will halt. When
operating asynchronously, Timer0 will continue to
increment and wake the device from Sleep (if Timer0
interrupts are enabled) provided that the input clock
source is active.
27.6 Timer0 Interrupts

The Timer0 interrupt flag bit (TMR0IF) is set when
either of the following conditions occur:
• 8-bit TMR0L matches the TMR0H value
• 16-bit TMR0 rolls over from ‘FFFFh’
When the postscaler bits (T0OUTPS<3:0>) are set to
1:1 operation (no division), the T0IF flag bit will be set
with every TMR0 match or rollover. In general, the
TMR0IF flag bit will be set every T0OUTPS +1 matches
or rollovers.
If Timer0 interrupts are enabled (TMR0IE bit of the
PIE0 register = 1), the CPU will be interrupted and the
device may wake from sleep (see Section 27.2, Clock
Source Selection for more details).

PIC16(L)F18857/77
FIGURE 27-1: BLOCK DIAGRAM OF TIMER0
Rev. 10-000017E
6/15/2016
Reserved 111
LC1_out 110
SOSC 101 T0CKPS<3:0> TMR0
LFINTOSC 100 body T0OUTPS<3:0> TMR0IF
Prescaler 1
HFINTOSC 011 IN OUT Postscaler TMR0_overflow
SYNC 0
FOSC/4 010
PPS 001 FOSC/4 T016BIT TMR0
T0ASYNC D Q PPS
000
T0CKIPPS CK Q RxyPPS
T0CS<2:0>
8-bit TMR0 Body Diagram (T016BIT = 0) 16-bit TMR0 Body Diagram (T016BIT = 1)
Clear IN TMR0 High OUT

IN TMR0L R TMR0L Byte
Read TMR0L
COMPARATOR OUT
Write TMR0L
8
8 TMR0H
TMR0 High
Byte
Latch 8
Enable
TMR0H
8
Internal Data Bus

PIC16(L)F18857/77
REGISTER 27-1: T0CON0: TIMER0 CONTROL REGISTER 0
R/W-0/0 U-0 R-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
T0EN — T0OUT T016BIT T0OUTPS<3:0>
bit 7 bit 0
Legend:
bit 7 T0EN: TMR0 Enable bit

1 = The module is enabled and operating
0 = The module is disabled and in the lowest power mode
bit 5 T0OUT: TMR0 Output bit (read-only)
TMR0 output bit
bit 4 T016BIT: TMR0 Operating as 16-bit Timer Select bit
1 = TMR0 is a 16-bit timer
0 = TMR0 is an 8-bit timer
bit 3-0 T0OUTPS<3:0>: TMR0 output postscaler (divider) select bits
1111 = 1:16 Postscaler

PIC16(L)F18857/77
REGISTER 27-2: T0CON1: TIMER0 CONTROL REGISTER 1
T0CS<2:0> T0ASYNC T0CKPS<3:0>
bit 7 bit 0
Legend:
bit 7-5 T0CS<2:0>: Timer0 Clock Source select bits

111 = Reserved
110 = LC1_out
101 = SOSC
100 = LFINTOSC
011 = HFINTOSC
010 = FOSC/4
001 = T0CKIPPS (Inverted)
000 = T0CKIPPS (True)
bit 4 T0ASYNC: TMR0 Input Asynchronization Enable bit
1 = The input to the TMR0 counter is not synchronized to system clocks
0 = The input to the TMR0 counter is synchronized to FOSC/4
bit 3-0 T0CKPS<3:0>: Prescaler Rate Select bit
1111 = 1:32768
1110 = 1:16384
1101 = 1:8192
1100 = 1:4096
1011 = 1:2048
1010 = 1:1024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1

PIC16(L)F18857/77
TABLE 27-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Register
on Page
TMR0L Holding Register for the Least Significant Byte of the 16-bit TMR0 Register 393*
TMR0H Holding Register for the Most Significant Byte of the 16-bit TMR0 Register 393*
T0CON0 T0EN ― T0OUT T016BIT T0OUTPS<3:0> 396
T0CON1 T0CS<2:0> T0ASYNC T0CKPS<3:0> 397
T0CKIPPS ― ― ― — T0CKIPPS<3:0> 240
TMR0PPS ― ― ― TMR0PPS<4:0> 240
ADACT ― ― ― ADACT<4:0> 350
CLCxSELy ― ― ― LCxDyS<4:0> 320
T1GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 409
PIR0 ― ― TMR0IF IOCIF ― ― ― INTF 143
PIE0 ― ― TMR0IE IOCIE ― ― ― INTE 134
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page with Register information.

PIC16(L)F18857/77
28.0 TIMER1/3/5 MODULE WITH
GATE CONTROL
The Timer1/3/5 modules are 16-bit timer/counters with
the following features:
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Auto-conversion Trigger (with CCP)
• Selectable Gate Source Polarity
• Gate Toggle mode
• Gate Single-Pulse mode
• Gate Value Status
• Gate Event Interrupt
Figure 28-1 is a block diagram of the Timer1 module.
This device has three instances of Timer1 type mod-
ules. They include:
• Timer1
• Timer3
• Timer5
All references to Timer1 and Timer1 Gate apply equally
to Timer3 and Timer5.

PIC16(L)F18857/77
FIGURE 28-1: TIMER1 BLOCK DIAGRAM
TMRxGATE<4:0> Rev. 10-000018K

7/15/2016
4
TxGPPS
TxGSPM
PPS 00000
1
0 Single Pulse D Q TxGVAL
NOTE (5) 0
11111
1 Acq. Control
Q1
D Q
TxGPOL TxGGO/DONE
CK Q
TMRxON Interrupt
set bit
R
TxGTM det TMRxGIF
TMRxGE
set flag bit
TMRxIF
TMRxON
EN
(2) To Comparators (6)
TMRx
Tx_overflow Synchronized Clock Input
TMRxH TMRxL Q D 0
1
TxCLK
TxSYNC
TMRxCLK<3:0>
4
TxCKIPPS
(1)
PPS 0000
Prescaler
Synchronize(3)
1,2,4,8
(4)
Note det
1111
2
Fosc/2
TxCKPS<1:0> Internal Sleep
Clock Input
Note 1: ST Buffer is high speed type when using TxCKIPPS.
2: TMRx register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: See Register 28-3 for Clock source selections.
5: See Register 28-4 for GATE source selections.
6: Synchronized comparator output should not be used in conjunction with synchronized input clock.

PIC16(L)F18857/77
28.1 Timer1 Operation 28.2.2 EXTERNAL CLOCK SOURCE
The Timer1 modules are 16-bit incrementing counters When the timer is enabled and the external clock input
which are accessed through the TMR1H:TMR1L source (ex: T1CKI PPS remappable input) is selected as
register pairs. Writes to TMR1H or TMR1L directly the clock source, the timer will increment on the rising
update the counter. edge of the external clock input.
When used with an internal clock source, the module is When using an external clock source, the timer can be
a timer and increments on every instruction cycle. configured to run synchronously or asynchronously, as
When used with an external clock source, the module described in Section 28.6 “Timer Operation in
can be used as either a timer or counter and incre- Asynchronous Counter Mode”.
ments on every selected edge of the external source. When used as a timer with a clock oscillator, an
The timer is enabled by configuring the TMR1ON and external 32.768 kHz crystal can be used connected to
GE bits in the T1CON and T1GCON registers, respec- the SOSCI/SOSCO pins.
tively. Table 28-1 displays the Timer1 enable selec- Note: In Counter mode, a falling edge must be
tions. registered by the counter prior to the first
incrementing rising edge after any one or
TABLE 28-1: TIMER1 ENABLE more of the following conditions:
SELECTIONS • The timer is first enabled after POR
Timer1 • Firmware writes to TMR1H or TMR1L
TMR1ON TMR1GE • The timer is disabled
Operation
• The timer is re-enabled (e.g.,
1 1 Count Enabled
TMR1ON-->1) when the T1CKI sig-
1 0 Always On nal is currently logic low.
0 1 Off
0 0 Off 28.3 Timer Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
28.2 Clock Source Selection divisions of the clock input. The CKPS bits of the
The T1CLK register is used to select the clock source for T1CON register control the prescale counter. The
the timer. Register 28-3 shows the possible clock prescale counter is not directly readable or writable;
sources that may be selected to make the timer however, the prescaler counter is cleared upon a write to
increment. TMR1H or TMR1L.
28.2.1 INTERNAL CLOCK SOURCE 28.4 Timer1 16-Bit Read/Write Mode

When the internal clock source FOSC is selected, the Timer1 can be configured for 16-bit reads and writes.
TMR1H:TMR1L register pair will increment on multiples of When the RD16 control bit (T1CON<1>) is set, the
FOSC as determined by the respective Timer1 prescaler. address for TMR1H is mapped to a buffer register for
When the FOSC internal clock source is selected, the the high byte of Timer1. A read from TMR1L loads the
timer register value will increment by four counts every contents of the high byte of Timer1 into the Timer1 High
instruction clock cycle. Due to this condition, a 2 LSB Byte Buffer register. This provides the user with the
error in resolution will occur when reading the ability to accurately read all 16 bits of Timer1 without
TMR1H:TMR1L value. To utilize the full resolution of the having to determine whether a read of the high byte,
timer in this mode, an asynchronous input signal must followed by a read of the low byte, has become invalid
be used to gate the timer clock input. due to a rollover between reads. A write to the high byte
Out of the total timer gate signal sources, the following of Timer1 must also take place through the TMR1H
subset of sources can be asynchronous and may be Buffer register. The Timer1 high byte is updated with
useful for this purpose: the contents of TMR1H when a write occurs to TMR1L.
This allows a user to write all 16 bits at once to both the
• CLC4 output high and low bytes of Timer1. The high byte of Timer1
• CLC3 output is not directly readable or writable in this mode. All
• CLC2 output reads and writes must take place through the Timer1
• CLC1 output High Byte Buffer register. Writes to TMR1H do not clear
the Timer1 prescaler. The prescaler is only cleared on
• Zero-Cross Detect output
writes to TMR1L.
• Comparator2 output
• Comparator1 output
• TxG PPS remappable input pin

PIC16(L)F18857/77
28.5 Secondary Oscillator 28.6.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
A dedicated low-power 32.768 kHz oscillator circuit is
MODE
built-in between pins SOSCI (input) and SOSCO
(amplifier output). This internal circuit is designed to be Reading TMR1H or TMR1L while the timer is running
used in conjunction with an external 32.768 kHz from an external asynchronous clock will ensure a valid
crystal. read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
The oscillator circuit is enabled by setting the SOSCEN
8-bit values itself, poses certain problems, since the
bit of the OSCEN register. The oscillator will continue to
timer may overflow between the reads.
run during Sleep.
For writes, it is recommended that the user simply stop
Note: The oscillator requires a start-up and the timer and write the desired values. A write
stabilization time before use. Thus, contention may occur by writing to the timer registers,
SOSCEN should be set and a suitable while the register is incrementing. This may produce an
delay observed prior to using Timer1 with unpredictable value in the TMR1H:TMR1L register pair.
the SOSC source. A suitable delay similar
to the OST delay can be implemented in
software by clearing the TMR1IF bit then
28.7 Timer Gate
presetting the TMR1H:TMR1L register Timer1 can be configured to count freely or the count
pair to FC00h. The TMR1IF flag will be set can be enabled and disabled using the time gate
when 1024 clock cycles have elapsed, circuitry. This is also referred to as Timer Gate Enable.
thereby indicating that the oscillator is
The timer gate can also be driven by multiple select-
running and reasonably stable.
able sources.
28.6 Timer Operation in Asynchronous 28.7.1 TIMER GATE ENABLE

Counter Mode The Timer Gate Enable mode is enabled by setting the
If the control bit SYNC of the T1CON register is set, the GE bit of the T1GCON register. The polarity of the
external clock input is not synchronized. The timer Timer Gate Enable mode is configured using the GPOL
increments asynchronously to the internal phase bit of the T1GCON register.
clocks. If the external clock source is selected then the When Timer Gate Enable mode is enabled, the timer
timer will continue to run during Sleep and can will increment on the rising edge of the Timer1 clock
generate an interrupt on overflow, which will wake-up source. When Timer Gate Enable mode is disabled, no
the processor. However, special precautions in incrementing will occur and the timer will hold the
software are needed to read/write the timer (see current count. See Figure 28-3 for timing details.
Section 28.6.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
TABLE 28-2: TIMER GATE ENABLE
Note: When switching from synchronous to SELECTIONS
asynchronous operation, it is possible to
skip an increment. When switching from T1CLK T1GPOL T1G Timer Operation
asynchronous to synchronous operation,  1 1 Counts
it is possible to produce an additional  1 0 Holds Count
increment.
 0 1 Holds Count
 0 0 Counts

PIC16(L)F18857/77
28.7.2 TIMER GATE SOURCE SELECTION 28.7.4 TIMER1 GATE SINGLE-PULSE
One of the several different external or internal signal MODE
sources may be chosen to gate the timer and allow the When Timer1 Gate Single-Pulse mode is enabled, it is
timer to increment. The gate input signal source can be possible to capture a single-pulse gate event. Timer1
selected based on the T1GATE register setting. See the Gate Single-Pulse mode is first enabled by setting the
T1GATE register (Register 28-4) description for a GSPM bit in the T1GCON register. Next, the
complete list of the available gate sources. The polarity GGO/DONE bit in the T1GCON register must be set.
for each available source is also selectable. Polarity The timer will be fully enabled on the next incrementing
selection is controlled by the GPOL bit of the T1GCON edge. On the next trailing edge of the pulse, the
register. GGO/DONE bit will automatically be cleared. No other
gate events will be allowed to increment the timer until
28.7.2.1 T1G Pin Gate Operation the GGO/DONE bit is once again set in software. See
The T1G pin is one source for the timer gate control. It Figure 28-5 for timing details.
can be used to supply an external source to the time If the Single-Pulse Gate mode is disabled by clearing the
gate circuitry. GSPM bit in the T1GCON register, the GGO/DONE bit
should also be cleared.
28.7.2.2 Timer0 Overflow Gate Operation
Enabling the Toggle mode and the Single-Pulse mode
When Timer0 overflows, or a period register match simultaneously will permit both sections to work
condition occurs (in 8-bit mode), a low-to-high pulse will together. This allows the cycle times on the timer gate
automatically be generated and internally supplied to source to be measured. See Figure 28-6 for timing
the Timer1 gate circuitry. details.
28.7.2.3 Comparator C1 Gate Operation 28.7.5 TIMER1 GATE VALUE STATUS
The output resulting from a Comparator 1 operation can When Timer1 Gate Value Status is utilized, it is possible
be selected as a source for the timer gate control. The to read the most current level of the gate control value.
Comparator 1 output can be synchronized to the timer The value is stored in the GVAL bit in the T1GCON reg-
clock or left asynchronous. For more information see ister. The GVAL bit is valid even when the timer gate is
Section 18.4.1 “Comparator Output not enabled (GE bit is cleared).
Synchronization”.
28.7.6 TIMER1 GATE EVENT INTERRUPT
28.7.2.4 Comparator C2 Gate Operation
When Timer1 Gate Event Interrupt is enabled, it is
The output resulting from a Comparator 2 operation possible to generate an interrupt upon the completion
can be selected as a source for the timer gate control. of a gate event. When the falling edge of T1GVAL
The Comparator 2 output can be synchronized to the occurs, the TMR1GIF flag bit in the PIR5 register will be
timer clock or left asynchronous. For more information set. If the TMR1GIE bit in the PIE5 register is set, then
see Section 18.4.1 “Comparator Output an interrupt will be recognized.
Synchronization”.
The TMR1GIF flag bit operates even when the timer
28.7.3 TIMER1 GATE TOGGLE MODE gate is not enabled (TMR1GE bit is cleared).
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a timer gate sig-
nal, as opposed to the duration of a single level pulse.
The timer gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 28-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
GTM bit of the T1GCON register. When the GTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
Note: Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.

PIC16(L)F18857/77
28.8 Timer1 Interrupts The Timer1 to CCP1/2/3/4/5 mapping is not fixed, and
can be assigned on an individual CCP module basis.
The timer register pair (TMR1H:TMR1L) increments to All of the CCP modules may be configured to share a
FFFFh and rolls over to 0000h. When the timer rolls single Timer1 (or Timer3, or Timer5) resource, or
over, the respective timer interrupt flag bit of the PIR4 different CCP modules may be configured to use
register is set. To enable the interrupt on rollover, you different Timer1 resources. This timer to CCP mapping
must set these bits: selection is made in the CCPTMRS0 and CCPTMRS1
• ON bit of the T1CON register registers.
• TMR1IE bit of the PIE4 register For more information, see Section 30.0
• PEIE bit of the INTCON register “Capture/Compare/PWM Modules”.
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
28.11 CCP Auto-Conversion Trigger
the Interrupt Service Routine. When any of the CCP’s are configured to trigger an
Note: To avoid immediate interrupt vectoring, auto-conversion, the trigger will clear the
the TMR1H:TMR1L register pair should TMR1H:TMR1L register pair. This auto-conversion
be preloaded with a value that is not immi- does not cause a timer interrupt. The CCP module may
nently about to rollover, and the TMR1IF still be configured to generate a CCP interrupt.
flag should be cleared prior to enabling In this mode of operation, the CCPRxH:CCPRxL
the timer interrupts. register pair becomes the period register for Timer1.
The timer should be synchronized and FOSC/4 should
28.9 Timer1 Operation During Sleep be selected as the clock source in order to utilize the
Auto-conversion Trigger. Asynchronous operation of
Timer1 can only operate during Sleep when setup in the timer can cause an Auto-conversion Trigger to be
Asynchronous Counter mode. In this mode, an external missed.
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device: In the event that a write to TMR1H or TMR1L coincides
with an Auto-conversion Trigger from the CCP, the
• ON bit of the T1CON register must be set write will take precedence.
• TMR1IE bit of the PIE4 register must be set
For more information, see Section 30.2.4 “Compare
• PEIE bit of the INTCON register must be set During Sleep”.
• SYNC bit of the T1CON register must be set
• CLK bits of the T1CLK register must be
configured
• The timer clock source must be enabled and
continue operation during sleep. When the SOSC
is used for this purpose, the SOSCEN bit of the
OSCEN register must be set.
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Secondary oscillator will continue to operate in Sleep
regardless of the SYNC bit setting.
28.10 CCP Capture/Compare Time Base

The CCP modules use the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPRxH:CCPRxL
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPRxH:CCPRxL register pair matches the value in
the TMR1H:TMR1L register pair. This event can be an
Auto-conversion Trigger.

PIC16(L)F18857/77
FIGURE 28-2: TIMER1 INCREMENTING EDGE
TxCKI = 1
when the timer is
enabled
TxCKI = 0
when the timer is
enabled
Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
FIGURE 28-3: TIMER1 GATE ENABLE MODE
TMRxGE
TxGPOL
selected
gate input
TxCKI
TxGVAL
TMRxH:TMRxL N N+1 N+2 N+3 N+4

Count

PIC16(L)F18857/77
FIGURE 28-4: TIMER1 GATE TOGGLE MODE
TMRxGE
TxGPOL
TxGTM
selected
gate input
TxCKI
TxGVAL
TMRxH:TMRxL N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8

Count
FIGURE 28-5: TIMER1 GATE SINGLE-PULSE MODE
TMRxGE
TxGPOL
TxGSPM
Cleared by hardware on
TxGGO/ Set by software falling edge of TxGVAL
DONE
Counting enabled on
rising edge of selected source
selected gate
source
TxCKI
TxGVAL
TMRxH:TMRxL N N+1 N+2

Count
Cleared by
TMRxGIF Cleared by software Set by hardware on software
falling edge of TxGVAL

PIC16(L)F18857/77
FIGURE 28-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMRxGE
TxGPOL
TxGSPM
TxGTM
Cleared by hardware on
TxGGO/ Set by software falling edge of TxGVAL
DONE Counting enabled on
rising edge of selected source
selected gate
source
TxCKI
TxGVAL
TMRxH:TMRxL N N+1 N+2 N+3 N+4

Count
Set by hardware on Cleared by
TMRxGIF Cleared by software falling edge of TxGVAL software

PIC16(L)F18857/77
28.12 Register Definitions: Timer1 Control start here with Memory chapter compare
Long bit name prefixes for the Timer1/3/5 are shown in
Table 28-3. Refer to Section 1.1 “Register and Bit
naming conventions” for more information
TABLE 28-3:
Timer1 T1
Timer3 T3
Timer5 T5
REGISTER 28-1: TxCON: TIMER1/3/5 CONTROL REGISTER

U-0 U-0 R/W-0/u R/W-0/u U-0 R/W-0/u R/W-0/u R/W-0/u
— — CKPS<1:0> — SYNC RD16 ON
bit 7 bit 0
Legend:

bit 5-4 CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
bit 2 SYNC: Timer1 Synchronization Control bit
When TMR1CLK = FOSC or FOSC/4
This bit is ignored. The timer uses the internal clock and no additional synchronization is performed.
When TMR1CS<1:0> = (any setting other than FOSC or FOSC/4)
1 = Do not synchronize external clock input
0 = Synchronized external clock input with system clock
bit 1 RD16: Timer1 On bit
1 = All 16 bits of Timer1 can be read simultaneously (TMR1H is buffered)
0 = 16-bit reads of Timer1 are disabled (TMR1H is not buffered)
bit 0 ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop

PIC16(L)F18857/77
REGISTER 28-2: TxGCON: TIMER1/3/5 GATE CONTROL REGISTER

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x U-0 U-0
GE GPOL GTM GSPM GGO/ GVAL — —
DONE
bit 7 bit 0
Legend:
bit 7 GE: Timer1 Gate Enable bit

If ON = 0:
This bit is ignored
If ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 is always counting
bit 6 GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5 GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4 GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3 GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when GSPM is cleared
bit 2 GVAL: Timer1 Gate Value Status bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L
Unaffected by Timer1 Gate Enable (GE)

PIC16(L)F18857/77
REGISTER 28-3: TxCLK TIMER1/3/5 CLOCK SELECT REGISTER

U-0 U-0 U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u
— — — — CS<3:0>
bit 7 bit 0
Legend:

bit 3-0 TxCS<3:0>: Timer1/3/5 Clock Select bits
1111 = LC4_out
1110 = LC3_out
1101 = LC2_out
1100 = LC1_out
1011 = TMR5 overflow output(3)
1000 = TMR0 overflow output
0111 = CLKR output clock
0110 = SOSC
0101 = MFINTOSC
0100 = LFINTOSC
0011 = HFINTOSC
0010 = FOSC
0001 = FOSC/4
0000 = TxCKIPPS
Note 1: For Timer1, this bit is Reserved.

2: For Timer3, this bit is Reserved.

PIC16(L)F18857/77
REGISTER 28-4: TxGATE TIMER1/3/5 GATE SELECT REGISTER

U-0 U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u
— — — GSS<4:0>
bit 7 bit 0
Legend:

bit 4-0 GSS<4:0>: Timer1 Gate Select bits
11111 = Reserved
•
•
•
11001 = Reserved
11000 = LC4_out
10111 = LC3_out
10110 = LC2_out
10101 = LC1_out
10100 = ZCD1_output
10011 = C2OUT_sync
10010 = C1OUT_sync
10001 = DDS_out
10000 = PWM7_out
01111 = PWM6_out
01110 = CCP5_out
01101 = CCP4_out
01100 = CCP3_out
01011 = CCP2_out
01010 = CCP1_out
01001 = SMT2_match
01000 = SMT1_match
00010 = TMR1 overflow output(1)t
00001 = TMR0 overflow output
00000 = T1GPPS


PIC16(L)F18857/77

Register
on Page

PIR4 ― ― TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF 133
T1CON — — CKPS<5:4> — SYNC RD16 ON 408
T1GCON GE GPOL GTM GSPM GGO/ GVAL — — 409
DONE
T1GATE — — — GSS<4:0> 411

T1CLK — — — — CS<3:0> 410
T1CKIPPS ― ― ― T1CKIPPS<4:0> 240
T1GPPS ― ― ― T1GPPS<4:0> 240
DONE
T3GATE — — — GSS<4:0> 411

T3CLK — — — — CS<3:0> 410
T3GPPS ― ― ― T3GPPS<4:0> 240
DONE
T5GATE — — — GSS<4:0> 411

T5CLK — — — — CS<3:0> 410
T5GPPS ― ― ― T5GPPS<4:0> 240
T0CON0 T0EN ― T0OUT T016BIT T0OUTPS<3:0> 396
CMxCON0 CxON CxOUT ― CxPOL ― CxSP CxHYS CxSYNC 270
CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 444
CCPTMRS1 — — P7TSEL<1:0> P6TSEL<1:0> C5TSEL<1:0> 444
CCPxCON CCPxEN ― CCPxOUT CCPxFMT CCPxMODE<3:0> 441
ADACT ― ― ― ADACT<4:0> 350
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the Timer1 modules.
* Page with register information.

PIC16(L)F18857/77
29.0 TIMER2/4/6 MODULE • Three modes of operation:
- Free Running Period
The Timer2/4/6 modules are 8-bit timers that can
- One-shot
operate as free-running period counters or in
conjunction with external signals that control start, run, - Monostable
freeze, and reset operation in One-Shot and See Figure 29-1 for a block diagram of Timer2. See
Monostable modes of operation. Sophisticated Figure 29-2 for the clock source block diagram.
waveform control such as pulse density modulation are
possible by combining the operation of these timers Note: Three identical Timer2 modules are
with other internal peripherals such as the comparators implemented on this device. The timers are
and CCP modules. Features of the timer include: named Timer2, Timer4, and Timer6. All
references to Timer2 apply as well to
• 8-bit timer register Timer4 and Timer6. All references to T2PR
• 8-bit period register apply as well to T4PR and T6PR.
• Selectable external hardware timer Resets
• Programmable prescaler (1:1 to 1:128)
• Programmable postscaler (1:1 to 1:16)
• Selectable synchronous/asynchronous operation
• Alternate clock sources
• Interrupt-on-period
FIGURE 29-1: TIMER2 BLOCK DIAGRAM

RSEL <:0> Rev. 10-000168C
9/10/2015
INPPS
TxIN PPS MODE<4:0> MODE<3>
Edge Detector reset

External
TMRx_ers Level Detector CCP_pset(1)
Reset
(2) Mode Control
Sources (2 clock Sync)
enable MODE<4:3>=01
Clear ON
MODE<4:1>=1011 D Q
CPOL
TMRx_clk Prescaler 0
R
T[7MR
Set flag bit
3 Sync 1 TMRxIF
CKPS<2:0> Fosc/4 PSYNC TMRx_postscaled

Comparator Postscaler
4
ON Sync
(2 Clocks)
1
7[PR OUTPS<3:0>
0
CSYNC
Note 1: Signal to the CCP to trigger the PWM pulse.

2: See Table 29.5 for description of CCP interaction in the different TMR modes.
3: See Register 29-4 for external Reset sources.

PIC16(L)F18857/77
FIGURE 29-2: TIMER2 CLOCK SOURCE 29.1.1 FREE RUNNING PERIOD MODE
BLOCK DIAGRAM The value of TMR2 is compared to that of the Period
TxCLKCON register, T2PR, on each clock cycle. When the two
values match, the comparator resets the value of TMR2
Rev. 10-000 169B
5/29/201 4
TXINPPS to 00h on the next cycle and increments the output

TXIN PPS postscaler counter. When the postscaler count equals
the value in the OUTPS<4:0> bits of the TMRxCON1
register then a one clock period wide pulse occurs on the
TMR2_postscaled output, and the postscaler count is
cleared.
Timer Clock Sources TMR2_clk
(See Register 29-1)
29.1.2 ONE-SHOT MODE
The One-Shot mode is identical to the Free Running
Period mode except that the ON bit is cleared and the
timer is stopped when TMR2 matches T2PR and will
not restart until the T2ON bit is cycled off and on.
Postscaler OUTPS<4:0> values other than 0 are
meaningless in this mode because the timer is stopped
29.1 Timer2 Operation at the first period event and the postscaler is reset
when the timer is restarted.
Timer2 operates in three major modes:
• Free Running Period 29.1.3 MONOSTABLE MODE
• One-shot Monostable modes are similar to One-Shot modes
• Monostable except that the ON bit is not cleared and the timer can
Within each mode there are several options for starting, be restarted by an external Reset event.
stopping, and reset. Table 29-1 lists the options.
In all modes, the TMR2 count register is incremented
29.2 Timer2 Output
on the rising edge of the clock signal from the program- The Timer2 module’s primary output is TMR2_posts-
mable prescaler. When TMR2 equals T2PR, a high caled, which pulses for a single TMR2_clk period when
level is output to the postscaler counter. TMR2 is the postscaler counter matches the value in the
cleared on the next clock input. OUTPS bits of the TMR2CON register. The T2PR post-
An external signal from hardware can also be config- scaler is incremented each time the TMR2 value
ured to gate the timer operation or force a TMR2 count matches the T2PR value. This signal can be selected
Reset. In Gate modes the counter stops when the gate as an input to several other input modules:
is disabled and resumes when the gate is enabled. In • The ADC module, as an Auto-conversion Trigger
Reset modes the TMR2 count is reset on either the • CWG, as an auto-shutdown source
level or edge from the external source.
• Memory Scanner, as a trigger to begin a scan
The TMR2 register is directly readable and writable. • Timer 1/3/5, as a gate input
The TMR2 register is cleared on any device Reset. The
• Timer 2/4/6, as an external reset signal
T2PR register is double-buffered and initializes to 0xFF
on any device Reset. The SFR is directly readable and • SMT, as both a window and signal input
writable, but the actual period buffer is only updated In addition, the Timer2 is also used by the CCP module
with the SFR value when the following events occur: for pulse generation in PWM mode. Both the actual
• a write to the TMR2 register TMR2 value as well as other internal signals are sent to
• a write to the T2CON register the CCP module to properly clock both the period and
• a write to the T2HLT register pulse width of the PWM signal. See Section 30.0
• TMR2 = T2PR and the prescaler is full “Capture/Compare/PWM Modules” for more details
• External Reset Source even that resets the timer. on setting up Timer2 for use with the CCP, as well as
the timing diagrams in Section 29.5 “Operation
Both the prescaler and postscaler counters are cleared Examples” for examples of how the varying Timer2
on the following events: modes affect CCP PWM output.
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset
• External Reset Source event that resets the timer.
Note: TMR2 is not cleared when T2CON is
written.

PIC16(L)F18857/77
29.3 External Reset Sources
In addition to the clock source, the Timer2 also takes in
an external Reset source. This external Reset source
is selected for Timer2, Timer4, and Timer6 with the
T2RST, T4RST, and T6RST registers, respectively.
This source can control starting and stopping of the
timer, as well as resetting the timer, depending on
which mode the timer is in. The mode of the timer is
controlled by the MODE<4:0> bits of the TMRxHLT
register. Edge-Triggered modes require six Timer clock
periods between external triggers. Level-Triggered
modes require the triggering level to be at least three
Timer clock periods long. External triggers are ignored
while in Debug Freeze mode.

PIC16(L)F18857/77
TABLE 29-1: TIMER2 OPERATING MODES

MODE<4:0> Output Timer Control
Mode Operation
<4:3> <2:0> Operation Start Reset Stop
000 Software gate (Figure 29-4) ON = 1 — ON = 0
Hardware gate, active-high ON = 1 and — ON = 0 or
001 Period
(Figure 29-5) TMRx_ers = 1 TMRx_ers = 0
Pulse
ON = 1 and — ON = 0 or
010 Hardware gate, active-low
TMRx_ers = 0 TMRx_ers = 1
Free 011 Rising or falling edge Reset TMRx_ers ↕
Running 00
Period 100 Period Rising edge Reset (Figure 29-6) TMRx_ers ↑ ON = 0
101 Pulse Falling edge Reset TMRx_ers ↓
with ON = 1 ON = 0 or
110 Hardware Low level Reset TMRx_ers = 0
TMRx_ers = 0
Reset
High level Reset (Figure 29-7) ON = 0 or
111 TMRx_ers = 1
TMRx_ers = 1
000 One-shot Software start (Figure 29-8) ON = 1 —
ON = 1 and
001 Rising edge start (Figure 29-9) —
Edge TMRx_ers ↑
triggered ON = 1 and
010 Falling edge start —
start TMRx_ers ↓
(Note 1) ON = 1 and ON = 0
011 Any edge start — or
TMRx_ers ↕
Next clock
One-shot 01 Rising edge start and ON = 1 and
100 TMRx_ers ↑ after
Edge Rising edge Reset (Figure 29-10) TMRx_ers ↑ TMRx = PRx
triggered Falling edge start and ON = 1 and (Note 2)
101 start TMRx_ers ↓
Falling edge Reset TMRx_ers ↓
and
hardware Rising edge start and ON = 1 and
110 TMRx_ers = 0
Reset Low level Reset (Figure 29-11) TMRx_ers ↑
(Note 1) Falling edge start and ON = 1 and
111 TMRx_ers = 1
High level Reset TMRx_ers ↓
000 Reserved
Rising edge start ON = 1 and ON = 0
001 —
Edge (Figure 29-12) TMRx_ers ↑ or
Mono-stable triggered ON = 1 and Next clock
010 Falling edge start —
start TMRx_ers ↓ after
(Note 1) ON = 1 and TMRx = PRx
011 Any edge start — (Note 3)
TMRx_ers ↕
Reserved 10 100 Reserved
Reserved 101 Reserved
Level High level start and ON = 1 and
110 TMRx_ers = 0
triggered Low level Reset (Figure 29-13) TMRx_ers = 1
ON = 0 or
start
One-shot Held in Reset
and Low level start & ON = 1 and
111 TMRx_ers = 1 (Note 2)
hardware High level Reset TMRx_ers = 0
Reset
Reserved 11 xxx Reserved
Note 1: If ON = 0 then an edge is required to restart the timer after ON = 1.
2: When TMRx = PRx then the next clock clears ON and stops TMRx at 00h.
3: When TMRx = PRx then the next clock stops TMRx at 00h but does not clear ON.

PIC16(L)F18857/77
29.4 Timer2 Interrupt
Timer2 can also generate a device interrupt. The
interrupt is generated when the postscaler counter
matches one of 16 postscale options (from 1:1 through
1:16), which are selected with the postscaler control
bits, OUTPS<3:0> of the T2CON register. The interrupt
is enabled by setting the TMR2IE interrupt enable bit of
the PIE4 register. Interrupt timing is illustrated in
Figure 29-3.
FIGURE 29-3: TIMER2 PRESCALER, POSTSCALER, AND INTERRUPT TIMING DIAGRAM
Rev. 10-000205A
4/7/2016
CKPS 0b010
PRx 1
OUTPS 0b0001
TMRx_clk
TMRx 0 1 0 1 0 1 0
TMRx_postscaled
(1) (2) (1)

TMRxIF
Note 1: Setting the interrupt flag is synchronized with the instruction clock.
Synchronization may take as many as 2 instruction cycles
2: Cleared by software.

PIC16(L)F18857/77
29.5 Operation Examples 29.5.1 SOFTWARE GATE MODE
Unless otherwise specified, the following notes apply to This mode corresponds to legacy Timer2 operation.
the following timing diagrams: The timer increments with each clock input when
ON = 1 and does not increment when ON = 0. When
- Both the prescaler and postscaler are set to the TMRx count equals the PRx period count the timer
1:1 (both the CKPS and OUTPS bits in the resets on the next clock and continues counting from 0.
TxCON register are cleared). Operation with the ON bit software controlled is illus-
- The diagrams illustrate any clock except trated in Figure 29-4. With PRx = 5, the counter
Fosc/4 and show clock-sync delays of at advances until TMRx = 5, and goes to zero with the
least two full cycles for both ON and next clock.
Timer2_ers. When using Fosc/4, the
clock-sync delay is at least one instruction
period for Timer2_ers; ON applies in the next
instruction period.
- The PWM Duty Cycle and PWM output are
illustrated assuming that the timer is used for
the PWM function of the CCP module as
described in Section 30.0 “Capture/Com-
pare/PWM Modules”. The signals are not a
part of the Timer2 module.
FIGURE 29-4: SOFTWARE GATE MODE TIMING DIAGRAM (MODE = 00000)

Rev. 10-000195B
5/30/2014
MODE 0b00000
TMRx_clk
Instruction(1) BSF BCF BSF
ON
PRx 5
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

PIC16(L)F18857/77
29.5.2 HARDWARE GATE MODE When MODE<4:0> = 00001 then the timer is stopped
when the external signal is high. When
The Hardware Gate modes operate the same as the
MODE<4:0> = 00010 then the timer is stopped when
Software Gate mode except the TMRx_ers external
the external signal is low.
signal can also gate the timer. When used with the CCP
the gating extends the PWM period. If the timer is Figure 29-5 illustrates the Hardware Gating mode for
stopped when the PWM output is high then the duty MODE<4:0> = 00001 in which a high input level starts
cycle is also extended. the counter.
FIGURE 29-5: HARDWARE GATE MODE TIMING DIAGRAM (MODE = 00001)

Rev. 10-000 196B
5/30/201 4
MODE 0b00001
TMRx_clk
TMRx_ers
PRx 5
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output

PIC16(L)F18857/77
29.5.3 EDGE-TRIGGERED HARDWARE When the timer is used in conjunction with the CCP in
LIMIT MODE PWM mode then an early Reset shortens the period
and restarts the PWM pulse after a two clock delay.
In Hardware Limit mode the timer can be reset by the
Refer to Figure 29-6.
TMRx_ers external signal before the timer reaches the
period count. Three types of Resets are possible:
• Reset on rising or falling edge
(MODE<4:0>= 00011)
• Reset on rising edge (MODE<4:0> = 00100)
• Reset on falling edge (MODE<4:0> = 00101)
FIGURE 29-6: EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM

(MODE = 00100)
Rev. 10-000 197B
5/30/201 4
MODE 0b00100
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output

PIC16(L)F18857/77
29.5.4 LEVEL-TRIGGERED HARDWARE When the CCP uses the timer as the PWM time base
LIMIT MODE then the PWM output will be set high when the timer
starts counting and then set low only when the timer
In the Level-Triggered Hardware Limit Timer modes the
count matches the CCPRx value. The timer is reset
counter is reset by high or low levels of the external
when either the timer count matches the PRx value or
signal TMRx_ers, as shown in Figure 29-7. Selecting
two clock periods after the external Reset signal goes
MODE<4:0> = 00110 will cause the timer to reset on a
true and stays true.
low level external signal. Selecting
MODE<4:0> = 00111 will cause the timer to reset on a The timer starts counting, and the PWM output is set
high level external signal. In the example, the counter high, on either the clock following the PRx match or two
is reset while TMRx_ers = 1. ON is controlled by BSF clocks after the external Reset signal relinquishes the
and BCF instructions. When ON = 0 the external signal Reset. The PWM output will remain high until the timer
is ignored. counts up to match the CCPRx pulse width value. If the
external Reset signal goes true while the PWM output
is high then the PWM output will remain high until the
Reset signal is released allowing the timer to count up
to match the CCPRx value.
FIGURE 29-7: LEVEL-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM

(MODE = 00111)
Rev. 10-000198B
5/30/2014
MODE 0b00111
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output

PIC16(L)F18857/77
29.5.5 SOFTWARE START ONE-SHOT When One-Shot mode is used in conjunction with the
MODE CCP PWM operation the PWM pulse drive starts con-
current with setting the ON bit. Clearing the ON bit
In One-Shot mode the timer resets and the ON bit is
while the PWM drive is active will extend the PWM
cleared when the timer value matches the PRx period
drive. The PWM drive will terminate when the timer
value. The ON bit must be set by software to start
value matches the CCPRx pulse width value. The
another timer cycle. Setting MODE<4:0> = 01000
PWM drive will remain off until software sets the ON bit
selects One-Shot mode which is illustrated in
to start another cycle. If software clears the ON bit after
Figure 29-8. In the example, ON is controlled by BSF
the CCPRx match but before the PRx match then the
and BCF instructions. In the first case, a BSF instruc-
PWM drive will be extended by the length of time the
tion sets ON and the counter runs to completion and
ON bit remains cleared. Another timing cycle can only
clears ON. In the second case, a BSF instruction starts
be initiated by setting the ON bit after it has been
the cycle, BCF/BSF instructions turn the counter off
cleared by a PRx period count match.
and on during the cycle, and then it runs to completion.
FIGURE 29-8: SOFTWARE START ONE-SHOT MODE TIMING DIAGRAM (MODE = 01000)
Rev. 10-000199B
4/7/2016
MODE 0b01000
TMRx_clk
PRx 5
Instruction(1) BSF BSF BCF BSF
ON
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions
executed by the CPU to set or clear the ON bit of TxCON. CPU
execution is asynchronous to the timer clock input.

PIC16(L)F18857/77
29.5.6 EDGE-TRIGGERED ONE-SHOT If the timer is halted by clearing the ON bit then another
MODE TMRx_ers edge is required after the ON bit is set to
resume counting. Figure 29-9 illustrates operation in
The Edge-Triggered One-Shot modes start the timer the rising edge One-Shot mode.
on an edge from the external signal input, after the ON
When Edge-Triggered One-Shot mode is used in con-
bit is set, and clear the ON bit when the timer matches
junction with the CCP then the edge-trigger will activate
the PRx period value. The following edges will start the the PWM drive and the PWM drive will deactivate when
timer: the timer matches the CCPRx pulse width value and
• Rising edge (MODE<4:0> = 01001) stay deactivated when the timer halts at the PRx period
• Falling edge (MODE<4:0> = 01010) count match.
• Rising or Falling edge (MODE<4:0> = 01011)
FIGURE 29-9: EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM (MODE = 01001)

Rev. 10-000200B
5/19/2016
MODE 0b01001
TMRx_clk
PRx 5
Instruction(1) BSF BSF BCF
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 2
CCP_pset
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output

29.5.7 EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT The timer resets and clears the ON bit when the timer value matches the PRx
PIC16(L)F18857/77
MODE period value. External signal edges will have no effect until after software sets
the ON bit. Figure 29-10 illustrates the rising edge hardware limit one-shot
In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first operation.
external signal edge after the ON bit is set and resets on all subsequent edges.
When this mode is used in conjunction with the CCP then the first starting edge
Only the first edge after the ON bit is set is needed to start the timer. The
trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM
counter will resume counting automatically two clocks after all subsequent drive will deactivate when the timer matches the CCPRx pulse-width value and
external Reset edges. Edge triggers are as follows: stay deactivated until the timer halts at the PRx period match unless an external
• Rising edge start and Reset (MODE<4:0> = 01100) signal edge resets the timer before the match occurs.
• Falling edge start and Reset (MODE<4:0> = 01101)
FIGURE 29-10: EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01100)
Rev. 10-000201B
4/7/2016
MODE 0b01100
TMRx_clk
PRx 5
Instruction(1) BSF BSF
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
DS40001825F-page 424
29.5.8 LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT When the timer count matches the PRx period count, the timer is reset and the
PIC16(L)F18857/77
ONE-SHOT MODES ON bit is cleared. When the ON bit is cleared by either a PRx match or by soft-
ware control a new external signal edge is required after the ON bit is set to start
In Level -Triggered One-Shot mode the timer count is reset on the external the counter.
signal level and starts counting on the rising/falling edge of the transition from
When Level-Triggered Reset One-Shot mode is used in conjunction with the
Reset level to the active level while the ON bit is set. Reset levels are selected
CCP PWM operation the PWM drive goes active with the external signal edge
as follows: that starts the timer. The PWM drive goes inactive when the timer count equals
• Low Reset level (MODE<4:0> = 01110) the CCPRx pulse width count. The PWM drive does not go active when the
• High Reset level (MODE<4:0> = 01111) timer count clears at the PRx period count match.
FIGURE 29-11: LOW LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01110)
Rev. 10-000202B
4/7/2016
MODE 0b01110
TMRx_clk
PRx 5
Instruction(1) BSF BSF
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
DS40001825F-page 425
29.5.9 EDGE-TRIGGERED MONOSTABLE MODES When an Edge-Triggered Monostable mode is used in conjunction with the
PIC16(L)F18857/77
CCP PWM operation the PWM drive goes active with the external Reset signal
The Edge-Triggered Monostable modes start the timer on an edge from the
edge that starts the timer, but will not go active when the timer matches the PRx
external Reset signal input, after the ON bit is set, and stop incrementing the
value. While the timer is incrementing, additional edges on the external Reset
timer when the timer matches the PRx period value. The following edges will
signal will not affect the CCP PWM.
start the timer:
• Rising edge (MODE<4:0> = 10001)
• Falling edge (MODE<4:0> = 10010)
• Rising or Falling edge (MODE<4:0> = 10011)
FIGURE 29-12: RISING EDGE-TRIGGERED MONOSTABLE MODE TIMING DIAGRAM (MODE = 10001)
Rev. 10-000203A
4/7/2016
MODE 0b10001
TMRx_clk
PRx 5
Instruction(1) BSF BCF BSF BCF BSF
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
DS40001825F-page 426
29.5.10 LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT • High Reset level (MODE<4:0> = 10111)
PIC16(L)F18857/77
MODES When the timer count matches the PRx period count, the timer is reset and the
The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset ON bit is cleared. When the ON bit is cleared by either a PRx match or by soft-
on an external Reset level and start counting when both the ON bit is set and ware control the timer will stay in Reset until both the ON bit is set and the exter-
the external signal is not at the Reset level. If one of either the external signal nal signal is not at the Reset level.
is not in Reset or the ON bit is set then the other signal being set/made active When Level-Triggered Hardware Limit One-Shot modes are used in conjunc-
will start the timer. Reset levels are selected as follows: tion with the CCP PWM operation the PWM drive goes active with either the
• Low Reset level (MODE<4:0> = 10110) external signal edge or the setting of the ON bit, whichever of the two starts the
timer.
FIGURE 29-13: LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 10110)
Rev. 10-000204A
4/7/2016
MODE 0b10110
TMR2_clk
PRx 5
Instruction(1) BSF BSF BCF BSF
ON
TMR2_ers
TMRx 0 1 2 3 4 5 0 1 2 3 0 1 2 3 4 5 0
TMR2_postscaled
PWM Duty
‘D3
Cycle
PWM Output
DS40001825F-page 427
PIC16(L)F18857/77
29.6 Timer2 Operation During Sleep
When PSYNC = 1, Timer2 cannot be operated while
the processor is in Sleep mode. The contents of the
TMR2 and T2PR registers will remain unchanged while
processor is in Sleep mode.
When PSYNC = 0, Timer2 will operate in Sleep as long
as the clock source selected is also still running.
Selecting the LFINTOSC, MFINTOSC, or HFINTOSC
oscillator as the timer clock source will keep the
selected oscillator running during Sleep.

PIC16(L)F18857/77
29.7 Register Definitions: Timer2/4/6 Control
Long bit name prefixes for the Timer2/4/6 peripherals are
shown in Table 29-2. Refer to Section 1.1 “Register
and Bit naming conventions” for more information
TABLE 29-2:
Timer2 T2
Timer4 T4
Timer6 T6
REGISTER 29-1: TxCLKCON: TIMER2/4/6 CLOCK SELECTION REGISTER

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — CS<3:0>
bit 7 bit 0
Legend:

bit 3-0 CS<3:0>: Timer2/4/6 Clock Select bits
1111 = Reserved
1110 = Reserved
1101 = LC4_out
1100 = LC3_out
1011 = LC2_out
1010 = LC1_out
1001 = ZCD1_output
1000 = NCO output
0111 = CLKR
0110 = SOSC
0101 = MFINTOSC/16 (31.25 kHz)
0100 = LFINTOSC
0011 = HFINTOSC (16 MHz)
0010 = FOSC
0001 = FOSC/4
0000 = TxCKIPPS

PIC16(L)F18857/77
REGISTER 29-2: TxCON: TIMER2/4/6 CONTROL REGISTER

R/W/HC-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ON(1) CKPS<2:0> OUTPS<3:0>
bit 7 bit 0
Legend:
bit 7 ON: Timerx On bit

1 = Timerx is on
0 = Timerx is off: all counters and state machines are reset
bit 6-4 CKPS<2:0>: Timer2-type Clock Prescale Select bits
111 = 1:128 Prescaler
011 = 1:8 Prescaler
010 = 1:4 Prescaler
001 = 1:2 Prescaler
000 = 1:1 Prescaler
bit 3-0 OUTPS<3:0>: Timerx Output Postscaler Select bits
Note 1: In certain modes, the ON bit will be auto-cleared by hardware. See Section 29.5 “Operation Examples”.

PIC16(L)F18857/77
REGISTER 29-3: TxHLT: TIMERx HARDWARE LIMIT CONTROL REGISTER

PSYNC(1, 2) CKPOL(3) CKSYNC(4, 5) MODE<4:0>(6, 7)
bit 7 bit 0
Legend:
bit 7 PSYNC: Timerx Prescaler Synchronization Enable bit(1, 2)

1 = TMRx Prescaler Output is synchronized to Fosc/4
0 = TMRx Prescaler Output is not synchronized to Fosc/4
bit 6 CKPOL: Timerx Clock Polarity Selection bit(3)
1 = Falling edge of input clock clocks timer/prescaler
0 = Rising edge of input clock clocks timer/prescaler
bit 5 CKSYNC: Timerx Clock Synchronization Enable bit(4, 5)
1 = ON register bit is synchronized to TMR2_clk input
0 = ON register bit is not synchronized to TMR2_clk input
bit 4-0 MODE<4:0>: Timerx Control Mode Selection bits(6, 7)
See Table 29-1.
Note 1: Setting this bit ensures that reading TMRx will return a valid value.
2: When this bit is ‘1’, Timer2 cannot operate in Sleep mode.
3: CKPOL should not be changed while ON = 1.
4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
5: When this bit is set then the timer operation will be delayed by two TMRx input clocks after the ON bit is set.
6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value
of TMRx).
7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.

PIC16(L)F18857/77
REGISTER 29-4: TXRST: TIMER2/4/6 EXTERNAL RESET SIGNAL SELECTION REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — RSEL<4:0>
bit 7 bit 0
Legend:

bit 4-0 RSEL<4:0>: Timer2 External Reset Signal Source Selection bits
11111 = Reserved
•
•
•
10010 = Reserved
10001 = LC4_out
10000 = LC3_out
01111 = LC2_out
01110 = LC1_out
01101 = ZCD1_output
01100 = C2OUT_sync
01011 = C1OUT_sync
01010 = PWM7_out
01001 = PWM6_out
01000 = CCP5_out
00111 = CCP4_out
00110 = CCP3_out
00101 = CCP2_out
00100 = CCP1_out
00011 = TMR6_postscaled(3)
00000 = Pin selected by TxINPPS


PIC16(L)F18857/77
Register
on Page
CCP1CON EN — OUT FMT MODE<3:0> 441
T2PR Timer2 Module Period Register 414*
TMR2 Holding Register for the 8-bit TMR2 Register 414*
T2CLKCON — — — — CS<3:0> 429
T2RST — — — RSEL<4:0> 432
T2HLT PSYNC CKPOL CKSYNC — MODE<3:0> 431
T4CLKCON — — — — — CS<3:0> 429
T4RST — — — RSEL<4:0> 432
T6CLKCON — — — — — CS<2:0> 429
T6RST — — — RSEL<4:0> 432
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
* Page provides register information.

PIC16(L)F18857/77
30.0 CAPTURE/COMPARE/PWM
MODULES
The Capture/Compare/PWM module is a peripheral
that allows the user to time and control different events,
and to generate Pulse-Width Modulation (PWM)
signals. In Capture mode, the peripheral allows the
timing of the duration of an event. The Compare mode
allows the user to trigger an external event when a
predetermined amount of time has expired. The PWM
mode can generate Pulse-Width Modulated signals of
varying frequency and duty cycle.
The Capture/Compare/PWM modules available are
shown in Table 30-1.
TABLE 30-1: AVAILABLE CCP MODULES

Device CCP1 CCP2 CCP3 CCP4 CCP5
PIC16(L)F18857/77 ● ● ● ● ●
The Capture and Compare functions are identical for all
CCP modules.
Note 1: In devices with more than one CCP
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the CCP1CON
and CCP2CON control the same
operational aspects of two completely
different CCP modules.
2: Throughout this section, generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to CCPx module.
Register names, module signals, I/O pins,
and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module,
when required.

PIC16(L)F18857/77
30.1 Capture Mode Figure 30-1 shows a simplified diagram of the capture
operation.
The Capture mode function described in this section is
available and identical for all CCP modules. 30.1.1 CAPTURE SOURCES
Capture mode makes use of the 16-bit Timer1 In Capture mode, the CCPx pin should be configured
resource. When an event occurs on the capture as an input by setting the associated TRIS control bit.
source, the 16-bit CCPRxH:CCPRxL register pair
captures and stores the 16-bit value of the Note: If the CCPx pin is configured as an output,
TMR1H:TMR1L register pair, respectively. An event is a write to the port can cause a capture
defined as one of the following and is configured by the condition.
CCPxMODE<3:0> bits of the CCPxCON register: The capture source is selected by configuring the
• Every falling edge CCPxCTS<2:0> bits of the CCPxCAP register. The
following sources can be selected:
• Every rising edge
• Every 4th rising edge • CCPxPPS input
• C1OUT_sync
• Every 16th rising edge
• C2OUT_sync
When a capture is made, the Interrupt Request Flag bit • IOC_interrupt
CCPxIF of the PIR6 register is set. The interrupt flag • LC1_out
must be cleared in software. If another capture occurs • LC2_out
before the value in the CCPRxH, CCPRxL register pair • LC3_out
is read, the old captured value is overwritten by the new • LC4_out
captured value.
FIGURE 30-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
Rev. 10-000158F
9/1/2015
RxyPPS
CCPx
CTS<2:0>
TRIS Control
LC4_out 111
LC3_out 110 CCPRxH CCPRxL
LC2_out 101 16
set CCPxIF
LC1_out 100 Prescaler and
IOC_interrupt 011 1,4,16 Edge Detect
16
C2OUT_sync 010
C1OUT_sync 001 MODE <3:0> TMR1H TMR1L
CCPx PPS 000
CCPxPPS

PIC16(L)F18857/77
30.1.2 TIMER1 MODE RESOURCE 30.1.5 CAPTURE DURING SLEEP
Timer1 must be running in Timer mode or Synchronized Capture mode depends upon the Timer1 module for
Counter mode for the CCP module to use the capture proper operation. There are two options for driving the
feature. In Asynchronous Counter mode, the capture Timer1 module in Capture mode. It can be driven by the
operation may not work. instruction clock (FOSC/4), or by an external clock source.
See Section 28.0 “Timer1/3/5 Module with Gate When Timer1 is clocked by FOSC/4, Timer1 will not
Control” for more information on configuring Timer1. increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
30.1.3 SOFTWARE INTERRUPT MODE
Capture mode will operate during Sleep when Timer1
When the Capture mode is changed, a false capture is clocked by an external clock source.
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIE6 register clear to 30.2 Compare Mode
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIR6 register The Compare mode function described in this section
following any change in Operating mode. is available and identical for all CCP modules.
Note: Clocking Timer1 from the system clock Compare mode makes use of the 16-bit Timer1
(FOSC) should not be used in Capture resource. The 16-bit value of the CCPRxH:CCPRxL
mode. In order for Capture mode to register pair is constantly compared against the 16-bit
recognize the trigger event on the CCPx value of the TMR1H:TMR1L register pair. When a
pin, Timer1 must be clocked from the match occurs, one of the following events can occur:
instruction clock (FOSC/4) or from an • Toggle the CCPx output
external clock source. • Set the CCPx output
• Clear the CCPx output
30.1.4 CCP PRESCALER
• Generate an Auto-conversion Trigger
There are four prescaler settings specified by the • Generate a Software Interrupt
CCPxMODE<3:0> bits of the CCPxCON register.
Whenever the CCP module is turned off, or the CCP The action on the pin is based on the value of the
module is not in Capture mode, the prescaler counter CCPxMODE<3:0> control bits of the CCPxCON
is cleared. Any Reset will clear the prescaler counter. register. At the same time, the interrupt flag CCPxIF bit
is set, and an ADC conversion can be triggered, if
Switching from one capture prescaler to another does not selected.
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by All Compare modes can generate an interrupt and
clearing the CCPxCON register before changing the trigger and ADC conversion.
prescaler. Example 30-1 demonstrates the code to Figure 30-2 shows a simplified diagram of the compare
perform this function. operation.
EXAMPLE 30-1: CHANGING BETWEEN FIGURE 30-2: COMPARE MODE

CAPTURE PRESCALERS OPERATION BLOCK
BANKSEL CCPxCON ;Set Bank bits to point DIAGRAM
;to CCPxCON
CCPxMODE<3:0>
CLRF CCPxCON ;Turn CCP module off Mode Select
MOVLW NEW_CAPT_PS ;Load the W reg with
;the new prescaler
Set CCPxIF Interrupt Flag
;move value and CCP ON (PIR6)
MOVWF CCPxCON ;Load CCPxCON with this CCPx 4
Pin CCPRxH CCPRxL
;value
Q S
Output Comparator
R Logic Match
TMR1H TMR1L
TRIS
Output Enable
Auto-conversion Trigger

PIC16(L)F18857/77
30.2.1 CCPX PIN CONFIGURATION 30.3 PWM Overview
The software must configure the CCPx pin as an output Pulse-Width Modulation (PWM) is a scheme that
by clearing the associated TRIS bit and defining the provides power to a load by switching quickly between
appropriate output pin through the RxyPPS registers. fully on and fully off states. The PWM signal resembles
See Section 13.0 “Peripheral Pin Select (PPS) a square wave where the high portion of the signal is
Module” for more details. considered the on state and the low portion of the signal
The CCP output can also be used as an input for other is considered the off state. The high portion, also known
peripherals. as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
Note: Clearing the CCPxCON register will force the load. Lowering the number of steps applied, which
the CCPx compare output latch to the shortens the pulse width, supplies less power. The
default low level. This is not the PORT I/O PWM period is defined as the duration of one complete
data latch. cycle or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
30.2.2 TIMER1 MODE RESOURCE
that can be present in a single PWM period. A higher
In Compare mode, Timer1 must be running in either resolution allows for more precise control of the pulse
Timer mode or Synchronized Counter mode. The width time and in turn the power that is applied to the
compare operation may not work in Asynchronous load.
Counter mode.
The term duty cycle describes the proportion of the on
See Section 28.0 “Timer1/3/5 Module with Gate time to the off time and is expressed in percentages,
Control” for more information on configuring Timer1. where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
Note: Clocking Timer1 from the system clock
duty cycle corresponds to more power applied.
(FOSC) should not be used in Compare
mode. In order for Compare mode to Figure 30-3 shows a typical waveform of the PWM
recognize the trigger event on the CCPx signal.
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an 30.3.1 STANDARD PWM OPERATION
external clock source. The standard PWM function described in this section is
available and identical for all CCP modules.
30.2.3 AUTO-CONVERSION TRIGGER
The standard PWM mode generates a Pulse-Width
All CCPx modes set the CCP interrupt flag (CCPxIF). Modulation (PWM) signal on the CCPx pin with up to
When this flag is set and a match occurs, an ten bits of resolution. The period, duty cycle, and
Auto-conversion Trigger can take place if the CCP resolution are controlled by the following registers:
module is selected as the conversion trigger source.
• PR2 registers
Refer to Section 23.2.6 “Auto-Conversion Trigger” • T2CON registers
for more information.
• CCPRxL registers
Note: Removing the match condition by • CCPxCON registers
changing the contents of the CCPRxH
Figure 30-4 shows a simplified block diagram of PWM
and CCPRxL register pair, between the
operation.
clock edge that generates the
Auto-conversion Trigger and the clock
edge that generates the Timer1 Reset, will Note: The corresponding TRIS bit must be
preclude the Reset from occurring cleared to enable the PWM output on the
CCPx pin.
30.2.4 COMPARE DURING SLEEP
Since FOSC is shut down during Sleep mode, the
FIGURE 30-3: CCP PWM OUTPUT SIGNAL
Compare mode will not function properly during Sleep,
unless the timer is running. The device will wake on Period
interrupt (if enabled).
Pulse Width
TMR2 = PR2
TMR2 = CCPRxH:CCPRxL
TMR2 = 0

PIC16(L)F18857/77
FIGURE 30-4: SIMPLIFIED PWM BLOCK DIAGRAM
Rev. 10-000 157C
Duty cycle registers 9/5/201 4
CCPRxH CCPRxL
CCPx_out
To Peripherals
set CCPIF
10-bit Latch(2)
(Not accessible by user)
Comparator R Q PPS CCPx
S RxyPPS
TMR2 Module TRIS Control
R
TMR2 (1)
ERS logic
Comparator CCPx_pset
PR2
30.3.2 SETUP FOR PWM OPERATION 6. Enable PWM output pin:

The following steps should be taken when configuring • Wait until the Timer overflows and the
the CCP module for standard PWM operation: TMR2IF bit of the PIR4 register is set. See
Note below.
1. Use the desired output pin RxyPPS control to
• Enable the CCPx pin output driver by
select CCPx as the source and disable the
clearing the associated TRIS bit.
CCPx pin output driver by setting the associated
TRIS bit. Note: In order to send a complete duty cycle and
2. Load the PR2 register with the PWM period period on the first PWM output, the above
value. steps must be included in the setup
sequence. If it is not critical to start with a
3. Configure the CCP module for the PWM mode
complete PWM signal on the first output,
by loading the CCPxCON register with the
then step 6 may be ignored.
appropriate values.
4. Load the CCPRxL register, and the CCPRxH
30.3.3 CCP/PWM CLOCK SELECTION
register with the PWM duty cycle value and
configure the CCPxFMT bit of the CCPxCON The PIC16F18857/77 allows each individual CCP and
register to set the proper register alignment. PWM module to select the timer source that controls
5. Configure and start Timer2: the module. Each module has an independent selec-
tion.
• Clear the TMR2IF interrupt flag bit of the
PIR4 register. See Note below. As there are up to three 8-bit timers with auto-reload
• Configure the T2CKPS bits of the T2CON (Timer2/4/6), PWM mode on the CCP and PWM mod-
register with the Timer prescale value. ules can use any of these timers. The CCPTMRS0 and
CCPTMRS1 registers is used to select which timer is
• Enable the Timer by setting the TMR2ON
used.
bit of the T2CON register.

PIC16(L)F18857/77
30.3.4 TIMER2 TIMER RESOURCE FIGURE 30-5: PWM 10-BIT ALIGNMENT
This device has a newer version of the TMR2 module Rev. 10-000 160A
that has many new modes, which allow for greater 12/9/201 3
customization and control of the PWM signals than on CCPRxH CCPRxL

older parts. Refer to Section 29.5, Operation Examples 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FMT = 0
for examples of PWM signal generation using the
different modes of Timer2. The CCP operation requires CCPRxH CCPRxL
that the timer used as the PWM time base has the FMT = 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
FOSC/4 clock source selected
30.3.5 PWM PERIOD 10-bit Duty Cycle

The PWM period is specified by the PR2/4/6 register of 9 8 7 6 5 4 3 2 1 0
Timer2/4/6. The PWM period can be calculated using
the formula of Equation 30-1.
EQUATION 30-1: PWM PERIOD EQUATION 30-2: PULSE WIDTH
PWM Period =   PR2  + 1   4  T OSC  Pulse Width =  CCPRxH:CCPRxL register pair  

(TMR2 Prescale Value) T OSC  (TMR2 Prescale Value)
Note 1: TOSC = 1/FOSC

EQUATION 30-3: DUTY CYCLE RATIO
When TMR2/4/6 is equal to PR2, the following three
events occur on the next increment cycle:
• TMR2/4/6 is cleared Duty Cycle Ratio = ---------------------------------------------------------------------------------
CCPRxH:CCPRxL register pair -
4  PR2 + 1 
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
CCPRxH:CCPRxL register pair are used to double
• The PWM duty cycle is transferred from the
buffer the PWM duty cycle. This double buffering is
CCPRxL/H register pair into a 10-bit buffer.
essential for glitchless PWM operation.
Note: The Timer postscaler (see Section 29.4 The 8-bit timer TMR2 register is concatenated with
“Timer2 Interrupt”) is not used in the either the 2-bit internal system clock (FOSC), or two bits
determination of the PWM frequency. of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
30.3.6 PWM DUTY CYCLE When the 10-bit time base matches the
The PWM duty cycle is specified by writing a 10-bit CCPRxH:CCPRxL register pair, then the CCPx pin is
value to the CCPRxH:CCPRxL register pair. The cleared (see Figure 30-4).
alignment of the 10-bit value is determined by the
CCPRxFMT bit of the CCPxCON register (see 30.3.7 PWM RESOLUTION
Figure 30-5). The CCPRxH:CCPRxL register pair can The resolution determines the number of available duty
be written to at any time; however the duty cycle value cycles for a given period. For example, a 10-bit resolution
is not latched into the 10-bit buffer until after a match will result in 1024 discrete duty cycles, whereas an 8-bit
between PR2 and TMR2. resolution will result in 256 discrete duty cycles.
Equation 30-2 is used to calculate the PWM pulse The maximum PWM resolution is ten bits when PR2 is
width. 255. The resolution is a function of the PR2 register
Equation 30-3 is used to calculate the PWM duty cycle value as shown by Equation 30-4.
ratio.
EQUATION 30-4: PWM RESOLUTION
log  4  PR2 + 1  - bits

Resolution = -----------------------------------------
log  2 
Note: If the pulse width value is greater than the

period the assigned PWM pin(s) will
remain unchanged.

PIC16(L)F18857/77

PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5
30.3.8 OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
30.3.9 CHANGES IN SYSTEM CLOCK

FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 6.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.
30.3.10 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.

PIC16(L)F18857/77
30.4 Register Definitions: CCP Control
Long bit name prefixes for the CCP peripherals are
shown in Section 1.1 “Register and Bit naming con-
ventions”.
FOR CCP PERIPHERALS
CCP1 CCP1
CCP2 CCP2
CCP3 CCP3
CCP4 CCP4
CCP5 CCP5
REGISTER 30-1: CCPxCON: CCPx CONTROL REGISTER

R/W-0/0 U-0 R-x R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
EN — OUT FMT MODE<3:0>
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
bit 7 EN: CCPx Module Enable bit

1 = CCPx is enabled
0 = CCPx is disabled
bit 5 OUT: CCPx Output Data bit (read-only)
bit 4 FMT: CCPW (Pulse Width) Alignment bit
MODE = Capture mode
Unused
MODE = Compare mode
Unused
MODE = PWM mode
1 = Left-aligned format
0 = Right-aligned format

PIC16(L)F18857/77
REGISTER 30-1: CCPxCON: CCPx CONTROL REGISTER (CONTINUED)
bit 3-0 MODE<3:0>: CCPx Mode Select bits(1)
1111 = PWM mode
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Compare mode: output will pulse 0-1-0; Clears TMR1

1010 = Compare mode: output will pulse 0-1-0
1001 = Compare mode: clear output on compare match
1000 = Compare mode: set output on compare match
0111 = Capture mode: every 16th rising edge of CCPx input

0110 = Capture mode: every 4th rising edge of CCPx input
0101 = Capture mode: every rising edge of CCPx input
0100 = Capture mode: every falling edge of CCPx input
0011 = Capture mode: every edge of CCPx input

0010 = Compare mode: toggle output on match
0001 = Compare mode: toggle output on match; clear TMR1
0000 = Capture/Compare/PWM off (resets CCPx module)
Note 1: All modes will set the CCPxIF bit, and will trigger an ADC conversion if CCPx is selected as the ADC
trigger source.

PIC16(L)F18857/77
REGISTER 30-2: CCPxCAP: CAPTURE INPUT SELECTION REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0/x R/W-0/x R/W-0/x
— — — — — CTS<2:0>
bit 7 bit 0
Legend:

bit 2-0 CTS<2:0>: Capture Trigger Input Selection bits
CTS CCP1.capture CCP2.capture CCP3.capture CCP4.capture CCP5.capture

111 LC4_out
110 LC3_out
101 LC2_out
100 LC1_out
011 IOC_interrupt
010 C2OUT
001 C1OUT
000 CCP1PPS CCP2PPS CCP3PPS CCP4PPS CCP5PPS
REGISTER 30-3: CCPRxL REGISTER: CCPx REGISTER LOW BYTE

CCPRx<7:0>
bit 7 bit 0
Legend:
bit 7-0 CCPxMODE = Capture mode

CCPRxL<7:0>: Capture value of TMR1L
CCPxMODE = Compare mode
CCPRxL<7:0>: LS Byte compared to TMR1L
CCPxMODE = PWM modes when CCPxFMT = 0:
CCPRxL<7:0>: Pulse-width Least Significant eight bits
CCPRxL<7:6>: Pulse-width Least Significant two bits
CCPRxL<5:0>: Not used.

PIC16(L)F18857/77
REGISTER 30-4: CCPRxH REGISTER: CCPx REGISTER HIGH BYTE
CCPRx<15:8>
bit 7 bit 0
Legend:
bit 7-0 CCPxMODE = Capture mode

CCPRxH<7:0>: Captured value of TMR1H
CCPxMODE = Compare mode
CCPRxH<7:0>: MS Byte compared to TMR1H
CCPRxH<7:2>: Not used
CCPRxH<1:0>: Pulse-width Most Significant two bits
CCPRxH<7:0>: Pulse-width Most Significant eight bits
REGISTER 30-5: CCPTMRS0: CCP TIMERS CONTROL 0 REGISTER

C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0>
bit 7 bit 0
Legend:
bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection

11 = CCP4 based on TMR5 (Capture/Compare) or TMR6 (PWM)
00 = Reserved
00 = Reserved
00 = Reserved
00 = Reserved

PIC16(L)F18857/77
REGISTER 30-6: CCPTMRS1: CCP TIMERS CONTROL 1 REGISTER
U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1
— — P7TSEL<1:0> P6TSEL<1:0> C5TSEL<1:0>
bit 7 bit 0
Legend:

bit 5-4 P7TSEL<1:0>: PWM7 Timer Selection
11 = PWM7 based on TMR6
00 = Reserved
bit 3-2 P6TSEL<1:0>: PWM6 Timer Selection
00 = Reserved
00 = Reserved

PIC16(L)F18857/77
TABLE 30-5: SUMMARY OF REGISTERS ASSOCIATED WITH CCPx

Register
on Page
CCP1CAP — — — — — CTS<2:0> 443
CCPR1L Capture/Compare/PWM Register 1 (LSB) 443
CCPR1H Capture/Compare/PWM Register 1 (MSB) 444
CCP2CAP — — — — CTS<2:0> 443
CCPR2L Capture/Compare/PWM Register 1 (LSB) 443
CCPR2H Capture/Compare/PWM Register 1 (MSB) 443
ADACT — — — ADACT<4:0> 350
CLCxSELy — — — LCxDyS<4:0> 320
CWG1ISM — — — — IS<3:0> 303
MDSRC — — — MDMS<4:0> 389
MDCARH — — — — MDCHS<3:0> 390
MDCARL — — — — MDCLS<3:0> 391
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the CCP module.

PIC16(L)F18857/77
31.0 HOST SYNCHRONOUS SERIAL
PORT (MSSP) MODULES
31.1 MSSP Module Overview
The Host Synchronous Serial Port (MSSP) module is a
serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The SPI interface supports the following modes and
features:
• Host mode
• Client mode
• Clock Parity
• Client Select Synchronization (Client mode only)
• Daisy-chain connection of client devices
Figure 31-1 is a block diagram of the SPI interface
module.
FIGURE 31-1: MSSP BLOCK DIAGRAM (SPI MODE)
Data Bus
Read Write
SSPxBUF Reg
SSPDATPPS
SDI
PPS SSPSR Reg
SDO bit 0 Shift
Clock
PPS
RxyPPS
SS SS Control 2 (CKP, CKE)

PPS Enable Clock Select
Edge
SSPSSPPS Select
SSPCLKPPS(2) SSPM<3:0>
SCK PPS
4
( T2_match
2
)
Edge Prescaler TOSC
PPS Select 4, 16, 64
TRIS bit RxyPPS(1) Baud Rate

Generator
(SSPxADD)
Note 1: Output selection for host mode
2: Input selection for client mode

PIC16(L)F18857/77
The I2C interface supports the following modes and
features:
Note 1: In devices with more than one MSSP
• Host mode module, it is very important to pay close
• Client mode attention to SSPxCONx register names.
• Byte NACKing (Client mode) SSPxCON1 and SSPxCON2 registers
• Limited multi-host support control different operational aspects of
the same module, while SSPxCON1 and
• 7-bit and 10-bit addressing
SSP2CON1 control the same features for
• Start and Stop interrupts two different modules.
• Interrupt masking
2: Throughout this section, generic refer-
• Clock stretching ences to an MSSPx module in any of its
• Bus collision detection operating modes may be interpreted as
• General call address matching being equally applicable to MSSPx or
• Address masking MSSP2. Register names, module I/O sig-
nals, and bit names may use the generic
• Address Hold and Data Hold modes
designator ‘x’ to indicate the use of a
• Selectable SDA hold times numeral to distinguish a particular module
Figure 31-2 is a block diagram of the I2C interface when required.
module in Host mode. Figure 31-3 is a diagram of the
I2C interface module in Client mode.
FIGURE 31-2: MSSP BLOCK DIAGRAM (I2C HOST MODE)
Internal
data bus [SSPM<3:0>]
SSPDATPPS(1) Read Write
SDA
SDA in
PPS SSPxBUF Baud Rate
Generator
(SSPxADD)
Shift
RxyPPS(1) Clock
Clock arbitrate/BCOL detect

SSPSR
Clock Cntl
(Hold off clock source)

PPS MSb LSb
Receive Enable (RCEN)
Start bit, Stop bit,

Acknowledge
SSPCLKPPS(2) Generate (SSPxCON2)
SCL
PPS
PPS
Start bit detect,

RxyPPS(2) Stop bit detect
Write collision detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV
SCL in
Clock arbitration Reset SEN, PEN (SSPxCON2)
State counter for Set SSPxIF, BCL1IF
Bus Collision end of XMIT/RCV
Address Match detect
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output

PIC16(L)F18857/77
FIGURE 31-3: MSSP BLOCK DIAGRAM (I2C CLIENT MODE)
Internal
Data Bus
Read Write
SSPCLKPPS(2) SSPxBUF Reg

SCL
PPS
Shift
Clock
Clock
PPS Stretching SSPSR Reg
MSb LSb
RxyPPS(2)
SSPxMSK Reg
(1)
SSPDATPPS
SDA Match Detect Addr Match
PPS
SSPxADD Reg
PPS
Start and Set, Reset
RxyPPS(1) Stop bit Detect S, P bits
(SSPxSTAT Reg)
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output

PIC16(L)F18857/77
31.2 SPI Mode Overview During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the host
The Serial Peripheral Interface (SPI) bus is a device is sending out the MSb from its shift register (on
synchronous serial data communication bus that its SDO pin) and the client device is reading this bit and
operates in Full-Duplex mode. Devices communicate saving it as the LSb of its shift register, that the client
in a host/client environment where the host device device is also sending out the MSb from its shift register
initiates the communication. A client device is (on its SDO pin) and the host device is reading this bit
controlled through a Chip Select known as Client and saving it as the LSb of its shift register.
Select.
After eight bits have been shifted out, the host and cli-
The SPI bus specifies four signal connections: ent have exchanged register values.
• Serial Clock (SCK) If there is more data to exchange, the shift registers are
• Serial Data Out (SDO) loaded with new data and the process repeats itself.
• Serial Data In (SDI) Whether the data is meaningful or not (dummy data),
• Client Select (CS) depends on the application software. This leads to
Figure 31-1 shows the block diagram of the MSSP three scenarios for data transmission:
module when operating in SPI mode. • Host sends useful data and client sends dummy
The SPI bus operates with a single host device and one data.
or more client devices. When multiple client devices • Host sends useful data and client sends useful
are used, an independent Client Select connection is data.
required from the host device to each client device. • Host sends dummy data and client sends useful
Figure 31-4 shows a typical connection between a host data.
device and multiple client devices. Transmissions may involve any number of clock
The host selects only one client at a time. Most client cycles. When there is no more data to be transmitted,
devices have tri-state outputs so their output signal the host stops sending the clock signal and it deselects
appears disconnected from the bus when they are not the client.
selected. Every client device connected to the bus that has not
Transmissions involve two shift registers, eight bits in been selected through its client select line must disre-
size, one in the host and one in the client. With either gard the clock and transmission signals and must not
the host or the client device, data is always shifted out transmit out any data of its own.
one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 31-5 shows a typical connection between two
processors configured as host and client devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The host device transmits information out on its SDO
output pin which is connected to, and received by, the
client’s SDI input pin. The client device transmits infor-
mation out on its SDO output pin, which is connected
to, and received by, the host’s SDI input pin.
To begin communication, the host device first sends out
the clock signal. Both the host and the client devices
should be configured for the same clock polarity.
The host device starts a transmission by sending out
the MSb from its shift register. The client device reads
this bit from that same line and saves it into the LSb
position of its shift register.

PIC16(L)F18857/77
FIGURE 31-4: SPI HOST AND MULTIPLE CLIENT CONNECTION
SCK SCK
SPI Host
SDO SDI SPI Client
SDI SDO #1
General I/O SS
General I/O
General I/O SCK
SDI SPI Client
SDO #2
SS
SCK
SDI SPI Client
SDO #3
SS
31.2.1 SPI MODE REGISTERS

The MSSP module has five registers for SPI mode
operation. These are:
• MSSP STATUS register (SSPxSTAT)
• MSSP Control register 1 (SSPxCON1)
• MSSP Control register 3 (SSPxCON3)
• MSSP Data Buffer register (SSPxBUF)
• MSSP Address register (SSPxADD)
• MSSP Shift register (SSPxSR)
(Not directly accessible)
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower six bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
In one SPI host mode, SSPxADD can be loaded with a
value used in the Baud Rate Generator. More informa-
tion on the Baud Rate Generator is available in
Section 31.7 “Baud Rate Generator”.
SSPxSR is the shift register used for shifting data in
and out. SSPxBUF provides indirect access to the
SSPxSR register. SSPxBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSPxSR and SSPxBUF
together create a buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not buffered. A
write to SSPxBUF will write to both SSPxBUF and
SSPxSR.

PIC16(L)F18857/77
31.2.2 SPI MODE OPERATION The MSSP consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
When initializing the SPI, several options need to be SSPxSR shifts the data in and out of the device, MSb first.
specified. This is done by programming the appropriate The SSPxBUF holds the data that was written to the
control bits (SSPxCON1<3:0> and SSPxSTAT<7:6>). SSPxSR until the received data is ready. Once the eight
These control bits allow the following to be specified: bits of data have been received, that byte is moved to the
• Host mode (SCK is the clock output) SSPxBUF register. Then, the Buffer Full Detect bit, BF of
• Client mode (SCK is the clock input) the SSPxSTAT register, and the interrupt flag bit, SSPxIF,
• Clock Polarity (Idle state of SCK) are set. This double-buffering of the received data
(SSPxBUF) allows the next byte to start reception before
• Data Input Sample Phase (middle or end of data
reading the data that was just received. Any write to the
output time)
SSPxBUF register during transmission/reception of data
• Clock Edge (output data on rising/falling edge of will be ignored and the write collision detect bit WCOL of
SCK) the SSPxCON1 register, will be set. User software must
• Clock Rate (Host mode only) clear the WCOL bit to allow the following write(s) to the
• Client Select mode (Client mode only) SSPxBUF register to complete successfully.
To enable the serial port, SSP Enable bit, SSPEN of the When the application software is expecting to receive
SSPxCON1 register, must be set. To reset or reconfig- valid data, the SSPxBUF should be read before the next
ure SPI mode, clear the SSPEN bit, re-initialize the byte of data to transfer is written to the SSPxBUF. The
SSPxCONx registers and then set the SSPEN bit. This Buffer Full bit, BF of the SSPxSTAT register, indicates
configures the SDI, SDO, SCK and SS pins as serial port when SSPxBUF has been loaded with the received data
pins. For the pins to behave as the serial port function, (transmission is complete). When the SSPxBUF is read,
some must have their data direction bits (in the TRISx the BF bit is cleared. This data may be irrelevant if the
register) appropriately programmed as follows: SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
• SDI must have corresponding TRIS bit set
has completed. If the interrupt method is not going to be
• SDO must have corresponding TRIS bit cleared used, then software polling can be done to ensure that a
• SCK (Host mode) must have corresponding TRIS write collision does not occur.
bit cleared
The SSPxSR is not directly readable or writable and
• SCK (Client mode) must have corresponding can only be accessed by addressing the SSPxBUF
TRIS bit set register. Additionally, the SSPxSTAT register indicates
• SS must have corresponding TRIS bit set the various Status conditions.
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 31-5: SPI HOST/CLIENT CONNECTION
SPI Host SSPM<3:0> = 00xx SPI Client SSPM<3:0> = 010x

= 1010
SDO SDI
Serial Input Buffer Serial Input Buffer

(SSPxBUF) (SSPxBUF)
Shift Register SDI SDO Shift Register

(SSPxSR) (SSPxSR)
MSb LSb MSb LSb
Serial Clock
SCK SCK
Client Select
General I/O SS
Processor 1 (optional) Processor 2

PIC16(L)F18857/77
31.2.3 SPI HOST MODE The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
The host can initiate the data transfer at any time
and the CKE bit of the SSPxSTAT register. This then,
because it controls the SCK line. The host determines
would give waveforms for SPI communication as
when the client (Processor 2, Figure 31-5) is to
shown in Figure 31-6, Figure 31-8, Figure 31-9 and
broadcast data by the software protocol.
Figure 31-10, where the MSB is transmitted first. In
In Host mode, the data is transmitted/received as soon Host mode, the SPI clock rate (bit rate) is user
as the SSPxBUF register is written to. If the SPI is only programmable to be one of the following:
going to receive, the SDO output could be disabled
• FOSC/4 (or TCY)
(programmed as an input). The SSPxSR register will
continue to shift in the signal present on the SDI pin at • FOSC/16 (or 4 * TCY)
the programmed clock rate. As each byte is received, it • FOSC/64 (or 16 * TCY)
will be loaded into the SSPxBUF register as if a normal • Timer2 output/2
received byte (interrupts and Status bits appropriately • FOSC/(4 * (SSPxADD + 1))
set).
Figure 31-6 shows the waveforms for Host mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
FIGURE 31-6: SPI MODE WAVEFORM (HOST MODE)
Write to
SSPxBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 7 bit 0
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF

PIC16(L)F18857/77
31.2.4 SPI CLIENT MODE 31.2.5 CLIENT SELECT
In Client mode, the data is transmitted and received as SYNCHRONIZATION
external clock pulses appear on SCK. When the last The Client Select can also be used to synchronize
bit is latched, the SSPxIF interrupt flag bit is set. communication. The Client Select line is held high until
Before enabling the module in SPI Client mode, the clock the host device is ready to communicate. When the Cli-
line must match the proper Idle state. The clock line can ent Select line is pulled low, the client knows that a new
be observed by reading the SCK pin. The Idle state is transmission is starting.
determined by the CKP bit of the SSPxCON1 register. If the client fails to receive the communication properly,
While in Client mode, the external clock is supplied by it will be reset at the end of the transmission, when the
the external clock source on the SCK pin. This external Client Select line returns to a high state. The client is
clock must meet the minimum high and low times as then ready to receive a new transmission when the Cli-
specified in the electrical specifications. ent Select line is pulled low again. If the Client Select
line is not used, there is a risk that the client will
While in Sleep mode, the client can transmit/receive
eventually become out of sync with the host. If the cli-
data. The shift register is clocked from the SCK pin
ent misses a bit, it will always be one bit off in future
input and when a byte is received, the device will
transmissions. Use of the Client Select line allows the
generate an interrupt. If enabled, the device will
client and host to align themselves at the beginning of
wake-up from Sleep.
each transmission.
31.2.4.1 Daisy-Chain Configuration The SS pin allows a Synchronous Client mode. The
SPI must be in Client mode with SS pin control enabled
The SPI bus can sometimes be connected in a
(SSPxCON1<3:0> = 0100).
daisy-chain configuration. The first client output is
connected to the second client input, the second client When the SS pin is low, transmission and reception are
output is connected to the third client input, and so on. enabled and the SDO pin is driven.
The final client output is connected to the host input. When the SS pin goes high, the SDO pin is no longer
Each client sends out, during a second group of clock driven, even if in the middle of a transmitted byte and
pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down
first group of clock pulses. The whole chain acts as resistors may be desirable depending on the applica-
one large communication shift register. The tion.
daisy-chain feature only requires a single Client Select
line from the host device. Note 1: When the SPI is in Client mode with SS
pin control enabled (SSPxCON1<3:0> =
Figure 31-7 shows the block diagram of a typical
0100), the SPI module will reset if the SS
daisy-chain connection when operating in SPI mode.
pin is set to VDD.
In a daisy-chain configuration, only the most recent
2: When the SPI is used in Client mode with
byte on the bus is required by the client. Setting the
CKE set; the user must enable SS pin
BOEN bit of the SSPxCON3 register will enable writes
control.
to the SSPxBUF register, even if the previous byte has
not been read. This allows the software to ignore data 3: While operated in SPI Client mode the
that may not apply to it. SMP bit of the SSPxSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.

PIC16(L)F18857/77
FIGURE 31-7: SPI DAISY-CHAIN CONNECTION
SCK SCK
SPI Host
SDO SDI SPI Client
SDI SDO #1
General I/O SS
SCK
SDI SPI Client
SDO #2
SS
SCK
SDI SPI Client
SDO #3
SS
FIGURE 31-8: CLIENT SELECT SYNCHRONOUS WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPxSR
and bit count are reset
SSPxBUF to
SSPxSR
SDO bit 7 bit 6 bit 7 bit 6 bit 0
SDI bit 0
bit 7 bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF

PIC16(L)F18857/77
FIGURE 31-9: SPI MODE WAVEFORM (CLIENT MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDI
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
FIGURE 31-10: SPI MODE WAVEFORM (CLIENT MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDI
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active

PIC16(L)F18857/77
31.2.6 SPI OPERATION IN SLEEP MODE There are four potential modes of operation for a given
device:
In SPI Host mode, module clocks may be operating at
a different speed than when in Full-Power mode; in the • Host Transmit mode
case of the Sleep mode, all clocks are halted. (host is transmitting data to a client)
• Host Receive mode
Special care must be taken by the user when the MSSP
(host is receiving data from a client)
clock is much faster than the system clock.
• Client Transmit mode
In Client mode, when MSSP interrupts are enabled, (client is transmitting data to a host)
after the host completes sending data, an MSSP inter-
• Client Receive mode
rupt will wake the controller from Sleep.
(client is receiving data from the host)
If an exit from Sleep mode is not desired, MSSP
To begin communication, a host device starts out in
interrupts should be disabled.
Host Transmit mode. The host device sends out a Start
In SPI Host mode, when the Sleep mode is selected, all bit followed by the address byte of the client it intends
module clocks are halted and the transmission/recep- to communicate with. This is followed by a single
tion will remain in that state until the device wakes. Read/Write bit, which determines whether the host
After the device returns to Run mode, the module will intends to transmit to or receive data from the client
resume transmitting and receiving data. device.
In SPI Client mode, the SPI Transmit/Receive Shift If the requested client exists on the bus, it will respond
register operates asynchronously to the device. This with an Acknowledge bit, otherwise known as an ACK.
allows the device to be placed in Sleep mode and data The host then continues in either Transmit mode or
to be shifted into the SPI Transmit/Receive Shift Receive mode and the client continues in the comple-
register. When all eight bits have been received, the ment, either in Receive mode or Transmit mode,
MSSP interrupt flag bit will be set and if enabled, will respectively.
wake the device.
A Start bit is indicated by a high-to-low transition of the
31.3 I2C MODE OVERVIEW SDA line while the SCL line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Inter-Integrated Circuit (I2C) bus is a multi-host The Read/Write bit is sent out as a logical one when the
serial data communication bus. Devices communicate host intends to read data from the client, and is sent out
in a host/client environment where the host devices ini- as a logical zero when it intends to write data to the cli-
tiate the communication. A client device is controlled ent.
through addressing.
The I2C bus specifies two signal connections: FIGURE 31-11: I2C HOST/
CLIENT CONNECTION
• Serial Clock (SCL)
• Serial Data (SDA)
VDD
Figure 31-11 shows the block diagram of the MSSP
module when operating in I2C mode.
Both the SCL and SDA connections are bidirectional SCL SCL
open-drain lines, each requiring pull-up resistors for the VDD
supply voltage. Pulling the line to ground is considered Host Client
a logical zero and letting the line float is considered a
logical one. SDA SDA
Figure 31-11 shows a typical connection between two
processors configured as host and client devices.
The I2C bus can operate with one or more host devices The Acknowledge bit (ACK) is an active-low signal,
and one or more client devices. which holds the SDA line low to indicate to the transmit-
ter that the client device has received the transmitted
data and is ready to receive more.
The transition of a data bit is always performed while
the SCL line is held low. Transitions that occur while the
SCL line is held high are used to indicate Start and Stop
bits.

PIC16(L)F18857/77
If the host intends to write to the client, then it repeat- 31.3.2 ARBITRATION
edly sends out a byte of data, with the client responding
Each host device must monitor the bus for Start and
after each byte with an ACK bit. In this example, the
Stop bits. If the device detects that the bus is busy, it
host device is in Host Transmit mode and the client is
cannot begin a new message until the bus returns to an
in Client Receive mode.
Idle state.
If the host intends to read from the client, then it repeat-
However, two host devices may try to initiate a trans-
edly receives a byte of data from the client, and
mission on or about the same time. When this occurs,
responds after each byte with an ACK bit. In this exam-
the process of arbitration begins. Each transmitter
ple, the host device is in Host Receive mode and the
checks the level of the SDA data line and compares it
client is Client Transmit mode.
to the level that it expects to find. The first transmitter to
On the last byte of data communicated, the host device observe that the two levels do not match, loses arbitra-
may end the transmission by sending a Stop bit. If the tion, and must stop transmitting on the SDA line.
host device is in Receive mode, it sends the Stop bit in
For example, if one transmitter holds the SDA line to a
place of the last ACK bit. A Stop bit is indicated by a
logical one (lets it float) and a second transmitter holds
low-to-high transition of the SDA line while the SCL line
it to a logical zero (pulls it low), the result is that the
is held high.
SDA line will be low. The first transmitter then observes
In some cases, the host may want to maintain control that the level of the line is different than expected and
of the bus and re-initiate another transmission. If so, concludes that another transmitter is communicating.
the host device may send another Start bit in place of
The first transmitter to notice this difference is the one
the Stop bit or last ACK bit when it is in receive mode.
that loses arbitration and must stop driving the SDA
The I2C bus specifies three message protocols; line. If this transmitter is also a host device, it also must
• Single message where a host writes data to a cli- stop driving the SCL line. It then can monitor the lines
ent. for a Stop condition before trying to reissue its trans-
mission. In the meantime, the other device that has not
• Single message where a host reads data from a
noticed any difference between the expected and
client.
actual levels on the SDA line continues with its original
• Combined message where a host initiates a transmission. It can do so without any complications,
minimum of two writes, or two reads, or a because so far, the transmission appears exactly as
combination of writes and reads, to one or more expected with no other transmitter disturbing the mes-
clients. sage.
When one device is transmitting a logical one, or letting Client Transmit mode can also be arbitrated, when a
the line float, and a second device is transmitting a log- host addresses multiple clients, but this is less
ical zero, or holding the line low, the first device can common.
detect that the line is not a logical one. This detection,
when used on the SCL line, is called clock stretching. If two host devices are sending a message to two
Clock stretching gives client devices a mechanism to different client devices at the address stage, the host
control the flow of data. When this detection is used on sending the lower client address always wins arbitra-
the SDA line, it is called arbitration. Arbitration ensures tion. When two host devices send messages to the
that there is only one host device communicating at any same client address, and addresses can sometimes
single time. refer to multiple clients, the arbitration process must
continue into the data stage.
31.3.1 CLOCK STRETCHING Arbitration usually occurs very rarely, but it is a
When a client device has not completed processing necessary process for proper multi-host support.
data, it can delay the transfer of more data through the
process of clock stretching. An addressed client device
may hold the SCL clock line low after receiving or send-
ing a bit, indicating that it is not yet ready to continue.
The host that is communicating with the client will
attempt to raise the SCL line in order to transfer the
next bit, but will detect that the clock line has not yet
been released. Because the SCL connection is
open-drain, the client has the ability to hold that line low
until it is ready to continue communicating.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.

PIC16(L)F18857/77
31.4 I2C MODE OPERATION TABLE 31-1: I2C BUS TERMS
TERM Description
All MSSP I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and two Transmitter The device which shifts data out
interrupt flags interface the module with the PIC® onto the bus.
microcontroller and user software. Two pins, SDA and Receiver The device which shifts data in
SCL, are exercised by the module to communicate from the bus.
with other external I2C devices. Host The device that initiates a transfer,
31.4.1 BYTE FORMAT generates clock signals and termi-
nates a transfer.
All communication in I2C is done in 9-bit segments. A Client The device addressed by the host.
byte is sent from a host to a client or vice-versa, fol- Multi-host A bus with more than one device
lowed by an Acknowledge bit sent back. After the that can initiate data transfers.
eighth falling edge of the SCL line, the device output-
Arbitration Procedure to ensure that only one
ting data on the SDA changes that pin to an input and
host at a time controls the bus.
reads in an acknowledge value on the next clock
Winning arbitration ensures that
pulse.
the message is not corrupted.
The clock signal, SCL, is provided by the host. Data is Synchronization Procedure to synchronize the
valid to change while the SCL signal is low, and sam- clocks of two or more devices on
pled on the rising edge of the clock. Changes on the the bus.
SDA line while the SCL line is high define special con-
Idle No host is controlling the bus, and
ditions on the bus, explained below.
both SDA and SCL lines are high.
31.4.2 DEFINITION OF I2C TERMINOLOGY Active Any time one or more host devices
are controlling the bus.
There is language and terminology in the description
of I2C communication that have definitions specific to Addressed Cli- Client device that has received a
I2C. That word usage is defined below and may be ent matching address and is actively
used in the rest of this document without explanation. being clocked by a host.
This table was adapted from the Philips I2C Matching Address byte that is clocked into a
specification. Address client that matches the value
stored in SSPxADD.
31.4.3 SDA AND SCL PINS Write Request Client receives a matching
Selection of any I2C mode with the SSPEN bit set, address with R/W bit clear, and is
forces the SCL and SDA pins to be open-drain. These ready to clock in data.
pins should be set by the user to inputs by setting the Read Request Host sends an address byte with
appropriate TRIS bits. the R/W bit set, indicating that it
wishes to clock data out of the Cli-
Note 1: Data is tied to output zero when an I2C ent. This data is the next and all
mode is enabled. following bytes until a Restart or
2: Any device pin can be selected for SDA Stop.
and SCL functions with the PPS peripheral. Clock Stretching When a device on the bus hold
These functions are bidirectional. The SDA SCL low to stall communication.
input is selected with the SSPDATPPS Bus Collision Any time the SDA line is sampled
registers. The SCL input is selected with low by the module while it is out-
the SSPCLKPPS registers. Outputs are putting and expected high state.
selected with the RxyPPS registers. It is the
user’s responsibility to make the selections
so that both the input and the output for
each function is on the same pin.
31.4.4 SDA HOLD TIME
The hold time of the SDA pin is selected by the SDAHT

bit of the SSPxCON3 register. Hold time is the time
SDA is held valid after the falling edge of SCL. Setting
the SDAHT bit selects a longer 300 ns minimum hold
time and may help on buses with large capacitance.

PIC16(L)F18857/77
31.4.5 START CONDITION 31.4.7 RESTART CONDITION
The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid.
transition of SDA from a high to a low state while SCL A host can issue a Restart if it wishes to hold the bus
line is high. A Start condition is always generated by after terminating the current transfer. A Restart has the
the host and signifies the transition of the bus from an same effect on the client that a Start would, resetting
Idle to an Active state. Figure 31-12 shows wave all client logic and preparing it to clock in an address.
forms for Start and Stop conditions. The host may want to address the same or another cli-
A bus collision can occur on a Start condition if the ent. Figure 31-13 shows the wave form for a Restart
module samples the SDA line low before asserting it condition.
low. This does not conform to the I2C Specification that In 10-bit Addressing Client mode a Restart is required
states no bus collision can occur on a Start. for the host to clock data out of the addressed client.
Once a client has been fully addressed, matching both
31.4.6 STOP CONDITION high and low address bytes, the host can issue a
A Stop condition is a transition of the SDA line from Restart and the high address byte with the R/W bit set.
low-to-high state while the SCL line is high. The client logic will then hold the clock and prepare to
clock out data.
Note: At least one SCL low time must appear
After a full match with R/W clear in 10-bit mode, a prior
before a Stop is valid, therefore, if the SDA
match flag is set and maintained until a Stop condition, a
line goes low then high again while the SCL
high address with R/W clear, or high address match fails.
line stays high, only the Start condition is
detected. 31.4.8 START/STOP CONDITION INTERRUPT
MASKING
The SCIE and PCIE bits of the SSPxCON3 register

can enable the generation of an interrupt in Client
modes that do not typically support this function. Client
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
FIGURE 31-12: I2C START AND STOP CONDITIONS
SDA
SCL
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition
FIGURE 31-13: I2C RESTART CONDITION
Sr
Change of Change of
Data Allowed Data Allowed
Restart
Condition

PIC16(L)F18857/77
31.4.9 ACKNOWLEDGE SEQUENCE 31.5 I2C CLIENT MODE OPERATION
The 9th SCL pulse for any transferred byte in I2C is The MSSP Client mode operates in one of four modes
dedicated as an Acknowledge. It allows receiving selected by the SSPM bits of SSPxCON1 register. The
devices to respond back to the transmitter by pulling modes can be divided into 7-bit and 10-bit Addressing
the SDA line low. The transmitter must release control mode. 10-bit Addressing modes operate the same as
of the line during this time to shift in the response. The 7-bit with some additional overhead for handling the
Acknowledge (ACK) is an active-low signal, pulling the larger addresses.
SDA line low indicates to the transmitter that the
device has received the transmitted data and is ready Modes with Start and Stop bit interrupts operate the
to receive more. same as the other modes with SSPxIF additionally
getting set upon detection of a Start, Restart, or Stop
The result of an ACK is placed in the ACKSTAT bit of condition.
the SSPxCON2 register.
31.5.1 CLIENT MODE ADDRESSES
Client software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to The SSPxADD register (Register 31-6) contains the
the transmitter. The ACKDT bit of the SSPxCON2 Client mode address. The first byte received after a
register is set/cleared to determine the response. Start or Restart condition is compared against the
Client hardware will generate an ACK response if the value stored in this register. If the byte matches, the
AHEN and DHEN bits of the SSPxCON3 register are value is loaded into the SSPxBUF register and an
clear. interrupt is generated. If the value does not match, the
module goes idle and no indication is given to the
There are certain conditions where an ACK will not be
software that anything happened.
sent by the client. If the BF bit of the SSPxSTAT regis-
ter or the SSPOV bit of the SSPxCON1 register are The SSP Mask register (Register 31-5) affects the
set when a byte is received. address matching process. See Section 31.5.9 “SSP
Mask Register” for more information.
When the module is addressed, after the eighth falling
edge of SCL on the bus, the ACKTIM bit of the SSPx- 31.5.1.1 I2C Client 7-bit Addressing Mode
CON3 register is set. The ACKTIM bit indicates the
acknowledge time of the active bus. The ACKTIM Sta- In 7-bit Addressing mode, the LSb of the received data
tus bit is only active when the AHEN bit or DHEN bit is byte is ignored when determining if there is an address
enabled. match.
31.5.1.2 I2C Client 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb’s of the 10-bit address and
stored in bits 2 and 1 of the SSPxADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPxADD
with the low address. The low address byte is clocked
in and all eight bits are compared to the low address
value in SSPxADD. Even if there is not an address
match; SSPxIF and UA are set, and SCL is held low
until SSPxADD is updated to receive a high byte
again. When SSPxADD is updated the UA bit is
cleared. This ensures the module is ready to receive
the high address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the client is addressed, and clocking in
the high address with the R/W bit set. The client
hardware will then acknowledge the read request and
prepare to clock out data. This is only valid for a client
after it has received a complete high and low address
byte match.

PIC16(L)F18857/77
31.5.2 CLIENT RECEPTION 31.5.2.2 7-bit Reception with AHEN and DHEN
When the R/W bit of a matching received address byte Client device reception with AHEN and DHEN set
is clear, the R/W bit of the SSPxSTAT register is operate the same as without these options with extra
cleared. The received address is loaded into the interrupts and clock stretching added after the eighth
SSPxBUF register and acknowledged. falling edge of SCL. These additional interrupts allow
When the overflow condition exists for a received the client software to decide whether it wants to ACK
address, then not Acknowledge is given. An overflow the receive address or data byte, rather than the hard-
condition is defined as either bit BF of the SSPxSTAT ware. This functionality adds support for PMBus™ that
register is set, or bit SSPOV of the SSPxCON1 register was not present on previous versions of this module.
is set. The BOEN bit of the SSPxCON3 register modi- This list describes the steps that need to be taken by
fies this operation. For more information see client software to use these options for I2C communi-
Register 31-4. cation. Figure 31-16 displays a module using both
An MSSP interrupt is generated for each transferred address and data holding. Figure 31-17 includes the
data byte. Flag bit, SSPxIF, must be cleared by operation with the SEN bit of the SSPxCON2 register
software. set.
When the SEN bit of the SSPxCON2 register is set, 1. S bit of SSPxSTAT is set; SSPxIF is set if
SCL will be held low (clock stretch) following each interrupt on Start detect is enabled.
received byte. The clock must be released by setting 2. Matching address with R/W bit clear is clocked
the CKP bit of the SSPxCON1 register, except in. SSPxIF is set and CKP cleared after the
sometimes in 10-bit mode. See Section 31.5.6.2 eighth falling edge of SCL.
“10-bit Addressing Mode” for more detail. 3. Client clears the SSPxIF.
4. Client can look at the ACKTIM bit of the
31.5.2.1 7-bit Addressing Reception
SSPxCON3 register to determine if the SSPxIF
This section describes a standard sequence of events was after or before the ACK.
for the MSSP module configured as an I2C client in 5. Client reads the address value from SSPxBUF,
7-bit Addressing mode. Figure 31-14 and Figure 31-15 clearing the BF flag.
is used as a visual reference for this description. 6. Client sets ACK value clocked out to the host by
This is a step by step process of what typically must setting ACKDT.
be done to accomplish I2C communication. 7. Client releases the clock by setting CKP.
1. Start bit detected. 8. SSPxIF is set after an ACK, not after a NACK.
2. S bit of SSPxSTAT is set; SSPxIF is set if 9. If SEN = 1 the client hardware will stretch the
interrupt on Start detect is enabled. clock after the ACK.
3. Matching address with R/W bit clear is received. 10. Client clears SSPxIF.
4. The client pulls SDA low sending an ACK to the Note: SSPxIF is still set after the ninth falling edge
host, and sets SSPxIF bit. of SCL even if there is no clock stretching
5. Software clears the SSPxIF bit. and BF has been cleared. Only if NACK is
6. Software reads received address from sent to host is SSPxIF not set
SSPxBUF clearing the BF flag. 11. SSPxIF set and CKP cleared after eighth falling
7. If SEN = 1; Client software sets CKP bit to edge of SCL for a received data byte.
release the SCL line.
12. Client looks at ACKTIM bit of SSPxCON3 to
8. The host clocks out a data byte. determine the source of the interrupt.
9. Client drives SDA low sending an ACK to the 13. Client reads the received data from SSPxBUF
host, and sets SSPxIF bit. clearing BF.
10. Software clears SSPxIF. 14. Steps 7-14 are the same for each received data
11. Software reads the received byte from byte.
SSPxBUF clearing BF. 15. Communication is ended by either the client
12. Steps 8-12 are repeated for all received bytes sending an ACK = 1, or the host sending a Stop
from the host. condition. If a Stop is sent and Interrupt on Stop
13. Host sends Stop condition, setting P bit of SSPx- Detect is disabled, the client will only know by
STAT, and the bus goes idle. polling the P bit of the SSPxSTAT register.

FIGURE 31-14:
Bus Host sends

Stop condition
From Client to Host

Receiving Address Receiving Data Receiving Data ACK = 1
SDA
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
PIC16(L)F18857/77
S P
SSPxIF
SSPxIF set on 9th
Cleared by software Cleared by software falling edge of
SCL
BF
First byte
SSPxBUF is read of data is
available
in SSPxBUF
SSPOV
SSPOV set because

SSPxBUF is still full.
ACK is not sent.
I2C CLIENT, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
DS40001825F-page 463
FIGURE 31-15:
Bus Host sends

Stop condition
Receive Address Receive Data Receive Data ACK

SDA A7 A6 A5 A4 A3 A2 A1 R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL S 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 P
Clock is held low until CKP is set to ‘1’

PIC16(L)F18857/77
SSPxIF
SSPxIF set on 9th

Cleared by software Cleared by software falling edge of SCL
BF
First byte
of data is
SSPxBUF is read available
in SSPxBUF
SSPOV
SSPOV set because

SSPxBUF is still full.
ACK is not sent.
CKP
SCL is not held

CKP is written to ‘1’ in software, CKP is written to ‘1’ in software,
low because
releasing SCL releasing SCL
ACK= 1
DS40001825F-page 464
Host Releases SDA Host sends
to client for ACK sequence Stop condition
FIGURE 31-16:
SDA Receiving Address Receiving Data ACK Received Data ACK=1

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

SSPxIF
If AHEN = 1: SSPxIF is set on
SSPxIF is set 9th falling edge of Cleared by software No interrupt
SCL, after ACK after not ACK
BF from Client
PIC16(L)F18857/77
Address is
read from Data is read from SSPxBUF
ACKDT SSPxBUF
Client software
clears ACKDT to Client software
ACK the received sets ACKDT to
CKP byte not ACK
When AHEN = 1:
When DHEN = 1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCL is released
and SCL is stretched hardware on 8th falling
edge of SCL
ACKTIM
ACKTIM set by hardware ACKTIM cleared by ACKTIM set by hardware

on 8th falling edge of SCL hardware in 9th on 8th falling edge of SCL
rising edge of SCL
P
DS40001825F-page 465
Host sends
FIGURE 31-17:
Stop condition
Host releases
R/W = 0 SDA to client for ACK sequence
Receiving Address Receive Data Receive Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

S
SSPxIF
Cleared by software No interrupt after
if not ACK
PIC16(L)F18857/77
from Client
BF
Received
address is loaded into Received data is SSPxBUF can be
SSPxBUF available on SSPxBUF read any time before
next byte is loaded
ACKDT
Client software clears

Client sends
ACKDT to ACK not ACK
the received byte
CKP
When AHEN = 1; When DHEN = 1; CKP is not cleared
on the 8th falling edge on the 8th falling edge Set by software, if not ACK
of SCL of an address of SCL of a received release SCL
byte, CKP is cleared data byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware ACKTIM is cleared by hardware

on 8th falling edge of SCL on 9th rising edge of SCL
P
DS40001825F-page 466
PIC16(L)F18857/77
31.5.3 CLIENT TRANSMISSION 31.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set A host device can transmit a read request to a client,
and an address match occurs, the R/W bit of the and then clock data out of the client. The list below
SSPxSTAT register is set. The received address is outlines what software for a client will need to do to
loaded into the SSPxBUF register, and an ACK pulse is accomplish a standard transmission. Figure 31-18 can
sent by the client on the ninth bit. be used as a reference to this list.
Following the ACK, client hardware clears the CKP bit 1. Host sends a Start condition on SDA and SCL.
and the SCL pin is held low (see Section 31.5.6 2. S bit of SSPxSTAT is set; SSPxIF is set if
“Clock Stretching” for more detail). By stretching the interrupt on Start detect is enabled.
clock, the host will be unable to assert another clock 3. Matching address with R/W bit set is received by
pulse until the client is done preparing the transmit the Client setting SSPxIF bit.
data.
4. Client hardware generates an ACK and sets
The transmit data must be loaded into the SSPxBUF SSPxIF.
register which also loads the SSPxSR register. Then 5. SSPxIF bit is cleared by user.
the SCL pin should be released by setting the CKP bit
6. Software reads the received address from
of the SSPxCON1 register. The eight data bits are
SSPxBUF, clearing BF.
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL 7. R/W is set so CKP was automatically cleared
high time. after the ACK.
8. The client software loads the transmit data into
The ACK pulse from the host-receiver is latched on the
SSPxBUF.
rising edge of the ninth SCL input pulse. This ACK value
is copied to the ACKSTAT bit of the SSPxCON2 register. 9. CKP bit is set releasing SCL, allowing the host
If ACKSTAT is set (not ACK), then the data transfer is to clock the data out of the client.
complete. In this case, when the not ACK is latched by 10. SSPxIF is set after the ACK response from the
the client, the client goes idle and waits for another host is loaded into the ACKSTAT register.
occurrence of the Start bit. If the SDA line was low 11. SSPxIF bit is cleared.
(ACK), the next transmit data must be loaded into the 12. The client software checks the ACKSTAT bit to
SSPxBUF register. Again, the SCL pin must be released see if the host wants to clock out more data.
by setting bit CKP.
Note 1: If the host ACKs the clock will be
An MSSP interrupt is generated for each data transfer stretched.
byte. The SSPxIF bit must be cleared by software and
the SSPxSTAT register is used to determine the status 2: ACKSTAT is the only bit updated on the
of the byte. The SSPxIF bit is set on the falling edge of rising edge of SCL (9th) rather than the
the ninth clock pulse. falling.
13. Steps 9-13 are repeated for each transmitted
31.5.3.1 Client Mode Bus Collision byte.
A client receives a read request and begins shifting 14. If the host sends a not ACK; the clock is not held,
data out on the SDA line. If a bus collision is detected but SSPxIF is still set.
and the SBCDE bit of the SSPxCON3 register is set, 15. The host sends a Restart condition or a Stop.
the BCL1IF bit of the PIR3 register is set. Once a bus
16. The client is no longer addressed.
collision is detected, the client goes idle and waits to be
addressed again. User software can use the BCL1IF bit
to handle a client bus collision.

Host sends
Stop condition
FIGURE 31-18:
Receiving Address Transmitting Data Automatic Transmitting Data ACK

R/W = 1 Automatic
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPxIF

Cleared by software
BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
PIC16(L)F18857/77
is read from SSPxBUF loaded into SSPxBUF edge of SCL
CKP
When R/W is set CKP is not
SCL is always held for not
held low after 9th SCL Set by software ACK
falling edge
ACKSTAT
Hosts not ACK

is copied to
ACKSTAT
R/W
R/W is copied from the
matching address byte
D/A
I2C CLIENT, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
Indicates an address
has been received
DS40001825F-page 468
PIC16(L)F18857/77
31.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt
generation after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
Figure 31-19 displays a standard waveform of a 7-bit
address client transmission with AHEN enabled.
1. Bus starts Idle.
2. Host sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Host sends matching address with R/W bit set.
After the eighth falling edge of the SCL line the
CKP bit is cleared and SSPxIF interrupt is gen-
erated.
4. Client software clears SSPxIF.
5. Client software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
6. Client reads the address value from the
SSPxBUF register clearing the BF bit.
7. Client software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
8. Client sets the CKP bit releasing SCL.
9. Host clocks in the ACK value from the client.
10. Client hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Client software clears SSPxIF.
12. Client loads value to transmit to the host into
SSPxBUF setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
13. Client sets the CKP bit releasing the clock.
14. Host clocks out the data from the client and
sends an ACK value on the ninth SCL pulse.
15. Client hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the host from the client.
17. If the host sends a not ACK the client releases
the bus allowing the host to send a Stop and end
the communication.
Note: Host must send a not ACK on the last byte
to ensure that the client releases the SCL
line to receive a Stop.

Host sends
Host releases SDA Stop condition
FIGURE 31-19:
to client for ACK sequence

Receiving Address R/W = 1 Automatic Transmitting Data Automatic Transmitting Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P

SSPxIF
Cleared by software
BF BF is automatically
Received address Data to transmit is cleared after 8th falling
PIC16(L)F18857/77
is read from SSPxBUF loaded into SSPxBUF edge of SCL
ACKDT
Client clears
ACKDT to ACK
address
ACKSTAT
Host’s ACK
response is copied
to SSPxSTAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCL
address. cleared after ACK
ACKTIM
I2C CLIENT, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
ACKTIM is set on 8th falling ACKTIM is cleared

edge of SCL on 9th rising edge of SCL
R/W
D/A
DS40001825F-page 470
PIC16(L)F18857/77
31.5.4 CLIENT MODE 10-BIT ADDRESS 31.5.5 10-BIT ADDRESSING WITH ADDRESS OR
RECEPTION DATA HOLD
This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSP module configured as an I2C client in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSPxADD register
Figure 31-20 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCL line is held low are the
same. Figure 31-21 can be used as a reference of a
This is a step by step process of what must be done by client in 10-bit addressing with AHEN set.
client software to accomplish I2C communication.
Figure 31-22 shows a standard waveform for a client
1. Bus starts Idle. transmitter in 10-bit Addressing mode.
2. Host sends Start condition; S bit of SSPxSTAT is
set; SSPxIF is set if interrupt on Start detect is
enabled.
3. Host sends matching high address with R/W bit
clear; UA bit of the SSPxSTAT register is set.
4. Client sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. Client loads low address into SSPxADD,
releasing SCL.
8. Host sends matching low address byte to the cli-
ent; UA bit is set.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
9. Client sends ACK and SSPxIF is set.

Note: If the low address does not match, SSPxIF
and UA are still set so that the client
software can set SSPxADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Client clears SSPxIF.
11. Client reads the received matching address
from SSPxBUF clearing BF.
12. Client loads high address into SSPxADD.
13. Host clocks a data byte to the client and clocks
out the clients ACK on the ninth SCL pulse;
SSPxIF is set.
14. If SEN bit of SSPxCON2 is set, CKP is cleared
by hardware and the clock is stretched.
15. Client clears SSPxIF.
16. Client reads the received byte from SSPxBUF
clearing BF.
17. If SEN is set the client sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Host sends Stop to end the transmission.

FIGURE 31-20:
Host sends
Stop condition
Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDA
1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SCL is held low
while CKP = 0
PIC16(L)F18857/77
SSPxIF
Set by hardware Cleared by software
on 9th falling edge
BF
If address matches Receive address is Data is read
SSPxADD it is loaded into read from SSPxBUF from SSPxBUF
SSPxBUF
UA
When UA = 1; Software updates SSPxADD
SCL is held low and releases SCL
CKP
When SEN = 1; Set by software,

CKP is cleared after releasing SCL
9th falling edge of received byte
DS40001825F-page 472
Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
FIGURE 31-21:
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5
SCL S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2

SSPxIF
Set by hardware Cleared by software Cleared by software
on 9th falling edge
PIC16(L)F18857/77
BF
SSPxBUF can be Received data

read anytime before is read from
the next received byte SSPxBUF
ACKDT
Client software clears
ACKDT to ACK
the received byte
UA
Update to SSPxADD is Update of SSPxADD,

not allowed until 9th
clears UA and releases
falling edge of SCL
SCL
CKP If when AHEN = 1;

on the 8th falling edge Set CKP with software
of SCL of an address releases SCL
byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL
DS40001825F-page 473
FIGURE 31-22:
Host sends
Host sends Stop condition
Restart event Host sends
not ACK
Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
Sr
PIC16(L)F18857/77
SSPxIF
Set by hardware Cleared by software Set by hardware
BF
SSPxBUF loaded Received address is Data to transmit is

with received address read from SSPxBUF loaded into SSPxBUF
UA
High address is loaded
UA indicates SSPxADD After SSPxADD is back into SSPxADD
must be updated updated, UA is cleared
CKP and SCL is released
When R/W = 1; Set by software

ACKSTAT CKP is cleared on releases SCL
9th falling edge of SCL
Hosts not ACK

is copied
R/W
R/W is copied from the
matching address byte
D/A
Indicates an address
has been received
I2C CLIENT, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
DS40001825F-page 474
PIC16(L)F18857/77
31.5.6 CLOCK STRETCHING 31.5.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set the
holds the SCL line low, effectively pausing communi- clock is always stretched. This is the only time the SCL
cation. The client may stretch the clock to allow more is stretched without CKP being cleared. SCL is
time to handle data or prepare a response for the host released immediately after a write to SSPxADD.
device. A host device is not concerned with stretching
Note: Previous versions of the module did not
as anytime it is active on the bus and not transferring
stretch the clock if the second address byte
data it is stretching. Any stretching done by a client is
did not match.
invisible to the host software and handled by the hard-
ware that generates SCL. 31.5.6.3 Byte NACKing
The CKP bit of the SSPxCON1 register is used to
control stretching in software. Any time the CKP bit is When AHEN bit of SSPxCON3 is set; CKP is cleared
cleared, the module will wait for the SCL line to go low by hardware after the eighth falling edge of SCL for a
and then hold it. Setting CKP will release SCL and received matching address byte. When DHEN bit of
allow more communication. SSPxCON3 is set; CKP is cleared after the eighth fall-
ing edge of SCL for received data.
31.5.6.1 Normal Clock Stretching Stretching after the eighth falling edge of SCL allows
Following an ACK if the R/W bit of SSPxSTAT is set, a the client to look at the received address or data and
read request, the client hardware will clear CKP. This decide if it wants to ACK the received data.
allows the client time to update SSPxBUF with data to 31.5.7 CLOCK SYNCHRONIZATION AND THE
transfer to the host. If the SEN bit of SSPxCON2 is CKP BIT
set, the client hardware will always stretch the clock
after the ACK sequence. Once the client is ready; CKP Any time the CKP bit is cleared, the module will wait
is set by software and communication resumes. for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
Note 1: The BF bit has no effect on if the clock will
until the SCL output is already sampled low. There-
be stretched or not. This is different than
fore, the CKP bit will not assert the SCL line until an
previous versions of the module that
external I2C host device has already asserted the SCL
would not stretch the clock, clear CKP, if
line. The SCL output will remain low until the CKP bit
SSPxBUF was read before the ninth
is set and all other devices on the I2C bus have
falling edge of SCL.
released SCL. This ensures that a write to the CKP bit
2: Previous versions of the module did not will not violate the minimum high time requirement for
stretch the clock for a transmission if SCL (see Figure 31-23).
SSPxBUF was loaded before the ninth
falling edge of SCL. It is now always
cleared for read requests.
FIGURE 31-23: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX ‚ – 1
SCL
Host device
CKP asserts clock
Host device
releases clock
WR
SSPxCON1

PIC16(L)F18857/77
31.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The client
The addressing procedure for the I2C bus is such that will prepare to receive the second byte as data, just as
the first byte after the Start condition usually deter- it would in 7-bit mode.
mines which device will be the client addressed by the
host device. The exception is the general call address If the AHEN bit of the SSPxCON3 register is set, just
which can address all devices. When this address is as with any other address reception, the client hard-
used, all devices should, in theory, respond with an ware will stretch the clock after the eighth falling edge
acknowledge. of SCL. The client must then set its ACKDT value and
release the clock with communication progressing as it
The general call address is a reserved address in the would normally.
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPxCON2 register is set, the client
module will automatically ACK the reception of this
address regardless of the value stored in SSPxADD.
After the client clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and client
software can read SSPxBUF and respond.
Figure 31-24 shows a general call reception
sequence.
FIGURE 31-24: CLIENT MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address
after ACK, set interrupt
R/W = 0 Receiving Data ACK

SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
SSPxBUF is read
GCEN (SSPxCON2<7>)
’1’
31.5.9 SSP MASK REGISTER

An SSP Mask (SSPxMSK) register (Register 31-5) is
available in I2C Client mode as a mask for the value
held in the SSPxSR register during an address
comparison operation. A zero (‘0’) bit in the SSPxMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.

PIC16(L)F18857/77
31.6 I2C Host Mode 31.6.1 I2C HOST MODE OPERATION
Host mode is enabled by setting and clearing the The host device generates all of the serial clock pulses
appropriate SSPM bits in the SSPxCON1 register and and the Start and Stop conditions. A transfer is ended
by setting the SSPEN bit. In Host mode, the SDA and with a Stop condition or with a Repeated Start condi-
SCK pins must be configured as inputs. The MSSP tion. Since the Repeated Start condition is also the
peripheral hardware will override the output driver TRIS beginning of the next serial transfer, the I2C bus will not
controls when necessary to drive the pins low. be released.
Host mode of operation is supported by interrupt gen- In Host Transmitter mode, serial data is output through
eration on the detection of the Start and Stop SDA, while SCL outputs the serial clock. The first byte
conditions. The Stop (P) and Start (S) bits are cleared transmitted contains the client address of the receiving
from a Reset or when the MSSP module is disabled. device (7 bits) and the Read/Write (R/W) bit. In this
Control of the I 2C bus may be taken when the P bit is case, the R/W bit will be logic ‘0’. Serial data is trans-
set, or the bus is Idle. mitted eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
In Firmware Controlled Host mode, user code conducts
Stop conditions are output to indicate the beginning
all I 2C bus operations based on Start and Stop bit
and the end of a serial transfer.
condition detection. Start and Stop condition detection
is the only active circuitry in this mode. All other In Host Receive mode, the first byte transmitted
communication is done by the user software directly contains the client address of the transmitting device
manipulating the SDA and SCL lines. (7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit client
The following events will cause the SSP Interrupt Flag address followed by a ‘1’ to indicate the receive bit.
bit, SSPxIF, to be set (SSP interrupt, if enabled): Serial data is received via SDA, while SCL outputs the
• Start condition detected serial clock. Serial data is received eight bits at a time.
• Stop condition detected After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
• Data transfer byte transmitted/received
beginning and end of transmission.
• Acknowledge transmitted/received
A Baud Rate Generator is used to set the clock
• Repeated Start generated
frequency output on SCL. See Section 31.7 “Baud
Note 1: The MSSP module, when configured in Rate Generator” for more detail.
I2C Host mode, does not allow queuing of
events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPxBUF did not occur
2: Host mode suspends Start/Stop detection
when sending the Start/Stop condition by
means of the SEN/PEN control bits. The
SSPxIF bit is set at the end of the
Start/Stop generation when hardware
clears the control bit.

PIC16(L)F18857/77
31.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the host, during any

receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate
Generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPxADD<7:0> and begins count-
ing. This ensures that the SCL high time will always be
at least one BRG rollover count in the event that the
clock is held low by an external device (Figure 31-25).
FIGURE 31-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA DX DX ‚ – 1
SCL deasserted but client holds SCL allowed to transition high

SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCL is sampled high, reload takes

place and BRG starts its count
BRG
Reload
31.6.3 WCOL STATUS FLAG
If the user writes the SSPxBUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not idle.
Note: Because queuing of events is not allowed,
writing to the lower five bits of SSPxCON2
is disabled until the Start condition is
complete.

PIC16(L)F18857/77
31.6.4 I2C HOST MODE START CONDITION
TIMING
Note 1: If at the beginning of the Start condition,
To initiate a Start condition (Figure 31-26), the user the SDA and SCL pins are already
sets the Start Enable bit, SEN bit of the SSPxCON2 sampled low, or if during the Start condi-
register. If the SDA and SCL pins are sampled high, tion, the SCL line is sampled low before
the Baud Rate Generator is reloaded with the contents the SDA line is driven low, a bus collision
of SSPxADD<7:0> and starts its count. If SCL and occurs, the Bus Collision Interrupt Flag,
SDA are both sampled high when the Baud Rate Gen- BCLIF, is set, the Start condition is
erator times out (TBRG), the SDA pin is driven low. The aborted and the I2C module is reset into
action of the SDA being driven low while SCL is high is its Idle state.
the Start condition and causes the S bit of the 2: The Philips I2C specification states that a
SSPxSTAT1 register to be set. Following this, the bus collision cannot occur on a Start.
Baud Rate Generator is reloaded with the contents of
SSPxADD<7:0> and resumes its count. When the
Baud Rate Generator times out (TBRG), the SEN bit of
the SSPxCON2 register will be automatically cleared
by hardware; the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
FIGURE 31-26: FIRST START BIT TIMING
Write to SEN bit occurs here Set S bit (SSPxSTAT<3>)
At completion of Start bit,

SDA = 1,
SCL = 1 hardware clears SEN bit
and sets SSPxIF bit
TBRG TBRG Write to SSPxBUF occurs here
SDA 1st bit 2nd bit
TBRG
SCL
S
TBRG

PIC16(L)F18857/77
31.6.5 I2C HOST MODE REPEATED START cally cleared and the Baud Rate Generator will not be
CONDITION TIMING reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
A Repeated Start condition (Figure 31-27) occurs when the S bit of the SSPxSTAT register will be set. The
the RSEN bit of the SSPxCON2 register is pro- SSPxIF bit will not be set until the Baud Rate Generator
grammed high and the host state machine is no longer has timed out.
active. When the RSEN bit is set, the SCL pin is
asserted low. When the SCL pin is sampled low, the Note 1: If RSEN is programmed while any other
Baud Rate Generator is loaded and begins counting. event is in progress, it will not take effect.
The SDA pin is released (brought high) for one Baud 2: A bus collision during the Repeated Start
Rate Generator count (TBRG). When the Baud Rate condition occurs if:
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is • SDA is sampled low when SCL
sampled high, the Baud Rate Generator is reloaded goes from low-to-high.
and begins counting. SDA and SCL must be sampled • SCL goes low before SDA is
high for one TBRG. This action is then followed by asserted low. This may indicate
assertion of the SDA pin (SDA = 0) for one TBRG while that another host is attempting to
SCL is high. SCL is asserted low. Following this, the transmit a data ‘1’.
RSEN bit of the SSPxCON2 register will be automati-
FIGURE 31-27: REPEATED START CONDITION WAVEFORM
S bit set by hardware

Write to SSPxCON2
occurs here At completion of Start bit,
SDA = 1, SDA = 1,
hardware clears RSEN bit
SCL (no change) SCL = 1 and sets SSPxIF
TBRG TBRG TBRG
SDA 1st bit
Write to SSPxBUF occurs here

TBRG
SCL
Sr TBRG
Repeated Start

PIC16(L)F18857/77
31.6.6 I2C HOST MODE TRANSMISSION 31.6.6.3 ACKSTAT Status Flag
Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit of the SSPxCON2
other half of a 10-bit address is accomplished by simply register is cleared when the client has sent an Acknowl-
writing a value to the SSPxBUF register. This action will edge (ACK = 0) and is set when the client does not
set the Buffer Full flag bit, BF, and allow the Baud Rate Acknowledge (ACK = 1). A client sends an Acknowl-
Generator to begin counting and start the next trans- edge when it has recognized its address (including a
mission. Each bit of address/data will be shifted out general call), or when the client has properly received
onto the SDA pin after the falling edge of SCL is its data.
asserted. SCL is held low for one Baud Rate Generator
31.6.6.4 Typical transmit sequence:
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it 1. The user generates a Start condition by setting
is held that way for TBRG. The data on the SDA pin the SEN bit of the SSPxCON2 register.
must remain stable for that duration and some hold 2. SSPxIF is set by hardware on completion of the
time after the next falling edge of SCL. After the eighth Start.
bit is shifted out (the falling edge of the eighth clock),
3. SSPxIF is cleared by software.
the BF flag is cleared and the host releases SDA. This
allows the client device being addressed to respond 4. The MSSP module will wait the required start
with an ACK bit during the ninth bit time if an address time before any other operation takes place.
match occurred, or if data was received properly. The 5. The user loads the SSPxBUF with the client
status of ACK is written into the ACKSTAT bit on the ris- address to transmit.
ing edge of the ninth clock. If the host receives an 6. Address is shifted out the SDA pin until all eight
Acknowledge, the Acknowledge Status bit, ACKSTAT, bits are transmitted. Transmission begins as
is cleared. If not, the bit is set. After the ninth clock, the soon as SSPxBUF is written to.
SSPxIF bit is set and the host clock (Baud Rate Gener- 7. The MSSP module shifts in the ACK bit from the
ator) is suspended until the next data byte is loaded into client device and writes its value into the
the SSPxBUF, leaving SCL low and SDA unchanged ACKSTAT bit of the SSPxCON2 register.
(Figure 31-28). 8. The MSSP module generates an interrupt at the
After the write to the SSPxBUF, each bit of the address end of the ninth clock cycle by setting the
will be shifted out on the falling edge of SCL until all SSPxIF bit.
seven address bits and the R/W bit are completed. On 9. The user loads the SSPxBUF with eight bits of
the falling edge of the eighth clock, the host will release data.
the SDA pin, allowing the client to respond with an 10. Data is shifted out the SDA pin until all eight bits
Acknowledge. On the falling edge of the ninth clock, the are transmitted.
host will sample the SDA pin to see if the address was
11. The MSSP module shifts in the ACK bit from the
recognized by a client. The status of the ACK bit is
client device and writes its value into the
loaded into the ACKSTAT Status bit of the SSPxCON2
ACKSTAT bit of the SSPxCON2 register.
register. Following the falling edge of the ninth clock
transmission of the address, the SSPxIF is set, the BF 12. Steps 8-11 are repeated for all transmitted data
flag is cleared and the Baud Rate Generator is turned bytes.
off until another write to the SSPxBUF takes place, 13. The user generates a Stop or Restart condition
holding SCL low and allowing SDA to float. by setting the PEN or RSEN bits of the SSPx-
CON2 register. Interrupt is generated once the
31.6.6.1 BF Status Flag Stop/Restart condition is complete.
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all eight bits are shifted out.
31.6.6.2 WCOL Status Flag

If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.

FIGURE 31-28:
Write SSPxCON2<0> SEN = 1 ACKSTAT in

Start condition begins SSPxCON2 = 1
From client, clear ACKSTAT bit SSPxCON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Client R/W = 0
of 10-bit Address ACK

SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
SSPxBUF written with 7-bit address and R/W

start transmit
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
PIC16(L)F18857/77
SCL held low

while CPU
responds to SSPxIF
SSPxIF
Cleared by software service routine
Cleared by software from SSP interrupt
Cleared by software
BF (SSPxSTAT<0>)
SSPxBUF written SSPxBUF is written by software

SEN
After Start condition, SEN cleared by hardware
PEN
R/W
I2C HOST MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS40001825F-page 482
PIC16(L)F18857/77
31.6.7 I2C HOST MODE RECEPTION 31.6.7.4 Typical Receive Sequence:
Host mode reception (Figure 31-29) is enabled by 1. The user generates a Start condition by setting
programming the Receive Enable bit, RCEN bit of the the SEN bit of the SSPxCON2 register.
SSPxCON2 register. 2. SSPxIF is set by hardware on completion of the
Note: The MSSP module must be in an Idle Start.
state before the RCEN bit is set or the 3. SSPxIF is cleared by software.
RCEN bit will be disregarded. 4. User writes SSPxBUF with the client address to
The Baud Rate Generator begins counting and on each transmit and the R/W bit set.
rollover, the state of the SCL pin changes 5. Address is shifted out the SDA pin until all eight
(high-to-low/low-to-high) and data is shifted into the bits are transmitted. Transmission begins as
SSPxSR. After the falling edge of the eighth clock, the soon as SSPxBUF is written to.
receive enable flag is automatically cleared, the 6. The MSSP module shifts in the ACK bit from the
contents of the SSPxSR are loaded into the SSPxBUF, client device and writes its value into the
the BF flag bit is set, the SSPxIF flag bit is set and the ACKSTAT bit of the SSPxCON2 register.
Baud Rate Generator is suspended from counting, 7. The MSSP module generates an interrupt at the
holding SCL low. The MSSP is now in Idle state end of the ninth clock cycle by setting the
awaiting the next command. When the buffer is read by SSPxIF bit.
the CPU, the BF flag bit is automatically cleared. The 8. User sets the RCEN bit of the SSPxCON2
user can then send an Acknowledge bit at the end of register and the host clocks in a byte from the
reception by setting the Acknowledge Sequence client.
Enable, ACKEN bit of the SSPxCON2 register.
9. After the eighth falling edge of SCL, SSPxIF and
31.6.7.1 BF Status Flag BF are set.
10. Host clears SSPxIF and reads the received byte
In receive operation, the BF bit is set when an address
from SSPxBUF, clears BF.
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read. 11. Host sets ACK value sent to client in ACKDT bit
of the SSPxCON2 register and initiates the ACK
31.6.7.2 SSPOV Status Flag by setting the ACKEN bit.
In receive operation, the SSPOV bit is set when eight 12. Host’s ACK is clocked out to the client and
bits are received into the SSPxSR and the BF flag bit is SSPxIF is set.
already set from a previous reception. 13. User clears SSPxIF.
14. Steps 8-13 are repeated for each received byte
31.6.7.3 WCOL Status Flag from the client.
If the user writes the SSPxBUF when a receive is 15. Host sends a not ACK or Stop to end
already in progress (i.e., SSPxSR is still shifting in a communication.
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).

Write to SSPxCON2<4>
to start Ackno1wledge sequence
SDA = ACKDT (SSPxCON2<5>) = 0
Write to SSPxCON2<0>(SEN = 1),
FIGURE 31-29:
begin Start condition ACK from Host Set ACKEN, start Acknowledge sequence
Host configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPxCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPxBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Client next receive automatically written here
start XMIT automatically
Transmit Address to Client Receiving Data from Client Receiving Data from Client
SDA A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Bus host
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPxIF at end
of receive Set SSPxIF interrupt
PIC16(L)F18857/77
Set SSPxIF interrupt at end of Acknow-

Set SSPxIF interrupt ledge sequence
at end of receive
at end of Acknowledge
SSPxIF sequence
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPxSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPxIF
responds to SSPxIF
BF
(SSPxSTAT<0>) Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF
SSPOV
SSPOV is set because

SSPxBUF is still full
ACKEN
I2C HOST MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
RCEN
Host configured as a receiver RCEN cleared ACK from Host RCEN cleared
by programming SSPxCON2<3> (RCEN = 1) automatically SDA = ACKDT = 0 automatically
DS40001825F-page 484
PIC16(L)F18857/77
31.6.8 ACKNOWLEDGE SEQUENCE 31.6.9 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPxCON2 register. At the end of a
SSPxCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDA pin. If the user wishes to the host will assert the SDA line low. When the SDA line
generate an Acknowledge, then the ACKDT bit should is sampled low, the Baud Rate Generator is reloaded
be cleared. If not, the user should set the ACKDT bit and counts down to ‘0’. When the Baud Rate Generator
before starting an Acknowledge sequence. The Baud times out, the SCL pin will be brought high and one
Rate Generator then counts for one rollover period TBRG (Baud Rate Generator rollover count) later, the
(TBRG) and the SCL pin is deasserted (pulled high). SDA pin will be deasserted. When the SDA pin is
When the SCL pin is sampled high (clock arbitration), sampled high while SCL is high, the P bit of the
the Baud Rate Generator counts for TBRG. The SCL pin SSPxSTAT register is set. A TBRG later, the PEN bit is
is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure 31-31).
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into IDLE mode 31.6.9.1 WCOL Status Flag
(Figure 31-30). If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
31.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does
If the user writes the SSPxBUF when an Acknowledge not occur).
sequence is in progress, then WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 31-30: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, ACKEN automatically cleared
write to SSPxCON2
ACKEN = 1, ACKDT = 0
TBRG TBRG
SDA D0 ACK
SCL 8 9
SSPxIF
Cleared in
SSPxIF set at software
the end of receive Cleared in
software SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 31-31: STOP CONDITION RECEIVE OR TRANSMIT MODE

Write to SSPxCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG
set PEN after SDA sampled high. P bit (SSPxSTAT<4>) is set.
Falling edge of PEN bit (SSPxCON2<2>) is cleared by

9th clock hardware and the SSPxIF bit is set
TBRG
SCL
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.

PIC16(L)F18857/77
31.6.10 SLEEP OPERATION 31.6.13 MULTI-HOST COMMUNICATION,
2
While in Sleep mode, the I C client module can receive BUS COLLISION AND BUS
addresses or data and when an address match or ARBITRATION
complete byte transfer occurs, wake the processor Multi-Host mode support is achieved by bus arbitration.
from Sleep (if the MSSP interrupt is enabled). When the host outputs address/data bits onto the SDA
pin, arbitration takes place when the host outputs a ‘1’
31.6.11 EFFECTS OF A RESET on SDA, by letting SDA float high and another host
A Reset disables the MSSP module and terminates the asserts a ‘0’. When the SCL pin floats high, data should
current transfer. be stable. If the expected data on SDA is a ‘1’ and the
data sampled on the SDA pin is ‘0’, then a bus collision
31.6.12 MULTI-HOST MODE has taken place. The host will set the Bus Collision
In Multi-Host mode, the interrupt generation on the Interrupt Flag, BCL1IF and reset the I2C port to its Idle
detection of the Start and Stop conditions allows the state (Figure 31-32).
determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision
Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is
MSSP module is disabled. Control of the I 2C bus may cleared, the SDA and SCL lines are deasserted and the
be taken when the P bit of the SSPxSTAT register is SSPxBUF can be written to. When the user services
set, or the bus is Idle, with both the S and P bits clear. the bus collision Interrupt Service Routine and if the I2C
When the bus is busy, enabling the SSP interrupt will bus is free, the user can resume communication by
generate the interrupt when the Stop condition occurs. asserting a Start condition.
In multi-host operation, the SDA line must be monitored If a Start, Repeated Start, Stop or Acknowledge condi-
for arbitration to see if the signal level is the expected tion was in progress when the bus collision occurred, the
output level. This check is performed by hardware with condition is aborted, the SDA and SCL lines are deas-
the result placed in the BCL1IF bit. serted and the respective control bits in the SSPxCON2
The states where arbitration can be lost are: register are cleared. When the user services the bus
collision Interrupt Service Routine and if the I2C bus is
• Address Transfer free, the user can resume communication by asserting a
• Data Transfer Start condition.
• A Start Condition The host will continue to monitor the SDA and SCL pins.
• A Repeated Start Condition If a Stop condition occurs, the SSPxIF bit will be set.
• An Acknowledge Condition A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Host mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 31-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,
Data changes SDA line pulled low data does not match what is driven
while SCL = 0 by another source by the host.
Bus collision has occurred.
SDA released
by host
SDA
SCL Set bus collision

interrupt (BCL1IF)
BCL1IF

PIC16(L)F18857/77
31.6.13.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the
Condition BRG is reset and the SDA line is asserted early
(Figure 31-35). If, however, a ‘1’ is sampled on the SDA
During a Start condition, a bus collision occurs if:
pin, the SDA pin is asserted low at the end of the BRG
a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and
the Start condition (Figure 31-33). counts down to zero; if the SCL pin is sampled as ‘0’
b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the
(Figure 31-34). end of the BRG count, the SCL pin is asserted low.
During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a
pins are monitored. factor during a Start condition is that no
If the SDA pin is already low, or the SCL pin is already two bus hosts can assert a Start condition
low, then all of the following occur: at the exact same time. Therefore, one
host will always assert SDA before the
• the Start condition is aborted,
other. This condition does not cause a bus
• the BCL1IF flag is set and collision because the two hosts must be
• the MSSP module is reset to its Idle state allowed to arbitrate the first address fol-
(Figure 31-33). lowing the Start condition. If the address is
The Start condition begins with the SDA and SCL pins the same, arbitration must be allowed to
deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated
Baud Rate Generator is loaded and counts down. If the Start or Stop conditions.
SCL pin is sampled low while SDA is high, a bus
collision occurs because it is assumed that another
host is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 31-33: BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.
Set BCL1IF,
S bit and SSPxIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCL1IF.
S bit and SSPxIF set because
BCL1IF SDA = 0, SCL = 1.
SSPxIF and BCL1IF are
cleared by software
SSPxIF
SSPxIF and BCL1IF are

cleared by software

PIC16(L)F18857/77
FIGURE 31-34: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG TBRG
SDA
SCL Set SEN, enable Start

sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
bus collision occurs. Set BCL1IF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCL1IF.
BCL1IF
Interrupt cleared
by software
S ’0’ ’0’
SSPxIF ’0’ ’0’
FIGURE 31-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPxIF
Less than TBRG
TBRG
SDA SDA pulled low by other host.

Reset BRG and assert SDA.
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCL1IF ’0’
SSPxIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPxIF by software

PIC16(L)F18857/77
31.6.13.2 Bus Collision During a Repeated counting. If SDA goes from high-to-low before the BRG
Start Condition times out, no bus collision occurs because no two hosts
can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if: If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
a) A low level is sampled on SDA when SCL goes
occurs. In this case, another host is attempting to
from low level to high level (Case 1).
transmit a data ‘1’ during the Repeated Start condition,
b) SCL goes low before SDA is asserted low, see Figure 31-37.
indicating that another host is attempting to
transmit a data ‘1’ (Case 2). If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
When the user releases SDA and the pin is allowed to reloaded and begins counting. At the end of the count,
float high, the BRG is loaded with SSPxADD and regardless of the status of the SCL pin, the SCL pin is
counts down to zero. The SCL pin is then deasserted driven low and the Repeated Start condition is
and when sampled high, the SDA pin is sampled. complete.
If SDA is low, a bus collision has occurred (i.e., another
host is attempting to transmit a data ‘0’, Figure 31-36). If
SDA is sampled high, the BRG is reloaded and begins
FIGURE 31-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.

If SDA = 0, set BCL1IF and release SDA and SCL.
RSEN
BCL1IF
Cleared by software
S ’0’
SSPxIF ’0’
FIGURE 31-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG TBRG
SDA
SCL
SCL goes low before SDA,

BCL1IF set BCL1IF. Release SDA and SCL.
Interrupt cleared
by software
RSEN
S ’0’
SSPxIF

PIC16(L)F18857/77
31.6.13.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low.
Condition When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
Bus collision occurs during a Stop condition if:
the Baud Rate Generator is loaded with SSPxADD and
a) After the SDA pin has been deasserted and counts down to zero. After the BRG times out, SDA is
allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has
the BRG has timed out (Case 1). occurred. This is due to another host attempting to
b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure 31-38). If the SCL pin is sampled
low before SDA goes high (Case 2). low before SDA is allowed to float high, a bus collision
occurs. This is another case of another host attempting
to drive a data ‘0’ (Figure 31-39).
FIGURE 31-38: BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG TBRG TBRG SDA sampled

low after TBRG,
set BCL1IF
SDA
SDA asserted low

SCL
PEN
BCL1IF
P ’0’
SSPxIF ’0’
FIGURE 31-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG TBRG TBRG
SDA
Assert SDA SCL goes low before SDA goes high,

set BCL1IF
SCL
PEN
BCL1IF
P ’0’
SSPxIF ’0’

PIC16(L)F18857/77
31.7 BAUD RATE GENERATOR module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSP is
The MSSP module has a Baud Rate Generator avail- being operated in.
able for clock generation in both I2C and SPI Host
Table 31-2 demonstrates clock rates based on
modes. The Baud Rate Generator (BRG) reload value
instruction cycles and the BRG value loaded into
is placed in the SSPxADD register (Register 31-6).
SSPxADD.
When a write occurs to SSPxBUF, the Baud Rate
Generator will automatically begin counting down.
EQUATION 31-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will FOSC
FCLOCK = --------------------------------------------------
-
remain in its last state.  SSP1ADD + 1   4 
An internal signal “Reload” in Figure 31-40 triggers the

value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
FIGURE 31-40: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0> SSPxADD<7:0>
SSPM<3:0> Reload Reload

SCL Control
SSPCLK BRG Down Counter FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSPxADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 31-2: MSSP CLOCK RATE W/BRG

FCLOCK
FOSC FCY BRG Value
(2 Rollovers of BRG)
32 MHz 8 MHz 13h 400 kHz
32 MHz 8 MHz 4Fh 100 kHz
16 MHz 4 MHz 0Ch 308 kHz
Note: Refer to the I/O port electrical specifications in Table 37-4 to ensure the system is designed to support IOL
requirements.

PIC16(L)F18857/77
31.8 Register Definitions: MSSPx Control
REGISTER 31-1: SSPxSTAT: SSPx STATUS REGISTER
R/W-0/0 R/W-0/0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0
SMP CKE(1) D/A P(2) S(2) R/W UA BF
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS/HC = Hardware set/clear
bit 7 SMP: SPI Data Input Sample bit

SPI Host mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Client mode:
SMP must be cleared when SPI is used in Client mode
In I2 C Host or Client mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)(1)
In SPI Host or Client mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C™ mode only:
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit(2)
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit (2)
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the
next Start bit, Stop bit, or not ACK bit.
In I2 C Client mode:
1 = Read
0 = Write
In I2 C Host mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE mode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPxADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPxBUF is full
0 = Receive not complete, SSPxBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty
Note 1: Polarity of clock state is set by the CKP bit of the SSPxCON register.
2: This bit is cleared on Reset and when SSPEN is cleared.

PIC16(L)F18857/77
REGISTER 31-2: SSPxCON1: SSPx CONTROL REGISTER 1

R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
WCOL SSPOV(1) SSPEN CKP SSPM<3:0>
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)

1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.
Overflow can only occur in Client mode. In Client mode, the user must read the SSPxBUF, even if only transmitting data, to avoid
setting overflow. In Host mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPxBUF register (must be cleared in software).
0 = No overflow
2
In I C mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, the following pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C Client mode:
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2 C Host mode:
Unused in this mode
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Client mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Client mode, 7-bit address with Start and Stop bit interrupts enabled
1101 = Reserved
1100 = Reserved
1011 = I2C firmware controlled Host mode (client idle)
1010 = SPI Host mode, clock = FOSC/(4 * (SSPxADD+1))(5)
1001 = Reserved
1000 = I2C Host mode, clock = FOSC / (4 * (SSPxADD+1))(4)
0111 = I2C Client mode, 10-bit address
0110 = I2C Client mode, 7-bit address
0101 = SPI Client mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Client mode, clock = SCK pin, SS pin control enabled
0011 = SPI Host mode, clock = T2_match/2
0010 = SPI Host mode, clock = FOSC/64
Note 1: In Host mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
2: When enabled, these pins must be properly configured as input or output. Use SSPxSSPPS, SSPxCLKPPS, SSPxDATPPS, and
RxyPPS to select the pins.
3: When enabled, the SDA and SCL pins must be configured as inputs. Use SSPxCLKPPS, SSPxDATPPS, and RxyPPS to select the pins.
4: SSPxADD values of 0, 1 or 2 are not supported for I2C mode.
5: SSPxADD value of ‘0’ is not supported. Use SSPM = 0000 instead.

PIC16(L)F18857/77
REGISTER 31-3: SSPxCON2: SSPx CONTROL REGISTER 2 (I2C MODE ONLY)(1)

R/W-0/0 R/HS/HC-0 R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set
bit 7 GCEN: General Call Enable bit (in I2C Client mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Host mode only)
In Host Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Host mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Host mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Host mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Host mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Client mode:
1 = Clock stretching is enabled for both client transmit and client receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).

PIC16(L)F18857/77
REGISTER 31-4: SSPxCON3: SSPx CONTROL REGISTER 3

R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0
Legend:
bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock
bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C Client mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5 SCIE: Start Condition Interrupt Enable bit (I2C Client mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4 BOEN: Buffer Overwrite Enable bit
In SPI Client mode:(1)
1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the SSPxCON1
register is set, and the buffer is not updated
In I2 C™ Host mode and SPI Host mode:
In I2 C™ Client mode:
1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the
SSPOV bit only if the BF bit = 0.
0 = SSPxBUF is only updated when SSPOV is clear
bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only)
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2 SBCDE: Client Mode Bus Collision Detect Enable bit (I2C Client mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the
PIR3 register is set, and bus goes idle
1 = Enable client bus collision interrupts
0 = Client bus collision interrupts are disabled
bit 1 AHEN: Address Hold Enable bit (I2C Client mode only)
1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the SSPxCON1
register will be cleared and the SCL will be held low.
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I2C Client mode only)
1 = Following the eighth falling edge of SCL for a received data byte; client hardware clears the CKP bit of the
SSPxCON1 register and SCL is held low.
0 = Data holding is disabled
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new
byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
2: This bit has no effect in Client modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

PIC16(L)F18857/77
REGISTER 31-5: SSPxMSK: SSPx MASK REGISTER

SSPMSK<7:0>
bit 7 bit 0
Legend:
bit 7-1 SSPMSK<7:1>: Mask bits

1 = The received address bit n is compared to SSPxADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 SSPMSK<0>: Mask bit for I2C Client mode, 10-bit Address
I2C Client mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Client mode, 7-bit address:
MSK0 bit is ignored.
REGISTER 31-6: SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE)
SSPADD<7:0>
bit 7 bit 0
Legend:
Host mode:
bit 7-0 SSPADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Client mode – Most Significant Address Byte:
bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit
pattern sent by host is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 SSPADD<2:1>: Two Most Significant bits of 10-bit Address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Client mode – Least Significant Address Byte:
bit 7-0 SSPADD<7:0>: Eight Least Significant bits of 10-bit Address

7-Bit Client mode:
bit 7-1 SSPADD<7:1>: 7-bit Address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.

PIC16(L)F18857/77
REGISTER 31-7: SSPxBUF: MSSPx BUFFER REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SSPBUF<7:0>
bit 7 bit 0
Legend:
bit 7-0 SSPBUF<7:0>: MSSP Buffer bits
TABLE 31-3: SUMMARY OF REGISTERS ASSOCIATED WITH MSSPx

Register
on Page

SSP1STAT SMP CKE D/A P S R/W UA BF 492
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 493
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 494
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 492
SSP1MSK SSPMSK<7:0> 496
SSP1ADD SSPADD<7:0> 496
SSP1BUF SSPBUF<7:0> 497
SSP2STAT SMP CKE D/A P S R/W UA BF 492
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 493
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 494
SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 492
SSP2MSK SSPMSK<7:0> 496
SSP2ADD SSPADD<7:0> 496
SSP2BUF SSPBUF<7:0> 497
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx module
Note 1: When using designated I2C pins, the associated pin values in INLVLx will be ignored.

PIC16(L)F18857/77
32.0 SIGNAL MEASUREMENT TIMER
(SMT)
The SMT is a 24-bit counter with advanced clock and
gating logic, which can be configured for measuring a
variety of digital signal parameters such as pulse width,
frequency and duty cycle, and the time difference
between edges on two signals.
Features of the SMT include:
• 24-bit timer/counter
- Three 8-bit registers (SMTxL/H/U)
- Readable and writable
- Optional 16-bit operating mode
• Two 24-bit measurement capture registers
• One 24-bit period match register
• Multi-mode operation, including relative timing
measurement
• Interrupt on period match
• Multiple clock, gate and signal sources
• Interrupt on acquisition complete
• Ability to read current input values
Note: These devices implement two SMT

modules. All references to SMTx apply to
SMT1 and SMT2.

PIC16(L)F18857/77
FIGURE 32-1: SMT BLOCK DIAGRAM
Rev. 10-000161C
7/28/2015
Period Latch
Set SMTxPRAIF
SMT_window SMT
Clock SMTxPR
Sync
Circuit
Control Set SMTxIF
Logic Comparator
SMT_signal SMT
Clock
Sync
Circuit
24-bit
Reset SMTxCPR
Buffer
Enable SMTxTMR 24-bit

SMTxCPW
CLKR 111 Buffer
SOSC 110 Window Latch

Set SMTxPWAIF
MFINTOSC/16 101
MFINTOSC 100
Prescaler
LFINTOSC 011
HFINTOSC 16
010
MHz
FOSC 001
FOSC/4 000
SMTxCLK<2:0>
FIGURE 32-2: SMT SIGNAL AND WINDOW BLOCK DIAGRAM

Rev. 10-000173B
7/21/2014
See See
SMTxSIG SMT_signal SMTxWIN SMT_window
Register Register
SMTxSIG<3:0> SMTxWIN<3:0>

PIC16(L)F18857/77
32.1 SMT Operation The SMTxCPW registers can also be updated with the
current value of the SMTxTMR value by setting the
The core of the module is the 24-bit counter, SMTxTMR CPWUP bit of the SMTxSTAT register.
combined with a complex data acquisition front-end.
Depending on the mode of operation selected, the SMT 32.2.3 PERIOD LATCH REGISTERS
can perform a variety of measurements summarized in
The SMTxCPR registers are the 24-bit SMT period
Table 32-1.
latch. They are used to latch in other values of the
32.1.1 CLOCK SOURCES SMTxTMR when triggered by various other signals,
which are determined by the mode the SMT is currently
Clock sources available to the SMT include: in.
• FOSC The SMTxCPR registers can also be updated with the
• FOSC/4 current value of the SMTxTMR value by setting the
• HFINTOSC (16 MHz) CPRU bit in the SMTxSTAT register.
• LFINTOSC
• MFINTOSC/16 (31.25 kHz) 32.3 Halt Operation
The SMT clock source is selected by configuring the The counter can be prevented from rolling-over using
CSEL<2:0> bits in the SMTxCLK register. The clock the STP bit in the SMTxCON0 register. When halting is
source can also be prescaled using the PS<1:0> bits of enabled, the period match interrupt persists until the
the SMTxCON0 register. The prescaled clock source is SMTxTMR is reset (either by a manual reset, Section
used to clock both the counter and any synchronization 32.2.1 “Time Base”) or by clearing the SMTxGO bit of
logic used by the module. the SMTxCON1 register and writing the SMTxTMR
values in software.
32.1.2 PERIOD MATCH INTERRUPT
Similar to other timers, the SMT triggers an interrupt 32.4 Polarity Control
when SMTxTMR rolls over to ‘0’. This happens when
The three input signals for the SMT have polarity
SMTxTMR = SMTxPR, regardless of mode. Hence, in
control to determine whether or not they are active
any mode that relies on an external signal or a window
high/positive edge or active low/negative edge signals.
to reset the timer, proper operation requires that
SMTxPR be set to a period larger than that of the The following bits apply to Polarity Control:
expected signal or window. • WSEL bit (Window Polarity)
• SSEL bit (Signal Polarity)
32.2 Basic Timer Function Registers • CSEL bit (Clock Polarity)
The SMTxTMR time base and the These bits are located in the SMTxCON0 register.
SMTxCPW/SMTxPR/SMTxCPR buffer registers serve
several functions and can be manually updated using 32.5 Status Information
software.
The SMT provides input status information for the user
32.2.1 TIME BASE without requiring the need to deal with the polarity of
The SMTxTMR is the 24-bit counter that is the center of the incoming signals.
the SMT. It is used as the basic counter/timer for
measurement in each of the modes of the SMT. It can be 32.5.1 WINDOW STATUS
reset to a value of 24’h00_0000 by setting the RST bit of Window status is determined by the WS bit of the
the SMTxSTAT register. It can be written to and read SMTxSTAT register. This bit is only used in Windowed
from software, but it is not guarded for atomic access, Measure, Gated Counter and Gated Window Measure
therefore reads and writes to the SMTxTMR should only modes, and is only valid when TS = 1, and will be
be made when the GO = 0, or the software should have delayed in time by synchronizer delays in non-Counter
other measures to ensure integrity of SMTxTMR modes.
reads/writes.
32.5.2 SIGNAL STATUS
32.2.2 PULSE WIDTH LATCH REGISTERS Signal status is determined by the AS bit of the
The SMTxCPW registers are the 24-bit SMT pulse SMTxSTAT register. This bit is used in all modes except
width latch. They are used to latch in the value of the Window Measure, Time of Flight and Capture modes,
SMTxTMR when triggered by various signals, which and is only valid when TS = 1, and will be delayed in
are determined by the mode the SMT is currently in. time by synchronizer delays in non-Counter modes.

PIC16(L)F18857/77
32.5.3 GO STATUS 32.6.1 TIMER MODE
Timer run status is determined by the TS bit of the Timer mode is the simplest mode of operation where
SMTxSTAT register, and will be delayed in time by the SMTxTMR is used as a 16/24-bit timer. No data
synchronizer delays in non-Counter modes. acquisition takes place in this mode. The timer
increments as long as the SMTxGO bit has been set by
32.6 Modes of Operation software. No SMT window or SMT signal events affect
the SMTxGO bit. Everything is synchronized to the
The modes of operation are summarized in Table 32-1. SMT clock source. When the timer experiences a
The following sections provide detailed descriptions, period match (SMTxTMR = SMTxPR), SMTxTMR is
examples of how the modes can be used. Note that all reset and the period match interrupt trips. See
waveforms assume WPOL/SPOL/CPOL = 0. When Figure 32-3.
WPOL/SPOL/CPOL = 1, all SMTSIGx, SMTWINx and
SMT clock signals will have a polarity opposite to that
indicated. For all modes, the REPEAT bit controls
whether the acquisition is repeated or single. When
REPEAT = 0 (Single Acquisition mode), the timer will
stop incrementing and the SMTxGO bit will be reset
upon the completion of an acquisition. Otherwise, the
timer will continue and allow for continued acquisitions
to overwrite the previous ones until the timer is stopped
in software.
TABLE 32-1: MODES OF OPERATION

Synchronous
MODE Mode of Operation Reference
Operation
0000 Timer Yes Section 32.6.1 “Timer Mode”
0001 Gated Timer Yes Section 32.6.2 “Gated Timer Mode”
0010 Period and Duty Cycle Acquisition Yes Section 32.6.3 “Period and Duty-Cycle Mode”
0011 High and Low Time Measurement Yes Section 32.6.4 “High and Low Measure Mode”
0100 Windowed Measurement Yes Section 32.6.5 “Windowed Measure Mode”
0101 Gated Windowed Measurement Yes Section 32.6.6 “Gated Window Measure Mode”
0110 Time of Flight Yes Section 32.6.7 “Time of Flight Measure Mode”
0111 Capture Yes Section 32.6.8 “Capture Mode”
1000 Counter No Section 32.6.9 “Counter Mode”
1001 Gated Counter No Section 32.6.10 “Gated Counter Mode”
1010 Windowed Counter No Section 32.6.11 “Windowed Counter Mode”
1011-1111 Reserved — —

FIGURE 32-3: TIMER MODE TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000 174A
12/19/201 3
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxPR 11
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9
SMTxIF
DS40001825F-page 502
PIC16(L)F18857/77
32.6.2 GATED TIMER MODE
Gated Timer mode uses the SMTSIGx input to control
whether or not the SMTxTMR will increment. Upon a
falling edge of the external signal, the SMTxCPW
register will update to the current value of the
SMTxTMR. Example waveforms for both repeated and
single acquisitions are provided in Figure 32-4 and
Figure 32-5.

FIGURE 32-4: GATED TIMER MODE REPEAT ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000 176A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxPR 0xFFFFFF
SMTxTMR 0 1 2 3 4 5 6 7
SMTxCPW 5 7
SMTxPWAIF
DS40001825F-page 504
FIGURE 32-5: GATED TIMER MODE SINGLE ACQUISITION TIMING DIAGRAM
DS40001825F-page 505
PIC16(L)F18857/77
Rev. 10-000 175A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxPR 0xFFFFFF
SMTxTMR 0 1 2 3 4 5
SMTxCPW 5
SMTxPWAIF
PIC16(L)F18857/77
32.6.3 PERIOD AND DUTY-CYCLE MODE
In Duty-Cycle mode, either the duty cycle or period
(depending on polarity) of the SMTx_signal can be
acquired relative to the SMT clock. The CPW register is
updated on a falling edge of the signal, and the CPR
register is updated on a rising edge of the signal, along
with the SMTxTMR resetting to 0x0001. In addition, the
SMTxGO bit is reset on a rising edge when the SMT is
in Single Acquisition mode. See Figure 32-6 and
Figure 32-7.

FIGURE 32-6: PERIOD AND DUTY-CYCLE REPEAT ACQUISITION MODE TIMING DIAGRAM
DS40001825F-page 507
PIC16(L)F18857/77
Rev. 10-000 177A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5
SMTxCPW 5 2
SMTxCPR 11
SMTxPWAIF
SMTxPRAIF
FIGURE 32-7: PERIOD AND DUTY-CYCLE SINGLE ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000 178A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11
SMTxCPW 5
SMTxCPR 11
SMTxPWAIF
SMTxPRAIF
DS40001825F-page 508
PIC16(L)F18857/77
32.6.4 HIGH AND LOW MEASURE MODE
This mode measures the high and low pulse time of the
SMTSIGx relative to the SMT clock. It begins
incrementing the SMTxTMR on a rising edge on the
SMTSIGx input, then updates the SMTxCPW register
with the value and resets the SMTxTMR on a falling
edge, starting to increment again. Upon observing
another rising edge, it updates the SMTxCPR register
with its current value and once again resets the
SMTxTMR value and begins incrementing again. See
Figure 32-8 and Figure 32-9.

FIGURE 32-8: HIGH AND LOW MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000 180A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 1 2 3 4 5 6 1 2 1 2 3
SMTxCPW 5 2
SMTxCPR 6
SMTxPWAIF
SMTxPRAIF
DS40001825F-page 510
FIGURE 32-9: HIGH AND LOW MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000 179A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 1 2 3 4 5 6
SMTxCPW 5
SMTxCPR 6
SMTxPWAIF
SMTxPRAIF
DS40001825F-page 511
PIC16(L)F18857/77
32.6.5 WINDOWED MEASURE MODE
This mode measures the window duration of the
SMTWINx input of the SMT. It begins incrementing the
timer on a rising edge of the SMTWINx input and
updates the SMTxCPR register with the value of the
timer and resets the timer on a second rising edge. See

FIGURE 32-10: WINDOWED MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000 182A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 1 2 3 4
SMTxCPR 12 8
SMTxPRAIF
DS40001825F-page 513
FIGURE 32-11: WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000 181A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12
SMTxCPR 12
SMTxPRAIF
DS40001825F-page 514
PIC16(L)F18857/77
32.6.6 GATED WINDOW MEASURE MODE
This mode measures the duty cycle of the SMTx_signal
input over a known input window. It does so by
incrementing the timer on each pulse of the clock signal
while the SMTx_signal input is high, updating the
SMTxCPR register and resetting the timer on every
rising edge of the SMTWINx input after the first. See

FIGURE 32-12: GATED WINDOWED MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000 184A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 0 1 2 3 0
SMTxCPR 6 3
SMTxPRAIF
DS40001825F-page 516
FIGURE 32-13: GATED WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAMS
PIC16(L)F18857/77
Rev. 10-000 183A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6
SMTxCPR 6
SMTxPRAIF
DS40001825F-page 517
PIC16(L)F18857/77
32.6.7 TIME OF FLIGHT MEASURE MODE
This mode measures the time interval between a rising
edge on the SMTWINx input and a rising edge on the
SMTx_signal input, beginning to increment the timer
upon observing a rising edge on the SMTWINx input,
while updating the SMTxCPR register and resetting the
timer upon observing a rising edge on the SMTx_signal
input. In the event of two SMTWINx rising edges
without an SMTx_signal rising edge, it will update the
SMTxCPW register with the current value of the timer
and reset the timer value. See Figure 32-14 and
Figure 32-15.

FIGURE 32-14: TIME OF FLIGHT MODE REPEAT ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000186A
4/22/2016
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2
SMTxCPW 13
SMTxCPR 4
SMTxPWAIF
SMTxPRAIF
DS40001825F-page 519
FIGURE 32-15: TIME OF FLIGHT MODE SINGLE ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000185A
4/26/2016
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5
SMTxCPW
SMTxCPR 4
SMTxPWAIF
SMTxPRAIF
DS40001825F-page 520
PIC16(L)F18857/77
32.6.8 CAPTURE MODE
This mode captures the Timer value based on a rising
or falling edge on the SMTWINx input and triggers an
interrupt. This mimics the capture feature of a CCP
module. The timer begins incrementing upon the
SMTxGO bit being set, and updates the value of the
SMTxCPR register on each rising edge of SMTWINx,
and updates the value of the CPW register on each
falling edge of the SMTWINx. The timer is not reset by
any hardware conditions in this mode and must be
reset by software, if desired. See Figure 32-16 and
Figure 32-17.

FIGURE 32-16: CAPTURE MODE REPEAT ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000 188A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SMTxCPW 3 19 32
SMTxCPR 2 18 31
SMTxPWAIF
SMTxPRAIF
DS40001825F-page 522
FIGURE 32-17: CAPTURE MODE SINGLE ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000 187A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3
SMTxCPW 3
SMTxCPR 2
SMTxPWAIF
SMTxPRAIF
DS40001825F-page 523
PIC16(L)F18857/77
32.6.9 COUNTER MODE
This mode increments the timer on each pulse of the
SMTx_signal input. This mode is asynchronous to the
SMT clock and uses the SMTx_signal as a time source.
The SMTxCPW register will be updated with the
current SMTxTMR value on the falling edge of the
SMTxWIN input. See Figure 32-18.

FIGURE 32-18: COUNTER MODE TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000189A
4/12/2016
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SMTxCPW 12 25
DS40001825F-page 525
PIC16(L)F18857/77
32.6.10 GATED COUNTER MODE
This mode counts pulses on the SMTx_signal input,
gated by the SMTxWIN input. It begins incrementing
the timer upon seeing a rising edge of the SMTxWIN
input and updates the SMTxCPW register upon a fall-
ing edge on the SMTxWIN input. See Figure 32-19
and Figure 32-20.

FIGURE 32-19: GATED COUNTER MODE REPEAT ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000190A
12/18/2013
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13
SMTxCPW 8 13
SMTxPWAIF
FIGURE 32-20: GATED COUNTER MODE SINGLE ACQUISITION TIMING DIAGRAM

Rev. 10-000191A
12/18/2013
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8
DS40001825F-page 527
SMTxCPW 8
SMTxPWAIF
PIC16(L)F18857/77
32.6.11 WINDOWED COUNTER MODE
This mode counts pulses on the SMTx_signal input,
within a window dictated by the SMTxWIN input. It
begins counting upon seeing a rising edge of the
SMTxWIN input, updates the SMTxCPW register on a
falling edge of the SMTxWIN input, and updates the
SMTxCPR register on each rising edge of the
SMTxWIN input beyond the first. See Figure 32-21 and
Figure 32-22.

FIGURE 32-21: WINDOWED COUNTER MODE REPEAT ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000192A
12/18/2013
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
SMTxCPW 9 5
SMTxCPR 16
SMTxPWAIF
SMTxPRAIF
DS40001825F-page 529
FIGURE 32-22: WINDOWED COUNTER MODE SINGLE ACQUISITION TIMING DIAGRAM
PIC16(L)F18857/77
Rev. 10-000193A
12/18/2013
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SMTxCPW 9
SMTxCPR 16
SMTxPWAIF
DS40001825F-page 530
PIC16(L)F18857/77
32.7 Interrupts
The SMT can trigger an interrupt under three different
conditions:
• PW Acquisition Complete
• PR Acquisition Complete
• Counter Period Match
The interrupts are controlled by the PIR and PIE
registers of the device.
32.7.1 PW AND PR ACQUISITION

INTERRUPTS
The SMT can trigger interrupts whenever it updates the
SMTxCPW and SMTxCPR registers, the circum-
stances for which are dependent on the SMT mode,
and are discussed in each mode’s specific section. The
SMTxCPW interrupt is controlled by SMTxPWAIF and
SMTxPWAIE bits in registers PIR8 and PIE8, respec-
tively. The SMTxCPR interrupt is controlled by the
SMTxPRAIF and SMTxPRAIE bits, also located in reg-
isters PIR8 and PIE8, respectively.
In synchronous SMT modes, the interrupt trigger is
synchronized to the SMTxCLK. In Asynchronous
modes, the interrupt trigger is asynchronous. In either
mode, once triggered, the interrupt will be synchro-
nized to the CPU clock.
32.7.2 COUNTER PERIOD MATCH

INTERRUPT
As described in Section 32.1.2 “Period Match
interrupt”, the SMT will also interrupt upon SMTxTMR,
matching SMTxPR with its period match limit functionality
described in Section 32.3 “Halt Operation”. The period
match interrupt is controlled by SMTxIF and SMTxIE,
located in registers PIR8 and PIE8, respectively.

PIC16(L)F18857/77
32.8 Register Definitions: SMT Control
Long bit name prefixes for the Signal Measurement
Timer peripherals are shown in Section 1.1 “Register
and Bit naming conventions”.
FOR SMT PERIPHERALS
SMT1 SMT1
SMT2 SMT2
REGISTER 32-1: SMTxCON0: SMT CONTROL REGISTER 0

R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
EN(1) — STP WPOL SPOL CPOL SMTxPS<1:0>
bit 7 bit 0
Legend:
bit 7 EN: SMT Enable bit(1)

1 = SMT is enabled
0 = SMT is disabled; internal states are reset, clock requests are disabled
bit 5 STP: SMT Counter Halt Enable bit
When SMTxTMR = SMTxPR:
1 = Counter remains SMTxPR; period match interrupt occurs when clocked
0 = Counter resets to 24’h000000; period match interrupt occurs when clocked
bit 4 WPOL: SMTxWIN Input Polarity Control bit
1 = SMTxWIN signal is active-low/falling edge enabled
0 = SMTxWIN signal is active-high/rising edge enabled
bit 3 SPOL: SMTxSIG Input Polarity Control bit
1 = SMTx_signal is active-low/falling edge enabled
0 = SMTx_signal is active-high/rising edge enabled
bit 2 CPOL: SMT Clock Input Polarity Control bit
1 = SMTxTMR increments on the falling edge of the selected clock signal
0 = SMTxTMR increments on the rising edge of the selected clock signal
bit 1-0 SMTxPS<1:0>: SMT Prescale Select bits
11 = Prescaler = 1:8
Note 1: Setting EN to ‘0’ does not affect the register contents.

PIC16(L)F18857/77
REGISTER 32-2: SMTxCON1: SMT CONTROL REGISTER 1

R/W/HC-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
SMTxGO REPEAT — — MODE<3:0>
bit 7 bit 0
Legend:
bit 7 SMTxGO: SMT GO Data Acquisition bit

1 = Incrementing, acquiring data is enabled
0 = Incrementing, acquiring data is disabled
bit 6 REPEAT: SMT Repeat Acquisition Enable bit
1 = Repeat Data Acquisition mode is enabled
0 = Single Acquisition mode is enabled
bit 3-0 MODE<3:0> SMT Operation Mode Select bits
1111 = Reserved
•
•
•
1011 = Reserved
1010 = Windowed counter
1001 = Gated counter
1000 = Counter
0111 = Capture
0110 = Time of flight
0101 = Gated windowed measure
0100 = Windowed measure
0011 = High and low time measurement
0010 = Period and Duty-Cycle Acquisition
0001 = Gated Timer
0000 = Timer

PIC16(L)F18857/77
REGISTER 32-3: SMTxSTAT: SMT STATUS REGISTER

R/W/HC-0/0 R/W/HC-0/0 R/W/HC-0/0 U-0 U-0 R-0/0 R-0/0 R-0/0
CPRUP CPWUP RST — — TS WS AS
bit 7 bit 0
Legend:
bit 7 CPRUP: SMT Manual Period Buffer Update bit

1 = Request update to SMTxPRx registers
0 = SMTxPRx registers update is complete
bit 6 CPWUP: SMT Manual Pulse Width Buffer Update bit
1 = Request update to SMTxCPW registers
0 = SMTxCPW registers update is complete
bit 5 RST: SMT Manual Timer Reset bit
1 = Request Reset to SMTxTMR registers
0 = SMTxTMR registers update is complete
bit 2 TS: SMT GO Value Status bit
1 = SMT timer is incrementing
0 = SMT timer is not incrementing
bit 1 WS: SMTxWIN Value Status bit
1 = SMT window is open
0 = SMT window is closed
bit 0 AS: SMT_signal Value Status bit
1 = SMT acquisition is in progress
0 = SMT acquisition is not in progress

PIC16(L)F18857/77
REGISTER 32-4: SMTxCLK: SMT CLOCK SELECTION REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — CSEL<2:0>
bit 7 bit 0
Legend:

bit 2-0 CSEL<2:0>: SMT Clock Selection bits
111 = Reference Clock Output
110 = SOSC
101 = MFINTOSC/16
100 = MFINTOSC
011 = LFINTOSC
010 = HFINTOSC 16 MHz
001 = FOSC
000 = FOSC/4

PIC16(L)F18857/77
REGISTER 32-5: SMTxWIN: SMT1 WINDOW INPUT SELECT REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — WSEL<4:0>
bit 7 bit 0
Legend:

bit 4-0 WSEL<4:0>: SMTx Window Selection bits
11111 = Reserved
•
•
•
11000 = Reserved
10111 = LC4_out
10110 = LC3_out
10101 = LC2_out
10100 = LC1_out
10011 = ZCD1_output
10010 = C2OUT_sync
10001 = C1OUT_sync
10000 = PWM7_out
01111 = PWM6_out
01110 = CCP5_out
01101 = CCP4_out
01100 = CCP3_out
01011 = CCP2_out
01010 = CCP1_out
01001 = SMT2_match(1)
01000 = SMT1_match(1)
00100 = TMR0_overflow
00011 = SOSC
00010 = MFINTOSC/16
00001 = LFINTOSC
00000 = SMTxWINPPS
Note 1: The SMT_match corresponding to the SMT selected becomes reserved.

PIC16(L)F18857/77
REGISTER 32-6: SMTxSIG: SMT1 SIGNAL INPUT SELECT REGISTER

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — SSEL<4:0>
bit 7 bit 0
Legend:

bit 4-0 SSEL<4:0>: SMTx Signal Selection bits
11111 = Reserved
•
•
•
11000 = LC4_out
10111 = LC3_out
10110 = LC2_out
10101 = LC1_out
10100 = ZCD1_output
10011 = C2OUT_sync
10010 = C1OUT_sync
10001 = NCO output
10000 = PWM7_out
01111 = PWM6_out
01110 = CCP5_out
01101 = CCP4_out
01100 = CCP3_out
01011 = CCP2_out
01010 = CCP1_out
01001 = SMT2_match(1)
01000 = SMT1_match(1)
00001 = TMR0_overflow
00000 = SMTxSIGPPS
Note 1: The SMT_match corresponding to the SMT selected becomes reserved.

PIC16(L)F18857/77
REGISTER 32-7: SMTxTMRL: SMT TIMER REGISTER – LOW BYTE

SMTxTMR<7:0>
bit 7 bit 0
Legend:
bit 7-0 SMTxTMR<7:0>: Significant bits of the SMT Counter – Low Byte
REGISTER 32-8: SMTxTMRH: SMT TIMER REGISTER – HIGH BYTE

SMTxTMR<15:8>
bit 7 bit 0
Legend:
bit 7-0 SMTxTMR<15:8>: Significant bits of the SMT Counter – High Byte
REGISTER 32-9: SMTxTMRU: SMT TIMER REGISTER – UPPER BYTE

SMTxTMR<23:16>
bit 7 bit 0
Legend:
bit 7-0 SMTxTMR<23:16>: Significant bits of the SMT Counter – Upper Byte

PIC16(L)F18857/77
REGISTER 32-10: SMTxCPRL: SMT CAPTURED PERIOD REGISTER – LOW BYTE

R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x
SMTxCPR<7:0>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPR<7:0>: Significant bits of the SMT Period Latch – Low Byte
REGISTER 32-11: SMTxCPRH: SMT CAPTURED PERIOD REGISTER – HIGH BYTE

SMTxCPR<15:8>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPR<15:8>: Significant bits of the SMT Period Latch – High Byte
REGISTER 32-12: SMTxCPRU: SMT CAPTURED PERIOD REGISTER – UPPER BYTE

SMTxCPR<23:16>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPR<23:16>: Significant bits of the SMT Period Latch – Upper Byte

PIC16(L)F18857/77
REGISTER 32-13: SMTxCPWL: SMT CAPTURED PULSE WIDTH REGISTER – LOW BYTE
SMTxCPW<7:0>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPW<7:0>: Significant bits of the SMT PW Latch – Low Byte
REGISTER 32-14: SMTxCPWH: SMT CAPTURED PULSE WIDTH REGISTER – HIGH BYTE
SMTxCPW<15:8>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPW<15:8>: Significant bits of the SMT PW Latch – High Byte
REGISTER 32-15: SMTxCPWU: SMT CAPTURED PULSE WIDTH REGISTER – UPPER BYTE
SMTxCPW<23:16>
bit 7 bit 0
Legend:
bit 7-0 SMTxCPW<23:16>: Significant bits of the SMT PW Latch – Upper Byte

PIC16(L)F18857/77
REGISTER 32-16: SMTxPRL: SMT PERIOD REGISTER – LOW BYTE

R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1
SMTxPR<7:0>
bit 7 bit 0
Legend:
bit 7-0 SMTxPR<7:0>: Significant bits of the SMT Timer Value for Period Match – Low Byte
REGISTER 32-17: SMTxPRH: SMT PERIOD REGISTER – HIGH BYTE

SMTxPR<15:8>
bit 7 bit 0
Legend:
bit 7-0 SMTxPR<15:8>: Significant bits of the SMT Timer Value for Period Match – High Byte
REGISTER 32-18: SMTxPRU: SMT PERIOD REGISTER – UPPER BYTE

SMTxPR<23:16>
bit 7 bit 0
Legend:
bit 7-0 SMTxPR<23:16>: Significant bits of the SMT Timer Value for Period Match – Upper Byte

PIC16(L)F18857/77
TABLE 32-3: SUMMARY OF REGISTERS ASSOCIATED WITH SMTx
Register
on Page
PIE8 — — SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE 142

PIR8 — — SMT2PWAIF SMT2PRAIF SMT2IF SMT1PWAIF SMT1PRAIF SMT1IF 152
SMT1TMRL SMT1TMR<7:0> 538
SMT1TMRH SMT1TMR<15:8> 538
SMT1TMRU SMT1TMR<23:16> 538
SMT1CPRL SMT1CPR<7:0> 539
SMT1CPRH SMT1CPR<15:8> 539
SMT1CPRU SMT1CPR<23:16> 539
SMT1CPWL SMT1CPW<7:0> 540
SMT1CPWH SMT1CPW<15:8> 540
SMT1CPWU SMT1CPW<23:16> 540
SMT1PRL SMT1PR<7:0> 541
SMT1PRH SMT1PR<15:8> 541
SMT1PRU SMT1PR<23:16> 541
SMT1CON0 EN — STP WPOL SPOL CPOL SMT1PS<1:0> 532
SMT1CON1 SMT1GO REPEAT — — MODE<3:0> 533
SMT1STAT CPRUP CPWUP RST — — TS WS AS 534
SMT1CLK — — — — — CSEL<2:0> 535
SMT1SIG — — — SSEL<4:0> 537
SMT1WIN — — — WSEL<4:0> 536
SMT2TMRL SMT2TMR<7:0> 538
SMT2TMRH SMT2TMR<15:8> 538
SMT2TMRU SMT2TMR<23:16> 538
SMT2CPRL SMT2CPR<7:0> 539
SMT2CPRH SMT2CPR<15:8> 539
SMT2CPRU SMT2CPR<23:16> 539
SMT2CPWL SMT2CPW<7:0> 540
SMT2CPWH SMT2CPW<15:8> 540
SMT2CPWU SMT2CPW<23:16> 540
SMT2PRL SMT2PR<7:0> 541
SMT2PRH SMT2PR<15:8> 541
SMT2PRU SMT2PR<23:16> 541
SMT2CON0 EN — STP WPOL SPOL CPOL SMT2PS<1:0> 532
SMT2CON1 SMT2GO REPEAT — — MODE<3:0> 533
SMT2STAT CPRUP CPWUP RST — — TS WS AS 534
SMT2CLK — — — — — CSEL<2:0> 535
SMT2SIG — — — SSEL<4:0> 537
SMT2WIN — — — WSEL<4:0> 536
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for SMTx module.

PIC16(L)F18857/77
33.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities:
SYNCHRONOUS • Full-duplex asynchronous transmit and receive
ASYNCHRONOUS RECEIVER • Two-character input buffer
TRANSMITTER (EUSART) • One-character output buffer
• Programmable 8-bit or 9-bit character length
The Enhanced Universal Synchronous Asynchronous
• Address detection in 9-bit mode
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock • Input buffer overrun error detection
generators, shift registers and data buffers necessary • Received character framing error detection
to perform an input or output serial data transfer • Half-duplex synchronous host
independent of device program execution. The • Half-duplex synchronous client
EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous
Interface (SCI), can be configured as a full-duplex modes
asynchronous system or half-duplex synchronous
• Sleep operation
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT The EUSART module implements the following
terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in
Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems:
with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate
circuits, serial EEPROMs or other microcontrollers.
• Wake-up on Break reception
These devices typically do not have internal clocks for
baud rate generation and require the external clock • 13-bit Break character transmit
signal provided by a host synchronous device. Block diagrams of the EUSART transmitter and
receiver are shown in Figure 33-1 and Figure 33-2.
The EUSART transmit output (TX_out) is available to
the TX/CK pin and internally to the following peripherals:
• Configurable Logic Cell (CLC)
FIGURE 33-1: EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIE
SYNC
Interrupt
CSRC
TXxREG Register TXIF
8 RxyPPS(1)
CK pin TXEN
MSb LSb RX/DT pin
PPS 1 (8) 0 Pin Buffer
• • • and Control PPS
0 Transmit Shift Register (TSR)
CKPPS SYNC
TRMT TX_out
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D TX/CK pin
SYNC 1 X 0 0 0 0
PPS
SPxBRGH SPxBRGL BRGH X 1 1 0 0
1
BRG16 X 1 0 1 0
RxyPPS
SYNC
Note 1: In Synchronous mode the DT output and RX input PPS CSRC
selections should enable the same pin.

PIC16(L)F18857/77
FIGURE 33-2: EUSART RECEIVE BLOCK DIAGRAM
SPEN CREN OERR RCIDL
RXPPS(1)
RX/DT pin MSb RSR Register LSb
Pin Buffer Data
PPS and Control Recovery
Stop (8) 7 ••• 1 0 Start
Baud Rate Generator FOSC RX9

÷n
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPxBRGH SPxBRGL BRGH X 1 1 0 0 FIFO
FERR RX9D RCxREG Register
BRG16 X 1 0 1 0
8
Data Bus
Note 1: In Synchronous mode the DT output and RX input PPS RCIF Interrupt
selections should enable the same pin. RCIE
The operation of the EUSART module is controlled

through three registers:
• Transmit Status and Control (TX1STA)
• Receive Status and Control (RC1STA)
• Baud Rate Control (BAUD1CON)
These registers are detailed in Register 33-1,
Register 33-2 and Register 33-3, respectively.
The RX input pin is selected with the RXPPS. The CK
input is selected with the TXPPS register. TX, CK, and
DT output pins are selected with each pin’s RxyPPS
register. Since the RX input is coupled with the DT output
in Synchronous mode, it is the user’s responsibility to
select the same pin for both of these functions when
operating in Synchronous mode. The EUSART control
logic will control the data direction drivers automatically.

PIC16(L)F18857/77
33.1 EUSART Asynchronous Mode 33.1.1.2 Transmitting Data
The EUSART transmits and receives data using the A transmission is initiated by writing a character to the
standard non-return-to-zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the
implemented with two levels: a VOH Mark state which previous character has been completely flushed from
represents a ‘1’ data bit, and a VOL Space state which the TSR, the data in the TXREG is immediately
represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains
consecutively transmitted data bits of the same value all or part of a previous character, the new character
stay at the output level of that bit without returning to a data is held in the TXREG until the Stop bit of the
neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending
transmission port idles in the Mark state. Each character character in the TXREG is then transferred to the TSR
transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit
or nine data bits and is always terminated by one or transmission. The transmission of the Start bit, data bits
more Stop bits. The Start bit is always a space and the and Stop bit sequence commences immediately
Stop bits are always marks. The most common data following the transfer of the data to the TSR from the
format is eight bits. Each transmitted bit persists for a TXREG.
period of 1/(Baud Rate). An on-chip dedicated
8-bit/16-bit Baud Rate Generator is used to derive 33.1.1.3 Transmit Data Polarity
standard baud rate frequencies from the system The polarity of the transmit data can be controlled with
oscillator. See Table 33-3 for examples of baud rate the SCKP bit of the BAUD1CON register. The default
configurations. state of this bit is ‘0’ which selects high true transmit idle
The EUSART transmits and receives the LSb first. The and data bits. Setting the SCKP bit to ‘1’ will invert the
EUSART’s transmitter and receiver are functionally transmit data resulting in low true idle and data bits. The
independent, but share the same data format and baud SCKP bit controls transmit data polarity in
rate. Parity is not supported by the hardware, but can Asynchronous mode only. In Synchronous mode, the
be implemented in software and stored as the ninth SCKP bit has a different function. See Section 33.4.1.2
data bit. “Clock Polarity”.
33.1.1 EUSART ASYNCHRONOUS 33.1.1.4 Transmit Interrupt Flag

TRANSMITTER The TXIF interrupt flag bit of the PIR3 register is set
whenever the EUSART transmitter is enabled and no
The EUSART transmitter block diagram is shown in
character is being held for transmission in the TXREG.
Figure 33-1. The heart of the transmitter is the serial
In other words, the TXIF bit is only clear when the TSR
Transmit Shift Register (TSR), which is not directly
is busy with a character and a new character has been
accessible by software. The TSR obtains its data from
queued for transmission in the TXREG. The TXIF flag bit
the transmit buffer, which is the TXREG register.
is not cleared immediately upon writing TXREG. TXIF
33.1.1.1 Enabling the Transmitter becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
The EUSART transmitter is enabled for asynchronous the TXREG write will return invalid results. The TXIF bit
operations by configuring the following three control is read-only, it cannot be set or cleared by software.
bits:
The TXIF interrupt can be enabled by setting the TXIE
• TXEN = 1 interrupt enable bit of the PIE3 register. However, the
• SYNC = 0 TXIF flag bit will be set whenever the TXREG is empty,
• SPEN = 1 regardless of the state of TXIE enable bit.
All other EUSART control bits are assumed to be in To use interrupts when transmitting data, set the TXIE
their default state. bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
Setting the TXEN bit of the TX1STA register enables the
of the transmission to the TXREG.
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TX1STA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RC1STA register enables the EUSART and
automatically configures the TX/CK I/O pin as an output.
If the TX/CK pin is shared with an analog peripheral, the
analog I/O function must be disabled by clearing the
corresponding ANSEL bit.
Note: The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.

PIC16(L)F18857/77
33.1.1.5 TSR Status 33.1.1.7 Asynchronous Transmission Set-up:
The TRMT bit of the TX1STA register indicates the 1. Initialize the SPBRGH, SPBRGL register pair and
status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired
TRMT bit is set when the TSR register is empty and is baud rate (see Section 33.3 “EUSART Baud
cleared when a character is transferred to the TSR Rate Generator (BRG)”).
register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing
until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit.
No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9
poll this bit to determine the TSR status. control bit. A set ninth data bit will indicate that
Note: The TSR register is not mapped in data the eight Least Significant data bits are an
memory, so it is not available to the user. address when the receiver is set for address
detection.
33.1.1.6 Transmitting 9-Bit Characters 4. Set SCKP bit if inverted transmit is desired.
The EUSART supports 9-bit character transmissions. 5. Enable the transmission by setting the TXEN
When the TX9 bit of the TX1STA register is set, the control bit. This will cause the TXIF interrupt bit
EUSART will shift nine bits out for each character trans- to be set.
mitted. The TX9D bit of the TX1STA register is the 6. If interrupts are desired, set the TXIE interrupt
ninth, and Most Significant data bit. When transmitting enable bit of the PIE3 register. An interrupt will
9-bit data, the TX9D data bit must be written before occur immediately provided that the GIE and
writing the eight Least Significant bits into the TXREG. PEIE bits of the INTCON register are also set.
All nine bits of data will be transferred to the TSR shift 7. If 9-bit transmission is selected, the ninth bit
register immediately after the TXREG is written. should be loaded into the TX9D data bit.
A special 9-bit Address mode is available for use with 8. Load 8-bit data into the TXREG register. This
multiple receivers. See Section 33.1.2.7 “Address will start the transmission.
Detection” for more information on the Address mode.
FIGURE 33-3: ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)

PIC16(L)F18857/77
FIGURE 33-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY
TRMT bit Word 1 Word 2

(Transmit Shift Transmit Shift Reg. Transmit Shift Reg.
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
33.1.2 EUSART ASYNCHRONOUS 33.1.2.2 Receiving Data

RECEIVER The receiver data recovery circuit initiates character
The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit,
systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data
Figure 33-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of
drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is
is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts
the baud rate, whereas the serial Receive Shift character reception, without generating an error, and
Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If
or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data
are immediately transferred to a two character recovery circuit counts a full bit time to the center of the
First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect
allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
start of a third character before software must start This repeats until all data bits have been sampled and
servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and
registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always
Access to the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
33.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this
The EUSART receiver is enabled for asynchronous character. See Section 33.1.2.4 “Receive Framing
operation by configuring the following three control bits: Error” for more information on framing errors.
• CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
• SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
• SPEN = 1 flag bit of the PIR3 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCREG register.
Setting the CREN bit of the RC1STA register enables Note: If the receive FIFO is overrun, no additional
the receiver circuitry of the EUSART. Clearing the SYNC characters will be received until the overrun
bit of the TX1STA register configures the EUSART for condition is cleared. See Section 33.1.2.5
asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more
RC1STA register enables the EUSART. The information on overrun errors.
programmer must set the corresponding TRIS bit to
configure the RX/DT I/O pin as an input.
Note: If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.

PIC16(L)F18857/77
33.1.2.3 Receive Interrupts 33.1.2.6 Receiving 9-Bit Characters
The RCIF interrupt flag bit of the PIR3 register is set The EUSART supports 9-bit character reception. When
whenever the EUSART receiver is enabled and there is the RX9 bit of the RC1STA register is set the EUSART
an unread character in the receive FIFO. The RCIF will shift nine bits into the RSR for each character
interrupt flag bit is read-only, it cannot be set or cleared received. The RX9D bit of the RC1STA register is the
by software. ninth and Most Significant data bit of the top unread
RCIF interrupts are enabled by setting all of the character in the receive FIFO. When reading 9-bit data
following bits: from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
• RCIE, Interrupt Enable bit of the PIE3 register from the RCREG.
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register 33.1.2.7 Address Detection
• GIE, Global Interrupt Enable bit of the INTCON A special Address Detection mode is available for use
register when multiple receivers share the same transmission
The RCIF interrupt flag bit will be set when there is an line, such as in RS-485 systems. Address detection is
unread character in the FIFO, regardless of the state of enabled by setting the ADDEN bit of the RC1STA
interrupt enable bits. register.
Address detection requires 9-bit character reception.
33.1.2.4 Receive Framing Error When address detection is enabled, only characters
Each character in the receive FIFO buffer has a with the ninth data bit set will be transferred to the
corresponding framing error Status bit. A framing error receive FIFO buffer, thereby setting the RCIF interrupt
indicates that a Stop bit was not seen at the expected bit. All other characters will be ignored.
time. The framing error status is accessed via the Upon receiving an address character, user software
FERR bit of the RC1STA register. The FERR bit determines if the address matches its own. Upon
represents the status of the top unread character in the address match, user software must disable address
receive FIFO. Therefore, the FERR bit must be read detection by clearing the ADDEN bit before the next
before reading the RCREG. Stop bit occurs. When user software detects the end of
The FERR bit is read-only and only applies to the top the message, determined by the message protocol
unread character in the receive FIFO. A framing error used, software places the receiver back into the
(FERR = 1) does not preclude reception of additional Address Detection mode by setting the ADDEN bit.
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RC1STA register which resets the EUSART.
Clearing the CREN bit of the RC1STA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
33.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RC1STA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RC1STA register or by
resetting the EUSART by clearing the SPEN bit of the
RC1STA register.

PIC16(L)F18857/77
33.1.2.8 Asynchronous Reception Setup: 33.1.2.9 9-bit Address Detection Mode Setup
1. Initialize the SPBRGH, SPBRGL register pair This mode would typically be used in RS-485 systems.
and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address
desired baud rate (see Section 33.3 “EUSART Detect Enable:
Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRGL register pair
2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the
3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section 33.3 “EUSART
The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”).
operation. 2. Clear the ANSEL bit for the RX pin (if applicable).
4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit.
PIE3 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous
INTCON register. operation.
5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the
6. Enable reception by setting the CREN bit. PIE3 register and the GIE and PEIE bits of the
7. The RCIF interrupt flag bit will be set when a INTCON register.
character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit.
receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN
the RCIE interrupt enable bit was also set. bit.
8. Read the RC1STA register to get the error flags 7. Enable reception by setting the CREN bit.
and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a
data bit. character with the ninth bit set is transferred
9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt
from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit
register. was also set.
10. If an overrun occurred, clear the OERR flag by 9. Read the RC1STA register to get the error flags.
clearing the CREN receiver enable bit. The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 33-5: ASYNCHRONOUS RECEPTION

Start Start Start
RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift
Reg
Rcv Buffer Reg.
Word 1 Word 2
RCREG RCREG
RCIDL
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.

PIC16(L)F18857/77
33.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (INTOSC). However, the INTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two
methods may be used to adjust the baud rate clock, but
both require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See
Section 6.2.2.2 “Internal Oscillator Frequency
Adjustment” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 33.3.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.

PIC16(L)F18857/77
33.3 EUSART Baud Rate Generator EXAMPLE 33-1: CALCULATING BAUD
(BRG) RATE ERROR
The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate
timer that is dedicated to the support of both the of 9600, Asynchronous mode, 8-bit BRG:
asynchronous and synchronous EUSART operation. F OS C
Desired Baud Rate = -----------------------------------------------------------------------
-
By default, the BRG operates in 8-bit mode. Setting the 64  [SPBRGH:SPBRGL] + 1 
BRG16 bit of the BAUD1CON register selects 16-bit Solving for SPBRGH:SPBRGL:
mode.
F OS C
---------------------------------------------
The SPBRGH, SPBRGL register pair determines the Desired Baud Rate – 1
period of the free running baud rate timer. In X = ---------------------------------------------
64
Asynchronous mode the multiplier of the baud rate
16000000
period is determined by both the BRGH bit of the ------------------------
9600 - – 1
= -----------------------
TX1STA register and the BRG16 bit of the BAUD1CON 64
register. In Synchronous mode, the BRGH bit is ignored.
=  25.042  = 25
Table 33-1 contains the formulas for determining the
baud rate. Example 33-1 provides a sample calculation 16000000-
Calculated Baud Rate = --------------------------
for determining the baud rate and baud rate error. 64  25 + 1 
Typical baud rates and error values for various = 9615
Asynchronous modes have been computed for your
convenience and are shown in Table 33-3. It may be Error = Calc. Baud Rate – Desired Baud Rate-
-------------------------------------------------------------------------------------------
advantageous to use the high baud rate (BRGH = 1), Desired Baud Rate
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow = ----------------------------------
9615 – 9600  = 0.16%
9600
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRGL register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is idle before
changing the system clock.

PIC16(L)F18857/77
33.3.1 AUTO-BAUD DETECT and SPBRGL registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
The EUSART module supports automatic detection
average bit time when clocked at full speed.
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
In the Auto-Baud Detect (ABD) mode, the clock to the
auto-baud detection will occur on the byte
BRG is reversed. Rather than the BRG clocking the
following the Break character (see
incoming RX signal, the RX signal is timing the BRG.
Section 33.3.3 “Auto-Wake-up on
The Baud Rate Generator is used to time the period of
Break”).
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the
that it has five rising edges including the Stop bit edge. incoming character baud rate is within the
range of the selected BRG clock source.
Setting the ABDEN bit of the BAUD1CON register
Some combinations of oscillator frequency
starts the auto-baud calibration sequence. While the
and EUSART baud rates are not possible.
ABD sequence takes place, the EUSART state
machine is held in Idle. On the first rising edge of the 3: During the auto-baud process, the
receive line, after the Start bit, the SPBRG begins auto-baud counter starts counting at one.
counting up using the BRG counter clock as shown in Upon completion of the auto-baud
Figure 33-6. The fifth rising edge will occur on the RX sequence, to achieve maximum accuracy,
pin at the end of the eighth bit period. At that time, an subtract 1 from the SPBRGH:SPBRGL
accumulated value totaling the proper BRG period is register pair.
left in the SPBRGH, SPBRGL register pair, the ABDEN
bit is automatically cleared and the RCIF interrupt flag TABLE 33-1: BRG COUNTER CLOCK RATES
is set. The value in the RCREG needs to be read to
BRG Base BRG ABD
clear the RCIF interrupt. RCREG content should be BRG16 BRGH
Clock Clock
discarded. When calibrating for modes that do not use
the SPBRGH register the user can verify that the 0 0 FOSC/64 FOSC/512
SPBRGL register did not overflow by checking for 00h
in the SPBRGH register. 0 1 FOSC/16 FOSC/128
The BRG auto-baud clock is determined by the BRG16 1 0 FOSC/16 FOSC/128

and BRGH bits as shown in Table 33-1. During ABD, 1 1 FOSC/4 FOSC/32
both the SPBRGH and SPBRGL registers are used as Note: During the ABD sequence, SPBRGL and
a 16-bit counter, independent of the BRG16 bit setting. SPBRGH registers are both used as a 16-bit
While calibrating the baud rate period, the SPBRGH counter, independent of the BRG16 setting.
FIGURE 33-6: AUTOMATIC BAUD RATE CALIBRATION
BRG Value XXXXh 0000h 001Ch
Edge #1 Edge #2 Edge #3 Edge #4 Edge #5

RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit
BRG Clock
Set by User Auto Cleared

ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRGL XXh 1Ch
SPBRGH XXh 00h
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

PIC16(L)F18857/77
33.3.2 AUTO-BAUD OVERFLOW 33.3.3.1 Special Considerations
During the course of automatic baud detection, the Break Character
ABDOVF bit of the BAUD1CON register will be set if To avoid character errors or character fragments during
the baud rate counter overflows before the fifth rising a wake-up event, the wake-up character must be all
edge is detected on the RX pin. The ABDOVF bit indi- zeros.
cates that the counter has exceeded the maximum
count that can fit in the 16 bits of the When the wake-up is enabled the function works
SPBRGH:SPBRGL register pair. The overflow condi- independent of the low time on the data stream. If the
tion will set the RCIF flag. The counter continues to WUE bit is set and a valid non-zero character is
count until the fifth rising edge is detected on the RX received, the low time from the Start bit to the first rising
pin. The RCIDL bit will remain false (‘0’) until the fifth edge will be interpreted as the wake-up event. The
rising edge at which time the RCIDL bit will be set. If the remaining bits in the character will be received as a
RCREG is read after the overflow occurs but before the fragmented character and subsequent characters can
fifth rising edge then the fifth rising edge will set the result in framing or overrun errors.
RCIF again. Therefore, the initial character in the transmission must
Terminating the auto-baud process early to clear an be all ‘0’s. This must be ten or more bit times, 13-bit
overflow condition will prevent proper detection of the times recommended for LIN bus, or any number of bit
sync character fifth rising edge. If any falling edges of times for standard RS-232 devices.
the sync character have not yet occurred when the Oscillator Start-up Time
ABDEN bit is cleared then those will be falsely detected
Oscillator start-up time must be considered, especially
as Start bits. The following steps are recommended to
in applications using oscillators with longer start-up
clear the overflow condition:
intervals (i.e., LP, XT or HS/PLL mode). The Sync
1. Read RCREG to clear RCIF. Break (or wake-up signal) character must be of
2. If RCIDL is ‘0’ then wait for RDCIF and repeat sufficient length, and be followed by a sufficient
step 1. interval, to allow enough time for the selected oscillator
3. Clear the ABDOVF bit. to start and provide proper initialization of the EUSART.
WUE Bit
33.3.3 AUTO-WAKE-UP ON BREAK
The wake-up event causes a receive interrupt by
During Sleep mode, all clocks to the EUSART are setting the RCIF bit. The WUE bit is cleared in
suspended. Because of this, the Baud Rate Generator hardware by a rising edge on RX/DT. The interrupt
is inactive and a proper character reception cannot be condition is then cleared in software by reading the
performed. The Auto-Wake-up feature allows the RCREG register and discarding its contents.
controller to wake-up due to activity on the RX/DT line.
To ensure that no actual data is lost, check the RCIDL
This feature is available only in Asynchronous mode.
bit to verify that a receive operation is not in process
The Auto-Wake-up feature is enabled by setting the before setting the WUE bit. If a receive operation is not
WUE bit of the BAUD1CON register. Once set, the occurring, the WUE bit may then be set just prior to
normal receive sequence on RX/DT is disabled, and the entering the Sleep mode.
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 33-7), and asynchronously if
the device is in Sleep mode (Figure 33-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in IDLE mode waiting to
receive the next character.

PIC16(L)F18857/77
FIGURE 33-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto Cleared
WUE bit
RX/DT Line
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 33-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1
Bit Set by User Auto Cleared
WUE bit
RX/DT Line Note 1
RCIF
Cleared due to User Read of RCREG
Sleep Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
33.3.4 BREAK CHARACTER SEQUENCE 33.3.4.1 Break and Sync Transmit Sequence
The EUSART module has the capability of sending the The following sequence will start a message frame
special Break character sequences that are required by header made up of a Break, followed by an auto-baud
the LIN bus standard. A Break character consists of a Sync byte. This sequence is typical of a LIN bus host.
Start bit, followed by 12 ‘0’ bits and a Stop bit. 1. Configure the EUSART for the desired mode.
To send a Break character, set the SENDB and TXEN 2. Set the TXEN and SENDB bits to enable the
bits of the TX1STA register. The Break character trans- Break sequence.
mission is then initiated by a write to the TXREG. The 3. Load the TXREG with a dummy character to
value of data written to TXREG will be ignored and all initiate transmission (the value is ignored).
‘0’s will be transmitted.
4. Write ‘55h’ to TXREG to load the Sync character
The SENDB bit is automatically reset by hardware after into the transmit FIFO buffer.
the corresponding Stop bit is sent. This allows the user 5. After the Break has been sent, the SENDB bit is
to preload the transmit FIFO with the next transmit byte reset by hardware and the Sync character is
following the Break character (typically, the Sync then transmitted.
character in the LIN specification).
When the TXREG becomes empty, as indicated by the
The TRMT bit of the TX1STA register indicates when the TXIF, the next data byte can be written to TXREG.
transmit operation is active or idle, just as it does during
normal transmission. See Figure 33-9 for the timing of
the Break character sequence.

PIC16(L)F18857/77
33.3.5 RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RC1STA register and the received data
as indicated by RCREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when:
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
The second method uses the Auto-Wake-up feature
described in Section 33.3.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUD1CON register before placing the EUSART in
Sleep mode.
FIGURE 33-9: SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit

Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)

PIC16(L)F18857/77
33.4 EUSART Synchronous Mode 33.4.1.2 Clock Polarity
Synchronous serial communications are typically used A clock polarity option is provided for Microwire
in systems with a single host and one or more clients. compatibility. Clock polarity is selected with the SCKP
The host device contains the necessary circuitry for bit of the BAUD1CON register. Setting the SCKP bit
baud rate generation and supplies the clock for all sets the clock Idle state as high. When the SCKP bit is
devices in the system. Client devices can take advan- set, the data changes on the falling edge of each clock.
tage of the host clock by eliminating the internal clock Clearing the SCKP bit sets the Idle state as low. When
generation circuitry. the SCKP bit is cleared, the data changes on the rising
edge of each clock.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Clients use the 33.4.1.3 Synchronous Host Transmission
external clock supplied by the host to shift the serial
data into and out of their respective receive and trans- Data is transferred out of the device on the RX/DT pin.
mit shift registers. Since the data line is bidirectional, The RX/DT and TX/CK pin output drivers are automat-
synchronous operation is half-duplex only. Half-duplex ically enabled when the EUSART is configured for
refers to the fact that host and client devices can synchronous host transmit operation.
receive and transmit data but not both simultaneously. A transmission is initiated by writing a character to the
The EUSART can operate as either a host or client TXREG register. If the TSR still contains all or part of a
device. previous character the new character data is held in the
Start and Stop bits are not used in synchronous TXREG until the last bit of the previous character has
transmissions. been transmitted. If this is the first character, or the
previous character has been completely flushed from
33.4.1 SYNCHRONOUS HOST MODE the TSR, the data in the TXREG is immediately trans-
ferred to the TSR. The transmission of the character
The following bits are used to configure the EUSART commences immediately following the transfer of the
for synchronous host operation: data to the TSR from the TXREG.
• SYNC = 1 Each data bit changes on the leading edge of the host
• CSRC = 1 clock and remains valid until the subsequent leading
• SREN = 0 (for transmit); SREN = 1 (for receive) clock edge.
• CREN = 0 (for transmit); CREN = 1 (for receive) Note: The TSR register is not mapped in data
• SPEN = 1 memory, so it is not available to the user.
Setting the SYNC bit of the TX1STA register configures
the device for synchronous operation. Setting the CSRC 33.4.1.4 Synchronous Host Transmission
bit of the TX1STA register configures the device as a Set-up:
host. Clearing the SREN and CREN bits of the RC1STA 1. Initialize the SPBRGH, SPBRGL register pair
register ensures that the device is in the Transmit mode, and the BRGH and BRG16 bits to achieve the
otherwise the device will be configured to receive. Setting desired baud rate (see Section 33.3 “EUSART
the SPEN bit of the RC1STA register enables the Baud Rate Generator (BRG)”).
EUSART.
2. Enable the synchronous host serial port by set-
33.4.1.1 Host Clock ting bits SYNC, SPEN and CSRC.
3. Disable Receive mode by clearing bits SREN
Synchronous data transfers use a separate clock line,
and CREN.
which is synchronous with the data. A device config-
ured as a host transmits the clock on the TX/CK line. 4. Enable Transmit mode by setting the TXEN bit.
The TX/CK pin output driver is automatically enabled 5. If 9-bit transmission is desired, set the TX9 bit.
when the EUSART is configured for synchronous 6. If interrupts are desired, set the TXIE bit of the
transmit or receive operation. Serial data bits change PIE3 register and the GIE and PEIE bits of the
on the leading edge to ensure they are valid at the INTCON register.
trailing edge of each clock. One clock cycle is gener- 7. If 9-bit transmission is selected, the ninth bit
ated for each data bit. Only as many clock cycles are should be loaded in the TX9D bit.
generated as there are data bits. 8. Start transmission by loading data to the TXREG
register.

PIC16(L)F18857/77
FIGURE 33-10: SYNCHRONOUS TRANSMISSION
RX/DT
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Host mode, SPBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 33-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
33.4.1.5 Synchronous Host Reception To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
Data is received at the RX/DT pin. The RX/DT pin
TX/CK clock pin and is shifted into the Receive Shift
output driver is automatically disabled when the
Register (RSR). When a complete character is
EUSART is configured for synchronous host receive
received into the RSR, the RCIF bit is set and the char-
operation.
acter is automatically transferred to the two character
In Synchronous mode, reception is enabled by setting receive FIFO. The Least Significant eight bits of the top
either the Single Receive Enable bit (SREN of the character in the receive FIFO are available in RCREG.
RC1STA register) or the Continuous Receive Enable The RCIF bit remains set as long as there are unread
bit (CREN of the RC1STA register). characters in the receive FIFO.
When SREN is set and CREN is clear, only as many Note: If the RX/DT function is on an analog pin,
clock cycles are generated as there are data bits in a the corresponding ANSEL bit must be
single character. The SREN bit is automatically cleared cleared for the receiver to function.
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.

PIC16(L)F18857/77
33.4.1.6 Client Clock received. The RX9D bit of the RC1STA register is the
ninth, and Most Significant, data bit of the top unread
Synchronous data transfers use a separate clock line,
character in the receive FIFO. When reading 9-bit data
which is synchronous with the data. A device configured
from the receive FIFO buffer, the RX9D data bit must
as a client receives the clock on the TX/CK line. The
be read before reading the eight Least Significant bits
TX/CK pin output driver is automatically disabled when
from the RCREG.
the device is configured for synchronous client transmit
or receive operation. Serial data bits change on the
33.4.1.9 Synchronous Host Reception
leading edge to ensure they are valid at the trailing edge
Set-up:
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as 1. Initialize the SPBRGH, SPBRGL register pair for
there are data bits. the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
Note: If the device is configured as a client and the desired baud rate.
the TX/CK function is on an analog pin, the
2. Clear the ANSEL bit for the RX pin (if applicable).
corresponding ANSEL bit must be cleared.
3. Enable the synchronous host serial port by set-
33.4.1.7 Receive Overrun Error ting bits SYNC, SPEN and CSRC.
4. Ensure bits CREN and SREN are clear.
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its 5. If interrupts are desired, set the RCIE bit of the
entirety, is received before RCREG is read to access PIE3 register and the GIE and PEIE bits of the
the FIFO. When this happens the OERR bit of the INTCON register.
RC1STA register is set. Previous data in the FIFO will 6. If 9-bit reception is desired, set bit RX9.
not be overwritten. The two characters in the FIFO 7. Start reception by setting the SREN bit or for
buffer can be read, however, no additional characters continuous reception, set the CREN bit.
will be received until the error is cleared. The OERR bit 8. Interrupt flag bit RCIF will be set when reception
can only be cleared by clearing the overrun condition. of a character is complete. An interrupt will be
If the overrun error occurred when the SREN bit is set generated if the enable bit RCIE was set.
and CREN is clear then the error is cleared by reading 9. Read the RC1STA register to get the ninth bit (if
RCREG. If the overrun occurred when the CREN bit is enabled) and determine if any error occurred
set then the error condition is cleared by either clearing during reception.
the CREN bit of the RC1STA register or by clearing the
10. Read the 8-bit received data by reading the
SPEN bit which resets the EUSART.
RCREG register.
33.4.1.8 Receiving 9-bit Characters 11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RC1STA
The EUSART supports 9-bit character reception. When
register or by clearing the SPEN bit which resets
the RX9 bit of the RC1STA register is set the EUSART
the EUSART.
will shift nine bits into the RSR for each character
FIGURE 33-12: SYNCHRONOUS RECEPTION (HOST MODE, SREN)
RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’ ‘0’
RCIF bit
(Interrupt)
Read
RCREG
Note: Timing diagram demonstrates Sync Host mode with bit SREN = 1 and bit BRGH = 0.

PIC16(L)F18857/77
33.4.2 SYNCHRONOUS CLIENT MODE 33.4.2.1 EUSART Synchronous Client
The following bits are used to configure the EUSART Transmit
for synchronous client operation: The operation of the Synchronous Host and Client modes
• SYNC = 1 are identical (see Section 33.4.1.3 “Synchronous
Host Transmission”), except in the case of the Sleep
• CSRC = 0
mode.
• SREN = 0 (for transmit); SREN = 1 (for receive)
If two words are written to the TXREG and then the
• CREN = 0 (for transmit); CREN = 1 (for receive)
SLEEP instruction is executed, the following will occur:
• SPEN = 1
1. The first character will immediately transfer to
Setting the SYNC bit of the TX1STA register configures the TSR register and transmit.
the device for synchronous operation. Clearing the
2. The second word will remain in the TXREG
CSRC bit of the TX1STA register configures the device
register.
as a client. Clearing the SREN and CREN bits of the
RC1STA register ensures that the device is in the 3. The TXIF bit will not be set.
Transmit mode, otherwise the device will be configured to 4. After the first character has been shifted out of
receive. Setting the SPEN bit of the RC1STA register TSR, the TXREG register will transfer the second
enables the EUSART. character to the TSR and the TXIF bit will now be
set.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
33.4.2.2 Synchronous Client Transmission

Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the ANSEL bit for the CK pin (if applicable).
3. Clear the CREN and SREN bits.
4. If interrupts are desired, set the TXIE bit of the
PIE3 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant eight bits to the TXREG register.

PIC16(L)F18857/77
33.4.2.3 EUSART Synchronous Client 33.4.2.4 Synchronous Client Reception
Reception Set-up:
The operation of the Synchronous Host and Client 1. Set the SYNC and SPEN bits and clear the
modes is identical (Section 33.4.1.5 “Synchronous CSRC bit.
Host Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins
• Sleep (if applicable).
• CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RCIE bit of the
never idle PIE3 register and the GIE and PEIE bits of the
• SREN bit, which is a “don’t care” in Client mode INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the 5. Set the CREN bit to enable reception.
word is received, the RSR register will transfer the data 6. The RCIF bit will be set when reception is
to the RCREG register. If the RCIE enable bit is set, the complete. An interrupt will be generated if the
interrupt generated will wake the device from Sleep RCIE bit was set.
and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most
set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RC1STA
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RC1STA
register or by clearing the SPEN bit which resets
the EUSART.

PIC16(L)F18857/77
33.5 EUSART Operation During Sleep 33.5.2 SYNCHRONOUS TRANSMIT
DURING SLEEP
The EUSART will remain active during Sleep only in the
Synchronous Client mode. All other modes require the To transmit during Sleep, all the following conditions
system clock and therefore cannot generate the neces- must be met before entering Sleep mode:
sary signals to run the Transmit or Receive Shift • The RC1STA and TX1STA Control registers must
registers during Sleep. be configured for synchronous client transmission
Synchronous Client mode uses an externally generated (see Section 33.4.2.2 “Synchronous Client
clock to run the Transmit and Receive Shift registers. Transmission Set-up:”).
• The TXIF interrupt flag must be cleared by writing
33.5.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the
SLEEP TSR and transmit buffer.
To receive during Sleep, all the following conditions • If interrupts are desired, set the TXIE bit of the
must be met before entering Sleep mode: PIE3 register and the PEIE bit of the INTCON
register.
• RC1STA and TX1STA Control registers must be
configured for Synchronous Client Reception (see • Interrupt enable bits TXIE of the PIE3 register and
Section 33.4.2.4 “Synchronous Client PEIE of the INTCON register must set.
Reception Set-up:”). Upon entering Sleep mode, the device will be ready to
• If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the
PIE3 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been
INTCON register. completely clocked out by the external device, the
• The RCIF interrupt flag must be cleared by read- pending byte in the TXREG will transfer to the TSR and
ing RCREG to unload any pending characters in the TXIF flag will be set. Thereby, waking the processor
the receive buffer. from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
Upon entering Sleep mode, the device will be ready to clear the TXIF flag.
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely Upon waking from Sleep, the instruction following the
clocked in by the external device, the RCIF interrupt SLEEP instruction will be executed. If the Global
flag bit of the PIR3 register will be set. Thereby, waking Interrupt Enable (GIE) bit is also set then the Interrupt
the processor from Sleep. Service Routine at address 0004h will be called.
Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit of the INTCON register is
also set, then the Interrupt Service Routine at address
004h will be called.

PIC16(L)F18857/77
33.6 Register Definitions: EUSART Control
REGISTER 33-1: TX1STA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Unused in this mode – value ignored
Synchronous mode:
1 = Host mode (clock generated internally from BRG)
0 = Client mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send SYNCH BREAK on next transmission – start bit, followed by 12 ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = SYNCH BREAK transmission disabled or completed
Synchronous mode:
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC16(L)F18857/77
REGISTER 33-2: RC1STA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0
SPEN(1) RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
bit 7 SPEN: Serial Port Enable bit(1)

1 = Serial port enabled
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Synchronous mode – Host:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Client
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection – enable interrupt and load of the receive buffer when the ninth bit in
the receive buffer is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Note 1: The EUSART module automatically changes the pin from tri-state to drive as needed. Configure the
associated TRIS bits for TX/CK and RX/DT to 1.

PIC16(L)F18857/77
REGISTER 33-3: BAUD1CON: BAUD RATE CONTROL REGISTER

R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 4 SCKP: Clock/Transmit Polarity Select bit
Asynchronous mode:
1 = Idle state for transmit (TX) is a low level
0 = Idle state for transmit (TX) is a high level
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = USART will continue to sample the Rx pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge.
0 = RX pin not monitored nor rising edge detected
Synchronous mode:
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character – requires reception of a SYNCH field
(55h);
cleared in hardware upon completion
0 = Baud rate measurement disabled or completed
Synchronous mode:

PIC16(L)F18857/77
REGISTER 33-4: RC1REG(1): RECEIVE DATA REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RC1REG<7:0>
bit 7 bit 0
Legend:
bit 7-0 RC1REG<7:0>: Lower eight bits of the received data; read-only; see also RX9D (Register 33-2)
Note 1: RCREG (including the 9th bit) is double buffered, and data is available while new data is being received.
REGISTER 33-5: TX1REG(1): TRANSMIT DATA REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TX1REG<7:0>
bit 7 bit 0
Legend:
bit 7-0 TX1REG<7:0>: Lower eight bits of the received data; read-only; see also RX9D (Register 33-1)
Note 1: TXREG (including the 9th bit) is double buffered, and can be written when previous data has started
shifting.
REGISTER 33-6: SP1BRGL(1): BAUD RATE GENERATOR REGISTER

SP1BRG<7:0>
bit 7 bit 0
Legend:
bit 7-0 SP1BRG<7:0>: Lower eight bits of the Baud Rate Generator
Note 1: Writing to SP1BRG resets the BRG counter.

PIC16(L)F18857/77
REGISTER 33-7: SP1BRGH(1, 2): BAUD RATE GENERATOR HIGH REGISTER
SP1BRG<15:8>
bit 7 bit 0
Legend:
bit 7 SP1BRG<15:8>: Upper eight bits of the Baud Rate Generator
Note 1: SPBRGH value is ignored for all modes unless BAUD1CON<BRG16> is active.
2: Writing to SPBRGH resets the BRG counter.

PIC16(L)F18857/77
TABLE 33-2: SUMMARY OF REGISTERS ASSOCIATED WITH EUSART
Register
on Page

RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 563
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 562
BAUD1CON ABDOVF RCIDL ― SCKP BRG16 ― WUE ABDEN 564
RC1REG RC1REG<7:0> 547*
TX1REG TX1REG<7:0> 545*
SPB1RGL SP1BRG<7:0> 551*
SPB1RGH SP1BRG<15:8> 551*
RXPPS ― ― ― RXPPS<4:0> 240
CKPPS ― ― ― CXPPS<4:0> 240
RxyPPS ― ― ― RxyPPS<4:0> 241
MDSRC ― ― ― MDMS<4:0> 389
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the EUSART module.
* Page with register information.

PIC16(L)F18857/77
TABLE 33-3: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair.
TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143
2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71
9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17
10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16
19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8
57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2
115.2k — — — — — — — — — — — —
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —

PIC16(L)F18857/77
TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5
SYNC = 0, BRGH = 1, BRG16 = 0
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
SYNC = 0, BRGH = 0, BRG16 = 1
300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303
1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575
2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5

PIC16(L)F18857/77
TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215
1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303
2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151
9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287
10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264
19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47
115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

PIC16(L)F18857/77
34.0 REFERENCE CLOCK OUTPUT 34.3 SELECTABLE DUTY CYCLE
MODULE The CLKRDC<1:0> bits of the CLKRCON register can
The Reference Clock Output module provides the be used to modify the duty cycle of the output clock. A
ability to send a clock signal to the clock reference duty cycle of 25%, 50%, or 75% can be selected for all
output pin (CLKR). The Reference Clock Output can clock rates, with the exception of the undivided base
also be used as a signal for other peripherals, such as FOSC value.
the Data Signal Modulator (DSM). The duty cycle can be changed while the module is
The Reference Clock Output module has the following enabled; however, in order to prevent glitches on the
features: output, the CLKRDC<1:0> bits should only be changed
when the module is disabled (CLKREN = 0).
• Selectable input clock
• Programmable clock divider
• Selectable duty cycle Note: The CLKRDC1 bit is reset to ‘1’. This
makes the default duty cycle 50% and not
34.1 CLOCK SOURCE 0%.
The Reference Clock Output module has a selectable
clock source. The CLKRCLK register (Register 34-2) 34.4 OPERATION IN SLEEP MODE
controls which input is used. The Reference Clock Output module is not affected by
Sleep mode. The Reference Clock Output module can
34.1.1 CLOCK SYNCHRONIZATION
still operate during Sleep if the clock source selected by
Once the reference clock enable (CLKREN) is set, the CLKRCLK is also active during Sleep.
module is ensured to be glitch-free at start-up.
When the Reference Clock Output is disabled, the
output signal will be disabled immediately.
Clock dividers and clock duty cycles can be changed
while the module is enabled, but glitches may occur on
the output. To avoid possible glitches, clock dividers
and clock duty cycles should be changed only when the
CLKREN is clear.
34.2 PROGRAMMABLE CLOCK

DIVIDER
The module takes the selected clock input and divides
it based on the value of the CLKRDIV<2:0> bits of the
CLKRCON register (Register 34-1).
The following configurations can be made based on the
CLKRDIV<2:0> bits:
• Base input clock value
• Input clock divided by 2
The clock divider values can be changed while the
module is enabled; however, in order to prevent
glitches on the output, the CLKRDIV<2:0> bits should
only be changed when the module is disabled
(CLKREN = 0).

PIC16(L)F18857/77
FIGURE 34-1: CLOCK REFERENCE BLOCK DIAGRAM
Rev. 10-000261A
9/10/2015
CLKRDIV<2:0>
CLKREN Counter Reset
128
111
Reference Clock Divider

See 64 CLKRDC<1:0>
110
CLKRCLK 32
Register 101
16 CLKR
100
8 Duty Cycle PPS
011
4
010
2
001 To Peripherals
CLKREN
D Q 000
CLKRCLK<3:0>
FREEZE ENABLED(1) EN
ICD FREEZE MODE(1)
FIGURE 34-2: CLOCK REFERENCE TIMING
P1 P2
FOSC
CLKREN
CLKR Output
CLKRDIV[2:0] = 001
Duty Cycle
CLKRDC[1:0] = 10
(50%)
CLKR Output FOSC / 2

CLKRDIV[2:0] = 001
CLKRDC[1:0] = 01
Duty Cycle (25%)

PIC16(L)F18857/77
REGISTER 34-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER

R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
CLKREN — — CLKRDC<1:0> CLKRDIV<2:0>
bit 7 bit 0
Legend:
bit 7 CLKREN: Reference Clock Module Enable bit

1 = Reference Clock module enabled
0 = Reference Clock module is disabled
bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits (1)
11 = Clock outputs duty cycle of 75%
bit 2-0 CLKRDIV<2:0>: Reference Clock Divider bits
111 = Input clock divided by 128
000 = Input clock
Note 1: Bits are valid for Reference Clock divider values of two or larger, the base clock cannot be further divided.

PIC16(L)F18857/77
REGISTER 34-2: CLKRCLK: CLOCK REFERENCE CLOCK SELECTION REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — CLKRCLK<3:0>
bit 7 bit 0
Legend:

bit 3-0 CLKRCLK<3:0>: CLKR Input bits
Clock Selection
1111 = Reserved
•
•
•
1010 = Reserved
1001 = LC4_out
1000 = LC3_out
0111 = LC2_out
0110 = LC1_out
0101 = NCO output
0100 = SOSC
0011 = MFINTOSC
0010 = LFINTOSC
0001 = HFINTOSC
0000 = FOSC
TABLE 34-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK REFERENCE OUTPUT

Register
on Page
CLKRCON CLKREN — — CLKRDC<1:0> CLKRDIV<2:0> 573
CLKRCLK — — — — CLKRCLK<3:0> 574
CLCxSELy — — — LCxDyS<4:0> 320
MDCARH — — — — MDCHS<3:0> 390
MDCARL — — — — MDCLS<3:0> 391
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the CLKR module.

PIC16(L)F18857/77
35.0 IN-CIRCUIT SERIAL 35.3 Common Programming Interfaces
PROGRAMMING™ (ICSP™) Connection to a target device is typically done through
ICSP™ programming allows customers to manufacture an ICSP™ header. A commonly found connector on
circuit boards with unprogrammed devices. Programming development tools is the RJ-11 in the 6P6C (6-pin,
can be done after the assembly process, allowing the 6-connector) configuration. See Figure 35-1.
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™ FIGURE 35-1: ICD RJ-11 STYLE
programming: CONNECTOR INTERFACE
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
ICSPDAT
• VSS
2 4 6 NC
VDD
In Program/Verify mode the program memory, User IDs ICSPCLK
and the Configuration Words are programmed through 1 3 5
Target
serial communications. The ICSPDAT pin is a VPP/MCLR PC Board
VSS
bidirectional I/O used for transferring the serial data Bottom Side
and the ICSPCLK pin is the clock input. For more
information on ICSP™ refer to the
“PIC16(L)F1783XX Memory Programming Pin Description*
Specification” (DS400001738).
1 = VPP/MCLR
2 = VDD Target
35.1 High-Voltage Programming Entry 3 = VSS (ground)
Mode 4 = ICSPDAT
The device is placed into High-Voltage Programming 5 = ICSPCLK

Entry mode by holding the ICSPCLK and ICSPDAT 6 = No Connect
pins low then raising the voltage on MCLR/VPP to VIHH.
Another connector often found in use with the PICkit™
35.2 Low-Voltage Programming Entry programmers is a standard 6-pin header with 0.1 inch
Mode spacing. Refer to Figure 35-2.
The Low-Voltage Programming Entry mode allows the For additional interface recommendations, refer to your
PIC® Flash MCUs to be programmed using VDD only, specific device programmer manual prior to PCB
without high voltage. When the LVP bit of Configuration design.
Words is set to ‘1’, the low-voltage ICSP programming It is recommended that isolation devices be used to
entry is enabled. To disable the Low-Voltage ICSP separate the programming pins from other circuitry.
mode, the LVP bit must be programmed to ‘0’. The type of isolation is highly dependent on the specific
Entry into the Low-Voltage Programming Entry mode application and may include devices such as resistors,
requires the following steps: diodes, or even jumpers. See Figure 35-3 for more
information.
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 5.4 “MCLR” for more
information.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.

PIC16(L)F18857/77
FIGURE 35-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1 1 = VPP/MCLR
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
* The 6-pin header (0.100" spacing) accepts 0.025" square pins.
FIGURE 35-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming VDD Device to be
Signals Programmed
VDD VDD
VPP MCLR/VPP
VSS VSS
Data ICSPDAT
Clock ICSPCLK
* * *
To Normal Connections
* Isolation devices (as required).

PIC16(L)F18857/77
36.0 INSTRUCTION SET SUMMARY 36.1 Read-Modify-Write Operations
Each instruction is a 14-bit word containing the Any instruction that specifies a file register as part of
operation code (opcode) and all required operands. the instruction performs a Read-Modify-Write (R-M-W)
The opcodes are broken into three broad categories. operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
• Byte Oriented
tion, or the destination designator ‘d’. A read operation
• Bit Oriented is performed on a register even if the instruction writes
• Literal and Control to that register.
The literal and control category contains the most
varied instruction word format. TABLE 36-1: OPCODE FIELD
Table 36-4 lists the instructions recognized by the DESCRIPTIONS
MPASMTM assembler. Field Description
All instructions are executed within a single instruction f Register file address (0x00 to 0x7F)
cycle, with the following exceptions, which may take
W Working register (accumulator)
two or three cycles:
b Bit address within an 8-bit file register
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two k Literal field, constant data or label
cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1).
• Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0.
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for
• One additional instruction cycle will be used when compatibility with all Microchip software tools.
any instruction references an indirect file register d Destination select; d = 0: store result in W,
and the file select register is pointing to program d = 1: store result in file register f.
memory. Default is d = 1.
One instruction cycle consists of 4 oscillator cycles; for n FSR or INDF number. (0-1)
an oscillator frequency of 4 MHz, this gives a nominal mm Prepost increment-decrement mode selection
instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to TABLE 36-2: ABBREVIATION
represent a hexadecimal number, where ‘h’ signifies a
DESCRIPTIONS
hexadecimal digit.
Field Description
PC Program Counter
TO Time-Out bit
C Carry bit
DC Digit Carry bit
Z Zero bit
PD Power-Down bit

PIC16(L)F18857/77
TABLE 36-3: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations

13 8 7 6 0
OPCODE d f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address

f = 7-bit file register address
Literal and control operations

General
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only

13 11 10 0
OPCODE k (literal)
MOVLP instruction only

13 7 6 0
OPCODE k (literal)
MOVLB instruction only

13 6 5 0
OPCODE k (literal)
BRA instruction only

13 9 8 0
OPCODE k (literal)
FSR Offset instructions

13 7 6 5 0
OPCODE n k (literal)
n = appropriate FSR
FSR Increment instructions

13 3 2 1 0
OPCODE n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13 0
OPCODE

PIC16(L)F18857/77
TABLE 36-4: INSTRUCTION SET
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2
ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2
ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2
LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2
LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0000 00xx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 2
INCF f, d Increment f 1 00 1010 dfff ffff Z 2
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 2
MOVWF f Move W to f 1 00 0000 1fff ffff 2
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2
SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2
BYTE ORIENTED SKIP OPERATIONS
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2

INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 2

BSF f, b Bit Set f 1 01 01bb bfff ffff 2
BIT-ORIENTED SKIP OPERATIONS

BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2
LITERAL OPERATIONS
ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLB k Move literal to BSR 1 00 0001 01kk kkkk
MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk
MOVLW k Move literal to W 1 11 0000 kkkk kkkk
SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.

PIC16(L)F18857/77
TABLE 36-4: INSTRUCTION SET (CONTINUED)
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW – Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW – Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP – No Operation 1 00 0000 0000 0000
RESET – Software device Reset 1 00 0000 0000 0001
SLEEP – Go into Standby or IDLE mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.

PIC16(L)F18857/77
36.2 Instruction Descriptions
ADDFSR Add Literal to FSRn ANDLW AND literal with W

Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k
Operands: -32  k  31 Operands: 0  k  255
n  [ 0, 1]
Operation: (W) .AND. (k)  (W)
Operation: FSR(n) + k  FSR(n) Status Affected: Z
Status Affected: None
Description: The contents of W register are
Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The
the contents of the FSRnH:FSRnL result is placed in the W register.
register pair.
FSRn is limited to the range

0000h-FFFFh. Moving beyond these
bounds will cause the FSR to
wrap-around.
ANDWF AND W with f

ADDLW Add literal and W
Syntax: [ label ] ANDWF f,d
Syntax: [ label ] ADDLW k Operands: 0  f  127
Operands: 0  k  255 d 0,1
Operation: (W) + k  (W) Operation: (W) .AND. (f)  (destination)
Status Affected: C, DC, Z Status Affected: Z
Description: The contents of the W register are Description: AND the W register with register ‘f’. If
added to the 8-bit literal ‘k’ and the ‘d’ is ‘0’, the result is stored in the W
result is placed in the W register. register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF Arithmetic Right Shift

ADDWF Add W and f
Syntax: [ label ] ASRF f {,d}
Syntax: [ label ] ADDWF f,d Operands: 0  f  127
Operands: 0  f  127 d [0,1]
d 0,1 Operation: (f<7>) dest<7>
Operation: (W) + (f)  (destination) (f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected: C, DC, Z
Status Affected: C, Z
Description: Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is Description: The contents of register ‘f’ are shifted
stored in the W register. If ‘d’ is ‘1’, the one bit to the right through the Carry
result is stored back in register ‘f’. flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
register f C
ADDWFC ADD W and CARRY bit to f
Syntax: [ label ] ADDWFC f {,d}
Operands: 0  f  127
d [0,1]
Operation: (W) + (f) + (C)  dest
Description: Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.

PIC16(L)F18857/77
BCF Bit Clear f BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b
Operands: 0  f  127 Operands: 0  f  127

0b7 0b7
Operation: 0  (f<b>) Operation: skip if (f<b>) = 0
Status Affected: None Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BRA Relative Branch BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b
[ label ] BRA $+k Operands: 0  f  127
Operands: -256  label - PC + 1  255 0b<7
-256  k  255 Operation: skip if (f<b>) = 1
Operation: (PC) + 1 + k  PC Status Affected: None
Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
Description: Add the signed 9-bit literal ‘k’ to the instruction is executed.
PC. Since the PC will have If bit ‘b’ is ‘1’, then the next instruction
incremented to fetch the next is discarded and a NOP is executed
instruction, the new address will be instead, making this a 2-cycle
PC + 1 + k. This instruction is a instruction.
2-cycle instruction. This branch has a
limited range.
BRW Relative Branch with W

Syntax: [ label ] BRW
Operands: None
Operation: (PC) + (W)  PC
Description: Add the contents of W (unsigned) to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 1 + (W). This instruction is a
2-cycle instruction.
BSF Bit Set f

Syntax: [ label ] BSF f,b
0b7
Operation: 1  (f<b>)
Description: Bit ‘b’ in register ‘f’ is set.

PIC16(L)F18857/77
CALL Call Subroutine CLRWDT Clear Watchdog Timer

Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT
Operands: 0  k  2047 Operands: None
Operation: (PC)+ 1 TOS, Operation: 00h  WDT
k  PC<10:0>, 0  WDT prescaler,
(PCLATH<6:3>)  PC<14:11> 1  TO
Status Affected: None 1  PD
Description: Call Subroutine. First, return address Status Affected: TO, PD
(PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch-
The 11-bit immediate address is dog Timer. It also resets the prescaler
loaded into PC bits <10:0>. The upper of the WDT. Status bits TO and PD
bits of the PC are loaded from are set.
PCLATH. CALL is a 2-cycle
instruction.
CALLW Subroutine Call With W COMF Complement f
Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d

Operands: None Operands: 0  f  127
d  [0,1]
Operation: (PC) +1  TOS,
(W)  PC<7:0>, Operation: (f)  (destination)
(PCLATH<6:0>) PC<14:8> Status Affected: Z
Description: The contents of register ‘f’ are
Status Affected: None complemented. If ‘d’ is ‘0’, the result is
Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is
return address (PC + 1) is pushed stored back in register ‘f’.
onto the return stack. Then, the
contents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a 2-cycle
instruction.
CLRF Clear f DECF Decrement f

Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d
d  [0,1]
Operation: 00h  (f)
1Z Operation: (f) - 1  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
and the Z bit is set. result is stored in the W register. If ‘d’
register ‘f’.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h  (W)
1Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z) is
set.

PIC16(L)F18857/77
DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
d  [ 0 ,1 ] d  [0,1]
Operation: (f) - 1  (destination); Operation: (f) + 1  (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’. is placed back in register ‘f’.
If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is
NOP is executed instead, making it a executed instead, making it a 2-cycle
2-cycle instruction. instruction.
GOTO Unconditional Branch IORLW Inclusive OR literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0  k  2047 Operands: 0  k  255
Operation: k  PC<10:0> Operation: (W) .OR. k  (W)
PCLATH<6:3>  PC<14:11>
Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. The OR’ed with the 8-bit literal ‘k’. The
11-bit immediate value is loaded into result is placed in the W register.
PC bits <10:0>. The upper bits of PC
are loaded from PCLATH<4:3>. GOTO
is a 2-cycle instruction.
INCF Increment f IORWF Inclusive OR W with f

Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d
d  [0,1] d  [0,1]
Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis-
mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in
in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is
is placed back in register ‘f’. placed back in register ‘f’.

PIC16(L)F18857/77
LSLF Logical Left Shift MOVF Move f

Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d
d [0,1] d  [0,1]
Operation: (f<7>)  C Operation: (f)  (dest)
(f<6:0>)  dest<7:1> Status Affected: Z
0  dest<0>
Description: The contents of register f is moved to
Status Affected: C, Z a destination dependent upon the
Description: The contents of register ‘f’ are shifted status of d. If d = 0, destination is W
one bit to the left through the Carry flag. register. If d = 1, the destination is file
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, register f itself. d = 1 is useful to test a
the result is placed in W. If ‘d’ is ‘1’, the file register since status flag Z is
result is stored back in register ‘f’. affected.
C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
LSRF Logical Right Shift
W = value in FSR register
Syntax: [ label ] LSRF f {,d} Z = 1
d [0,1]
Operation: 0  dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0 register f C

PIC16(L)F18857/77
MOVIW Move INDFn to W MOVLP Move literal to PCLATH

Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k
[ label ] MOVIW --FSRn
Operands: 0  k  127
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn-- Operation: k  PCLATH
[ label ] MOVIW k[FSRn] Status Affected: None
Operands: n  [0,1] Description: The 7-bit literal ‘k’ is loaded into the
mm  [00,01, 10, 11] PCLATH register.
-32  k  31
Operation: INDFn  W
Effective address is determined by MOVLW Move literal to W
• FSR + 1 (preincrement)
• FSR - 1 (predecrement) Syntax: [ label ] MOVLW k
• FSR + k (relative offset) Operands: 0  k  255
After the Move, the FSR value will be Operation: k  (W)
either:
• FSR + 1 (all increments) Status Affected: None
• FSR - 1 (all decrements) Description: The 8-bit literal ‘k’ is loaded into W reg-
• Unchanged ister. The “don’t cares” will assemble as
Status Affected: Z ‘0’s.
Words: 1
Mode Syntax mm Cycles: 1
Preincrement ++FSRn 00 Example: MOVLW 0x5A
Predecrement --FSRn 01 After Instruction

W = 0x5A
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Description: This instruction is used to move data
between W and one of the indirect Operands: 0  f  127
registers (INDFn). Before/after this Operation: (W)  (f)
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it. Status Affected: None
Description: Move data from W register to register
Note: The INDFn registers are not ‘f’.
physical registers. Any instruction that
Words: 1
accesses an INDFn register actually
accesses the register at the address Cycles: 1
specified by the FSRn. Example: MOVWF LATA
Before Instruction
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it LATA = 0xFF
W = 0x4F
beyond these bounds will cause it to
After Instruction
wrap-around.
LATA = 0x4F
W = 0x4F
MOVLB Move literal to BSR
Syntax: [ label ] MOVLB k
Operation: k  BSR
Description: The 6-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).

PIC16(L)F18857/77
MOVWI Move W to INDFn NOP No Operation

Syntax: [ label ] NOP
Syntax: [ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn Operands: None
[ label ] MOVWI FSRn++
Operation: No operation
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn] Status Affected: None
Operands: n  [0,1] Description: No operation.

mm  [00,01, 10, 11] Words: 1
-32  k  31
Cycles: 1
Operation: W  INDFn
Example: NOP
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
RESET Software Reset
• FSR + 1 (all increments) Syntax: [ label ] RESET
• FSR - 1 (all decrements)
Unchanged Operands: None
Operation: Execute a device Reset. Resets the
RI flag of the PCON register.
Mode Syntax mm
Description: This instruction provides a way to
Preincrement ++FSRn 00 execute a hardware Reset by
Predecrement --FSRn 01 software.
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE k
Description: This instruction is used to move data
between W and one of the indirect Operands: None
registers (INDFn). Before/after this Operation: TOS  PC,
move, the pointer (FSRn) is updated by 1  GIE
pre/post incrementing/decrementing it.
Note: The INDFn registers are not Description: Return from Interrupt. Stack is POPed
physical registers. Any instruction that and Top-of-Stack (TOS) is loaded in
accesses an INDFn register actually the PC. Interrupts are enabled by
accesses the register at the address setting Global Interrupt Enable bit,
specified by the FSRn. GIE (INTCON<7>). This is a 2-cycle
instruction.
FSRn is limited to the range Words: 1
0000h-FFFFh.
Cycles: 2
Incrementing/decrementing it beyond
these bounds will cause it to Example: RETFIE
wrap-around.
After Interrupt
PC = TOS
The increment/decrement operation on GIE = 1
FSRn WILL NOT affect any Status bits.

PIC16(L)F18857/77
RETLW Return with literal in W RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d
Syntax: [ label ] RETLW k
d  [0,1]
Operation: k  (W);
Operation: See description below
TOS  PC
Status Affected: None Status Affected: C
Description: The contents of register ‘f’ are rotated
Description: The W register is loaded with the 8-bit
literal ‘k’. The program counter is one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
loaded from the top of the stack (the
the W register. If ‘d’ is ‘1’, the result is
return address). This is a 2-cycle
instruction. stored back in register ‘f’.
C Register f
Words: 1
Cycles: 2
Words: 1
Example: CALL TABLE;W contains table
Cycles: 1
;offset value
• ;W now has table value Example: RLF REG1,0
TABLE • Before Instruction
• REG1 = 1110 0110
ADDWF PC ;W = offset C = 0
RETLW k1 ;Begin table After Instruction
RETLW k2 ; REG1 = 1110 0110
• W = 1100 1100
• C = 1
•
RETLW kn ; End of table
RRF Rotate Right f through Carry
Before Instruction
W = 0x07 Syntax: [ label ] RRF f,d
After Instruction Operands: 0  f  127
W = value of k8 d  [0,1]
Operation: See description below
RETURN Return from Subroutine Status Affected: C

Description: The contents of register ‘f’ are rotated
Syntax: [ label ] RETURN one bit to the right through the Carry
Operands: None flag. If ‘d’ is ‘0’, the result is placed in
Operation: TOS  PC the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
C Register f
Description: Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a 2-cycle instruction.

PIC16(L)F18857/77
SUBWFB Subtract W from f with Borrow

SLEEP Enter Sleep mode Syntax: SUBWFB f {,d}
Syntax: [ label ] SLEEP Operands: 0  f  127
d  [0,1]
Operands: None
Operation: (f) – (W) – (B) dest
Operation: 00h  WDT,
0  WDT prescaler, Status Affected: C, DC, Z
1  TO, Description: Subtract W and the BORROW flag
0  PD (CARRY) from register ‘f’ (2’s
Status Affected: TO, PD complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
Description: The power-down Status bit, PD is result is stored back in register ‘f’.
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its
prescaler are cleared.
See Section 8.2 “Sleep Mode” for SWAPF Swap Nibbles in f
more information.
Syntax: [ label ] SWAPF f,d
d  [0,1]
SUBLW Subtract W from literal Operation: (f<3:0>)  (destination<7:4>),
(f<7:4>)  (destination<3:0>)
Syntax: [ label ] SUBLW k
Operands: 0 k 255
Description: The upper and lower nibbles of
Operation: k - (W) W) register ‘f’ are exchanged. If ‘d’ is ‘0’,
Status Affected: C, DC, Z the result is placed in the W register. If
‘d’ is ‘1’, the result is placed in register
Description: The W register is subtracted (2’s
‘f’.
complement method) from the 8-bit
literal ‘k’. The result is placed in the W
register.
TRIS Load TRIS Register with W
C=0 Wk
Syntax: [ label ] TRIS f
C=1 Wk
Operands: 5f7
DC = 0 W<3:0>  k<3:0>
Operation: (W)  TRIS register ‘f’
DC = 1 W<3:0>  k<3:0>
Description: Move data from W register to TRIS
register.
SUBWF Subtract W from f When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
Syntax: [ label ] SUBWF f,d
When ‘f’ = 7, TRISC is loaded.
Operands: 0 f 127
d  [0,1]
Operation: (f) - (W) destination)
Description: Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f.
C=0 Wf
C=1 Wf
DC = 0 W<3:0>  f<3:0>
DC = 1 W<3:0>  f<3:0>

PIC16(L)F18857/77
XORLW Exclusive OR literal with W

Syntax: [ label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register are
XOR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d
d  [0,1]
Operation: (W) .XOR. (f) destination)
Status Affected: Z
Description: Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
register ‘f’.

PIC16(L)F18857/77
37.0 ELECTRICAL SPECIFICATIONS
37.1 Absolute Maximum Ratings(†)
Ambient temperature under bias...................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC16F18857/77 ....................................................................................................... -0.3V to +6.5V
PIC16LF18857/77 ..................................................................................................... -0.3V to +4.0V
on MCLR pin ........................................................................................................................... -0.3V to +9.0V
on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)
Maximum current
on VSS pin(1)
-40°C  TA  +85°C .............................................................................................................. 350 mA
85°C  TA  +125°C ............................................................................................................. 120 mA
on VDD pin for 28-Pin devices(1)
-40°C  TA  +85°C .............................................................................................................. 250 mA
85°C  TA  +125°C ............................................................................................................... 85 mA
on VDD pin for 40-Pin devices(1)
-40°C  TA  +85°C .............................................................................................................. 350 mA
85°C  TA  +125°C ............................................................................................................. 120 mA
on any standard I/O pin ...................................................................................................................... 50 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA
Total power dissipation(2)................................................................................................................................ 800 mW
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 37-6 to calculate device
specifications.
2: Power dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + VDD - VOH) x IOH} + VOI x IOL
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.

PIC16(L)F18857/77
37.2 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage: VDDMIN VDD VDDMAX
Operating Temperature: TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC16LF18857/77
VDDMIN (Fosc  16 MHz) ......................................................................................................... +1.8V
VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +3.6V
PIC16F18857/77
VDDMIN (Fosc  16 MHz) ......................................................................................................... +2.3V
VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ..................................................................................................................................... -40°C
TA_MAX.................................................................................................................................... +85°C
Extended Temperature
TA_MIN ..................................................................................................................................... -40°C
TA_MAX.................................................................................................................................. +125°C
Note 1: See Parameter Supply Voltage, DS Characteristics: Supply Voltage.

PIC16(L)F18857/77
FIGURE 37-1: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16F18857/77 ONLY
5.5
VDD (V)
2.5
2.3
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table for each Oscillator mode’s supported frequencies.
FIGURE 37-2: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16LF18857/77 ONLY

VDD (V)
3.6
2.5
1.8
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table for each Oscillator mode’s supported frequencies.

PIC16(L)F18857/77
37.3 DC Characteristics
TABLE 37-1: SUPPLY VOLTAGE
PIC16LF18857/77 Standard Operating Conditions (unless otherwise stated)
PIC16F18857/77
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
Supply Voltage
D002 VDD 1.8 — 3.6 V FOSC  16 MHz
2.5 — 3.6 V FOSC  16 MHz
D002 VDD 2.3 — 5.5 V FOSC  16 MHz
2.5 — 5.5 V FOSC 16 MHz
RAM Data Retention(1)
D003 VDR 1.5 — — V Device in Sleep mode
D003 VDR 1.5 — — V Device in Sleep mode
Power-on Reset Release Voltage(2)
D004 VPOR — 1.6 — V BOR or LPBOR disabled(3)
D004 VPOR — 1.6 — V BOR or LPBOR disabled(3)
Power-on Reset Rearm Voltage(2)
D005 VPORR — 0.8 — V BOR or LPBOR disabled(3)
D005 VPORR — 1.2 — V BOR or LPBOR disabled(3)
VDD Rise Rate to ensure internal Power-on Reset signal(2)
D006 SVDD 0.05 — — V/ms BOR or LPBOR disabled(3)
D006 SVDD 0.05 — — V/ms BOR or LPBOR disabled(3)
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: See Figure 37-3, POR and POR REARM with Slow Rising VDD.
3: Please see Table 37-11 for BOR and LPBOR trip point information.

PIC16(L)F18857/77
FIGURE 37-3: POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
TVLOW(3) TPOR(2)
Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.

PIC16(L)F18857/77
TABLE 37-2: SUPPLY CURRENT (IDD)(1,2,4)

PIC16F18857/77
Param. Conditions
Symbol Device Characteristics Min. Typ.† Max. Units
No. VDD Note
D100 IDDXT4 XT = 4 MHz — 400 650 A 3.0V
D100 IDDXT4 XT = 4 MHz — 450 700 A 3.0V
D101 IDDHFO16 HFINTOSC = 16 MHz — 1.8 2.6 mA 3.0V
D101 IDDHFO16 HFINTOSC = 16 MHz — 1.9 2.7 mA 3.0V
D102 IDDHFOPLL HFINTOSC = 32 MHz — 2.6 4.25 mA 3.0V
D102 IDDHFOPLL HFINTOSC = 32 MHz — 2.7 4.25 mA 3.0V
D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.6 4.1 mA 3.0V
D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.7 4.1 mA 3.0V
D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.05 — mA 3.0V
D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.15 — mA 3.0V
D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.1 — mA 3.0V
D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.2 — mA 3.0V
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switch-
ing rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.
3: IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (Register 8-2).
4: PMD bits are all in the default state, no modules are disabled.

PIC16(L)F18857/77
TABLE 37-3: POWER-DOWN CURRENT (IPD)(1,2)

Standard Operating Conditions (unless otherwise stated)

PIC16F18857/77
VREGPM = 1
Param. Max. Max. Conditions

Symbol Device Characteristics Min. Typ.† Units
No. +85°C +125°C VDD Note
D200 IPD IPD Base — 0.05 2 9 A 3.0V
D200 IPD IPD Base — 0.4 4 12 A 3.0V

D200A — 10 15 20 A 3.0V VREGPM = 0
D201 IPD_WDT Low-Frequency Internal — 0.4 — — A 3.0V
Oscillator/WDT
D201 IPD_WDT Low-Frequency Internal — 0.6 5 13 A 3.0V
Oscillator/WDT
D202 IPD_SOSC Secondary Oscillator (SOSC) — 0.6 5 13 A 3.0V
D202 IPD_SOSC Secondary Oscillator (SOSC) — 0.8 8.5 15 A 3.0V
D203 IPD_FVR FVR — 31 65 80 A 3.0V
D203 IPD_FVR FVR — 32 65 80 A 3.0V
D204 IPD_BOR Brown-out Reset (BOR) — 9 14 18 A 3.0V
D204 IPD_BOR Brown-out Reset (BOR) — 14 19 21 A 3.0V
D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) — 0.5 3.0 10 A 3.0V
D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) — 0.7 5.0 13 A 3.0V
D206 IPD_ADCA ADC - Active — 250 — — A 3.0V ADC is converting (4)
D206 IPD_ADCA ADC - Active — 280 — — A 3.0V ADC is converting (4)
D207 IPD_CMP Comparator — 30 45 48 A 3.0V
D207 IPD_CMP Comparator — 31 47 50 A 3.0V
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The
peripheral ∆ current can be determined by subtracting the base IDD or IPD current from this limit. Max. values should be used
when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part
in Sleep mode with all I/O pins in high-impedance state and tied to VSS.
3: All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available.
4: ADC clock source is FRC.

PIC16(L)F18857/77
TABLE 37-4: I/O PORTS

Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
VIL Input Low Voltage
I/O PORT:
D300 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V
D301 — — 0.15 VDD V 1.8V  VDD 4.5V
D302 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V
D303 with I2C levels — — 0.3 VDD V
D304 with SMBus levels — — 0.8 V 2.7V  VDD  5.5V
D305 MCLR — — 0.2 VDD V
VIH Input High Voltage
I/O PORT:
D320 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V
D321 0.25 VDD + — — V 1.8V  VDD  4.5V
0.8
D322 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V
D323 with I2C levels 0.7 VDD — — V
D324 with SMBus levels 2.1 — — V 2.7V  VDD  5.5V
D325 MCLR 0.7 VDD — — V
IIL Input Leakage Current(1)
D340 I/O Ports — ±5 ± 125 nA VSS  VPIN  VDD,
Pin at high-impedance, 85°C
D341 — ±5 ± 1000 nA VSS  VPIN  VDD,
D342 MCLR(2) — ± 50 ± 200 nA VSS  VPIN  VDD,
IPUR Weak Pull-up Current
D350 25 120 200 A VDD = 3.0V, VPIN = VSS
VOL Output Low Voltage
D360 I/O ports — — 0.6 V IOL = 10.0mA, VDD = 3.0V
VOH Output High Voltage
D370 I/O ports VDD - 0.7 — — V IOH = 6.0 mA, VDD = 3.0V
D380 CIO All I/O pins — 5 50 pF
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.

PIC16(L)F18857/77
TABLE 37-5: MEMORY PROGRAMMING SPECIFICATIONS

Param.
No.
High Voltage Entry Programming Mode Specifications
MEM01 VIHH Voltage on MCLR/VPP pin to enter 8 — 9 V (Note 2, Note 3)
programming mode
MEM02 IPPGM Current on MCLR/VPP pin during — 1 — mA (Note 2)
programming mode
Programming Mode Specifications
MEM10 VBE VDD for Bulk Erase — 2.7 — V
MEM11 IDDPGM Supply Current during Programming — — 10 mA
operation
Data EEPROM Memory Specifications
MEM20 ED DataEE Byte Endurance 100k — — E/W -40C  TA  +85C
MEM21 TD_RET Characteristic Retention — 40 — Year Provided no other
specifications are violated
MEM22 ND_REF Total Erase/Write Cycles before 1M 10M — E/W
Refresh
MEM23 VD_RW VDD for Read or Erase/Write VDDMIN — VDDMAX V
operation
MEM24 TD_BEW Byte Erase and Write Cycle Time — 4.0 5.0 ms
Program Flash Memory Specifications
MEM30 EP Flash Memory Cell Endurance 10k — — E/W -40C  TA  +85C
(Note 1)
MEM32 TP_RET Characteristic Retention — 40 — Year Provided no other
specifications are violated
MEM33 VP_RD VDD for Read operation VDDMIN — VDDMAX V

MEM34 VP_REW VDD for Row Erase or Write VDDMIN — VDDMAX V
operation
MEM35 TP_REW Self-Timed Row Erase or Self-Timed — 2.0 2.5 ms
Write
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed
Write.
2: Required only if CONFIG4, bit LVP is disabled.
3: The MPLAB ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed between
the ICD2 and target system when programming or debugging with the ICD2.

PIC16(L)F18857/77
TABLE 37-6: THERMAL CHARACTERISTICS
Param.
Sym. Characteristic Typ. Units Conditions
No.
TH01 JA Thermal Resistance Junction to Ambient 60 C/W 28-pin SPDIP package
80 C/W 28-pin SOIC package
90 C/W 28-pin SSOP package
27.5 C/W 28-pin QFN 6x6mm package
47.2 C/W 40-pin PDIP package
41 C/W 40-pin UQFN 5x5mm package
28.95 C/W 40-pin VQFN 5x5x0.9mm package
46 C/W 44-pin TQFP package
24.4 C/W 44-pin QFN 8x8mm package
TH02 JC Thermal Resistance Junction to Case 31.4 C/W 28-pin SPDIP package
24 C/W 28-pin SOIC package
24 C/W 28-pin SSOP package
24 C/W 28-pin QFN 6x6mm package
24.7 C/W 40-pin PDIP package
5.5 C/W 40-pin UQFN 5x5mm package
1.61 C/W 40-pin VQFN 5x5x0.9mm package
14.5 C/W 44-pin TQFP package
20 C/W 44-pin QFN 8x8mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 P I /O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature

PIC16(L)F18857/77
37.4 AC Characteristics
FIGURE 37-4: LOAD CONDITIONS
Rev. 10-000133A
8/1/2013
Load Condition
Pin
CL
VSS
Legend: CL=50 pF for all pins

PIC16(L)F18857/77
FIGURE 37-5: CLOCK TIMING
Q4 Q1 Q2 Q3 Q4
CLKIN
OS1 OS2 OS2
OS20
Note 1: See Table 37-7.
TABLE 37-7: EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS

Param.
No.
ECL Oscillator
OS1 FECL Clock Frequency — — 500 kHz
OS2 TECL_DC Clock Duty Cycle 40 — 60 %
ECM Oscillator
OS3 FECM Clock Frequency — — 8 MHz
OS4 TECM_DC Clock Duty Cycle 40 — 60 %
ECH Oscillator
OS5 FECH Clock Frequency — — 32 MHz
OS6 TECH_DC Clock Duty Cycle 40 — 60 %
LP Oscillator
OS7 FLP Clock Frequency — — 100 kHz Note 4
XT Oscillator
OS8 FXT Clock Frequency — — 4 MHz Note 4
HS Oscillator
OS9 FHS Clock Frequency — — 20 MHz Note 4
System Oscillator
OS20 FOSC System Clock Frequency — — 32 MHz (Note 2, Note 3)
OS21 FCY Instruction Frequency — FOSC/4 — MHz
OS22 TCY Instruction Period 125 1/FCY — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in Section 6.0 “Oscil-
lator Module (with Fail-Safe Clock Monitor)”.
3: The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 37.2 “Standard
Operating Conditions”.
4: LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking
the device with the external square wave, one of the EC mode selections must be used.

PIC16(L)F18857/77
TABLE 37-8: INTERNAL OSCILLATOR PARAMETERS(1)
Param.
No.
OS50 FHFOSC Precision Calibrated HFINTOSC — 4 — MHz (Note 2)
Frequency 8
12
16
32
OS51 FHFOSCLP Low-Power Optimized HFINTOSC — 1 — MHz
Frequency — 2 — MHz
OS52 FMFOSC Internal Calibrated MFINTOSC — 500 — kHz
Frequency
OS53* FLFOSC Internal LFINTOSC Frequency — 31 — kHz (Note 3)
OS54* THFOSCST HFINTOSC — 11 20 s VREGPM = 0(4)
Wake-up from Sleep Start-up — 50 — s VREGPM = 1(4)
Time
OS56 TLFOSCST LFINTOSC — 0.2 — ms
Wake-up from Sleep Start-up Time
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 37-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Tempera-
ture, Figure 38-78 HFINTOSC Typical Frequency Error, PIC16FL18857/77 Only and Figure 38-79
HFINTOSC Typical Frequency Error, PIC16F18857/77 Only.
3: See Figure 38-7 LFINTOSC Frequency, PIC16LF18857/77 Only and Figure 38-8: LFINTOSC Frequency,
PIC16F18857/77 only.
4: On LF devices, the VREGPM bit is unimplemented. On LF devices, the VREGPM=0 parameter applies
when either the FVR or BOR are active in Sleep and the VREGPM=1 parameter applies when neither are
active in Sleep.

PIC16(L)F18857/77
FIGURE 37-6: PRECISION CALIBRATED HFINTOSC FREQUENCY ACCURACY OVER DEVICE
VDD AND TEMPERATURE
125
± 5%
85
± 3%
Temperature (°C)
60
± 2%
0
± 5%
-40
1.8 2.0 2.3 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16(L)F18857/77
TABLE 37-9: PLL SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) VDD 2.5V
Param.
No.
PLL01 FPLLIN PLL Input Frequency Range 4 — 8 MHz
PLL02 FPLLOUT PLL Output Frequency Range 16 — 32 MHz Note 1
PLL03 TPLLST PLL Lock Time from Start-up — 200 — s
PLL04 FPLLJIT PLL Output Frequency Stability (Jitter) -0.25 — 0.25 %
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
Note 1: The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002.

PIC16(L)F18857/77
FIGURE 37-7: CLKOUT AND I/O TIMING
Cycle Write Fetch Read Execute

Q4 Q1 Q2 Q3
FOSC
IO1 IO2
IO10
CLKOUT
IO8 IO4 IO7
IO5
I/O pin
(Input)
IO3
I/O pin Old Value New Value
(Output)
IO7, IO8
TABLE 37-10: I/O AND CLKOUT TIMING SPECIFICATIONS

Param.
No.
IO1* TCLKOUTH CLKOUT rising edge delay (rising edge — — 70 ns
Fosc (Q1 cycle) to falling edge CLKOUT
IO2* TCLKOUTL CLKOUT falling edge delay (rising edge — — 72 ns
Fosc (Q3 cycle) to rising edge CLKOUT
IO3* TIO_VALID Port output valid time (rising edge Fosc — 50 70 ns
(Q1 cycle) to port valid)
IO4* TIO_SETUP Port input setup time (Setup time before 20 — — ns
rising edge Fosc – Q2 cycle)
IO5* TIO_HOLD Port input hold time (Hold time after rising 50 — — ns
edge Fosc – Q2 cycle)
IO6* TIOR_SLREN Port I/O rise time, slew rate enabled — 25 — ns VDD = 3.0V
IO7* TIOR_SLRDIS Port I/O rise time, slew rate disabled — 5 — ns VDD = 3.0V
IO8* TIOF_SLREN Port I/O fall time, slew rate enabled — 25 — ns VDD = 3.0V
IO9* TIOF_SLRDIS Port I/O fall time, slew rate disabled — 5 — ns VDD = 3.0V
IO10* TINT INT pin high or low time to trigger an 25 — — ns
interrupt
IO11* TIOC Interrupt-on-Change minimum high or low 25 — — ns

time to trigger interrupt
*These parameters are characterized but not tested.

PIC16(L)F18857/77
FIGURE 37-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
RST01
Internal
POR
RST04
PWRT
Time-out RST05
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
RST03
RST02
RST02
I/O pins
Note 1: Asserted low.
FIGURE 37-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset) (Device not in Brown-out Reset)
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms
delay if PWRTE = 0.

PIC16(L)F18857/77
TABLE 37-11: RESET, WDT, OSCILLATOR START-UP TIMER, POWER-UP TIMER, BROWN-OUT
RESET AND LOW-POWER BROWN-OUT RESET SPECIFICATIONS
Param.
No.
RST01* TMCLR MCLR Pulse Width Low to ensure Reset 2 — — s

RST02* TIOZ I/O high-impedance from Reset detection — — 2 s
RST03 TWDT Watchdog Timer Time-out Period — 16 — ms 16 ms Nominal Reset Time
RST04* TPWRT Power-up Timer Period — 65 — ms
RST05 TOST Oscillator Start-up Timer Period(1,2) — 1024 — TOSC
RST06 VBOR Brown-out Reset Voltage(4) 2.55 2.70 2.85 V BORV = 0
2.30 2.45 2.60 V BORV = 1 (PIC16F18857/77)
1.80 1.90 2.10 V BORV = 1 (PIC16LF18857/77)
RST07 VBORHYS Brown-out Reset Hysteresis — 40 — mV
RST08 TBORDC Brown-out Reset Response Time — 3 — s
RST09 VLPBOR Low-Power Brown-out Reset Voltage 1.8 — 2.7 V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible.
0.1 F and 0.01 F values in parallel are recommended.
TABLE 37-12: ANALOG-TO-DIGITAL CONVERTER (ADC) ACCURACY SPECIFICATIONS(1,2):

Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param. Unit
Sym. Characteristic Min. Typ† Max. Conditions
No. s
AD01 NR Resolution — — 10 bit
AD02 EIL Integral Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V
AD03 EDL Differential Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V
AD04 EOFF Offset Error — 0.5 2.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V
AD05 EGN Gain Error — ±0.2 ±1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V
AD06 VADREF ADC Reference Voltage 1.8 — VDD V
(ADREF+ - ADREF-)
AD07 VAIN Full-Scale Range ADREF- — ADREF+ V
AD08 ZAIN Recommended Impedance of — 10 — k
Analog Voltage Source
AD09 RVREF ADC Voltage Reference Ladder — 10 — k Note 3
Impedance
*These parameters are characterized but not tested.
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors.
2: The ADC conversion result never decreases with an increase in the input and has no missing codes.
3: This is the impedance seen by the VREF pads when the external reference pads are selected.

PIC16(L)F18857/77
TABLE 37-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CONVERSION TIMING SPECIFICATIONS
Param.
No.
AD20 TAD ADC Clock Period 1 — 9 s Using FOSC as the ADC clock
source ADOCS = 0
AD21 1 2 6 s Using FRC as the ADC clock
source ADOCS = 1
AD22 TCNV Conversion Time — 11+3TCY — TAD Set of GO/DONE bit to Clear of
GO/DONE bit
AD23 TACQ Acquisition Time — 2 — s
AD24 THCD Sample and Hold Capacitor — — — s FOSC-based clock source
Disconnect Time FRC-based clock source
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 37-10: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)
Rev. 10-000321A
12/16/2016
BSF ADCON0, GO 1 TCY
AD24 AD22
Q4
AD20
ADC_clk
ADC Data 9 8 7 6 3 2 1 0
ADRES OLD DATA NEW DATA
ADIF 1 TCY
GO DONE
Sampling Stopped
Sample AD23

PIC16(L)F18857/77
FIGURE 37-11: ADC CONVERSION TIMING (ADC CLOCK FRC-BASED)
Rev. 10-000328A
3/20/2017
BSF ADCON0, GO 1 TCY
AD24 AD22
Q4
AD21
ADC_clk
ADC Data 9 8 7 6 3 2 1 0
ADRES OLD DATA NEW DATA
ADIF 1 TCY
GO DONE
Sampling Stopped
Sample AD23

PIC16(L)F18857/77
TABLE 37-14: COMPARATOR SPECIFICATIONS
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage — — ±30 mV VICM = VDD/2
CM02 VICM Input Common Mode Range GND — VDD V
CM03 CMRR Common Mode Input Rejection Ratio — 50 — dB
CM04 VHYST Comparator Hysteresis 15 25 35 mV
CM05 TRESP(1) Response Time, Rising Edge — 300 600 ns
Response Time, Falling Edge — 220 500 ns
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD.
2: A mode change includes changing any of the control register values, including module enable.
TABLE 37-15: 5-BIT DAC SPECIFICATIONS

VDD = 3.0V, TA = 25°C
Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
DSB01 VLSB Step Size — (VDACREF+ -VDACREF-) — V

/32
DSB01 VACC Absolute Accuracy — —  0.5 LSb
DSB03* RUNIT Unit Resistor Value — 5000 — 
DSB04* TST Settling Time(1) — — 10 s
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Settling time measured while DACR<4:0> transitions from ‘00000’ to ‘01111’.
TABLE 37-16: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS

Param.
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
FVR01 VFVR1 1x Gain (1.024V) -4 — +4 % VDD  2.5V, -40°C to 85°C
FVR04 TFVRST FVR Start-up Time — 25 — us
TABLE 37-17: ZERO CROSS DETECT (ZCD) SPECIFICATIONS

VDD = 3.0V, TA = 25°C
Param.
Sym. Characteristics Min Typ† Max Units Comments
No.
ZC01 VPINZC Voltage on Zero Cross Pin — 0.75 — V
ZC02 IZCD_MAX Maximum source or sink current — — 600 A
ZC03 TRESPH Response Time, Rising Edge — 1 — s
TRESPL Response Time, Falling Edge — 1 — s
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

PIC16(L)F18857/77
FIGURE 37-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
TABLE 37-18: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Operating Temperature -40°C TA +125°C
Param.
No.
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
42* TT0P T0CKI Period Greater of: — — ns N = prescale value
20 or TCY + 40
N
45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value
Period 30 or TCY + 40
N
48 F T1 Secondary Oscillator Input Frequency Range 32.4 32.768 33.1 kHz
(oscillator enabled by setting bit SOSCEN)
49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync
Increment mode
tested.

PIC16(L)F18857/77
FIGURE 37-13: CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCPx
(Capture mode)
CC01 CC02
CC03
Note: Refer to Figure 37-4 for load conditions.
TABLE 37-19: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Operating Temperature -40°C  TA  +125°C
Param.
No.
CC01* TccL CCPx Input Low Time No Prescaler 0.5TCY + 20 — — ns
CC02* TccH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns
CC03* TccP CCPx Input Period 3TCY + 40 — — ns N = prescale value
N
tested.

PIC16(L)F18857/77
FIGURE 37-14: CLC PROPAGATION TIMING
Rev. 10-000031A
6/16/2016
CLC LCx_in[n](1) CLC CLC

CLCxINn CLCx
Input time Module LCx_out(1) Output time
CLC CLC CLC

CLCxINn
Input time Module Output time
CLCx
LCx_in[n](1) LCx_out(1)
CLC01 CLC02 CLC03
Note 1: See Figure 22-1 to identify specific CLC signals.
TABLE 37-20: CONFIGURABLE LOGIC CELL (CLC) CHARACTERISTICS

Operating temperature -40°C TA +125°C
Param.
No.
CLC01* TCLCIN CLC input time — 7 OS17 ns (Note 1)
CLC02* TCLC CLC module input to output progagation time — 24 — ns VDD = 1.8V
— 12 — ns VDD > 3.6V
CLC03* TCLCOUT CLC output time Rise Time — OS18 — — (Note 1)
Fall Time — OS19 — — (Note 1)
CLC04* FCLCMAX CLC maximum switching frequency — 32 FOSC MHz
tested.
Note 1: See Table 37-10 for OS17, OS18 and OS19 rise and fall times.

PIC16(L)F18857/77
FIGURE 37-15: EUSART SYNCHRONOUS TRANSMISSION (HOST/CLIENT) TIMING
CK
US121 US121
DT
US120 US122
TABLE 37-21: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US120 TCKH2DTV SYNC XMIT (Host and Client) — 80 ns 3.0V  VDD  5.5V
Clock high to data-out valid — 100 ns 1.8V  VDD  5.5V
US121 TCKRF Clock out rise time and fall time — 45 ns 3.0V  VDD  5.5V
(Host mode) — 50 ns 1.8V  VDD  5.5V
US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V  VDD  5.5V
— 50 ns 1.8V  VDD  5.5V
FIGURE 37-16: EUSART SYNCHRONOUS RECEIVE (HOST/CLIENT) TIMING
CK
US125
DT
US126
TABLE 37-22: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Param.
No.
US125 TDTV2CKL SYNC RCV (Host and Client)
Data-setup before CK  (DT hold time) 10 — ns
US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns

PIC16(L)F18857/77
FIGURE 37-17: SPI HOST MODE TIMING (CKE = 0, SMP = 0)
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SDO MSb bit 6 - - - - - -1 LSb
SP75, SP76
SDI MSb In bit 6 - - - -1 LSb In
SP74
SP73
FIGURE 37-18: SPI HOST MODE TIMING (CKE = 1, SMP = 1)
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SP78
SP75, SP76
SP74

PIC16(L)F18857/77
FIGURE 37-19: SPI CLIENT MODE TIMING (CKE = 0)
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP75, SP76 SP77
SP74
SP73
FIGURE 37-20: SPI CLIENT MODE TIMING (CKE = 1)
SP82
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SCK
(CKP = 1)
SP80
SP77
SP75, SP76
SDI
MSb In bit 6 - - - -1 LSb In
SP74

PIC16(L)F18857/77
TABLE 37-23: SPI MODE REQUIREMENTS
Param.
Symbol Characteristic Min. Typ† Max. Units Conditions
No.
SP70* TSSL2SCH, SS to SCK or SCK input 2.25*TCY — — ns

TSSL2SCL
SP71* TSCH SCK input high time (Client mode) TCY + 20 — — ns
SP72* TSCL SCK input low time (Client mode) TCY + 20 — — ns
SP73* TDIV2SCH, Setup time of SDI data input to SCK 100 — — ns
TDIV2SCL edge
SP74* TSCH2DIL, Hold time of SDI data input to SCK edge 100 — — ns
TSCL2DIL
SP75* TDOR SDO data output rise time — 10 25 ns 3.0V  VDD  5.5V
— 25 50 ns 1.8V  VDD  5.5V
SP76* TDOF SDO data output fall time — 10 25 ns
SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns
SP78* TSCR SCK output rise time — 10 25 ns 3.0V  VDD  5.5V
(Host mode) — 25 50 ns 1.8V  VDD  5.5V
SP79* TSCF SCK output fall time (Host mode) — 10 25 ns
SP80* TSCH2DOV, SDO data output valid after SCK edge — — 50 ns 3.0V  VDD  5.5V
TSCL2DOV — — 145 ns 1.8V  VDD  5.5V
SP81* TDOV2SCH, SDO data output setup to SCK edge 1 Tcy — — ns
TDOV2SCL
SP82* TSSL2DOV SDO data output valid after SS edge — — 50 ns
SP83* TSCH2SSH, SS after SCK edge 1.5 TCY + 40 — — ns
TSCL2SSH
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

PIC16(L)F18857/77
FIGURE 37-21: I2C BUS START/STOP BITS TIMING
SCL
SP91 SP93
SP90 SP92
SDA
Start Stop
Condition Condition
TABLE 37-24: I2C BUS START/STOP BITS REQUIREMENTS

Param.
Symbol Characteristic Min. Typ Max. Units Conditions
No.
SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Start
Setup time 400 kHz mode 600 — — condition
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first clock
Hold time 400 kHz mode 600 — — pulse is generated
SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
FIGURE 37-22: I2C BUS DATA TIMING
SP103 SP100 SP102

SP101
SCL
SP90
SP106
SP107
SP91 SP92
SDA
In
SP110
SP109
SP109
SDA
Out

PIC16(L)F18857/77
TABLE 37-25: I2C BUS DATA REQUIREMENTS
Param.
No.
SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns
time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10-400 pF
SP103* TF SDA and SCL fall time 100 kHz mode — 250 ns
400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1)
clock 400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free
400 kHz mode 1.3 — s before a new transmission
can start
SP111 CB Bus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement
TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of
the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL
line is released.

PIC16(L)F18857/77
38.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Unless otherwise noted, all graphs apply to both the L and LF devices.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each
temperature range.

PIC16(L)F18857/77
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
6 3.0
Graph represents 3ı Limits

5 Graph represents 3ı Limits
2.5
-40°C
4 2.0
VOH (V)
VOL (V)
3 1.5
25°C
Typical
yp
125°C 125°C -40°C
2 1.0
1 0.5
0 0.0
-45 -40 -35 -30 -25 -20 -15 -10 -5 0 0 5 10 15 20 25 30 35 40 45 50 55 60
IOH (mA) IOL (mA)
FIGURE 38-1: VOH vs. IOH Over FIGURE 38-4: VOL vs. IOL Over
Temperature, VDD = 5.0V, PIC16F18857/77 Temperature, VDD = 3.0V.
Only.
2.0
5 1.8
1.6
1.4
4
-40°C
1.2
125°C
VOH (V)
1.0
3
Typical
VOL (V)
0.8
0.6
2
25°C 0.4
125°C -40°C 0.2

02
1
0.0
-8 -7.5 -7 -6.5 -6 -5.5 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0
0 IOH (mA)
0 10 20 30 40 50 60 70 80 90 100 110
IOL (mA) FIGURE 38-5: VOH vs. IOH Over
FIGURE 38-2: VOL vs. IOL Over Temperature, VDD = 1.8V, PIC16LF18857/77
Temperature, VDD = 5.0V, PIC16F18857/77 Only.
Only.
1.8

3.5 1.6
Graph represents 3ı Limits 1.4

3.0
1.2
125°C Typical -40°C
2.5
VOL (V)
2.0 0.8
VOH (V)
-40°C
0.6
15
1.5
Typical 125°C 0.4
1.0
0.2
02
0.5 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
0.0
IOL (mA)
-30 -25 -20 -15 -10 -5 0
IOH (mA)
FIGURE 38-6: VOL vs. IOL Over
FIGURE 38-3: VOH vs. IOH Over Temperature, VDD = 1.8V, PIC16LF18857/77
Temperature, VDD = 3.0V. Only.

PIC16(L)F18857/77
36,000
4.2
35,000
34,000 4.1
33,000
Frequency (Hz)
ms)
Time (m
32,000 40
4.0
31,000
30,000 3.9
29,000
28,000 3.8
1.7 2.0 2.3 2.6 2.9 3.2 3.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V) VDD (V)
Typical 25°C
25 C +3 Sigma (-40°C
(-40 C to 125
125°C)
C) -3 Sigma (-40°C
(-40 C to 125°C)
125 C) Typical 25°C +3ı (-40°C to +125°C) -3ı (-40°C to +125°C)
FIGURE 38-7: LFINTOSC Frequency, FIGURE 38-10: WDT Time-Out Period,

PIC16LF18857/77 Only. PIC16LF18857/77 Only.
36,000
35,000
34,000
33,000
Frequency (Hz)
32,000
31,000
30,000
29,000
28,000
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)
Typical 25°C +3 Sigma (-40°C to 125°C) -3 Sigma (-40°C to 125°C)
FIGURE 38-8: LFINTOSC Frequency, FIGURE 38-11: Brown-Out Reset Voltage,

PIC16F18857/77 Only. Trip Point (BORV = 00).
4.2
4.1
ms)
Time (m
40
4.0
3.9
3.8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
Typical 25°C +3ı (-40°C to +125°C) -3ı (-40°C to +125°C)
FIGURE 38-9: WDT Time-Out Period, FIGURE 38-12: Brown-Out Reset Hysteresis,
PIC16F18857/77 Only. Low Trip Point (BORV = 00).

PIC16(L)F18857/77
FIGURE 38-13: Brown-Out Reset Voltage, FIGURE 38-16: Brown-Out Reset

Trip Point (BORV = 01). Hysteresis, Trip Point (BORV = 1x).
2.10
2.05
2.00
1.95
Voltage (V)
1.90
1.85
1.80
1.75
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
+3 Sigma Typical -3 Sigma
FIGURE 38-14: Brown-Out Reset FIGURE 38-17: Brown-Out Reset Voltage,

Hysteresis, Trip Point (BORV = 01). Trip Point (BORV = 11).
50.0
45.0
40.0
35.0
30.0
Voltage (mV)
25.0
20.0
15.0
10.0
5.0
0.0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
+3 Sigma Typical
FIGURE 38-15: Brown-Out Reset Voltage, FIGURE 38-18: Brown-Out Reset

Trip Point (BORV = 1x). Hysteresis, Trip Point (BORV = 11),
PIC16LF18857/77 Only.

PIC16(L)F18857/77
75.0
73.0
71.0
69.0
Time (ms)
67.0
65.0
63.0
61.0
59.0
57.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
Typical 25°C + 3ı (-40°C to +125°C) - 3ı (-40°C to +125°C)
FIGURE 38-19: LPBOR Reset Voltage, FIGURE 38-22: PWRT Period,

1.7
+3 Sigma
1.675
1.65 Typical
Voltage (V)
1.625
-3 Sigma
1.6
1.575
1.55
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 38-20: LPBOR Reset Hysteresis, FIGURE 38-23: POR Release Voltage.
1.6
1.8 Typical
Max: Typical + 3ı
1.4 +3 Sigma
1.7 Typical: 25°C
74.0 Min: Typical - 3ı
1.2
1.6
72.0 1
(V) (V)
Voltage
1.5
0.8 Typical
70.0
Voltage
0.6
1.4
Time (ms)
68.0
0.4 -3 Sigma
1.3
66.0 0.2
1.2
0
64.0
-40 -20 0 20 40 60 80 100 120
1.1
Temperature (°C)
62.0
1
60.0 -40 -20 0 20 40 60 80 100 120
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Temperature (°C)
VDD (V)
FIGURE 38-24: POR Rearm Voltage,

FIGURE 38-21: PWRT Period, VREGPM1 = 0, PIC16F18857/77 Only.

PIC16F18857/77 Only.

PIC16(L)F18857/77
1.6
1.8 Typical 120
Max: Typical + 3ı
1.4
1.7 Typical: 25°C 110
Min: Typical - 3ı
1.2
1.6 +3 Sigma
100
1.5
1 90
(V) (V)
1.4
Voltage
0.8 80
Time (us)
1.3
Voltage
0.6 Typical 70
1.2
0.4 60
1.1
0.2 50
1 -3 Sigma
40
0
0.9 -40 -20 0 20 40 60 80 100 120 30
0.8 Temperature (°C)
20
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.7
-40 -20 0 20 40 60 80 100 120 VDD (V)
Temperature (°C)
( C) Typical 25°C +3ı (-40°C to +125°C)
FIGURE 38-25: POR Rearm Voltage, FIGURE 38-28: Wake From Sleep,
VREGPM1 = 1, PIC16F18857/77 Only. VREGPM = 1, HFINTOSC = 4 MHz,
1.8
28
+3 Sigma
1.6
27
1.4 26
Voltage (V)
Typical 25
Time (us)
1.2
24
1
23
-3 Sigma
0.8 22
21
0.6
-40 -20 0 20 40 60 80 100 120 20
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Temperature (°C)
VDD (V)
FIGURE 38-26: POR Rearm Voltage, Typical 25°C +3ı (-40°C to +125°C)
Normal Power Mode, PIC16LF18857/77 Only. FIGURE 38-29: Wake From Sleep,
VREGPM = 0, HFINTOSC = 16 MHz,
18
17
120
16 110
Time (us)
100
15
90
Time (us)
14
80
13 70
60
12
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
50
VDD (V)
Typical 25°C +3ı (-40°C to +125°C)
40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 38-27: Wake From Sleep, VDD (V)
VREGPM = 0, HFINTOSC = 4 MHz, Typical 25°C +3ı (-40°C to +125°C)
PIC16F18857/77 Only. FIGURE 38-30: Wake From Sleep,

VREGPM = 1, HFINTOSC = 16 MHz,

PIC16(L)F18857/77
700 1.0
650
600 0.5
550
DNL (LSb)
Time (us)
500 0.0
450
400
-0.5
350
300
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 -1.0
0 128 256 384 512 640 768 896 1024
VDD (V)
Output Code
Typical 25°C + 3ı (-40°C to +125°C)
FIGURE 38-31: Wake From Sleep, FIGURE 38-34: ADC, DNL, VDD = 3.0V,
VREGPM = 1, LFINTOSC, PIC16F18857/77 TAD = 4 S, 25°C.
Only.
1.0
700
650
0.5
600
INL (LSb)
550
Time (us)
0.0
500
450
-0.5
400
350
-1.0
300 0 128 256 384 512 640 768 896 1024
1.7 2.2 2.7 3.2 3.7
Output Code
VDD (V)
Typical 25°C + 3ı (-40°C to +125°C) FIGURE 38-35: ADC, INL, VDD = 3.0V,
FIGURE 38-32: Wake From Sleep, TAD = 1 S, 25°C.
LFINTOSC, PIC16LF18857/77 Only.
1.0
1.0
0.5
INL (LSb)
0.5
DNL (LSb)
0.0
0.0
-0.5
-0.5
-1.0
0 128 256 384 512 640 768 896 1024
-1.0
Output Code
0 128 256 384 512 640 768 896 1024
Output Code
FIGURE 38-36: ADC, INL, VDD = 3.0V,
FIGURE 38-33: ADC, DNL, VDD = 3.0V, TAD = 4 S, 25°C.
TAD = 1 S, 25°C.

PIC16(L)F18857/77
1.5 1.5
1 1
Max
Max 0.5
0.5
INL (LSb)
DNL (LSb)
0 0
-0.5 -0.5
Min
Min
-1 -1
-1.5 -1.5
5.00E-07 1.00E-06 2.00E-06 4.00E-06 8.00E-06 1.8 2.3 3.0
TAD (S) VREF
FIGURE 38-37: ADC 10-bit Mode, FIGURE 38-40: ADC 10-bit Mode,
Single-Ended DNL, VDD = 3.0V, VREF = 3.0V. Single-Ended INL, VDD = 3.0V, TAD = 1 S.
900
800
1.5
700
1 600
ADC Output Codes

500
Max
0.5
400
INL (LSb)
300
0
200
ADC VREF+ set to VDD
-0.5 100 ADC VREF- set to Gnd
Min
0
-1 2.9 3.4 3.9 4.4 4.9 5.4
VDD (V)
-1.5 Typical +3 Sigma -3 Sigma

5.00E-07 1.00E-06 2.00E-06 4.00E-06 8.00E-06
TAD(S) FIGURE 38-41: Temp. Indicator Initial Offset,
FIGURE 38-38: ADC 10-bit Mode, High Range, Temp. = 20°C, PIC16F18857/77
Single-Ended INL, VDD = 3.0V, VREF = 3.0V. Only.
1.5 1,000
900
1
800
Max
0.5
ADC Output Codes
700
DNL (LSb)
0
600
-0.5 500

Min 400 ADC VREF- set to Gnd
-1
300
2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4
-1.5
VDD (V)
1.8 2.3 3.0
VREF Typical +3 Sigma -3 Sigma
FIGURE 38-39: ADC 10-bit Mode, FIGURE 38-42: Temp. Indicator Initial Offset,
Single-Ended DNL, VDD = 3.0V, TAD = 1 S. Low Range, Temp. = 20°C, PIC16F18857/77
Only.

PIC16(L)F18857/77
900 250
200
800
150
700
100
ADC Output Codes

ADC Output Codes
600 50
0
500
-50
400
-100 ADC VREF+ set to VDD
ADC VREF- set to Gnd
300 -150
2.2 2.5 2.8 3.1 3.4 3.7 -40 -20 0 20 40 60 80 100 120
VDD (V) Temperature (°C)
Typical Max Min Typical +3 Sigma -3 Sigma
FIGURE 38-43: Temp. Indicator Initial Offset, FIGURE 38-46: Temp. Indicator Slope
Low Range, Temp. = 20°C, PIC16LF18857/77 Normalized to 20°C, High Range, VDD = 3.0V.
Only.
150 120
125 100
100 80
75 60
ADC Output Codes
ADC Output Codes

50 40
25 20
0
0
-25
-20
-50 ADC VREF+ set to VDD ADC VREF+ set to VDD
ADC VREF- set to Gnd -40 ADC VREF- set to Gnd
-75
-40 -20 0 20 40 60 80 100 120 -60
-40 -20 0 20 40 60 80 100 120
Temperature (°C) Temperature (°C)
Typical +3 Sigma -3 Sigma Typical +3 Sigma -3 Sigma
FIGURE 38-44: Temp. Indicator Slope FIGURE 38-47: Temp. Indicator Slope
Normalized to 20°C, High Range, VDD = 5.5V, Normalized to 20°C, Low Range, VDD = 3.6V.
150
230
180 100
130
50
ADC Output Codes
ADC Output Codes
80
30 0
-20
-50
-70 ADC VREF+ set to VDD

ADC VREF+ set to VDD ADC VREF- set to Gnd
-100
-120 -40 -20 0 20 40 60 80 100 120
-40 -20 0 20 40 60 80 100 120 Temperature (°C)
Temperature (°C)
Typical +3 Sigma -3 Sigma

FIGURE 38-48: Temp. Indicator Slope
FIGURE 38-45: Temp. Indicator Slope Normalized to 20°C, Low Range, VDD = 3.0V.
Normalized to 20°C, High Range, VDD = 3.6V.

PIC16(L)F18857/77
200
30
25
150
20
100 15
Offset Voltage (mV)

MAX
ADC Output Codes
10
50 5
0
0
-5
-10
-50 MIN
ADC VREF+ set to VDD -15
-100 -20
-40 -20 0 20 40 60 80 100 120 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Temperature (°C)
Typical +3 Sigma -3 Sigma Common Mode Voltage (V)
FIGURE 38-49: Temp. Indicator Slope FIGURE 38-52: Comparator Offset,

Normalized to 20°C, Low Range, VDD = 2.3V. NP Mode (CxSP = 1), VDD = 3.0V, Typical
Measured Values from -40°C to 125°C.
45
43 50
-40°C
41
39 45
Hysteresis (mV)
25°C
37
Hysteresis (mV)
85°C 40
35 25°C
125° 125°
33 35
31
85°
29 30
27 -40°C
25
25
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
20
Common Mode Voltage (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
FIGURE 38-50: Comparator Hysteresis, Common Mode Voltage (V)
NP Mode (CxSP = 1), VDD = 3.0V, Typical FIGURE 38-53: Comparator Hysteresis,
Measured Values. NP Mode (CxSP = 1), VDD = 5.5V, Typical
Measured Values, PIC16F18857/77 Only.
30
25
30
20
25
15
Offset Voltage (mV)
20
10
MAX 15
Hysteresis (mV)
5 MAX
10
0
5
-5
0
MIN
-10
-5
-15
-10
MIN
-20
-15
0.0 0.5 1.0 1.5 2.0 2.5 3.0
-20
Common Mode Voltage (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FIGURE 38-51: Comparator Offset, Common Mode Voltage (V)
NP Mode (CxSP = 1), VDD = 3.0V, Typical FIGURE 38-54: Comparator Offset, NP Mode
Measured Values at 25°C. (CxSP = 1), VDD = 5.0V, Typical Measured Values
at 25°C, PIC16F18857/77 Only.

PIC16(L)F18857/77
0.025
40
0.02
30
0.015
Offset Voltage (mV)
20 0.01
DNL (LSb)
MAX 0.005
-40°C
10
25°C
0
85°C
0
-0.005 125°C
-0.01
-10
MIN
-0.015
-20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0.02
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
Common Mode Voltage (V) Output Code
FIGURE 38-55: Comparator Offset, NP Mode FIGURE 38-58: Typical DAC DNL Error,
(CxSP = 1), VDD = 5.5V, Typical Measured Values VDD = 3.0V, VREF = External 3V.
from -40°C to 125°C, PIC16F18857/77 Only.
140 0.00
Max: Typical + 3ı (-40°C to +125°C)
120 Typical; statistical mean @ 25°C -0.05
Min: Typical - 3ı (-40°C to +125°C)
-0.10
100
125°C -0.15
Time (nS)
80
INL (LSb)
-0.20
25°C -40°C
60 25°C
-0.25
85°C
40 -0.30 125°C
-40°C
-0.35
20
-0.40
0
1.7 2.0 2.3 2.6 2.9 3.2 3.5
-0.45
0 14 28 42 56 70 84 98 112126140154168182196210224238252
VDD (V)
Output Code
FIGURE 38-56: Comparator Response Time FIGURE 38-59: Typical DAC INL Error,
Over Voltage, NP Mode (CxSP = 1), Typical VDD = 3.0V, VREF = External 3V.
Measured Values, PIC16LF18857/77 Only.
0.020
90
0.015
80 Typical; statistical mean @ 25°C
0.010
70
125°C
60
DNL (LSb)
0.005
-40°C
Time (nS)
50 25°C
25°C 0.000
85°C
40
125°C
30 -0.005
20
-0.010
-40°C
10
-0.015
0 0 14 28 42 56 70 84 98 112126140154168182196210224238252
2.2 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 Output Code
VDD (V)
FIGURE 38-60: Typical DAC DNL Error,
FIGURE 38-57: Comparator Response Time VDD = 5.0V, VREF = External 5V,
Over Voltage, NP Mode (CxSP = 1), Typical PIC16F18857/77 Only.
Measured Values, PIC16F18857/77 Only.

PIC16(L)F18857/77
0.00 4.0
-0.05 3.5
-0.10 3.0
-0.15 2.5
Time (us)
INL (LSb)
-0.20 2.0
-40°C
25°C
-0.25 1.5
85°C
-0.30 125°C 1.0
-0.35 0.5
-0.40 0.0
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
-0.45 VDD (V)
0 14 28 42 56 70 84 98 112126140154168182196210224238252
Output Code Typical 25°C +3ı (-40°C to +125°C) -3ı (-40°C to +125°C)
FIGURE 38-61: Typical DAC INL Error, FIGURE 38-64: ADC RC Oscillator Period,
VDD = 5.0V, VREF = External 5V, PIC16F18857/77 Only.
24
70
22
Max.
60
20
50
DNL (LSb)
18 Time (us)
Typical 40
16
30
14
Min. Max: Typical + 3ı (-40°C to +125°C) 20

12 Typical; statistical mean @ 25°C
10
10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
Output Code Typical 25°C +3ı (-40°C to +125°C)
FIGURE 38-62: DAC INL Error, FIGURE 38-65: Bandgap Ready Time,
VDD = 3.0V, PIC16LF18857/77 Only. PIC16LF18857/77 Only.
5.0
5.0
4.5
4.5
4.0
4.0
3.5
3.5
3.0
Time (us)
3.0
Time (us)
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
0.0
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
VDD (V)
VDD (V)
Typical 25°C
25 C +3ı (-40
(-40°C
C to +125
+125°C)
C) -3ı (-40
(-40°C
C to +125
+125°C)
C)
Typical 25°C +3 Sigma 125°C
FIGURE 38-63: ADC RC Oscillator Period, FIGURE 38-66: BOR Response Time,

PIC16(L)F18857/77
7 700
6 600
5 500
Time (us)
Time (ns)
4 400
3 300
200
2
100
1
0
0 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)
VDD (V)
Typical 25°C +3 Sigma 125°C Typical 25°C +3 Sigma 125°C
FIGURE 38-67: BOR Response Time, FIGURE 38-70: Comparator Response Time,
PIC16F18857/77 Only. Rising Edge, PIC16LF18857/77 Only.
300 900
800
250
700
200 600
Time (ns)
Time (ns)
500
150
400
100 300
200
50
100
0 0
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VDD (V) VDD (V)

FIGURE 38-68: Comparator Response Time, FIGURE 38-71: Comparator Response Time,
Falling Edge, PIC16LF18857/77 Only. Rising Edge, PIC16F18857/77 Only.
250
70
200 60
50
150
Time (ns)
40
Time (us)
100 30
20
50
10 Note:
The FVR Stabiliztion Period applies when coming out of
RESET or exiting sleep mode.
0 0
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V) VDD (MV)
Typical 25°C +3 Sigma 125°C Typical 25°C +3ı (-40°C to +125°C)
FIGURE 38-69: Comparator Response Time, FIGURE 38-72: FVR Stabilization Period,
Falling Edge, PIC16F18857/77 Only. PIC16LF18857/77 Only.

PIC16(L)F18857/77
1.1% 1.0%
1.0%
0.8%
0.9%
0.8%
0.6%
0.7%
Error (%)
Error (%)
0.6% 0.4%
0.5%
0.4% 0.2%
0.3%
0.0%
0.2%
0.1%
-0.2%
0.0% 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
VDD (V)
VDD (V)
Typical -40°C Typical 25°C Typical 85°C Typical 125°C Typical -40°C Typical 25°C Typical 85°C Typical 125°C
FIGURE 38-73: Typical FVR Voltage 1x, FIGURE 38-76: FVR Voltage Error 2x,
PIC16LF18857/77 Only. PIC16F18857/77 Only.
1.2%
1.0%
1.0% 0.8%
0.6%
0.8%
Error (%)
Error (%)
0.4%
0.6%
0.2%
0.4%
0.0%
0.2%
-0.2%
0.0% -0.4%
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6
VDD (V) VDD (V)
Typical -40°C Typical 25°C Typical 85°C Typical 125°C
Typical -40°C
40°C Typical 25°C Typical 85°C Typical 125°C
FIGURE 38-74: FVR Voltage Error 1x, FIGURE 38-77: FVR Voltage Error 4x,
PIC16F18857/77 Only. PIC16F18857/77 Only.
1.0%
3.0%
0.8%
2.0%
0.6% 1.0%
0.0%
Error (%)
0.4%
Error (%)
-1.0%
0.2%
-2.0%
0.0%
-3.0%
-0.2%
-4.0%
-0.4% -5.0%
2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V) VDD (V)
Typical -40°C Typical 25°C Typical 85°C Typical 125°C Typical 25°C +3ı (-40°C to +125°C) -3ı (-40°C to +125°C)
FIGURE 38-75: FVR Voltage Error 2x, FIGURE 38-78: HFINTOSC Typical
PIC16LF18857/77 Only. Frequency Error, PIC16LF18857/77 Only.

PIC16(L)F18857/77
gg
3.0%
2.5
2.0%
2
1.0%
Voltage (V)
1.5
0.0%
Error (%)
-1.0% 1
-2.0%
0.5
-3.0%
0
-4.0% 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)
VDD (V)

FIGURE 38-79: HFINTOSC Typical FIGURE 38-82: Schmitt Trigger Low Values.
Frequency Error, PIC16F18857/77 Only.
3.0% 1.8
2.5% 1.6
2.0% 1.4
ltage (V)
1.5% 1.2
Voltage (
1.0% 1
Error (%)
0.8
0.5%
0.6
0.0%
0.4
-0.5%
0.2
-1.0%
0
-1.5% 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-2.0% VDD (V)
-50 0 50 100 150
Temperature (°C)
Typical +3 Sigma -3 Sigma

FIGURE 38-83: Input Level, TTL.
FIGURE 38-80: HFINTOSC Frequency
Error, VDD = 3.0V.
50
4 45
3.5 40
35
3
30
Time (ns)
2.5
Voltage (V)
25
2
20
1.5 15
1 10
5
0.5
0
0 1.5 2.5 3.5 4.5 5.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
VDD (V)
Typical 25°C +3 Sigma (-40°C to 125°C)

T i l 25°C
Typical +3ı
3 ((-40°C
40°C tto +125°C)
125°C) -3ı
3 ((-40°C
40°C to
t +125°C)
125°C)
FIGURE 38-84: Rise Time, Slew Rate

FIGURE 38-81: Schmitt Trigger High Values.
Control Enabled.

PIC16(L)F18857/77
60 4.00%
50 3.00% Typical; statistical mean @ 25°C
2.00%
40
Time (ns)
1 00%
1.00%
30
Error (%)
Max
0.00%
Min
20
-1.00% Average
10
-2.00%
0
-3.00%
1.5 2.5 3.5 4.5 5.5
VDD (V)
-4.00%
-32 -24 -16 -8 0 8 16 24 32
Min Center Max
Typical 25°C +3 Sigma (-40°C to 125°C) OSCTUNE Setting
FIGURE 38-85: Fall Time, Slew Rate Control FIGURE 38-88: OSCTUNE Center
Enabled. Frequency, PIC16LF18857/77 Only.
30
35.0
25 30.0
Pull-Up Current (uA)

20 25.0
Time (ns)
15 20.0
10 15.0
Pu
10.0
5
5.0
0
1.5 2.5 3.5 4.5 5.5
VDD (V) 0.0
2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
VDD (V)
Typical 25°C +3 Sigma (-40°C to 125°C)
FIGURE 38-86: Rise Time, Slew Rate FIGURE 38-89: Weak Pull-up Current,
Control Disabled. PIC16F18857/77 Only.
20
18
25.0
16
14
12 20.0
Time (ns)
Curre (uA)
10
Pull-Up Current
8 15.0
6
4 10.0
2
0 5.0
1.5 2.5 3.5 4.5 5.5
VDD (V)
0.0
Typical 25°C +3 Sigma (-40°C to 125°C) 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 38-87: Fall Time, Slew Rate Control
Disabled.
FIGURE 38-90: Weak Pull-up Current,

PIC16(L)F18857/77
39.0 DEVELOPMENT SUPPORT
Move a design from concept to production in record time with Microchip’s award-winning development tools. Microchip
tools work together to provide state of the art debugging for any project with easy-to-use Graphical User Interfaces (GUIs)
in our free MPLAB® X and Atmel Studio Integrated Development Environments (IDEs), and our code generation tools.
Providing the ultimate ease-of-use experience, Microchip’s line of programmers, debuggers and emulators work
seamlessly with our software tools. Microchip development boards help evaluate the best silicon device for an application,
while our line of third party tools round out our comprehensive development tool solutions.
Microchip’s MPLAB X and Atmel Studio ecosystems provide a variety of embedded design tools to consider, which sup-
port multiple devices, such as PIC® MCUs, AVR® MCUs, SAM MCUs and dsPIC® DSCs. MPLAB X tools are compatible
with Windows®, Linux® and Mac® operating systems while Atmel Studio tools are compatible with Windows.
Go to the following website for more information and details:
https://www.microchip.com/development-tools/

PIC16(L)F18857/77
40.0 PACKAGING INFORMATION
40.1 Package Marking Information
28-Lead SPDIP (.300”) Example
PIC16F18857
/SP e3
1525017
28-Lead SOIC (7.50 mm) Example
XXXXXXXXXXXXXXXXXXXX PIC16LF18857
XXXXXXXXXXXXXXXXXXXX /SO e3
XXXXXXXXXXXXXXXXXXXX
YYWWNNN 1525017
28-Lead SSOP (5.30 mm) Example
PIC16F18857
/SS e3
1525017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

PIC16(L)F18857/77
40.1 Package Marking Information (Continued)
28-Lead QFN (6x6 mm) Example
PIN 1 PIN 1
XXXXXXXX LF18857
XXXXXXXX /ML e3
YYWWNNN 1525017

Pb-free JEDEC® designator for Matte Tin (Sn)

PIC16(L)F18857/77
40-Lead PDIP (600 mil) Example
XXXXXXXXXXXXXXXXXX PIC16F18877
XXXXXXXXXXXXXXXXXX /P e3
XXXXXXXXXXXXXXXXXX
YYWWNNN 1525017
40-Lead UQFN (5x5x0.5 mm) Example
PIN 1 PIN 1
PIC16
LF18877
/MV e 3
1525017
40-Lead VQFN (5x5x0.9 mm) Example
PIN 1 PIN 1
PIC16
LF18877
/NHX e 3
1525017


PIC16(L)F18857/77
44-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX PIC16
XXXXXXXXXX F18877
XXXXXXXXXX /PT e3
YYWWNNN 1525017
44-Lead QFN (8x8x0.9 mm) Example
PIN 1 PIN 1
XXXXXXXXXXX LF18877
XXXXXXXXXXX /ML
XXXXXXXXXXX
YYWWNNN 1525017


PIC16(L)F18857/77
40.2 Package Details
The following sections give the technical details of the packages.
!
"# H ' * "'# ' J$ 5"+ ""' J &' '$'
'' GKK555* *K J
NOTE 1
E1
1 2 3
A A2
L c
A1 b1
b e eB
V'" X7Y;
*" [*'" X X\ ]
X#*/ &" X ^
' B7
' ' _ _
$$J J"" 9
B"' ' _ _
#$ ' #$ `$' ; 9 99
$$J`$' ; ^
\! [' 9 9j
' ' [ 9
[$ J"" ^
V [$`$' /
[ 5 [$`$' / ^
\! 5 6 B _ _ 9
"#
!"#$%&'# *! +/#'*#"'/ '$5' ' ' $
6&'7 ' "'
9 *" "$;$ '#$* $&" ' #" " $&" ' #" "" '%$? "$
*" $' ;@
B7G B"*" '%'!#" 55' #'' "
5 7B

PIC16(L)F18857/77
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

PIC16(L)F18857/77

PIC16(L)F18857/77

PIC16(L)F18857/77
$% & '* &!

"# H ' * "'# ' J$ 5"+ ""' J &' '$'
'' GKK555* *K J
D
N
E
E1
1 2
b
NOTE 1
e
c
A A2
φ
A1
L1 L
V'" [[; ;

*" [*'" X X\ ]
X#*/ &" X ^
' jB7
\! Y ' _ _
$$J J"" j ^
'$ && _ _
\! `$' ; ^ ^
$$J`$' ; 9 j
\! ['
H '[' [
H ' ' [ ;H
[$ J"" _
H ' { { ^{
[$`$' / _ 9^
"#
!"#$%&'# *! +/#'*#"'/ '$5' ' ' $
*" "$;$ '#$* $&" ' #" " $&" ' #" "" '%$** "$
9 *" $' ;@
B7G B"*" '%'!#" 55' #'' "
;HG & *" +#"#5' #'' +& & *' # ""
5 79B

PIC16(L)F18857/77

PIC16(L)F18857/77

PIC16(L)F18857/77

PIC16(L)F18857/77
+ ,4 " 5 7 9;9 +,"!
< $ *'' = 5$
"# H ' * "'# ' J$ 5"+ ""' J &' '$'
'' GKK555* *K J

PIC16(L)F18857/77
> 9 !

"# H ' * "'# ' J$ 5"+ ""' J &' '$'
'' GKK555* *K J
NOTE 1
E1
1 2 3
A A2
L c
b1
A1
b e eB
V'" X7Y;
*" [*'" X X\ ]
X#*/ &" X
' B7
' ' _ _
$$J J"" _
B"' ' _ _
#$ ' #$ `$' ; _ j
$$J`$' ; ^ _ ^
\! [' ^ _
' ' [ _
[$ J"" ^ _
V [$`$' / 9 _
[ 5 [$`$' / _ 9
\! 5 6 B _ _
"#
!"#$%&'# *! +/#'*#"'/ '$5' ' ' $
6&'7 ' "'
9 *" "$;$ '#$* $&" ' #" " $&" ' #" "" '%$? "$
*" $' ;@
B7G B"*" '%'!#" 55' #'' "
5 7jB

PIC16(L)F18857/77

PIC16(L)F18857/77

PIC16(L)F18857/77

PIC16(L)F18857/77
40-Lead Very Thin Plastic Quad Flat, No Lead Package (NHX) - 5x5x0.9 mm Body [VQFN]
With 3.7x3.7 mm Exposed Pad and Wettable Flanks
A1 40X
0.08 C
D A
0.10 C
N
B
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
TOP VIEW (A3)
0.10 C
A
C SEATING
L PLANE
0.10 C A B
D2 SIDE VIEW
0.10 C A B
A A
A4
E2
NOTE 1
2
D3
1
SECTION A-A
(K)
N
e 40X b
e
2 0.07 C A B
BOTTOM VIEW 0.04 C
Microchip Technology Drawing C04-425 Rev C Sheet 1 of 2

PIC16(L)F18857/77
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 40
Pitch e 0.40 BSC
Overall Height A 0.80 0.85 0.90
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.203 REF
Overall Length D 5.00 BSC
Exposed Pad Length D2 3.60 3.70 3.80
Overall Width E 5.00 BSC
Exposed Pad Width E2 3.60 3.70 3.80
Terminal Width b 0.15 0.20 0.25
Terminal Length L 0.30 0.40 0.50
Wettable Flank Height A4 0.10 – 0.19
Wettable Flank Width E3 – – 0.085
Terminal-to-Exposed-Pad K 0.25 REF
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-425 Rev C Sheet 2 of 2

PIC16(L)F18857/77
C1
X2
EV
G2
ØV
CH
C2 Y2 G1
EV
Y1
X1
SILK SCREEN E
RECOMMENDED LAND PATTERN

Units MILLIMETERS
Contact Pitch E 0.40 BSC
Optional Center Pad Width X2 3.80
Optional Center Pad Length Y2 3.80
Chamfer CH 0.38
Contact Pad Spacing C1 5.00
Contact Pad Width (X40) X1 0.20
Contact Pad Length (X40) Y1 0.80
Contact Pad to Pad (X36) G1 0.20
Contact Pad to Center Pad (X40) G2 0.20
Thermal Via Diameter V 0.30
Thermal Via Pitch EV 1.00
Notes:
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2425 Rev C

PIC16(L)F18857/77
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
D A
D1 B
NOTE 2
(DATUM A)
(DATUM B)
E1 E
NOTE 1 A A
2X
N
0.20 H A B
2X 1 2 3
0.20 H A B 4X 11 TIPS
TOP VIEW
0.20 C A B
A A2
C
SEATING PLANE
0.10 C A1
SIDE VIEW
1 2 3
NOTE 1
44 X b
e 0.20 C A B
BOTTOM VIEW
Microchip Technology Drawing C04-076C Sheet 1 of 2

PIC16(L)F18857/77
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
L θ
(L1)
SECTION A-A
Units MILLIMETERS
Number of Leads N 44
Lead Pitch e 0.80 BSC
Overall Height A - - 1.20
Standoff A1 0.05 - 0.15
Molded Package Thickness A2 0.95 1.00 1.05
Overall Width E 12.00 BSC
Molded Package Width E1 10.00 BSC
Overall Length D 12.00 BSC
Molded Package Length D1 10.00 BSC
Lead Width b 0.30 0.37 0.45
Lead Thickness c 0.09 - 0.20
Lead Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle θ 0° 3.5° 7°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Exact shape of each corner is optional.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076C Sheet 2 of 2

PIC16(L)F18857/77
44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP]
C1
44
1
2
G
C2
Y1
X1 E
SILK SCREEN
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Contact Pitch E 0.80 BSC
Contact Pad Width (X44) X1 0.55
Contact Pad Length (X44) Y1 1.50
Distance Between Pads G 0.25
Notes:
Microchip Technology Drawing No. C04-2076B

PIC16(L)F18857/77

PIC16(L)F18857/77

PIC16(L)F18857/77

PIC16(L)F18857/77
APPENDIX A: DATA SHEET Revision A (01/2016)
REVISION HISTORY Initial release of the document.
Revision F (03/2021)
Updated Figures 10-5, 20-1, and 20-3; Tables 3-8,
6-1, 9-2, 13-1, 28-4, 37-6, and 37-18; Updated
Registers 4-3, 6-4, 6-7, 13-2, 18-3, and 20-8.
Removed Register 26-6. Updated Sections 12.10.1,
18.2, 24.4, and 28.8.
Added 40-pin VQFN (5x5) pin diagram, added three
40-Lead VQFN (5x5x0.9 mm) diagrams in Package
Details, updated package marking information with
40-Lead VQFN (5x5x0.9 mm), updated Product Identi-
fication System. Other minor corrections.
Revision E (09/2020)
Updated Tables 1 and 3, added 40-pin VQFN (5x5) pin
diagram, updated Table 37-6, added three 40-Lead
VQFN (5x5x0.9 mm) diagrams in Package Details,
updated package marking information with 40-Lead
VQFN (5x5x0.9 mm), updated Product Identification
System, updated Equation 25-1; Other minor changes.
Revision D (08/2018)
Updated Table 37-2 and 37-3, updating specifications
D100, D102, D103 and D203 to properly match silicon
data.
Revision C (01/2018)
Updated the PIS page. Updated Registers 4-2 and
23-8; Sections 26.3 and 29.1; and Tables 1-2, 1-3, 3-9,
22-2, 29-3, 37-2, 37-3 and 37-12. Removed Section
12.14.10 (duplicate). Removed Table 3-8. Corrected
various typos.
Revision B (07/2017)
Removed Preliminary Status - Added Char Graphs;
Updated Figures 3-8, 3-9, 3-10, 6-1, 23-2, 27-1, 28-1,
29-2, 29-3, 29-8, 29-9, 29-10, 29-11, 29-12, 29-13,
32-14, 32-15, 32-18, 37-10; Registers 4-1, 4-3, 6-3,
8-2, 9-2, 12-2, 12-6, 12-12, 12-14, 12-16, 12-32, 12-33,
12-34, 12-35, 12-36, 12-37, 12-43, 12-45, 12-49, 20-9,
23-1, 23-3, 23-4, 27-2, 28-1, 28-3, 29-1, 31-4, 31-5,
31-6, 34-1, and 34-2; Sections 3.5.2, 9.1, 10.4.3, 21.5,
23.1.1, 23.1.4, 23.4.4, 23.5.2, 23.5.3, 29.1, 29.2, 31.6,
32.1.1, 32.6.9, 34.2, and 34.4; Tables 3-5, 3-6, 3-7, 3-8,
10-2, 20-2, 23-1, 31-3, 36-4, 37-3, 37-5, 37-11 and
37-13.
Added Figure 37-11. Added Section 6.2.2.4
MFINTOSC, 21.5.1 Correction by AC Coupling. Added
Section 28.4: Timer1 16-Bit Read/Write Mode.
Updated Instruction Sets MOVWF and NOP.
Remove Figure 37-11.

DEVICE FAMILY
THE MICROCHIP WEBSITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This website is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the website contains the following information:
• Field Application Engineer (FAE)
• Product Support – Data sheets and errata,
• Technical Support
application notes and sample programs, design
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or Field Application Engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the website
program member listing at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

PIC16(L)F18857/77
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) - X /XX XXX
Examples:
Device Tape and Reel Temperature Package Pattern a) PIC16F18857- E/SP
Option Range Extended temperature
SPDIP package
b) PIC16F18877- I/P
Industrial temperature
Device: PIC16F18857; PIC16LF18857;
PDIP package
PIC16F18877; PIC16LF18877
Tape and Reel Blank = Standard packaging (tube or tray)

Option: T = Tape and Reel(1)
Temperature I = -40C to +85C (Industrial)

Range: E = -40C to +125C (Extended)
Package:(2) ML = 28-lead QFN 6x6mm

ML = 44-lead QFN 8x8mm Note 1: Tape and Reel identifier only appears in
MV = 40-lead UQFN 5x5x0.5mm the catalog part number description. This
NHX = 40-lead VQFN 5x5x0.9mm identifier is used for ordering purposes and
P = 40-lead PDIP
PT = 44-lead TQFP 10x10x1 is not printed on the device package.
SO = 28-lead SOIC Check with your Microchip Sales Office
SP = 28-lead SPDIP for package availability with the Tape and
SS = 28-lead SSOP Reel option.
2: Small form-factor packaging options may
be available. Please check
Pattern: QTP, SQTP, Code or Special Requirements www.microchip.com/packaging for
(blank otherwise) small-form factor package availability, or
contact your local Sales Office.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specifications contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip
devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications
contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished
without violating Microchip's intellectual property rights.
• Microchip is willing to work with any customer who is concerned about the integrity of its code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or
other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication is provided for the sole Trademarks

purpose of designing with and using Microchip products. Infor- The Microchip name and logo, the Microchip logo, Adaptec,
mation regarding device applications and the like is provided AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
only for your convenience and may be superseded by updates. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
It is your responsibility to ensure that your application meets LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
with your specifications. Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
MICROCHIP MAKES NO REPRESENTATIONS OR WAR- SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A. and
WRITTEN OR ORAL, STATUTORY OR OTHERWISE, other countries.
RELATED TO THE INFORMATION INCLUDING BUT NOT
LIMITED TO ANY IMPLIED WARRANTIES OF NON- AgileSwitch, APT, ClockWorks, The Embedded Control Solutions
INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight
PARTICULAR PURPOSE OR WARRANTIES RELATED TO Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3,
Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-
ITS CONDITION, QUALITY, OR PERFORMANCE. Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, WinPath, and ZL are registered
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- trademarks of Microchip Technology Incorporated in the U.S.A.
RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN-
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DS40001825F-page 668  2016-2021 Microchip Technology Inc.

02/28/20

PIC16LF1885777 Data Sheet 40001825F

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PIC16(L)F18857/77

Full-Featured 28/40/44-Pin Microcontrollers

Core Features Power-Saving Functionality

 2016-2021 Microchip Technology Inc. DS40001825F-page 1

 2016-2021 Microchip Technology Inc. DS40001825F-page 2

CRC and Memory Scan

Peripheral Pin Select

PIC16(L)F18854 (1) 4096 7 256 512 25 24 1 2 3/4 2 Y Y 5/2 Y 3 1 4 1 1/2 Y Y

 2016-2021 Microchip Technology Inc. DS40001825F-page 3

Note: Pin details are subject to change.

28-pin SPDIP, SOIC, SSOP

Note 1: See Table 2 for location of all peripheral functions.

 2016-2021 Microchip Technology Inc. DS40001825F-page 4

28-pin QFN (6x6)

Note 1: See Table 3 for location of all peripheral function.

 2016-2021 Microchip Technology Inc. DS40001825F-page 5

40-pin UQFN (5x5)

Note 1: See Table 3 for location of all peripheral functions.

40-pin VQFN (5x5)

Note 1: See Table 3 for location of all peripheral functions.

 2016-2021 Microchip Technology Inc. DS40001825F-page 6

44-pin TQFP (10x10)

Note 1: See Table 3 for location of all peripheral functions.

44-pin QFN (8x8)

Note 1: See Table 3 for location of all peripheral functions.

 2016-2021 Microchip Technology Inc. DS40001825F-page 7

Clock Reference (CLKR)

CCP and PWM

RA0 2 27 ANA0 — — C1IN0- — — — — — — — CLCIN0(1) — — IOCA0 —

RA4 6 3 ANA4 — — — — — — MDCARH(1) T0CKI(1) CCP5(1) — — — — IOCA4 —

RA5 7 4 ANA5 — — — — SS1(1) — MDSRC(1) — — — — — — IOCA5 —

RA6 10 7 ANA6 — — — — — — — — — — — — — IOCA6 OSC2

Clock Reference (CLKR)

CCP and PWM

RB5 26 23 ANB5 — — — — — — — T1G(1) CCP3(1) — — — — IOCB5 —

RB7 28 25 ANB7 — DAC1OUT2 — — — — — T6IN(1) — — CLCIN3(1) — — IOCB7 ICSPDAT

RC0 11 8 ANC0 — — — — — — — T1CKI(1) — — — — — IOCC0 SOSCO

RC3 14 11 ANC3 — — — — SCL1(3,4) — — T2IN(1) — — — — — IOCC3 —

RC6 17 14 ANC6 — — — — — CK(3) — — — — — — — IOCC6 —

RC7 18 15 ANC7 — — — — — RX(1) — — — — — — — IOCC7 —

Clock Reference (CLKR)

CCP and PWM

Clock Reference (CLKR)

CCP and PWM

RA0 2 17 19 19 ANA0 — — C1IN0- — — — — — — — CLCIN0(1) — — IOCA0 —

RA5 7 22 24 24 ANA5 — — — — SS1(1) — MDSRC(1) — — — — — — IOCA5 —

RA6 14 29 33 31 ANA6 — — — — — — — — — — — — — IOCA6 OSC2

RB7 40 15 17 17 ANB7 — DAC1OUT2 — — — — — T6IN(1) — — CLCIN3(1) — — IOCB7 ICSPDAT

CCP and PWM

RC0 15 30 34 32 ANC0 — — — — — — — T1CKI(1) — — — — — IOCC0 SOSCO

RC2 17 32 36 36 ANC2 — — — — — — — T5CKI(1) CCP1(1) — — — — IOCC2 —

RC3 18 33 37 37 ANC3 — — — — SCL1(3,4) — — T2IN (1)

RC6 25 40 44 44 ANC6 — — — — — CK(3) — — — — — — — IOCC6 —

RC7 26 1 1 1 ANC7 — — — — — RX(1) — — — — — — — IOCC7 —

CCP and PWM

RE3 1 16 18 18 — — — — — — — — — — — — — — IOCE3 MCLR

 2016-2021 Microchip Technology Inc. DS40001825F-page 14

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