Pic32cm Mc00 Family Data Sheet Ds60001638d
Pic32cm Mc00 Family Data Sheet Ds60001638d
Pic32cm Mc00 Family Data Sheet Ds60001638d
Peripherals (Continued)
• CRC-32 generator
• Up to four Serial Communication Interfaces (SERCOM), each configurable
to operate as:
– USART with full-duplex and single-wire half-duplex configuration
– I2C up to 3.4 MHz
– SPI
– LIN host/client
– RS-485
• Configurable Custom Logic (CCL)
• Integrated Temperature Sensor
Table 1. Packages
Table of Contents
5-Volt, 128-KB Flash, 16-KB SRAM with Advanced Analog.......................................................................... 1
1. Configuration Summary.......................................................................................................................... 5
2. Ordering Information............................................................................................................................... 7
3. Block Diagram.........................................................................................................................................8
5. Signal Description................................................................................................................................. 19
7. Product Mapping................................................................................................................................... 24
8. Memories.............................................................................................................................................. 25
30. SERCOM Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART).............. 428
Trademarks................................................................................................................................................ 988
1. Configuration Summary
Table 1-1. PIC32CM MC00 Common Features
PIC32CM MC00
Maximum CPU frequency 48 MHz
Memory Protection Unit 8 regions
Systick timer 1
Serial Wire Debug Interface Yes
Oscillators 32.768 kHz crystal oscillator (XOSC32K)
0.4-32 MHz crystal oscillator (XOSC)
32.768 kHz internal oscillator (OSC32K)
32.768 kHz ultra low-power internal oscillator
(OSCULP32K)
48 MHz high-accuracy internal oscillator (OSC48M)
96 MHz Fractional Digital Phased Locked Loop
(FDPLL96M)
Generic Clock (GCLK) 9
DMA channels 12
Event System channels 12
External Interrupt lines 16 + 1 non-maskable
Divide and Square Root Accelerator (DIVAS) Yes
Waveform outputs/Capture inputs channels per TC instance 2
TC Maximum and Minimum Capture Yes
Timer Counter for Control (TCC) instances 3
Waveform output channels per TCC 8 for TCC0, 4 for TCC1, 2 for TCC2
Configurable Custom Logic (CCL) (number of LUTs) 4
Analog-to-Digital Converter (ADC) instances 2
Sigma-Delta Analog-to-Digital Converter (SDADC) 1
instances
Analog Comparators (AC) 1 AC made of 2 Comparators
Digital-to-Analog Converter (DAC) channels 1
Real-Time Counter (RTC) Yes
RTC alarms 1
RTC compare values One 32-bit value or two 16-bit values
Frequency Meter (FREQM) reference clock divider Yes
Watchdog Timer (WDT) Yes
Position Decoder (PDEC) Yes
Memories CRC32 computation (DSU) Yes (SRAM, Flash, Data Flash)
...........continued
PIC32CM MC00
Brown-out Detection (BOD) VDD, VDDCORE
2. Ordering Information
Figure 2-1. PIC32CM MC Family Ordering Information
Pin Count
032 = 32 pin
048 = 48 pin Tape and Reel Flag
T = Tape and Reel
No Character = Tray/Tube (Default)
Notes:
1. VQFN packages have wettable flanks.
2. Extended Temp devices are AEC-Q100 Qualified.
3. Block Diagram
IOBUS 128-KB
16-KB
TRACE BUFFER
RWW
CORTEX®-M0+ RAM
NVM
MICRO
SWCLK SERIAL PROCESSOR
Fmax 48 MHz NVM
SWDIO WIRE SRAM
CONTROLLER
CONTROLLER
Cache
DEVICE
SERVICE
UNIT
M M M S S
HIGH-SPEED
M DMA
Divide Accellerator S BUS MATRIX
PERIPHERAL S S S
ACCESS CONTROLLER
MAIN CLOCKS
CONTROLLER
PORT
OUT [3..0]
OSCILLATORS CONTROLLER 4x CCL
IN[11..0]
OSC48M
XIN DMA
PAD0
XOUT XOSC FDPLL96M PAD1
4x6SERCOM
x SERCOM PAD2
PAD3
GENERIC CLOCK
GCLK_IO[7..0]
PORT
CONTROLLER DMA
EVENT SYSTEM
WO0
WATCHDOG 5x TIMER/COUNTER
TIMER 8 x Timer Counter WO1
OSC32K
10-bit DAC
VREFA
RESETN RESET
CONTROLLER
FREQUENCY
METER DMA
INN[1:0]
2-CHANNEL INP[1:0]
TEMPERATURE
16-bit SDADC 3KSPS VREFB
SENSOR
PIC32CM1216MC00032
PIC32CM6408MC00032
Reset State
Pin name
SERCOM-ALT
Supply
CCL/PDEC
SERCOM
TC/TCC
SDADC
GCLK
PDEC
ADC0
ADC1
DAC
TCC
CCL
REF
AC/
EIC
AC
rotatethispage90
I/O,
PA00/ SERCOM1/ TCC2/
1 EXTINT[0] VDDANA HI-
XIN32 PAD[0] WO[0]
Z
I/O,
PA01/ SERCOM1/ TCC2/
2 EXTINT[1] VDDANA HI-
XOUT32 PAD[1] WO[1]
Z
I/O,
3 PA02 EXTINT[2] AIN[0] VOUT VDDANA HI-
Z
I/O,
4 PA03 EXTINT[3] VREFA AIN[1] VDDANA HI-
Z
Datasheet
I/O,
SERCOM0/ TCC0/ CCL/
5 PA04 EXTINT[4] VREFB AIN[4] AIN[0] VDDANA HI-
PAD[0] WO[0] IN[0]
Z
I/O,
SERCOM0/ TCC0/ CCL/
6 PA05 EXTINT[5] AIN[5] AIN[1] VDDANA HI-
PAD[1] WO[1] IN[1]
Z
I/O,
9 VDDANA VDDANA
DS60001638D-page 10
10 GNDANA GNDANA
I/O,
SERCOM0/ SERCOM2/ TCC0/ TCC1/ CCL/
11 PA08(1) NMI AIN[8] AIN[10] PDEC[0] VDDIO HI-
PAD[0] PAD[0] WO[0] WO[2] IN[3]
Z
and its subsidiaries
© 2021 Microchip Technology Inc.
...........continued
A B C D E F G H I J
32-pin QFP
Reset State
Pin name
SERCOM-ALT
Supply
CCL/PDEC
SERCOM
TC/TCC
SDADC
GCLK
PDEC
ADC0
ADC1
DAC
TCC
CCL
REF
AC/
EIC
AC
rotatethispage90
I/O,
SERCOM0/ SERCOM2/ TCC0/ TCC1/ CCL/
12 PA09(1) EXTINT[9] AIN[9] AIN[11] PDEC[1] VDDIO HI-
PAD[1] PAD[1] WO[1] WO[3] IN[4]
Z
I/O,
SERCOM0/ SERCOM2/ TCC1/ TCC0/ GCLK/ CCL/
13 PA10(2) EXTINT[10] AIN[10] PDEC[2] VDDIO HI-
PAD[2] PAD[2] WO[0] WO[2] IO[4] IN[5]
Z
I/O,
SERCOM0/ SERCOM2/ TCC1/ TCC0/ GCLK/ CCL/
14 PA11(2) EXTINT[11] AIN[11] VDDIO HI-
PAD[3] PAD[3] WO[1] WO[3] IO[5] OUT[1]
Z
I/O,
PA14/ SERCOM2/ TC4/ TCC0/ GCLK/
15 EXTINT[14] VDDIO HI-
XIN PAD[2] WO[0] WO[4] IO[0]
Z
Datasheet
I/O,
PA15/ SERCOM2/ TC4/ TCC0/ GCLK/
16 EXTINT[15] VDDIO HI-
XOUT PAD[3] WO[1] WO[5] IO[1]
Z
I/O,
SERCOM1/ SERCOM3/ TCC2/ TCC0/ PDEC/ GCLK/ CCL/
17 PA16(1) EXTINT[0] VDDIO HI-
I/O,
SERCOM1/ SERCOM3/ TCC2/ TCC0/ PDEC/ GCLK/ CCL/
18 PA17(1) EXTINT[1] VDDIO HI-
PAD[1] PAD[1] WO[1] WO[7] QDI[1] IO[3] IN[1]
Z
I/O,
SERCOM1/ SERCOM3/ TC4/ TCC0/ AC/ CCL/
20 PA19 EXTINT[3] VDDIO HI-
PAD[3] PAD[3] WO[1] WO[3] CMP[1] OUT[0]
Z
I/O,
SERCOM3/ TC0/ TCC0/ GCLK/ CCL/
21 PA22(1) EXTINT[6] VDDIO HI-
PAD[0] WO[0] WO[4] IO[6] IN[6]
Z
and its subsidiaries
© 2021 Microchip Technology Inc.
...........continued
A B C D E F G H I J
32-pin QFP
Reset State
Pin name
SERCOM-ALT
Supply
CCL/PDEC
SERCOM
TC/TCC
SDADC
GCLK
PDEC
ADC0
ADC1
DAC
TCC
CCL
REF
AC/
EIC
AC
rotatethispage90
I/O,
SERCOM3/ TC0/ TCC0/ GCLK/ CCL/
22 PA23(1) EXTINT[7] VDDIO HI-
PAD[1] WO[1] WO[5] IO[7] IN[7]
Z
I/O,
SERCOM3/ TC1/ TCC1/ CCL/
23 PA24 EXTINT[12] VDDIO HI-
PAD[2] WO[0] WO[2] IN[8]
Z
I/O,
SERCOM3/ TC1/ TCC1/ CCL/
24 PA25 EXTINT[13] VDDIO HI-
PAD[3] WO[1] WO[3] OUT[2]
Z
I/O,
GCLK/ CCL/
25 PA27 EXTINT[15] VDDIN HI-
IO[0] IN[10]
Z
Datasheet
I,
26 RESET(3) VDDIN
PU
I/O,
GCLK/ CCL/
27 PA28 EXTINT[8] VDDIN HI-
IO[0] IN[11]
Z
29 VDDCORE
30 VDDIN VDDIN
I/O,
PA31/ SERCOM1/ TCC1/ CCL/
32 EXTINT[11] VDDIN HI-
SWDIO PAD[3] WO[1] OUT[1]
Z
and its subsidiaries
© 2021 Microchip Technology Inc.
...........continued
A B C D E F G H I J
32-pin QFP
Reset State
Pin name
SERCOM-ALT
Supply
CCL/PDEC
SERCOM
TC/TCC
SDADC
GCLK
PDEC
ADC0
ADC1
DAC
TCC
CCL
REF
AC/
EIC
AC
rotatethispage90
Notes:
1. PA08, PA09, PA16, PA17, PA22, PA23 are TWIHS pins and have the same properties as standard pins when not used as SERCOM I2C pins. Refer to the Electrical Characteristics
section for additional information.
2. PA10, PA11 are high-sink pins and have different properties than all other GPIO. Refer to the electrical characteristics section for additional information.
3. The RESET pin has the same properties as standard GPIO.
Datasheet
PIC32CM1216MC00048
PIC32CM6408MC00048
Reset State
Pin name
SERCOM-ALT
Supply
CCL/PDEC
SERCOM
TC/TCC
SDADC
GCLK
PDEC
ADC0
ADC1
DAC
TCC
CCL
REF
AC/
EIC
AC
rotatethispage90
5 GNDANA GNDANA
6 VDDANA VDDANA
TC0/ CCL/
7 PB08 EXTINT[8] AIN[2] AIN[4] INN[1] VDDANA I/O, HI-Z
WO[0] IN[8]
Datasheet
TC0/ CCL/
8 PB09 EXTINT[9] AIN[3] AIN[5] INP[1] VDDANA I/O, HI-Z
WO[1] OUT[2]
...........continued
A B C D E F G H I J
48-pin QFN
Reset State
Pin name
SERCOM-ALT
Supply
CCL/PDEC
SERCOM
TC/TCC
SDADC
GCLK
PDEC
ADC0
ADC1
DAC
TCC
CCL
REF
AC/
EIC
AC
rotatethispage90
17 VDDIO VDDIO
18 GND GND
...........continued
A B C D E F G H I J
48-pin QFN
Reset State
Pin name
SERCOM-ALT
Supply
CCL/PDEC
SERCOM
TC/TCC
SDADC
GCLK
PDEC
ADC0
ADC1
DAC
TCC
CCL
REF
AC/
EIC
AC
rotatethispage90
35 GND GND
36 VDDIO VDDIO
GCLK/ CCL/
39 PA27 EXTINT[15] VDDIN I/O, HI-Z
IO[0] IN[10]
40 RESET(3) VDDIN I, PU
42 GND GND
43 VDDCORE
44 VDDIN VDDIN
...........continued
A B C D E F G H I J
48-pin QFN
Reset State
Pin name
SERCOM-ALT
Supply
CCL/PDEC
SERCOM
TC/TCC
SDADC
GCLK
PDEC
ADC0
ADC1
DAC
TCC
CCL
REF
AC/
EIC
AC
rotatethispage90
TC2/ CCL/
47 PB02 EXTINT[2] AIN[2] VDDANA I/O, HI-Z
WO[0] OUT[0]
TC2/
48 PB03 EXTINT[3] AIN[3] VDDANA I/O, HI-Z
WO[1]
Notes:
1. PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23 are TWIHS pins and have the same properties as standard pins when not used as SERCOM I2C pins. Refer to the Electrical
Characteristics section for additional information.
2. PA10, PA11, PB10, PB11 are high-sink pins and have different properties than all other GPIO. Refer to the electrical characteristics section for additional information.
3. The RESET pin has the same properties as standard GPIO.
Datasheet
5. Signal Description
The following tables provide the details on signal names classified by the peripheral.
Table 5-1. Signal Descriptions List
PA31-PA30, PA28-PA27, PA25-PA00 General Purpose I/O Pin in Port A Digital I/O
GCLK_IO[8:0] (2) Generic Clock Source (Input) or Generic Clock Signal (Output) Digital I/O
XIN Crystal Input or External Clock Input Analog Input (Crystal Oscillator) Digital Input (External Clock)
XIN32 32 kHz Crystal Input or External Clock Input Analog Input (Crystal Oscillator) Digital Input (External Clock)
...........continued
Signal Name Function Type
Notes:
1. VREFA is shared between the ADC and DAC peripherals.
2. GCLK8 does not support an input/output on a pin.
VDDCORE
PA[28:27]
PA[31:30]
GNDANA
VDDANA
VDDIO
VDDIN
GND
ADC0
Voltage OSC48M TOSC(1)
PA[7:2]
ADC1 Regulator
PB[3:2]
AC BODCORE
PB[9:8]
DAC
SDADC PA[25:16]
Digital Logic PA[13:8]
(CPU, PD1
Peripherals) POR
POR Digital Logic PB[23:22]
SERCOM[4:0],
TCC[2:0] PB[11:10]
BOD50 FDPLL96M
TC[3:0], DAC,
I2S,
LOWAES, TRNG
POWER
OSCULP32K NVM
PAC, DMAC XOSC
RAM
PA[15:14]
OSC32K LOW POWER
SRAM
RAM
PA[1:0] XOSC32K
Note:
1. TOSC is an independent Oscillator for the internal Temperature Sensor.
6.3 Power-Up
This section summarizes the power-up sequence of the PIC32CM MC. The behavior after power-up is controlled by
the Power Manager.
7. Product Mapping
Figure 7-1. PIC32CM MC00 Product Mapping
Global Memory Space Code AHB-APB Bridge C
0x00000000
0x00000000 Internal Flash 0x42000000
0x00020000 NVM MAIN 128KB EVSYS
FLASH 0x00400000 Internal Flash 0x42000400
0x00401000 (Data Flash) 4KB SERCOM0
0x20000000
0x00800000 Internal Flash 0x42000800
CAL/AUX SERCOM1
SRAM 0x0080A04C
0x42000C00
Reserved
0x22008000 SERCOM2
0x1FFFFFFF
0x42001000
Undefined SERCOM3
SRAM 0x42001400
0x40000000 0x20000000 Reserved
0x42001800
Peripherals SRAM Reserved
0x48000200 0x42001C00
0x20004000
Reserved
Reserved 0x42002000
AHB-APB Reserved
0x60000000 0x40000000 0x42002400
AHB-APB TCC0
0x60000000 IOBUS Bridge A 0x42002800
PORT 0x41000000 TCC1
0x60000200 0x60000400
AHB-APB 0x42002C00
DIVAS Bridge B TCC2
0x60000220 Reserved
0x42003000
0x42000000
Reserved 0xFFFFFFFF TC0
0x600003FF AHB-APB 0x42003400
Bridge C TC1
0x44000000
AHB-APB Bridge A 0x42003800
Reserved TC2
0x40000000
0x42003C00
PAC 0x45000000 TC3
0x40000400
PM Reserved 0x42004000
TC4
0x40000800
0x48000000 0x42004400
MCLK AHB ADC0
0x40000C00 DIVAS 0x42004800
RSTC 0x480001FF ADC1
0x40001000
AHB-APB Bridge B 0x42004C00
OSCCTRL SDADC
0x41000000
0x40001400
PORT 0x42005000
OSC32KCTRL 0x41002000 AC
0x40001800
DSU 0x42005400
SUPC DAC
0x40001C00 0x41004000
NVMCTRL 0x42005800
GCLK 0x41006000 Reserved
0x40002000 0x42005C00
DMAC
WDT 0x41008000 CCL
0x40002400 0x42006000
MTB
RTC Reserved
0x4100A000
0x40002800 0x42006400
Reserved
EIC 0x41FFFFFF Reserved
0x40002C00
0x42006800
FREQM PDEC
0x40003000
0x42006C00
TSENS Reserved
0x40003400 0x42FFFFFF
Reserved
0x40FFFFFF
8. Memories
...........continued
Bit Position Name Usage Production Related Peripheral Register
setting
13:8 BODVDD Level BODVDD Threshold Level at 0x8 SUPC.BODVDD.LEVEL
power on.
14 BODVDD Disable BODVDD Disable at power 0x0 SUPC.BODVDD.ENABLE
on.
16:15 BODVDD Action BODVDD Action at power 0x1 SUPC.BODVDD.ACTION
on.
25:17 BODCORE DO NOT CHANGE (1) 0x0A8 -
calibration
26 WDT Enable WDT Enable at power on. 0x0 WDT.CTRLA.ENABLE
27 WDT Always-On WDT Always-On at power 0x0 WDT.CTRLA.ALWAYSON
on.
31:28 WDT Period WDT Period at power on. 0xB WDT.CONFIG.PER
35:32 WDT Window WDT Window mode time-out 0xB WDT.CONFIG.WINDOW
at power on.
39:36 WDT EWOFFSET WDT Early Warning Interrupt 0xB WDT.EWCTRL.EWOFFSET
Time Offset at power on.
40 WDT WEN WDT Timer Window Mode 0x0 WDT.CTRLA.WEN
Enable at power on.
41 BODVDD BODVDD Hysteresis 0x0 SUPC.BODVDD.HYSTERESIS
Hysteresis configuration at power on.
42 BODCORE DO NOT CHANGE (1) 0x0 -
calibration
47:43 Reserved - 0x1F -
63:48 LOCK NVM Region Lock Bits. 0xFFFF NVMCTRL.LOCK
Note:
1. BODCORE is calibrated in production and its calibration parameters must not be changed to ensure the
correct device behavior.
...........continued
Bit Position Name Description
18:12 OSC32K CAL OSC32K Calibration. Should be written to OSC32KCTRL OSC32K.CALIB.
40:19 CAL48M OSC48M Calibration: Should be written to OSCCTRL.CAL48M[21:0].
63:41 Reserved Reserved
When the SysTick Overflow Interrupt is enabled, the RAM Back Bias Control must be disabled (PM-
>STDBYCFG.bit.BBIASHS = 0) before entering Standby Sleep mode.
• System Control Block (SCB)
– The System Control Block provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions. Refer to Cortex-M0+ Devices Generic User
Guide for details (www.arm.com).
• Micro Trace Buffer (MTB)
– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+ processor.
Refer to the section 9.3 Micro Trace Buffer and CoreSight MTB-M0+ Technical Reference Manual for
details (www.arm.com).
• Memory Protection Unit (MPU)
– The Memory Protection Unit divides the memory map into a number of regions, and defines the location,
size, access permissions and memory attributes of each region. Refer to Cortex-M0+ Devices Generic
User Guide for details (http://www.arm.com)
Address Peripheral
0xE000E000 System Control Space (SCS)
0xE000E010 System Timer (SysTick)
0xE000E100 Nested Vectored Interrupt Controller (NVIC)
0xE000ED00 System Control Block (SCB)
0xE000ED90 Memory Protection Unit (MPU)
0x41008000 Micro Trace Buffer (MTB)
9.1.4.1 Overview
Because accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently, the
Cortex-M0+ processor can fetch the next instructions while accessing the I/Os. This enables single cycle I/O
accesses to be sustained for as long as needed.
9.1.4.2 Description
Direct access to PORT registers and DIVAS registers.
9.2.1 Overview
The Nested Vectored Interrupt Controller (NVIC) in the PIC32CM MC00 supports 32 interrupt lines with four different
priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (www.arm.com).
The interrupt requests for one peripheral are ORed together on system level, generating one interrupt request for
each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending
registers (SETPEND/CLRPEND bits in ISPR/ICPR).
For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA
bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.
Table 9-3. Interrupt Line Mapping, PIC32CM MC00
...........continued
Peripheral Source NVIC Line
SDADC 25
Position Decoder (PDEC) 26
Reserved 27-31
Note:
1. These modules are not available on all variants. Refer to 1. Configuration Summary.
9.3.1 Features
• Program flow tracing for the Cortex-M0+ processor
• MTB SRAM can be used for both trace and general purpose storage by the processor
• The position and size of the trace buffer in SRAM is configurable by software
• CoreSight compliant
9.3.2 Overview
When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over the execution
trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+. This information is stored
as trace packets in the SRAM by the MTB. An off-chip debugger can extract the trace information using the Debug
Access Port to read the trace information from the SRAM. The debugger can then reconstruct the program flow from
this information.
The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the SRAM. The
MTB ensures that trace write accesses have priority over processor accesses.
The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the processor
PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during
exception entry. Refer to the CoreSight MTB-M0+ Technical Reference Manual for details on the MTB execution trace
packet format.
Tracing is enabled when the MASTER.EN bit in the Host Trace Control Register is 1. There are various ways to set
the bit to 1 to start tracing, or to 0 to stop tracing. Refer to the CoreSight Cortex-M0+ Technical Reference Manual
for details on the Trace start and stop and for a detailed description of the MTB’s MASTER register. The MTB can
be programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop
tracing by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer
overflows, then the buffer wraps around overwriting previous trace packets.
The base address of the MTB registers is 0x41008000, and this address is also written in the CoreSight ROM table.
The offset of each register from the base address is fixed and as defined by the CoreSight MTB-M0+ Technical
Reference Manual. The MTB has 4 programmable registers to control the behavior of the trace features:
• POSITION: Contains the trace write pointer and the wrap bit
• MASTER: Contains the main trace enable bit and other trace control fields
• FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits
• BASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable
auto discovery of the MTB SRAM location, by a debug agent.
Refer to the “CoreSight MTB-M0+ Technical Reference Manual” for a detailed description of these registers.
9.4.1 Features
High-Speed Bus Matrix has the following features:
• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different hosts to different clients
• 32-bit data bus
• Operation at a 1-to-1 clock frequency with the bus hosts
9.4.2 Configuration
Figure 9-1. Host/Client Relation High-Speed Bus Matrix, PIC32CM MC00
SRAM
AHB-APB Bridge C
AHB-APB Bridge A
AHB-APB Bridge B
Internal Flash
DMAC Fetch
DMAC Data
DMAC WB
Reserved
Reserved
DIVAS
CM0+
MTB
DSU
HOST ID
0 4 3 5 7 6 2 1 CLIENT ID
9 8 7 5-6 3-4 2 1 0 FlexRAM PORT ID
CM0+ 0
Multi-Client
HOSTS
DSU
DSU 1
DMAC
DSUData 2
MTB
FlexRAM-access
Priviledged
DMAC WB
HOSTS
DMAC Fetch
...........continued
Bus Matrix Clients
AHB-APB Bridge A
AHB-APB Bridge B
AHB-APB Bridge C
SRAM - DMAC Data Access
DIVAS - Divide Accelerator
Note: The SMBIST has a direct access to SRAM, by passing the SRAM ports.
If a host is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be minimum latency of one cycle for the
SRAM access.
The priority order for concurrent accesses are decided by two factors. First, the QoS level for the host and second, a
static priority given by the SRAM Port ID as defined in SRAM Port Connections. The lowest port ID has the highest
static priority.
The MTB has fixed QoS level HIGH (0x3) and the DSU has fixed QoS level LOW (0x1).
The CPU QoS level can be written/read at address 0x4100A110, bits [1:0]. Its reset value is 0x0.
Refer to the different host registers for configuring their QoS (MRCFG, QoS, and QOSCTRL for DMAC).
PM 0x40000400 0 - Y - 1 N - - - N/A
MCLK 0x40000800 0 - Y - 2 N - - - Y
WDT 0x40002000 1 - Y - 8 N - - - Y
3: CMP0/ALARM0
4: CMP1
RTC 0x40002400 2 - Y - 9 N - - Y
5: OVF
6:13: PER0-7
3: Measure
FREQM 0x40002C00 4 - Y 11 N - - - N/A
4: Reference
NVMCTRL 0x41004000 6 Y Y - 2 N - - - Y
42: START
MTB 0x41008000 - - N/A - 4 N - - N/A
43: STOP
19: CORE 2: RX
SERCOM0 0x42000400 9 - N 1 N - - Y
18: SLOW 3: TX
20: CORE 4: RX
SERCOM1 0x42000800 10 - N 2 N - - Y
18: SLOW 5: TX
21: CORE 6: RX
SERCOM2 0x42000C00 11 - N 3 N - - Y
18: SLOW 7: TX
...........continued
AHB APB Generic
PAC Events DMA
CLK CLK CLK
Sleep
Peripheral Base Address IRQ
Walking
Enabled Enabled Prot at
Index Index User Generator Index
at reset at reset reset
22: CORE 8: RX
SERCOM3 0x42001000 12 - N 4 N - - Y
18: SLOW 9: TX
Reserved 0x42001400 - - - - - - - - - -
35: OVF
9-10: EV0-1 10: OVF
36: TRG
TCC0 0x42002400 13 - N 23 9 N Y
37: CNT
11-14: MC0-3 11-14: MC0-3
38-41: MC0-3
42: OVF
15-16: EV0-1 15: OVF
43: TRG
TCC1 0x42002800 14 - N 23 10 N Y
44: CNT
17-18: MC0-1 16-17: MC0-1
45-46: MC0-1
47: OVF
19-20: EV0-1 18: OVF
48: TRG
TCC2 0x42002C00 15 - N 24 11 N Y
49: CNT
21-22: MC0-1 19-20: MC0-1
50-51: MC0-1
73-74: COMP0-1
AC 0x42005000 23 - N 33 20 N 34-35: SOC0-1 - Y
75: WIN0
Reserved 0x42005800 - - - - - - - - - -
Reserved 0x42006000 - - - - - - - - - -
...........continued
AHB APB Generic
PAC Events DMA
CLK CLK CLK
Sleep
Peripheral Base Address IRQ
Walking
Enabled Enabled Prot at
Index Index User Generator Index
at reset at reset reset
83: OVF
44: EVU0
84: ERR
85: DIR
PDEC 0x42006800 26 - N 34 26 N 45: EVU1 - Y
86: VLC
87: MC0
46: EVU2
88: MC1
Registers can be 8, 16, or 32 bits wide. Atomic 8-bit, 16-bit, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
PAC Write-Protection Register Property:
Some registers are optionally write-protected by the Peripheral Access Controller (PAC).
PAC write protection is denoted by the "PAC Write-Protection" property in each individual register description. For
more details, refer to the PAC - Peripheral Access Controller.
Read-Synchronized, Write-Synchronized Register Property:
Some registers or bit fields within a register require synchronization when read and/or written.
Synchronization is denoted by the "Read-Synchronized" ("Read-Synchronized Bits”) and "Write-Synchronized"
("Write-Synchronized Bits”) property in each individual register description. For more details, refer to Register
Synchronization.
Enable-Protected Register Property:
Some registers or bit fields within a register can only be written when the peripheral is disabled.
Such protection is denoted by the "Enable-Protected" ("Enable-Protected Bits") property in each individual register
description.
32kHz
Peripheral Channel y Peripheral z
OSCULP32K 1kHz
RTC
CLK_RTC_OSC
CLK_WDT_OSC
WDT
CLK_ULP32K
EIC
The clock system on the PIC32CM MC00 consists of these key features:
• Clock sources, controlled by OSCCTRL and OSC32KCTRL
– A Clock source is the base clock signal used in the system. Example clock sources are the internal 48 MHz
oscillator (OSC48M), External crystal oscillator (XOSC) and the Digital phase-locked loop (FDPLL96M).
• Generic Clock Controller (GCLK) which controls the clock distribution system, made up of the following:
– Generic Clock generators: A programmable prescaler, that can use any of the system clock sources as
its source clock. The Generic Clock Generator 0, also called GCLK_MAIN, is the clock feeding the Power
Manager used to generate synchronous clocks.
– Generic Clocks: Typically the clock input of a peripheral on the system. The generic clocks, through the
Generic Clock Multiplexer, can use any of the Generic Clock generators as its clock source. Multiple
instances of a peripheral will typically have a separate generic clock for each instance.
• Main Clock controller (MCLK)
– The MCLK controls synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB) as
well as the synchronous (to the CPU) user interfaces of the peripherals. It contains clock masks that can
turn on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks.
The figure below shows an example where SERCOM0 is clocked by the OSC48M. The OSC48M is enabled,
the Generic Clock Generator 1 uses the OSC48M as its clock source, and the generic clock 19, also called
GCLK_SERCOM0_CORE, that is connected to SERCOM0 uses generator 1 as its source. The SERCOM0 interface,
clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the MCLK.
Syncronous Clock
Controller
CLK_SERCOM0_APB
GCLK
OSCCTRL
Generic Clock Peripheral GCLK_SERCOM0_CORE
OSC48M SERCOM 0
Generator 1 Channel 19
11.3.1 Overview
All peripherals are composed of one digital bus interface, which is connected to the APB or AHB bus and
clocked using a corresponding synchronous clock, and one core clock, which is clocked using a generic clock.
Access between these clock domains must be synchronized. As this mechanism is implemented in hardware the
synchronization process takes place even if the different clocks domains are clocked from the same source and on
the same frequency. All registers in the bus interface are accessible without synchronization. All core registers in the
generic clock domain must be synchronized when written. Some core registers must be synchronized when read.
Registers that need synchronization has this denoted in each individual register description.
Offset Register
0x00 REGA
0x01 REGB
0x02
REGC
0x03
Since synchronization is per register, users can write REGA (8-bit access) then immediately write REGB (8-bit
access) without error.
Users can write REGC (16-bit access) without affecting REGA or REGB. But if user writes REGC in two consecutive
8-bit accesses, second write will be discarded and generate an error.
When users makes a 32-bit access to offset 0x00, all registers are written but REGA, REGB, REGC can be updated
at a different time because of independent write synchronization
Where:
PGCLK is the period of the generic clock and PAPB is the period of the peripheral bus clock. A normal peripheral bus
register access duration is 2 ⋅ PAPB.
ONDEMAND
All the clock sources in the system can be run in an on-demand mode, where the clock source is in a stopped state
when no peripherals are requesting the clock source. Clock requests propagate from the peripheral, through the
GCLK, to the clock source. If one or more peripheral is using a clock source, the clock source will be started/kept
running. As soon as the clock source is no longer needed and no peripheral have an active request the clock source
will be stopped until requested again. For the clock request to reach the clock source, the peripheral, the generic
clock and the clock from the Generic Clock Generator in-between must be enabled. The time taken from a clock
request being asserted to the clock source being ready is dependent on the clock source startup time, clock source
frequency as well as the divider used in the Generic Clock Generator. The total startup time from a clock request to
the clock is available for the peripheral is given below:
Delay_start_max = Clock source startup time + 2 * clock source periods + 2 * divided clock
source periods
Delay_start_min = Clock source startup time + 1 * clock source period + 1 * divided clock
source periodDelay_start_min = Clock source startup time + 1 * clock source period + 1 *
divided clock source period
The delay for shutting down the clock source when there is no longer an active request is given below:
The On-Demand principle can be disabled individually for each clock source by clearing the ONDEMAND bit located
in each clock source controller. The clock is always running whatever is the clock request. This has the effect to
remove the clock source startup time at the cost of the power consumption.
In standby mode, the clock request mechanism is still working if the modules are configured to run in Standby mode
(RUNSTDBY bit).
12.1 Overview
Depending on the application, peripherals may require specific clock frequencies to operate correctly. The Generic
Clock controller (GCLK) features 9 Generic Clock Generators 0..8 that can provide a wide range of clock frequencies.
Generators can be set to use different external and internal oscillators as source. The clock of each Generator can
be divided. The outputs from the Generators are used as sources for the Peripheral Channels, which provide the
Generic Clocks (GCLK_PERIPH) to the peripheral modules, as shown in the 12.3 Block Diagram. The number of
peripheral clocks depends on how many peripherals the device has.
Note: The Generic Clock Generator 0 is always the direct source of the GCLK_MAIN signal.
12.2 Features
• Provides a device-defined, configurable number of Peripheral Channel clocks
• Wide frequency range:
– Various clock sources
– Embedded dividers
FDPLL96M
Peripheral Channel
OSC48M
GCLK_PERIPH
OSC32K
GCLK_IO
GCLK_MAIN
MCLK
GCLK_MAIN
Generic Clock Generator 0
GCLK_IO[0]
Clock Sources Clock GCLK_GEN[0] (I/O output)
GCLK_IO[0] Divider &
(I/O input) Masker
Clock GCLK_PERIPH[m]
Generic Clock Generator 8
Gate
Clock GCLK_GEN[8]
Divider & x from 2 to 7
Masker m from 0 to 34
Notes:
1. One signal can be mapped on several pins.
2. Each GCLK_IO[x] signal is connected to the related Generic Clock Generator x, for x in [7:0].
3. There is no GCLK_IO8 input or output for the Generic Clock Generator 8.
GCLK 0x40001C00 - - Y - 7 N - - - -
A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the Generator.
A generator output is used by one or more Peripheral Channels to provide a peripheral generic clock signal
(GCLK_PERIPH) to the peripherals.
12.6.2.1 Initialization
Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock must be
configured as outlined by the following steps:
1. The Generator must be enabled (GENCTRLn.GENEN=1) and the division factor must be set
(GENTRLn.DIVSEL and GENCTRLn.DIV) by performing a single 32-bit write to the Generator Control register
(GENCTRLn).
2. The Generic Clock for a peripheral must be configured by writing to the respective Peripheral Channel Control
register (PCHCTRLm). The Generator used as the source for the Peripheral Clock must be written to the
GEN bit field in the Peripheral Channel Control register (PCHCTRLm.GEN). Ensure the Peripheral Channel is
enabled (PCHCTRLm.CHEN=1) before configuring the associated peripheral.
Note: Each Generator n is configured by one dedicated register GENCTRLn. Each Peripheral Channel m is
configured by one dedicated register PCHCTRLm. Refer to the Table 12-9 for the mapping of a peripheral to index m.
Clock Sources
DIVIDER
GCLK_IO GENCTRL.GENEN
(Except for Generator 8)
GENCTRL.DIVSEL
GENCTRL.SRC
GENCTRL.DIV
GCLKGEN[0]
GCLKGEN[1]
GCLKGEN[2]
Clock
Gate GCLK_PERIPHm
GCLKGEN[8] PCHCTRLm.CHEN
PCHCTRLm.GEN
yes - - active
no 1 1 active
no 1 0 OFF
no 0 1 OFF
no 0 0 OFF
12.6.2.13 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers must be
synchronized when written or read.
An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN). When
changing this bit, the bit value must be read-back to ensure the synchronization is complete and to assert glitch free
internal operation. Note that changing the bit value under ongoing synchronization will not generate an error.
Synchronization is denoted by the "Read-Synchronized" and "Write-Synchronized" property in each individual register
description.
For more details, refer to Register Synchronization.
...........continued
12.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized Bits
Bit 7 6 5 4 3 2 1 0
SWRST
Access R/W
Reset 0
Name: SYNCBUSY
Offset: 0x04
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
GENCTRL8 GENCTRL7 GENCTRL6
Access R R R
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
GENCTRL5 GENCTRL4 GENCTRL3 GENCTRL2 GENCTRL1 GENCTRL0 SWRST
Access R R R R R R R
Reset 0 0 0 0 0 0 0
Name: GENCTRLn
Offset: 0x20 + n*0x04 [n=0..8]
Reset: 0x00000106 for GENCTRL0, 0x00000000 for others
Property: -
GENCTRLn controls the settings of Generic Generator n (n=0..8). The reset value is 0x00000106 for Generator n=0,
else 0x00000000
Note: GENCTRLn is a write-synchronized register: SYNCBUSY.GENCTRLn must be checked to ensure the
GENCTRLn synchronization is complete.
Bit 31 30 29 28 27 26 25 24
DIV[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIV[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RUNSTDBY DIVSEL OE OOV IDC GENEN
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 x
Bit 7 6 5 4 3 2 1 0
SRC[4:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 x
Value Description
0 The Generator clock frequency equals the clock source frequency divided by GENCTRLn.DIV.
1 The Generator clock frequency equals the clock source frequency divided by 2^(GENCTRLn.DIV+1).
A Power Reset will reset all GENCTRLn registers. the Reset values of the GENCTRLn registers are shown in table
below.
Table 12-5. GENCTRLn Reset Value after a Power Reset
A User Reset will reset the associated GENCTRL register unless the Generator is the source of a locked Peripheral
Channel (PCHCTRLm.WRTLOCK=1). The reset values of the GENCTRL register are as shown in the table below.
Table 12-6. GENCTRLn Reset Value after a User Reset
Name: PCHCTRLm
Offset: 0x80 + m*0x04 [m=0..34]
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
WRTLOCK CHEN GEN[3:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Value Description
0x0 Generic Clock Generator 0
0x1 Generic Clock Generator 1
0x2 Generic Clock Generator 2
0x3 Generic Clock Generator 3
0x4 Generic Clock Generator 4
0x5 Generic Clock Generator 5
0x6 Generic Clock Generator 6
...........continued
Value Description
0x7 Generic Clock Generator 7
0x8 Generic Clock Generator 8
0x9 - 0xF Reserved
13.1 Overview
The Main Clock (MCLK) controls the synchronous clock generation of the device.
Using a clock provided by the Generic Clock Module (GCLK_MAIN), the Main Clock Controller provides synchronous
system clocks to the CPU and the modules connected to the AHBx and the APBx buses. The synchronous system
clocks are divided into a number of clock domains. Each clock domain can run at different frequencies, enabling
the user to save power by running peripherals at a relatively low clock frequency, while maintaining high CPU
performance or vice versa. In addition, the clock can be masked for individual modules, enabling the user to minimize
power consumption.
13.2 Features
• Generates CPU, AHB, and APB system clocks
– Clock source and division factor from GCLK
– Clock prescaler with 1x to 128x division
• Safe run-time clock switching from GCLK
• Module-level clock gating through maskable peripheral clocks
CLK_APBx
CLK_AHBx
GCLK_MAIN MAIN PERIPHERALS
GCLK
CLOCK CONTROLLER
CLK_CPU
CPU
MCLK 0x40000800 0 - Y - 2 N - - - Y
MASK PERIPHERALS
gate
Clock clk_ahb_ipn
Clock CLK_AHB_HS gate
Clock
Clock clk_ahb_ip1
gate gate clk_ahb_ip0
CPUDIV
new clock setting is effective. The clock settings (CLKCFG) must not be re-written while INTFLAG.CKRDY reads '0'.
The system may become unstable or hang, and a violation is reported to the PAC module.
13.5.3 Interrupts
The peripheral has the following interrupt sources:
• Clock Ready (CKRDY): indicates that CPU clocks are ready. This interrupt is a synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(13.6.3 INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be enabled individually by
writing a '1' to the corresponding enabling bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing
a '1' to the corresponding clearing bit in the Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset.
An interrupt flag is cleared by writing a '1' to the corresponding bit in the 13.6.3 INTFLAG register. Each peripheral
can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt
sources. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the
13.6.3 INTFLAG register to determine which interrupt condition is present.
0x00 Reserved
0x01 INTENCLR 7:0 CKRDY
0x02 INTENSET 7:0 CKRDY
0x03 INTFLAG 7:0 CKRDY
0x04 CPUDIV 7:0 CPUDIV[7:0]
0x05
... Reserved
0x0F
7:0 DMAC HSRAM NVMCTRL HMATRIXHS DSU APBC APBB APBA
15:8 DIVAS PAC
0x10 AHBMASK
23:16
31:24
OSC32KCTR
7:0 GCLK SUPC OSCCTRL RSTC MCLK PM PAC
L
0x14 APBAMASK 15:8 TSENS FREQM EIC RTC WDT
23:16
31:24
7:0 HMATRIXHS NVMCTRL DSU PORT
15:8
0x18 APBBMASK
23:16
31:24
7:0 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS
15:8 TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0
0x1C APBCMASK
23:16 CCL DAC AC SDADC ADC1 ADC0 TC4
31:24 PDEC
Name: INTENCLR
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 7 6 5 4 3 2 1 0
CKRDY
Access R/W
Reset 0
Name: INTENSET
Offset: 0x02
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 7 6 5 4 3 2 1 0
CKRDY
Access R/W
Reset 0
Name: INTFLAG
Offset: 0x03
Reset: 0x01
Property: –
Bit 7 6 5 4 3 2 1 0
CKRDY
Access R/W
Reset 1
Name: CPUDIV
Offset: 0x04
Reset: 0x01
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
CPUDIV[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 1
Name: AHBMASK
Offset: 0x10
Reset: 0x0000005FF
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
DIVAS PAC
Access R/W R/W
Reset 1 1
Bit 7 6 5 4 3 2 1 0
DMAC HSRAM NVMCTRL HMATRIXHS DSU APBC APBB APBA
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Value Description
1 The AHB clock for the HMATRIXHS is enabled.
Name: APBAMASK
Offset: 0x14
Reset: 0x00000FFF
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
TSENS FREQM EIC RTC WDT
Access R/W R/W R/W R/W R/W
Reset 0 1 1 1 1
Bit 7 6 5 4 3 2 1 0
GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Value Description
1 The APBA clock for the GCLK is enabled.
Name: APBBMASK
Offset: 0x18
Reset: 0x00000007
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
HMATRIXHS NVMCTRL DSU PORT
Access R/W R/W R/W R/W
Reset 0 1 1 1
Name: APBCMASK
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
PDEC
Access R/W
Reset 0
Bit 23 22 21 20 19 18 17 16
CCL DAC AC SDADC ADC1 ADC0 TC4
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Value Description
1 The APBC clock for the ADC1 is enabled.
Value Description
1 The APBC clock for the SERCOM2 is enabled.
14.1 Overview
The Oscillators Controller (OSCCTRL) provides a user interface to the XOSC, OSC48M and FDPLL96M modules,
refer to the OSC32KCTRL chapter for the user interface to the 32.768 kHz oscillators.
Through the interface registers, it is possible to enable, disable, calibrate, and monitor the OSCCTRL oscillators.
All oscillators statuses are collected in the Status register (STATUS). They can additionally trigger interrupts upon
status changes through the INTENSET, INTENCLR, and INTFLAG registers.
14.2 Features
• 0.4-32 MHz Crystal Oscillator (XOSC)
– Tunable gain control
– Programmable start-up time
– Crystal or external input clock on XIN I/O
– Clock failure detection with safe clock switch
– Clock failure event output
• 48 MHz Internal Oscillator (OSC48M)
– Fast start-up
– Programmable start-up time
– 4-bit linear divider available
• Fractional Digital Phase Locked Loop (FDPLL96M)
– 48 MHz to 96 MHz output frequency
– 32 kHz to 2 MHz reference clock
– A selection of sources for the reference clock
– Adjustable proportional integral controller
– Fractional part used to achieve 1/16th of reference clock step
OSC48M CLK_OSC48M
OSCILLATORS
CONTROL
FDPLL96M CLK_DPLL
STATUS
register
INTERRUPTS Interrupts
GENERATOR
0: FDPLL96M clk
OSCCTRL 0x40001000 0 - Y source 4 N - - - Y
1: FDPLL96M 32kHz
The XOSC will behave differently in different sleep modes, based on the settings of XOSCCTRL.RUNSTDBY,
XOSCCTRL.ONDEMAND, and XOSCCTRL.ENABLE. If XOSCCTRL.ENABLE = 0, the XOSC will be always
stopped. For XOSCCTRL.ENABLE = 1, this table is valid:
Table 14-1. XOSC Sleep Behavior
After a hard reset, or when waking up from a Sleep mode where the XOSC was disabled, the XOSC will need
time to stabilize on the correct frequency, depending on the external crystal specification. This start-up time can be
configured by changing the Oscillator Start-Up Time bit group (XOSCCTRL.STARTUP) in the External Multipurpose
Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no unstable
clock propagates to the digital logic.
The External Multipurpose Crystal Oscillator Ready bit in the Status register (STATUS.XOSCRDY) is set once the
external clock or crystal oscillator is stable and ready to be used as a clock source. An interrupt is generated on a
zero-to-one transition on STATUS.XOSCRDY if the External Multipurpose Crystal Oscillator Ready bit in the Interrupt
Enable Set register (INTENSET.XOSCRDY) is set.
After a clock failure is issued the monitoring of the XOSC clock continues, and the Clock Failure Detector
status bit in the Status register (STATUS.XOSCFAIL) reflects the current XOSC activity. If the CFD is disabled
(XOSCCTRL.CFDEN=0) the XOSC must be disabled (XOSCCTRL.ENABLE=0) before re-enabling the CFD. Not
following this guideline can lead to a false clock failure detection.
When the XOSC Clock Failure Detector is enabled (XOSCCTRL.CFDEN=1) and a failure is detected
(STATUS.XOSCFAIL=1), the XOSC ready bit is not cleared (STATUS.XOSCRDY=1). When checking the XOSC
ready status, the state of the XOSC clock failure status (STATUS.XOSCFAIL) must be checked before the XOSC
ready status bit and dismiss the XOSC ready status if the XOSC clock failure status is set (STATUS.XOSCFAIL=1).
Clock Switch
When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an active
clock during the XOSC clock failure. The safe clock source is the OSC48M oscillator clock. The safe clock source
frequency can be scaled down by a configurable prescaler to ensure that the safe clock frequency does not exceed
the operating conditions selected by the application. When the XOSC clock is switched to the safe clock, the Clock
Switch bit in the Status register (STATUS.XOSCCKSW) is set.
When the CFD has switched to the safe clock, the XOSC is not disabled. If desired, the application must take the
necessary actions to disable the oscillator. The application must also take the necessary actions to configure the
system clocks to continue normal operations.
In case the application can recover the XOSC, the application can switch back to the XOSC clock by writing a '1' to
Switch Back Enable bit in the Clock Failure Control register (XOSCCTRL.SWBEN). Once the XOSC clock is switched
back, the Switch Back bit (XOSCCTRL.SWBEN) is cleared by hardware.
Prescaler
The CFD has an internal configurable prescaler to generate the safe clock from the OSC48M oscillator. The prescaler
size allows to scale down the OSC48M oscillator so the safe clock frequency is not higher than the XOSC clock
frequency monitored by the CFD. The division factor is 2^P, with P being the value of the CFD Prescaler bits in the
CFD Prescaler Register (CFDPRESC.CFDPRESC).
Example 14-1.
For an external crystal oscillator at 0.4 MHz and the OSC48M frequency at 16 MHz, the
CFDPRESC.CFDPRESC value must be set scale down by more than factor 16/0.4 = 80, for
example, to 128, for a safe clock of adequate frequency.
Event
If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock failure will be
output on the Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on
the Event Output.
Sleep Mode
The CFD is halted depending on configuration of the XOSC and the peripheral clock request. For further details, refer
to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device from sleep modes.
After a hard reset, or when waking up from a Sleep mode where the OSC48M was disabled, the OSC48M will need
time to stabilize on the correct frequency (refer to 43. Electrical Characteristics 85℃). This start-up time can be
configured by changing the Oscillator Start-Up Delay bit group (OSC48MSTUP.STARTUP) in the OSC48M Startup
register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to
the digital logic. The OSC48M Ready bit in the Status register (STATUS.OSC48MRDY) is set when the oscillator
is stable and ready to be used as a clock source. An interrupt is generated on a zero-to-one transition on
STATUS.OSC48MRDY if the OSC48M Ready bit in the Interrupt Enable Set register (INTENSET.OSC48MRDY)
is set.
Faster start-up times are achievable by selecting shorter delays. However, the oscillator frequency may not stabilize
within tolerances when short delays are used. If a fast start-up time is desired at the expense of initial accuracy, the
division factor should be set to two or higher (OSC48MDIV.DIV > 0).
The OSC48M is used as a clock source for the generic clock generators. The OSC48M supports the change of
frequency while running with a write to the OSC48M Divider register (OSC48MDIV.DIV). The OSC48M must be
running and the OSC48M on demand bit (OSC48MCTRL.ONDEMAND) must be cleared when the OSC48MDIV.DIV
is changed, to ensure synchronization is complete. The OSC48M must remain enabled until the sync busy flag
returns to '0' (OSC48MSYNCBUSY.OSC48MDIV = 0).
CK
GCLK RATIO
DPLLCTRLB.REFCLK DPLLRATIO
When the controller is disabled, the output clock is low. If the Loop Divider Ratio Fractional part bit field in the DPLL
Ratio register (DPLLRATIO.LDRFRAC) is zero, the DPLL works in integer mode. Otherwise, the fractional mode is
activated. The fractional part has a negative impact on the jitter of the DPLL.
For example (integer mode only): assuming FCKR = 32 kHz and FCK = 48 MHz, the multiplication
ratio is 1500. It means that LDR shall be set to 1499.
For example (fractional mode): assuming FCKR = 32 kHz and FCK = 48.006 MHz, the multiplication
ratio is 1500.1875 (1500 + 3/16). Thus LDR is set to 1499 and LDRFRAC to 3.
ENABLE
CK
SYNCBUSY.ENABLE
The frequency of the DPLL output clock CK is stable when the module is enabled and when the Lock bit in the DPLL
Status register is set (DPLLSTATUS.LOCK).
When the Lock Time bit field in the DPLL Control B register (DPLLCTRLB.LTIME) is non-zero, a user defined lock
time is used to validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME = 0, the lock
signal is linked with the status bit of the DPLL, and the lock time varies depending on the filter selection and the final
target frequency.
When the Wake Up Fast bit (DPLLCTRLB.WUF) is set, the wake up fast mode is activated. In this mode the clock
gating cell is enabled at the end of the startup time. At this time the final frequency is not stable, as it is still during the
acquisition period, but it allows to save several milliseconds. After first acquisition, the clock gater (CG) generating
the output clock CLK_DPLL is gated by the LOCK signal when the Lock Bypass bit (DPLLCTRLB.LBYPASS) is
cleared or is not gated and delivers the output clock CLK_DPLL immediately when DPLLCTRLB.LBYPASS is set.
Table 14-3. CLK_DPLL Behavior from Startup to First Edge Detection
...........continued
WUF LTIME CLK_DPLL Behavior
0 Not Equal To Zero Lock Timer Timeout mode: First Edge when the timer down-counts to 0.
1 X Wake Up Fast Mode: First Edge when CK is active (startup time)
Figure 14-4. CK and CLK_DPLL Output from DPLL Off Mode to Running Mode
CKR
ENABLE
CK
CLK_DPLL
LOCK
CKR
PRESC 0 1
CK
CKDIV2
CLK_DPLL
SYNCBUSY.PRESC
DPLL_LOCK
CKR
LDR
mult0 mult1
LDRFRAC
CK
CLK_DPLL
LOCK
LOCKL
14.6.6 Interrupts
The OSCCTRL has the following interrupt sources:
• XOSCRDY - Multipurpose Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSCRDY bit is
detected
• XOSCFAIL - Clock Failure. A 0-to-1 transition on the STATUS.XOSCFAIL bit is detected
• OSC48MRDY - 48 MHz Internal Oscillator Ready: A 0-to-1 transition on the STATUS.OSC48MRDY bit is
detected
• DPLL-related:
– DPLLLOCKR - DPLL Lock Rise: A 0-to-1 transition of the STATUS.DPLLLOCKR bit is detected
– DPLLLOCKF - DPLL Lock Fall: A 0-to-1 transition of the STATUS.DPLLLOCKF bit is detected
– DPLLLTTO - DPLL Lock Timer Time-out: A 0-to-1 transition of the STATUS.DPLLLTTO bit is detected
– DPLLLDRTO - DPLL Loop Divider Ratio Update Complete. A 0-to-1 transition of the STATUS.DPLLLDRTO
bit is detected
All these interrupts are synchronous wake-up sources.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
As both INTENSET and INTENCLR always reflect the same value, the status of interrupt enablement can be read
from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the OSCCTRL is reset.
Refer to the INTFLAG register for details on how to clear interrupt flags.
The OSCCTRL has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG
register to determine which interrupt condition is present. Refer to the INTFLAG register for details.
Note: The interrupts must be globally enabled for interrupt requests to be generated.
14.6.7 Events
The CFD can generate the following output event:
• Clock Failure (XOSCFAIL): Generated when the Clock Failure status bit is set in the Status register
(STATUS.XOSCFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.XOSCCKSW) in the
Status register is set.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD output event.
Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the
event system.
14.6.8 Synchronization
OSC48M
Due to the multiple clock domains, values in the OSC48M control registers need to be synchronized to other clock
domains.
When executing an operation that requires synchronization, the relevant synchronization bit in the Synchronization
Busy register (OSC48MSYNCBUSY) will be set immediately, and cleared when synchronization is complete.
The following registers need synchronization when written:
• OSC48M Divider register (OSC48MDIV)
FDPLL96M
Due to the multiple clock domains, some registers in the FDPLL96M must be synchronized when accessed.
When executing an operation that requires synchronization, the relevant synchronization bit in the Synchronization
Busy register (DPLLSYNCBUSY) will be set immediately, and cleared when synchronization is complete.
The following bits need synchronization when written:
• Enable bit in control register A (DPLLCTRLA.ENABLE)
• DPLL Ratio register (DPLLRATIO)
• DPLL Prescaler register (DPLLPRESC)
Name: INTENCLR
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OSC48MRDY XOSCFAIL XOSCRDY
Access R/W R/W R/W
Reset 0 0 0
Name: INTENSET
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OSC48MRDY XOSCFAIL XOSCRDY
Access R/W R/W R/W
Reset 0 0 0
Name: INTFLAG
Offset: 0x08
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OSC48MRDY XOSCFAIL XOSCRDY
Access R/W R/W R/W
Reset 0 0 0
14.7.4 Status
Name: STATUS
Offset: 0x0C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR
Access R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OSC48MRDY XOSCCKSW XOSCFAIL XOSCRDY
Access R R R R
Reset 0 0 0 0
Value Description
1 XOSC is switched and provides the safe clock.
Name: XOSCCTRL
Offset: 0x10
Reset: 0x0080
Property: PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
STARTUP[3:0] AMPGC GAIN[2:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY SWBEN CFDEN XTALEN ENABLE
Access R/W R/W R/W R/W R/W R/W
Reset 1 0 0 0 0 0
STARTUP[3:0] Number of OSCULP32K Clock Number of XOSC Clock Approximate Equivalent Time
Cycles Cycles [µs]
0x0 1 3 31
0x1 2 3 61
0x2 4 3 122
0x3 8 3 244
0x4 16 3 488
0x5 32 3 977
0x6 64 3 1953
0x7 128 3 3906
0x8 256 3 7813
0x9 512 3 15625
0xA 1024 3 31250
0xB 2048 3 62500
0xC 4096 3 125000
0xD 8192 3 250000
0xE 16384 3 500000
0xF 32768 3 1000000
Notes:
1. Actual startup time is 1 OSCULP32K cycle + 3 XOSC cycles.
2. The given time neglects the three XOSC cycles before OSCULP32K cycle.
Name: CFDPRESC
Offset: 0x12
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
CFDPRESC[2:0]
Access R/W R/W R/W
Reset 0 0 0
Name: EVCTRL
Offset: 0x13
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
CFDEO
Access R/W
Reset 0
Name: OSC48MCTRL
Offset: 0x14
Reset: 0x82
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY ENABLE
Access R/W R/W R/W
Reset 1 0 1
Name: OSC48MDIV
Offset: 0x15
Reset: 0x0B
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
DIV[3:0]
Access R/W R/W R/W R/W
Reset 1 0 1 1
Name: OSC48MSTUP
Offset: 0x16
Reset: 0x07
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
STARTUP[2:0]
Access R/W R/W R/W
Reset 1 1 1
Name: OSC48MSYNCBUSY
Offset: 0x18
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
OSC48MDIV
Access R
Reset 0
Name: DPLLCTRLA
Offset: 0x1C
Reset: 0x80
Property: PAC Write-Protection, Write-Synchronized Bits
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY ENABLE
Access R/W R/W R/W
Reset 1 0 0
Name: DPLLRATIO
Offset: 0x20
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
LDRFRAC[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
LDR[11:8]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
LDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DPLLCTRLB
Offset: 0x24
Reset: 0x00
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
DIV[10:8]
Access R/W R/W R/W
Reset 0 0 0
Bit 23 22 21 20 19 18 17 16
DIV[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
LBYPASS LTIME[2:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
REFCLK[1:0] WUF LPEN FILTER[1:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: DPLLPRESC
Offset: 0x28
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
PRESC[1:0]
Access R/W R/W
Reset 0 0
Name: DPLLSYNCBUSY
Offset: 0x2C
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
DPLLPRESC DPLLRATIO ENABLE
Access R R R
Reset 0 0 0
Name: DPLLSTATUS
Offset: 0x30
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
CLKRDY LOCK
Access R R
Reset 0 0
Name: CAL48M
Offset: 0x38
Reset: Calibrated value for VDD range 3.6 V to 5.5 V
Property: PAC Write-Protection
This register (bits 0 to 21) must be updated with the CAL48M bit field from the NVM Software Calibration Area. Refer
to 8.4 NVM Software Calibration Area Mapping.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
TCAL[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset x x x x x x
Bit 15 14 13 12 11 10 9 8
FRANGE[1:0]
Access R/W R/W
Reset x x
Bit 7 6 5 4 3 2 1 0
FCAL[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset x x x x x x
15.1 Overview
The 32.768 kHz Oscillators Controller (OSC32KCTRL) provides a user interface to the 32.768 kHz oscillators:
XOSC32K, OSC32K, and OSCULP32K.
The OSC32KCTRL sub-peripherals can be enabled, disabled, calibrated, and monitored through interface registers.
All sub-peripheral statuses are collected in the Status register (STATUS). They can additionally trigger interrupts upon
status changes through the INTENSET, INTENCLR, and INTFLAG registers.
15.2 Features
• 32.768 kHz Crystal Oscillator (XOSC32K)
– Programmable start-up time
– Crystal or external input clock on XIN32 I/O
– Clock failure detection with safe clock switch
– Clock failure event output
• 32.768 kHz High Accuracy Internal Oscillator (OSC32K)
– Frequency fine tuning
– Programmable start-up time
• 32.768 kHz Ultra Low-Power Internal Oscillator (OSCULP32K)
– Ultra low-power, always-on oscillator
– Frequency fine tuning
• 1.024 kHz clock outputs available
OSC32KCTRL
XOUT32 XIN32
XOSC32K CLK_XOSC32K
OSC32K CLK_OSC32K
STATUS
register
INTERRUPTS
GENERATOR Interrupts
As a crystal oscillator usually requires a very long start-up time, the 32.768 kHz External Crystal Oscillator will keep
running across resets when XOSC32K.ONDEMAND = 0, except for Power-on Reset (POR). After a reset or when
waking up from a sleep mode where the XOSC32K was disabled, the XOSC32K will need time to stabilize on the
correct frequency, depending on the external crystal specification. This start-up time can be configured by changing
the Oscillator Start-Up Time bit group (XOSC32K.STARTUP) in the 32.768 kHz External Crystal Oscillator Control
register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the
digital logic.
Once the external clock or crystal oscillator is stable and ready to be used as a clock source, the XOSC32K
Ready bit in the Status register is set (STATUS.XOSC32KRDY = 1). The transition of STATUS.XOSC32KRDY
from '0' to '1' generates an interrupt if the XOSC32K Ready bit in the Interrupt Enable Set register is set
(INTENSET.XOSC32KRDY = 1).
The XOSC32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter
(RTC). Before enabling the GCLK or the RTC module, the corresponding oscillator output must be enabled
(XOSC32K.EN32K or XOSC32K.EN1K) in order to ensure proper operation. In the same way, the GCLK or RTC
modules must be disabled before the clock selection is changed. For details on RTC clock configuration, refer also to
15.6.7 Real-Time Counter Clock Selection.
When the XOSC32K 1024 Hz clock output is used to clock the RTC (RTCCTRL.RTCSEL=4), ensure the XOSC32K
is in the 'Always run' ( as shown above in Table 15-1 XOSC32K Sleep Behavior) configuration.
Clock Switch
When a clock failure is detected, the XOSC32K clock is replaced by the safe clock in order to maintain an active
clock during the XOSC32K clock failure. The safe clock source is the OSCULP32K oscillator clock. Both 32.768
kHz and 1.024 kHz outputs of the XOSC32K are replaced by the respective OSCULP32K 32.768 kHz and 1.024
kHz outputs. The safe clock source can be scaled down by a configurable prescaler to ensure that the safe clock
frequency does not exceed the operating conditions selected by the application. When the XOSC32K clock is
switched to the safe clock, the Clock Switch bit in the Status register (STATUS.CLKSW) is set.
When the CFD has switched to the safe clock, the XOSC32K is not disabled. If desired, the application must take
the necessary actions to disable the oscillator. The application must also take the necessary actions to configure the
system clocks to continue normal operations. In the case the application can recover the XOSC32K, the application
can switch back to the XOSC32K clock by writing a '1' to Switch Back Enable bit in the Clock Failure Control register
(CFDCTRL.SWBACK). Once the XOSC32K clock is switched back, the Switch Back bit (CFDCTRL.SWBACK) is
cleared by hardware.
Prescaler
The CFD has an internal configurable prescaler to generate the safe clock from the OSCULP32K oscillator. The
prescaler size allows to scale down the OSCULP32K oscillator so the safe clock frequency is not higher than the
XOSC32K clock frequency monitored by the CFD. The maximum division factor is 2.
The prescaler is applied on both outputs (32.768 kHz and 1.024 kHz) of the safe clock.
Example 15-1.
For an external crystal oscillator at 32.768 kHz and the OSCULP32K frequency is 32.768 kHz, the
XOSC32K.CFDPRESC should be set to 0 for a safe clock of equal frequency.
Event
If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock failure will be
output on the Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on
the Event Output.
Sleep Mode
The CFD is halted depending on configuration of the XOSC32K and the peripheral clock request. For further details,
refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device from sleep modes.
...........continued
CPU Mode OSC32KCTRL.RUNST OSC32KCTRL.ONDEM Sleep Behavior
DBY AND
Standby 1 1 Run if requested by peripheral
Standby 0 - Run if requested by peripheral
The OSC32K requires a start-up time. For this reason, OSC32K will keep running across resets when
OSC32K.ONDEMAND = 0, except for Power-on Reset (POR).
After such a reset, or when waking up from a Sleep mode where the OSC32K was disabled, the OSC32K will need
time to stabilize on the correct frequency.
This startup time can be configured by changing the Oscillator Start-Up Time bit group (OSC32K.STARTUP) in the
OSC32K Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock
propagates to the digital logic.
Once the oscillator is stable and ready to be used as a clock source, the OSC32K Ready bit in the Status register
is set (STATUS.OSC32KRDY=1). The transition of STATUS.OSC32KRDY from '0' to '1' generates an interrupt if the
OSC32K Ready bit in the Interrupt Enable Set register is set (INTENSET.OSC32KRDY = 1).
The OSC32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter (RTC).
Before enabling the GCLK or the RTC module, the corresponding oscillator output must be enabled (OSC32K.EN32K
or OSC32K.EN1K) in order to ensure proper operation. In the same way, the GCLK or RTC modules must be
disabled before the clock selection is changed.
15.6.8 Interrupts
The OSC32KCTRL has the following interrupt sources:
• XOSC32KRDY - 32.768 kHz Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSC32KRDY bit is
detected
• CLKFAIL - Clock Failure Detector: A 0-to-1 transition on the STATUS.CLKFAIL bit is detected
• OSC32KRDY - 32.768 kHz Internal Oscillator Ready: A 0-to-1 transition on the STATUS.OSC32KRDY bit is
detected
All these interrupts are synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be enabled individually by setting
the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by setting the corresponding
bit in the Interrupt Enable Clear register (INTENCLR). As both INTENSET and INTENCLR always reflect the same
value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the OSC32KCTRL is
reset. See the INTFLAG register for details on how to clear interrupt flags.
The OSC32KCTRL has one common interrupt request line for all the interrupt sources. The user must read the
INTFLAG register to determine which interrupt condition is present. Refer to the INTFLAG register for details.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
15.6.9 Events
The CFD can generate the following output event:
• Clock Failure Detector (CLKFAIL): Generated when the Clock Failure Detector status bit is set in the Status
register (STATUS.CLKFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.SWBACK) in
the Status register is set.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD output event.
Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the
event system.
XOSC32KRD
7:0 CLKFAIL OSC32KRDY
Y
0x00 INTENCLR 15:8
23:16
31:24
XOSC32KRD
7:0 CLKFAIL OSC32KRDY
Y
0x04 INTENSET 15:8
23:16
31:24
XOSC32KRD
7:0 CLKFAIL OSC32KRDY
Y
0x08 INTFLAG 15:8
23:16
31:24
XOSC32KRD
7:0 CLKSW CLKFAIL OSC32KRDY
Y
0x0C STATUS 15:8
23:16
31:24
7:0 RTCSEL[2:0]
15:8
0x10 RTCCTRL
23:16
31:24
7:0 ONDEMAND RUNSTDBY EN1K EN32K XTALEN ENABLE
0x14 XOSC32K
15:8 WRTLOCK STARTUP[2:0]
0x16 CFDCTRL 7:0 CFDPRESC SWBACK CFDEN
0x17 EVCTRL 7:0 CFDEO
7:0 ONDEMAND RUNSTDBY EN1K EN32K ENABLE
15:8 WRTLOCK STARTUP[2:0]
0x18 OSC32K
23:16 CALIB[6:0]
31:24
7:0 EN1K EN32K
15:8 WRTLOCK CALIB[4:0]
0x1C OSCULP32K
23:16
31:24
Name: INTENCLR
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CLKFAIL OSC32KRDY XOSC32KRDY
Access R/W R/W R/W
Reset 0 0 0
Name: INTENSET
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CLKFAIL OSC32KRDY XOSC32KRDY
Access R/W R/W R/W
Reset 0 0 0
Name: INTFLAG
Offset: 0x08
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CLKFAIL OSC32KRDY XOSC32KRDY
Access R/W R/W R/W
Reset 0 0 0
15.7.4 Status
Name: STATUS
Offset: 0x0C
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CLKSW CLKFAIL OSC32KRDY XOSC32KRDY
Access R R R R
Reset 0 0 0 0
Name: RTCCTRL
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
RTCSEL[2:0]
Access R/W R/W R/W
Reset 0 0 0
Name: XOSC32K
Offset: 0x14
Reset: 0x0080
Property: PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
WRTLOCK STARTUP[2:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY EN1K EN32K XTALEN ENABLE
Access R/W R/W R/W R/W R/W R/W
Reset 1 0 0 0 0 0
STARTUP[2:0] Number of OSCULP32K Clock Number of XOSC32K Clock Approximate Equivalent Time
Cycles Cycles [s]
0x0 1 3 0.000031
0x1 32 3 0.00098
0x2 2048 3 0.06
0x3 4096 3 0.125
0x4 16384 3 0.5
0x5 32768 3 1
0x6 65536 3 2
0x7 131072 3 4
Name: CFDCTRL
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
CFDPRESC SWBACK CFDEN
Access R/W R/W R/W
Reset 0 0 0
Name: EVCTRL
Offset: 0x17
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
CFDEO
Access R/W
Reset 0
Name: OSC32K
Offset: 0x18
Reset: 0x003F 0080 (Writing action by User required)
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
CALIB[6:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8
WRTLOCK STARTUP[2:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY EN1K EN32K ENABLE
Access R/W R/W R/W R/W R/W
Reset 1 0 0 0 0
15.7.10 32.768 kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
Name: OSCULP32K
Offset: 0x1C
Reset: 0x0000XX06
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
WRTLOCK CALIB[4:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 x x x x x
Bit 7 6 5 4 3 2 1 0
EN1K EN32K
Access R/W R/W
Reset 1 1
Bit 1 – EN32K
Value Description
0 The 32kHz output is disabled.
1 The 32kHz output is enabled.
16.1 Overview
The Power Manager (PM) controls the sleep modes of the device.
Various sleep modes are provided in order to fit power consumption requirements. This enables the PM to stop
unused modules in order to save power. In active mode, the CPU is executing application code. When the device
enters a sleep mode, program execution is stopped and some modules and clock domains are automatically
switched off by the PM according to the sleep mode. The application code decides which sleep mode to enter
and when. Interrupts from enabled peripherals and all enabled reset sources can restore the device from a sleep
mode to active mode.
16.2 Features
• Power management control:
– Sleep modes: Idle, Standby
POWER MANAGER
SLEEP MODE
MAIN CLOCK SUPPLY
CONTROLLER
CONTROLLER CONTROLLER
SLEEPCFG
POWER DOMAIN
CONTROLLER
STDBYCFG
PM 0x40000400 0 - Y - 1 N - - - -
16.5.1 Terminology
The following is a list of terms used to describe the Power Managemement features of this microcontroller.
16.5.3.1 Initialization
After a Power-on Reset (POR), the PM is enabled and the device is in Active mode.
Notes:
1. Asynchronous: interrupt generated on GCLK generic clock, external clock, or external event.
2. Synchronous: interrupt generated on the APB clock.
3. Synchronous interrupt only for peripherals configured to run in standby.
Note: The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section.
The sleep modes (idle, standby) and their effect on the clocks activity, the regulator and the SRAM state are
described in the table and the sections below.
Table 16-2. Sleep Mode Overview
Stop if RUNSTDBY =
Stop if RUNSTDBY = 0
0 Low
Stop LPVREG
STANDBY Stop Stop (4) (4) Run if Stop/Run if (7) Power
Stop/Run if (8)
RUNSTDBY = RUNSTDBY =
RUNSTDBY = 1 (5)
1 1 (6)
Notes:
1. The AHB/APB clocks are running up to MCLK, and then provided only to the IPs requesting them. For the
other IPs not requesting the clocks, they are gated at MCLK output.
2. Each GCLK1 to GCLK8 is running if the associated generated clock is requested by at least one IP. It is
stopped if no IP is requesting this clock.
3. The clock source is running if the clock is requested by at least one GCLK Generator. It is stopped if no GCLK
Generator is requesting this clock and will be restarted as soon as an IP requests a clock coming from a GCLK
fed by this clock source.
4. The AHB/APB clocks are stopped, except if requested by at least one IP, and in this case, only provided to
this/these IP(s) through GCLK0 and MCLK.
5. Each GCLK generators is stopped, except if the clock it generates is requested by at least one IP.
6. Each Clock Source is stopped, except if the clock it generates is requested by at least one GCLK Generator.
7. Regulator state is programmable by using STDBYCFG.VREGSMOD bits.
8. SRAM state is programmable by using STDBYCFG.BBIASHS bit.
16.5.3.3.1 IDLE Mode
The IDLE mode allows power optimization with the fastest wake-up time.
The CPU is stopped.
The clock source feeding the GCLK generator 0, the GCLK generator 0, and the MCLK are kept active. The
AHB/APB clocks are gated at the MCLK output, unless requested by a peripheral.
The other clock sources and the GCLK generators can be running or stopped depending on each clock source
ONDEMAND bit, and depending on the peripherals requesting these clocks.
If an AHB/APB clock is masked in MCLK.AHBMASK or MCLK.APBxMASK, then it is gated at the output of the MCLK
and not provided to the related peripheral (regardless of the related peripheral requesting it or not).
• Entering IDLE mode: The IDLE mode is entered by setting SLEEPCFG.SLEEPMODE = IDLE and by executing
the WFI instruction. Additionally, if the SLEEPONEXIT bit in the ARM Cortex System Control register (SCR) is
set, the IDLE mode will also be entered when the CPU exits the lowest priority ISR. This mechanism can be
useful for applications that only require the processor to run when an interrupt occurs. Before entering the IDLE
mode, the user must configure the Sleep Configuration register.
• Exiting IDLE mode: The processor wakes the system up when it detects any non-masked interrupt with sufficient
priority to cause exception entry. The system goes back to the ACTIVE mode. The CPU and affected modules
are restarted.
In IDLE mode, the regulator and SRAM operate in normal mode.
16.5.3.3.2 Standby Mode
The Standby mode is the lowest power configuration while keeping the state of the logic and the content of the
SRAM.
This mode depends on (As depicted in the previous table):
• The peripherals running in standby and requesting their asynchronous GCLK clock or their synchronous
AHB/APB clock
• The RUNSTDBY bit of the GCLK generators
• The RUNSTDBY/ONDEMAND bit combination of the clock sources
Each clock source and GCLK generator can be:
• Stopped during the whole standby
• Running during the whole standby
• Automatically woken up and switched off depending on the clocks requested by the peripherals during standby
(SleepWalking). For example a peripheral can run during standby and request its GCLK asynchronous clock,
which will wake up the related GCLK and clock source. Another peripheral may request its APB clock, which will
wake up the MCLK, GCLK generator 0 and the related clock source running. (In this case the other AHB/APB
clocks are kept gated at the MCLK output).
As described above, depending on the configuration, the current consumption of the device in Standby mode can be
slightly different.
All features that don’t require CPU intervention are supported in Standby mode. Here are examples:
• Autonomous peripherals features.
• Features relying on Event System allowing autonomous communication between peripherals.
• Features relying on on-demand clock.
• DMA transfers.
Entering Standby mode: This mode is entered by setting SLEEPCFG.SLEEPMODE = STANDBY and by executing
the WFI instruction. The SLEEPONEXIT feature is also available as in IDLE mode.
Exiting Standby mode: Any peripheral able to generate an asynchronous interrupt can wake up the system. For
example, a peripheral running on a GCLK clock can trigger an interrupt. When the enabled asynchronous wake-up
event occurs and the system is woken up, the device will either execute the interrupt service routine or continue the
normal program execution according to the Priority Mask Register (PRIMASK) configuration of the CPU.
STBYCDFG.BBIASHS SRAM
0x0 No Back Biasing SRAM is not back-biased if the device is in Standby Sleep mode.
0x1 Standby Back Biasing mode SRAM is back-biased if the device is in Standby Sleep mode.
0x00 Reserved
0x01 SLEEPCFG 7:0 SLEEPMODE[2:0]
0x02
... Reserved
0x07
7:0 VREGSMOD[1:0]
0x08 STDBYCFG
15:8 BBIASHS
Name: SLEEPCFG
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
SLEEPMODE[2:0]
Access R/W R/W R/W
Reset 0 0 0
Value Name
0x0 Reserved
0x1 Reserved
0x2 IDLE
0x3 Reserved
0x4 STANDBY
0x5 - 0x7 Reserved
Name: STDBYCFG
Offset: 0x08
Reset: 0x0400
Property: PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
BBIASHS
Access R/W
Reset 1
Bit 7 6 5 4 3 2 1 0
VREGSMOD[1:0]
Access R/W R/W
Reset 0 0
17.1 Overview
The Supply Controller (SUPC) manages the voltage reference and power supply of the device. The SUPC controls
the voltage regulators for the core (VDDCORE) domain. It sets the voltage regulators according to the sleep modes,
or the user configuration.
The SUPC embeds two Brown-out Detectors: BODVDD monitors the voltage applied to the device (VDD) and
BODCORE monitors the internal voltage to the core (VDDCORE). The BOD can monitor the supply voltage
continuously (continuous mode) or periodically (sampling mode).
The SUPC generates also a selectable reference voltage which can be used by analog modules, such as the ADC,
SDADC or DAC.
17.2 Features
• Voltage Regulator System
– Main voltage regulator: LDO in Active mode (MAINVREG)
– Low-power voltage regulator in Standby mode (LPVREG)
• Voltage Reference System
– Reference voltage for ADC, SDADC and DAC
• VDD Brown-out Detector (BODVDD)
– Programmable threshold
– Threshold value loaded from NVM User Row at startup
– Triggers resets or interrupts. Action loaded from NVM User Row
– Operating modes:
• Continuous mode
• Sampled mode for low-power applications with programmable sample frequency
– Hysteresis value from Flash User Calibration
• VDDCORE Brown-out Detector (BODCORE)
– Internal non-configurable Brown-out Detector
BODVDD BODVDD
BODCORE BODCORE
Main VREG
VREG LDO
VDDCORE
PM
sleep mode
LP VREG
Core
domain
VREF
VREFA reference voltage
17.5.1.2 Initialization
After a Reset, the LDO voltage regulator supplying VDDCORE is enabled.
17.5.2.1 Initialization
The voltage reference output is disabled after any Reset.
17.5.3.1 Initialization
Before a Brown-out Detector (BODVDD) is enabled, it must be configured, as outlined by the following:
• Set the BOD threshold level (BODVDD.LEVEL)
• Set the configuration in Active, Standby (BODVDD.ACTION, BODVDD.STDBYCFG)
• Set the prescaling value if the BOD will run in sampling mode (BODVDD.PSEL)
• Set the action and hysteresis (BODVDD.ACTION and BODVDD.HYST)
The BODVDD register is Enable-Protected, meaning that they can only be written when the BOD is disabled
(BODVDD.ENABLE = 0 and STATUS.BVDDSRDY = 0). As long as the Enable bit is '1', any writes to Enable-
Protected registers will be discarded, and an APB error will be generated. The Enable bits are not Enable-Protected.
17.5.3.7 Hysteresis
A hysteresis on the trigger threshold of a BOD will reduce the sensitivity to ripples on the monitored voltage: instead
of switching RESET at each crossing of VBOD, the thresholds for switching RESET on and off are separated (VBOD-
and VBOD+, respectively).
Figure 17-2. BOD Hysteresis Principle
Hysteresis OFF:
VCC
VBOD
RESET
Hysteresis ON:
VCC VBOD+
VBOD-
RESET
Enabling the BODVDD hysteresis by writing the Hysteresis bit in the BODVDD register (BODVDD.HYST) to '1' will
add hysteresis to the BODVDD threshold level.
The hysteresis functionality can be used in both Continuous and Sampling Mode (Refer to the 43. Electrical
Characteristics 85℃ section for more information on the hysteresis values).
17.5.4 Interrupts
The SUPC has the following interrupt sources, which are either synchronous or asynchronous wake-up sources:
• BODVDD Ready (BODVDDRDY), synchronous
• BODVDD Detection (BODVDDDET), asynchronous
• BODVDD Synchronization Ready (BVDDSRDY), synchronous
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
As both INTENSET and INTENCLR always reflect the same value, the status of interrupt enablement can be read
from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SUPC is reset.
See the INTFLAG register for details on how to clear interrupt flags. The SUPC has one common interrupt request
line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is
present.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
17.5.5 Synchronization
The prescaler counters that are used to trigger brown-out detections operate asynchronously from the peripheral bus.
As a consequence, the BODVDD Enable bit (BODVDD.ENABLE) need synchronization when written.
The Write-Synchronization of the Enable bit is triggered by writing a '1' to the Enable bit of the BODVDD Control
register. The Synchronization Ready bit (STATUS.BVDDSRDY) in the STATUS register will be cleared when the
Write-Synchronization starts, and set again when the Write-Synchronization is complete. Writing to the same register
while the Write-Synchronization is ongoing (STATUS.BVDDSRDY is '0') will generate a PAC error without stalling the
APB bus.
Name: INTENCLR
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
BVDDSRDY BODVDDDET BODVDDRDY
Access R/W R/W R/W
Reset 0 0 0
Name: INTENSET
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
BVDDSRDY BODVDDDET BODVDDRDY
Access R/W R/W R/W
Reset 0 0 0
Name: INTFLAG
Offset: 0x08
Reset: X determined from NVM User Row
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
BVDDSRDY BODVDDDET BODVDDRDY
Access R/W R/W R/W
Reset 0 0 x
17.6.4 Status
Name: STATUS
Offset: 0x0C
Reset: Determined from NVM User Row
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
BVDDSRDY BODVDDDET BODVDDRDY
Access R R R
Reset 0 0 y
Name: BODVDD
Offset: 0x10
Reset: X determined from NVM User Row
Property: Write-Synchronized Bits, Enable-Protected Bits, PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
LEVEL[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset x x x x x x
Bit 15 14 13 12 11 10 9 8
PSEL[3:0] ACTCFG
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RUNSTDBY STDBYCFG ACTION[1:0] HYST ENABLE
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 x x x x
Bit 2 – HYST Hysteresis
This bit indicates whether hysteresis is enabled for the BODVDD threshold voltage.
This bit is loaded from NVM User Row at start-up.
Note: This bit is enable-protected. This bit is not synchronized.
Value Description
0 No hysteresis.
1 Hysteresis enabled.
Bit 1 – ENABLE Enable
This bit is loaded from NVM User Row at start-up.
Notes:
1. This bit is write-synchronized: STATUS.BVDDSRDY must be checked to ensure the BODVDD.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value Description
0 BODVDD is disabled.
1 BODVDD is enabled.
Name: VREG
Offset: 0x18
Reset: 0x00000002
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RUNSTDBY ENABLE
Access R R/W R R R R R/W R
Reset 0 0 0 0 0 0 1 0
Name: VREF
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
SEL[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY VREFOE
Access R/W R/W R/W
Reset 0 0 0
18.1 Overview
The Reset Controller (RSTC) manages the reset of the microcontroller. It issues a microcontroller reset, sets the
device to its initial state and allows the reset source to be identified by software.
18.2 Features
• Reset the microcontroller and set it to an initial state according to the reset source
• Reset cause register for reading the reset source from the application code
• Multiple reset sources
– Power supply reset sources: POR, BODCORE, BODVDD
– User reset sources: External reset (RESET), Watchdog reset, and System Reset Request
Debug Logic
RESET
WDT
RCAUSE
RSTC 0x40000C00 - - Y - 3 N - - - -
18.6.2.1 Initialization
After a power-on Reset, the RSTC is enabled and the Reset Cause (RCAUSE) register indicates the POR source.
The external Reset is generated when pulling the RESET pin low.
The POR, BODCORE, and BODVDD Reset sources are generated by their corresponding module in the Supply
Controller Interface (SUPC).
The WDT Reset is generated by the Watchdog Timer.
The System Reset Request is a Reset generated by the CPU when asserting the SYSRESETREQ bit located in
the Reset Control register of the CPU (for details refer to the Arm Cortex Technical Reference Manual on http://
www.arm.com).
Note: Refer to the TRST specification in the Power Supply section of the Electrical Characteristics chapter.
Name: RCAUSE
Offset: 0x00
Property: –
When a Reset occurs, the bit corresponding to the Reset source is set to '1' and all other bits are written to '0'.
Bit 7 6 5 4 3 2 1 0
SYST WDT EXT BODVDD BODCORE POR
Access R R R R R R
Reset x x x x x x
19.1 Overview
The Peripheral Access Controller (PAC) provides an interface for the locking and unlocking of peripheral registers
within the device. It reports all violations that could happen when accessing a peripheral: write protected access,
illegal access, enable protected access, access when clock synchronization or software reset is on-going. These
errors are reported in a unique interrupt flag for a peripheral. The PAC module also reports errors occurring at the
client bus level, when an access to a non-existing address is detected.
19.2 Features
• Manages write protection access and reports access errors for the peripheral modules or bridges.
High-Speed BUS
PAC
IRQ Client ERROR
CLIENTs
APB INTFLAG
Peripheral ERROR
PERIPHERAL m
BUSn
PERIPHERAL 0
WRITE CONTROL
BUS0
PERIPHERAL 0
WRITE CONTROL
the user discretion. A set of Interrupt Flag and Status registers informs the user on the status of the violation in the
peripherals. In addition, client bus errors can be also reported in the cases where reserved area is accessed by the
application.
19.5.2.2 Operations
The PAC module allows the user to set, clear or lock the write protection status of all peripherals on all Peripheral
Bridges.
If a peripheral register violation occurs, the Peripheral Interrupt Flag n registers (INTFLAGn) are updated to inform
the user on the status of the violation in the peripherals connected to the Peripheral Bridge n (n = A,B,C ...). The
corresponding Peripheral Write Control Status n register (STATUSn) gives the state of the write protection for all
peripherals connected to the corresponding Peripheral Bridge n. Refer to 19.5.2.3 Peripheral Access Errors for
details.
The PAC module also reports the errors occurring at client bus level when an access to reserved area is detected.
AHB Client Bus Interrupt Flag register (INTFLAGAHB) informs the user on the status of the violation in the
corresponding client. Refer to the 19.5.2.6 AHB Client Bus Errors for details.
PAC also offers an additional safety feature for correct program execution with an interrupt generated on double
write clear protection or double write set protection. If a peripheral is write protected and a subsequent set protection
operation is detected then the PAC returns an error, and similarly for a double clear protection operation.
In addition, an error is generated when writing a “set and lock” protection to a write-protected peripheral or when a
write access is done to a locked set protection. This can be used to ensure that the application follows the intended
program flow by always following a write protect with an unprotect and conversely. However in applications where a
write protected peripheral is used in several contexts, e.g. interrupt, care should be taken so that either the interrupt
can not happen while the main application or other interrupt levels manipulates the write protection status or when
the interrupt handler needs to unprotect the peripheral based on the current protection status by reading the STATUS
register.
The errors generated while accessing the PAC module registers (for example, key error, double protect error, and so
on) will set the INTFLAGA.PAC flag.
19.5.3 Interrupts
The PAC has the following interrupt source:
• Error (ERR): Indicates that a peripheral access violation occurred in one of the peripherals controlled by the PAC
module, or a bridge error occurred in one of the bridges reported by the PAC
– This interrupt is a synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAGAHB and INTFLAGn) registers is set when the interrupt condition occurs.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the PAC is reset. All
interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request
to the NVIC 9.2 Nested Vector Interrupt Controller. The user must read the INTFLAGAHB and INTFLAGn registers
to determine which interrupt condition is present. Interrupts must be globally enabled for interrupt requests to be
generated.
19.5.4 Events
The PAC can generate the following output event:
• Error (ERR): Generated when one of the interrupt flag registers bits is set
Writing a '1' to an Event Output bit in the Event Control Register (EVCTRL.ERREO) enables the corresponding
output event. Writing a '0' to this bit disables the corresponding output event.
7:0 PERID[7:0]
15:8 PERID[15:8]
0x00 WRCTRL
23:16 KEY[7:0]
31:24
0x04 EVCTRL 7:0 ERREO
0x05
... Reserved
0x07
0x08 INTENCLR 7:0 ERR
0x09 INTENSET 7:0 ERR
0x0A
... Reserved
0x0F
7:0 DIVAS SRAMDMAC APBC APBA APBB HSRAMDSU HSRAMCM0P FLASH
15:8
0x10 INTFLAGAHB
23:16
31:24
OSC32KCTR
7:0 GCLK SUPC OSCCTRL RSTC MCLK PM PAC
L
0x14 INTFLAGA 15:8 FREQM EIC RTC WDT
23:16
31:24
7:0 HMATRIXHS MTB DMAC NVMCTRL DSU PORT
15:8
0x18 INTFLAGB
23:16
31:24
7:0 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS
15:8 TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0
0x1C INTFLAGC
23:16 CCL DAC AC SDADC ADC1 ADC0 TC4
31:24 PDEC
0x20
... Reserved
0x33
OSC32KCTR
7:0 GCLK SUPC OSCCTRL RSTC MCLK PM PAC
L
0x34 STATUSA 15:8 FREQM EIC RTC WDT
23:16
31:24
7:0 HMATRIXHS MTB DMAC NVMCTRL DSU PORT
15:8
0x38 STATUSB
23:16
31:24
7:0 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS
15:8 TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0
0x3C STATUSC
23:16 CCL DAC AC SDADC ADC1 ADC0 TC4
31:24 PDEC
Name: WRCTRL
Offset: 0x00
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
KEY[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
PERID[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PERID[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Peripheral Identifier
APBA Peripherals
PAC 0
PM 1
MCLK 2
RSTC 3
OSCCTRL 4
OSC32KCTRL 5
SUPC 6
GCLK 7
WDT 8
RTC 9
EIC 10
FREQM (4) 11
TEMPS (1) 12
APBB Peripherals
...........continued
Peripheral Identifier
PORT (2,3) 32
DSU 33
NVMCTRL 34
DMAC 35
MTB 36
HMATRIXHS 37
APBC Peripherals
EVSYS 64
SERCOM0 65
SERCOM1 66
SERCOM2 67
SERCOM3 68
TCC0 73
TCC1 74
TCC2 75
TC0 76
TC1 77
TC2 78
TC3 79
TC4 80
ADC0 81
ADC1 82
SDADC 83
AC 84
DAC 85
CCL 87
PDEC 90
Notes:
1. PAC protection for the TSENS should only be used when the TSENS is in Free Run mode.
2. IOBUS writes are not prevented to PAC write-protected registers when the PORT module is PAC protected.
3. PORT read/write attempts on non-implemented registers, including addresses beyond the last implemented
register group do not generate a PAC protection error.
4. Reading the Frequency Meter Control B register (FREQM.CTRLB) will result in a PAC error.
Name: EVCTRL
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ERREO
Access RW
Reset 0
Name: INTENCLR
Offset: 0x08
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
ERR
Access RW
Reset 0
Name: INTENSET
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
ERR
Access RW
Reset 0
Name: INTFLAGAHB
Offset: 0x10
Reset: 0x000000
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
DIVAS SRAMDMAC APBC APBA APBB HSRAMDSU HSRAMCM0P FLASH
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTFLAGA
Offset: 0x14
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
FREQM EIC RTC WDT
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTFLAGB
Offset: 0x18
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
HMATRIXHS MTB DMAC NVMCTRL DSU PORT
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: INTFLAGC
Offset: 0x1C
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
PDEC
Access R/W
Reset 0
Bit 23 22 21 20 19 18 17 16
CCL DAC AC SDADC ADC1 ADC0 TC4
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bits 12, 13, 14, 15, 16 – TC Interrupt Flag for TCn [n = 4..0]
Name: STATUSA
Offset: 0x34
Reset: 0x000000
Property: –
Value Description
0 Peripheral is not write protected.
1 Peripheral is write protected.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
FREQM EIC RTC WDT
Access R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: STATUSB
Offset: 0x38
Reset: 0x00000002
Property: –
Value Description
0 Peripheral is not write protected.
1 Peripheral is write protected.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
HMATRIXHS MTB DMAC NVMCTRL DSU PORT
Access R R R R R R
Reset 0 0 0 0 1 0
Name: STATUSC
Offset: 0x3C
Reset: 0x09000000
Property: –
Value Description
0 Peripheral is not write protected.
1 Peripheral is write protected.
Bit 31 30 29 28 27 26 25 24
PDEC
Access R
Reset 0
Bit 23 22 21 20 19 18 17 16
CCL DAC AC SDADC ADC1 ADC0 TC4
Access R R R R R R R
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TC3 TC2 TC1 TC0 TCC2 TCC1 TCC0
Access R R R R R R R
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS
Access R R R R R
Reset 0 0 0 0 0
Bits 12, 13, 14, 15, 16 – TC Peripheral TCn Write Protection Status [n = 4..0]
Bits 9, 10, 11 – TCC Peripheral TCCn [n = 2..0] Write Protection Status TCCn [n = 2..0]
20.1 Overview
The Device Service Unit (DSU) provides a means of detecting debugger probes. It enables the Arm Debug Access
Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level
™
services to debug adapters in an Arm debug system. It implements a CoreSight Debug ROM that provides device
identification as well as identification of other debug components within the system. Hence, it complies with the Arm
Peripheral Identification specification. The DSU also provides system services to applications that need memory
testing, as required for IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a
debugger and the CPU, as it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU
features will be limited or unavailable when the device is protected by the NVMCTRL security bit.
20.2 Features
• CPU reset extension
• Debugger probe detection (Cold-Plugging and Hot-Plugging)
• Chip-Erase command and status
• 32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix
• Arm® CoreSight™ compliant device identification
• Two debug communications channels
• Debug access port security filter
• DMA connection
• Onboard memory built-in self-test (MBIST)
DSU
debugger_present
RESET DMA request
DEBUGGER PROBE
SWCLK INTERFACE cpu_reset_extension
DAP CPU
DAP SECURITY FILTER DMA NVMCTRL
AHB-AP DBG
CORESIGHT ROM
PORT
M S S
CRC-32
SWDIO HIGH-SPEED
MBIST M
BUS MATRIX
CHIP ERASE
DSU 0x41002000 - Y Y - 1 Y - - - -
Figure 20-2. Typical CPU Reset Extension Set and Clear Timing Diagram
SWCLK
RESET
DSU CRSTEXT
Clear
CPU reset
extension
RESET
Hot-Plugging
The presence of a debugger probe is detected when either Hot Plugging or Cold Plugging is detected. Once
detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons,
Hot-Plugging is not available when the device is protected by the NVMCTRL security bit.
This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be done until
POR is released. If the device is protected, Cold Plugging is the only way to detect a debugger probe, and so the
external reset timing must be longer than the POR timing. If external reset is deasserted before POR release, the
user must retry the procedure above until it gets connected to the device.
Once the SCEHL command has been issued, STATUS2:CEHL will be set and it becomes permanently
WARNING
impossible to perform a Chip-Erase.
When the device is protected, the debugger must first reset the device in order to be detected. This ensures that
internal registers are reset after the protected state is removed. The Chip Erase operation is triggered by writing a
'1' to the Chip Erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected
by the Peripheral Access Controller (PAC). Once issued, the module clears volatile memories prior to erasing the
Flash array. To ensure that the Chip Erase operation is completed, check the Done bit of the Status A register
(STATUSA.DONE).
The Chip Erase operation depends on clocks and power management features that can be altered by the CPU. For
that reason, it is recommended to issue a Chip Erase after a Cold Plugging procedure to ensure that the device is in
a known and safe state.
The recommended sequence is as follows:
1. Issue the Cold Plugging procedure (refer to 20.6.3.1 Cold Plugging). The device then:
1.1. Detects the debugger probe.
1.2. Holds the CPU in reset.
2. Issue the Chip Erase command by writing a '1' to CTRL.CE. The device then:
2.1. Clears the system volatile memories.
2.2. Erases the whole Flash array (including the main array and Data Flash section, not including auxiliary
rows).
2.3. Clears the NVMCTRL security bit protection.
3. Check for completion by polling STATUSA.DONE (read as '1' when completed).
4. Reset the device to let the NVMCTRL update the fuses.
20.8 Programming
Programming the Flash or SRAM memories is only possible when the device is not protected by the NVMCTRL
security bit. The programming procedure is as follows:
1. At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state
until the input supply is above the POR threshold (refer to Power-on Reset (POR) characteristics). The system
continues to be held in this static state until the internally regulated supplies have reached a safe operating
state.
2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus
Clocks that do not have clock gate control). Internal resets are maintained due to the external reset.
3. The debugger maintains a low level on SWCLK. RESET is released, resulting in a debugger Cold-Plugging
procedure.
4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock.
5. The CPU remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released.
6. A Chip-Erase is issued to ensure that the Flash is fully erased prior to programming.
7. Programming is available through the AHB-AP.
8. After the operation is completed, the chip can be restarted either by asserting RESET or toggling power. Make
sure that the SWCLK pin is high when releasing RESET to prevent extending the CPU reset.
Mirrored
DSU operating
registers
0x01FF
DSU CoreSight
ROM
0x1FFF
Some features not activated by APB transactions are not available when the device is protected:
For more information, refer to the Arm Debug Interface Version 5 Architecture Specification.
20.11.2.1 Initialization
The module is enabled by enabling its clocks. The DSU registers can be PAC write-protected.
The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320
(reversed representation).
Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be
complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for
subsequent CRC32 calculations.
The actual test is started by writing a '1' in the 32-bit Cyclic Redundancy Check bit of the Control register
(CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing '1' to CTRL.SWRST).
The actual test is started by writing a '1' to CTRL.MBIST. A running MBIST operation can be canceled by
writing a '1' to CTRL.SWRST.
3. Interpreting the Results
The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set.
There are two different modes:
– ADDR.AMOD=0: exit-on-error (default)
In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both
cases, STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read
the DATA and ADDR registers to locate the fault.
– ADDR.AMOD=1: pause-on-error
In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only
STATUSA.FAIL is asserted. The state machine waits for user to clear STATUSA.FAIL by writing a '1' in
STATUSA.FAIL to resume. Prior to resuming, user can read the DATA and ADDR registers to locate the
fault.
4. Locating Faults
If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected
error. The position of the failing bit can be found by reading the following registers:
– ADDR: Address of the word containing the failing bit
– DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA
register will in this case contains the following bit groups:
Figure 20-6. DATA bits Description When MBIST Operation Returns an Error
Bit 31 30 29 28 27 26 25 24
Bit 23 22 21 20 19 18 17 16
Bit 15 14 13 12 11 10 9 8
phase
Bit 7 6 5 4 3 2 1 0
bit_index
• bit_index: contains the bit number of the failing bit
• phase: indicates which phase of the test failed and the cause of the error, as listed in the following table.
Table 20-4. MBIST Operation Phases
AMOD[1:0] Description
0x0 Exit on Error
0x1 Pause on Error
0x2, 0x3 Reserved
20.11.6 System Services Availability when Accessed Externally and Device is Protected
External access: Access performed in the DSU address offset 0x100-0x1FFF range.
Internal access: Access performed in the DSU address offset 0x000-0x0FF range.
Table 20-6. Available Features when Operated From The External Address Range and Device is Protected
...........continued
0x1FD4
... Reserved
0x1FDF
7:0 PARTNBL[7:0]
15:8
0x1FE0 PID0
23:16
31:24
7:0 JEPIDCL[3:0] PARTNBH[3:0]
15:8
0x1FE4 PID1
23:16
31:24
7:0 REVISION[3:0] JEPU JEPIDCH[2:0]
15:8
0x1FE8 PID2
23:16
31:24
7:0 REVAND[3:0] CUSMOD[3:0]
15:8
0x1FEC PID3
23:16
31:24
7:0 PREAMBLEB0[7:0]
15:8
0x1FF0 CID0
23:16
31:24
7:0 CCLASS[3:0] PREAMBLE[3:0]
15:8
0x1FF4 CID1
23:16
31:24
7:0 PREAMBLEB2[7:0]
15:8
0x1FF8 CID2
23:16
31:24
7:0 PREAMBLEB3[7:0]
15:8
0x1FFC CID3
23:16
31:24
20.12.1 Control
Name: CTRL
Offset: 0x0000
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
Reserved Reserved CE MBIST CRC SWRST
Access - - W W W W
Reset 0 0 0 0 0 0
Bit 7 – Reserved
Must be set to 0.
Bit 6 – Reserved
Must be set to 0.
Bit 4 – CE Chip-Erase
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the Chip-Erase operation.
Note: The chip erase operation can only be performed if the Chip Erase Hard Lock has not been set
(STATUS2:CEHL=0). Once STATUS2:CEHL=1, the chip erase feature becomes permanently disabled.
20.12.2 Status A
Name: STATUSA
Offset: 0x0001
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
PERR FAIL BERR CRSTEXT DONE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 3 – FAIL Failure
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Failure bit.
This bit is set when a DSU operation failure is detected.
Bit 0 – DONE Done
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Done bit.
This bit is set when a DSU operation is completed.
20.12.3 Status B
Name: STATUSB
Offset: 0x0002
Reset: x determined by Security Bit (SB) and Chip Erase Hard Lock (CEHL) bit configuration before reset
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
CEHL HPE DCCD1 DCCD0 DBGPRES PROT
Access R R R R R R
Reset x 1 0 0 0 x
Bit 0 – PROT Protected
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set at power-up when the device is protected (Meaning the Security Bit has been set).
This bit is never cleared.
20.12.4 Address
Name: ADDR
Offset: 0x0004
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
ADDR[29:22]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
ADDR[21:14]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
ADDR[13:6]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ADDR[5:0] AMOD[1:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
20.12.5 Length
Name: LENGTH
Offset: 0x0008
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
LENGTH[29:22]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
LENGTH[21:14]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
LENGTH[13:6]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
LENGTH[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
20.12.6 Data
Name: DATA
Offset: 0x000C
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
DATA[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DATA[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DATA[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DCC0
Offset: 0x0010
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
DATA[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DATA[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DATA[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DCC1
Offset: 0x0014
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
DATA[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DATA[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DATA[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DID
Offset: 0x0018
Property: -
Bit 31 30 29 28 27 26 25 24
PROCESSOR[3:0] FAMILY[4:1]
Access R R R R R R R R
Reset 0 0 0 1 0 0 0 1
Bit 23 22 21 20 19 18 17 16
FAMILY[0] SERIES[5:0]
Access R R R R R R R
Reset 0 0 0 0 1 1 0
Bit 15 14 13 12 11 10 9 8
DIE[3:0] REVISION[3:0]
Access R R R R R R R R
Reset d d d d r r r r
Bit 7 6 5 4 3 2 1 0
DEVSEL[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Value Description
Other Reserved
Name: ENTRY0
Offset: 0x1000
Reset: 0x9F0FC002
Property: -
Bit 31 30 29 28 27 26 25 24
ADDOFF[19:12]
Access R R R R R R R R
Reset x x x x x x x x
Bit 23 22 21 20 19 18 17 16
ADDOFF[11:4]
Access R R R R R R R R
Reset x x x x x x x x
Bit 15 14 13 12 11 10 9 8
ADDOFF[3:0]
Access R R R R
Reset x x x x
Bit 7 6 5 4 3 2 1 0
FMT EPRES
Access R R
Reset 1 x
Bit 1 – FMT Format
Always reads as '1', indicating a 32-bit ROM table.
Name: ENTRY1
Offset: 0x1004
Reset: 0xXXXXX00X
Property: -
Bit 31 30 29 28 27 26 25 24
Reserved[19:12]
Access R R R R R R R R
Reset x x x x x x x x
Bit 23 22 21 20 19 18 17 16
Reserved[11:4]
Access R R R R R R R R
Reset x x x x x x x x
Bit 15 14 13 12 11 10 9 8
Reserved[3:0]
Access R R R R
Reset x x x x
Bit 7 6 5 4 3 2 1 0
Reserved Reserved
Access R R
Reset x x
Bit 1 – Reserved
Bit 0 – Reserved
Name: END
Offset: 0x1008
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
END[31:24]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
END[23:16]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
END[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
END[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: MEMTYPE
Offset: 0x1FCC
Reset: 0x0000000x
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
SMEMP
Access R
Reset x
Name: PID4
Offset: 0x1FD0
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
FKBC[3:0] JEPCC[3:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: PID0
Offset: 0x1FE0
Reset: 0x000000D0
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
PARTNBL[7:0]
Access R R R R R R R R
Reset 1 1 0 1 0 0 0 0
Name: PID1
Offset: 0x1FE4
Reset: 0x000000FC
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
JEPIDCL[3:0] PARTNBH[3:0]
Access R R R R R R R R
Reset 1 1 1 1 1 1 0 0
Name: PID2
Offset: 0x1FE8
Reset: 0x00000009
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
REVISION[3:0] JEPU JEPIDCH[2:0]
Access R R R R R R R R
Reset 0 0 0 0 1 0 0 1
Name: PID3
Offset: 0x1FEC
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
REVAND[3:0] CUSMOD[3:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: CID0
Offset: 0x1FF0
Reset: 0x0000000D
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
PREAMBLEB0[7:0]
Access R R R R R R R R
Reset 0 0 0 0 1 1 0 1
Name: CID1
Offset: 0x1FF4
Reset: 0x00000010
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CCLASS[3:0] PREAMBLE[3:0]
Access R R R R R R R R
Reset 0 0 0 1 0 0 0 0
Name: CID2
Offset: 0x1FF8
Reset: 0x00000005
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
PREAMBLEB2[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 1 0 1
Name: CID3
Offset: 0x1FFC
Reset: 0x000000B1
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
PREAMBLEB3[7:0]
Access R R R R R R R R
Reset 1 0 1 1 0 0 0 1
21.1 Overview
The Divide and Square Root Accelerator (DIVAS) is a programmable 32-bit signed or unsigned hardware divider and
a 32-bit unsigned square root hardware engine. The DIVAS is connected to the high-speed bus matrix and may also
be accessed using the low-latency CPU local bus (IOBUS; Arm single-cycle I/O port). The DIVAS takes dividend and
divisor values and returns the quotient and remainder when it is used as divider. The DIVAS takes unsigned input
value and returns its square root and remainder when it is used as square root function.
21.2 Features
• Division accelerator for Cortex-M0+ systems
• 32-bit signed or unsigned integer division
• 32-bit unsigned square root
• 32-bit division in 2-16 cycles
• Programmable leading zero optimization
• Result includes quotient and remainder
• Result includes square root and remainder
• Busy and Divide-by-zero status
• Automatic start of operation when divisor or square root input is loaded
DIVAS
DIVIDEND
DEVIDE ENGINE AHB
DIVISOR
CTRLA
QUOTIENT
IOBUS
REMAINDER INTERFACE
DIVAS 0x48000000 - Y - - - - - - - -
the dividend and divide registers are programmed, the division starts and the result will be stored in the Result and
Remainder registers. The Busy and Divide-by-zero status can be read from STATUS register.
When the square root input register (21.6.7 SQRNUM) is programmed, the square root function starts and the result
will be stored in the Result and Remainder registers. The Busy status can be read from STATUS register.
21.5.2.1 Initialization
The DIVAS configuration cannot be modified while a divide operation is ongoing. The following bits must be written
prior to starting a division:
• Sign selection bit in Control A register (21.6.1 CTRLA.SIGNED)
• Leading zero mode bit in Control A register (21.6.1 CTRLA.DLZ)
21.6.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DLZ SIGNED
Access R/W R/W
Reset 0 0
21.6.2 Status
Name: STATUS
Offset: 0x04
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
DBZ BUSY
Access R/W R/W
Reset 0 0
Bit 1 – DBZ Disable-By-Zero
Writing a zero to this bit has no effect.
Writing a one to this bit clears DBZ to zero.
Value Description
0 A divide-by-zero fault has not occurred
1 A divide-by-zero fault has occurred
21.6.3 Dividend
Name: DIVIDEND
Offset: 0x08
Reset: 0x0000
Property: -
Bit 31 30 29 28 27 26 25 24
DIVIDEND[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIVIDEND[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DIVIDEND[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DIVIDEND[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
21.6.4 Divisor
Name: DIVISOR
Offset: 0x0C
Reset: 0x0000
Property: -
Bit 31 30 29 28 27 26 25 24
DIVISOR[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIVISOR[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DIVISOR[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DIVISOR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
21.6.5 Result
Name: RESULT
Offset: 0x10
Reset: 0x0000
Property: -
Bit 31 30 29 28 27 26 25 24
RESULT[31:24]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
RESULT[23:16]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RESULT[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RESULT[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
21.6.6 Remainder
Name: REM
Offset: 0x14
Reset: 0x0000
Property: -
Bit 31 30 29 28 27 26 25 24
REM[31:24]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
REM[23:16]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
REM[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
REM[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: SQRNUM
Offset: 0x18
Reset: 0x0000
Property: -
Bit 31 30 29 28 27 26 25 24
SQRNUM[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
SQRNUM[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SQRNUM[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SQRNUM[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
22.1 Overview
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to
recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out
period, and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a
system reset. An early-warning interrupt is available to indicate an upcoming watchdog time-out condition.
The window mode makes it possible to define a time slot or window inside the total time-out period during which
the WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will
be issued. Compared to the normal mode, this can also catch situations where a code error causes the WDT to be
cleared too frequently.
When enabled, the WDT will run in Active mode and all sleep modes. It is asynchronous and runs from a CPU-
independent clock source. The WDT will continue operation and issue a system reset or interrupt even if the main
clocks fail.
22.2 Features
• Issues a system reset if the Watchdog Timer is not cleared before its time-out period
• Early Warning interrupt generation
• Asynchronous operation from dedicated oscillator
• Two types of operation
– Normal mode
– Window mode
• Selectable time-out periods
– From 8 cycles to 16,384 cycles in Normal mode
– From 16 cycles to 32,768 cycles in Window mode
• Always-On capability
0
CLEAR
CLK_WDT_OSC
OSC32KCTRL COUNT
(1.024 kHz)
PER/WINDOWS/EWOFFSET
WDT 0x40002000 1 - Y - 8 N - - - Y
22.5.2.1 Initialization
The following bits are enable-protected, meaning that they can only be written when the WDT is disabled
(CTRLA.ENABLE=0):
• Control A register (CTRLA), except the Enable bit (CTRLA.ENABLE)
• Configuration register (CONFIG)
• Early Warning Interrupt Control register (EWCTRL)
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but
not at the same time as CTRLA.ENABLE is written to '0'.
The WDT can be configured only while the WDT is disabled. The WDT is configured by defining the required
Time-Out Period bits in the Configuration register (CONFIG.PER). If Window mode operation is desired, the Window
Enable bit in the Control A register must be set (CTRLA.WEN=1) and the Window Period bits in the Configuration
register (CONFIG.WINDOW) must be defined.
Enable-protection is denoted by the "Enable-Protected" property in the register description.
WDT Count
System Reset
EWOFFSET[3:0] = 0
Early Warning Interrupt
t[ms]
5 10 15 20 25 30 35
TOWDT
WDT Count
Open
Early WDT Clear
WINDOW[3:0] = 0
Early Warning Interrupt
Closed
System Reset
t[ms]
5 10 15 20 25 30 35
TOWDTW TOWDT
22.5.3 Interrupts
The WDT has the following interrupt source:
• Early Warning (EW): Indicates that the counter is approaching the time-out condition.
– This interrupt is an asynchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set
(INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR)
register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the WDT is reset. See
the 22.6.6 INTFLAG register description for details on how to clear interrupt flags. All interrupt requests from the
peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user
must read the INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
22.5.4 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following registers are synchronized when written:
• Enable bit in Control A register (CTRLA.ENABLE)
• Window Enable bit in Control A register (CTRLA.WEN)
• Always-On bit in control Control A (CTRLA.ALWAYSON)
• Watchdog Clear register (CLEAR)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
The Interrupt Clear and Interrupt Set registers are accessible in the Always-On mode. The Early Warning interrupt
can still be enabled or disabled while in the Always-On mode, but note that EWCTRL.EWOFFSET cannot be
changed.
Table WDT Operating Modes With Always-On shows the operation of the WDT for CTRLA.ALWAYSON=1.
Table 22-2. WDT Operating Modes With Always-On
Example:
If the WDT is operating in Normal mode with CONFIG.PER = 0x2 and EWCTRL.EWOFFSET =
0x1, the Early Warning interrupt is generated 16 CLK_WDT_OSC clock cycles after the start of the
time-out period. The time-out system reset is generated 32 CLK_WDT_OSC clock cycles after the
start of the watchdog time-out period.
22.6.1 Control A
Name: CTRLA
Offset: 0x00
Reset: X determined from NVM User Row
Property: PAC Write-Protection, Write-Synchronized Bits
Bit 7 6 5 4 3 2 1 0
ALWAYSON WEN ENABLE
Access R/W R/W R/W
Reset x x x
Bit 7 – ALWAYSON Always-On
This bit allows the WDT to run continuously. After being set, this bit cannot be written to '0', and the WDT will remain
enabled until a power-on Reset is received. When this bit is '1', the Control A register (CTRLA), the Configuration
register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any writes to these
registers are not allowed.
Writing a '0' to this bit has no effect.
This bit is loaded from NVM user row at start-up.
Note: This bit is not synchronized.
Value Description
0 The WDT is enabled and disabled through the ENABLE bit.
1 The WDT is enabled and can only be disabled by a Power-on Reset (POR).
Bit 1 – ENABLE Enable
This bit enables or disables the WDT. It can only be written if CTRLA.ALWAYSON=0.
This bit is not Enable-Protected.
This bit is loaded from NVM User Row at startup.
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
Value Description
0 The WDT is disabled.
1 The WDT is enabled.
22.6.2 Configuration
Name: CONFIG
Offset: 0x01
Reset: X determined from NVM User Row
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
WINDOW[3:0] PER[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset x x x x x x x x
Name: EWCTRL
Offset: 0x02
Reset: X determined from NVM User Row
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
EWOFFSET[3:0]
Access R/W R/W R/W R/W
Reset x x x x
Name: INTENCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 7 6 5 4 3 2 1 0
EW
Access R/W
Reset 0
Name: INTENSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 7 6 5 4 3 2 1 0
EW
Access R/W
Reset 0
Name: INTFLAG
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EW
Access R/W
Reset 0
Name: SYNCBUSY
Offset: 0x08
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CLEAR ALWAYSON WEN ENABLE
Access R R R R
Reset 0 0 0 0
22.6.8 Clear
Name: CLEAR
Offset: 0x0C
Reset: 0x00
Property: Write-Synchronized
Note: CLEAR is a write-synchronized register: SYNCBUSY.CLEAR must be checked to ensure the CLEAR
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CLEAR[7:0]
Access W W W W W W W W
Reset 0 0 0 0 0 0 0 0
23.1 Overview
The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs
continuously to keep track of time. The RTC can wake up the device from sleep modes using the alarm/compare
wake up, periodic wake up, or overflow wake up mechanisms.
The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts
and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt
and peripheral event, and can be reset on the occurrence of an alarm/compare match. This allows periodic interrupts
and peripheral events at very long and accurate intervals.
The 10-bit programmable prescaler can scale down the clock source. By this, a wide range of resolutions and
time-out periods can be configured. With a 32.768kHz clock source, the minimum counter tick interval is 30.5µs, and
time-out periods can range up to 36 hours. For a counter tick interval of 1s, the maximum time-out period is more
than 136 years.
23.2 Features
• 32-bit counter with 10-bit prescaler
• Multiple clock sources
• 32-bit or 16-bit counter mode
• One 32-bit or two 16-bit compare values
• Clock/Calendar mode
– Time in seconds, minutes, and hours (12/24)
– Date in day of month, month, and year
– Leap year correction
• Digital prescaler correction/tuning for increased accuracy
• Overflow, alarm/compare match and prescaler interrupts and events
– Optional clear on alarm/compare match
• Two GP Registers
CLK_RTC_OSC CLK_RTC_CNT
OSC32KCTRL PRESCALER COUNT OVF
= CMPn
Periodic Events
COMPn
CLK_RTC_OSC CLK_RTC_CNT
OSC32KCTRL PRESCALER COUNT
= OVF
Periodic Events PER
= CMPn
COMPn
CLK_RTC_OSC CLK_RTC_CNT
OSC32KCTRL PRESCALER CLOCK OVF
MASKn = ALARMn
Periodic Events
ALARMn
3: CMP0/ALARM0
4: CMP1
RTC 0x40002400 2 - Y - 9 N - - Y
5: OVF
6-13: PER0-7
23.5.2.1 Initialization
The following bits are enable-protected, meaning that they can only be written when the RTC is disabled
(CTRLA.ENABLE=0):
• Operating Mode bits in the Control A register (CTRLA.MODE)
• Prescaler bits in the Control A register (CTRLA.PRESCALER)
• Clear on Match bit in the Control A register (CTRLA.MATCHCLR)
• Clock Representation bit in the Control A register (CTRLA.CLKREP)
The following registers are enable-protected:
• Event Control register (EVCTRL)
Enable-protected bits and registers can be changed only when the RTC is disabled (CTRLA.ENABLE=0). If the
RTC is enabled (CTRLA.ENABLE=1), these operations are necessary: first write CTRLA.ENABLE=0 and check
whether the write synchronization has finished, then change the desired bit field value. Enable-protected bits in
CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as
CTRLA.ENABLE is written to '0'.
Enable-protection is denoted by the "Enable-Protected" property in the register description.
The RTC prescaler divides the source clock for the RTC counter.
Note: In Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter for correct
operation.
The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula:
fCLK_RTC_OSC
fCLK_RTC_CNT =
2PRESCALER
The frequency of the oscillator clock, CLK_RTC_OSC, is given by fCLK_RTC_OSC, and fCLK_RTC_CNT is the frequency of
the internal prescaled RTC clock, CLK_RTC_CNT.
23.5.3 Clocks
The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Main Clock module MCLK, and the default
state of CLK_RTC_APB can be found in the Peripheral Clock Masking section.
A 32.768 kHz or 1.024 kHz oscillator clock (CLK_RTC_OSC) is required to clock the RTC. This clock must be
configured and enabled in the 32.768 kHz oscillator controller (OSC32KCTRL) before using the RTC.
This oscillator clock is asynchronous to the bus clock (CLK_RTC_APB). Due to this asynchronicity, writing to certain
registers will require synchronization between the clock domains. Refer to Synchronization for further details.
23.5.4 Interrupts
The RTC has the following interrupt sources:
• Overflow (OVF): Indicates that the counter has reached its top value and wrapped to zero.
• Compare (CMP0-1): Indicates a match between the counter value and the compare register.
• Alarm (ALARM0): Indicates a match between the clock value and the alarm register.
• Period n (PER0-7): The corresponding bit in the prescaler has toggled. Refer to 23.5.8.1 Periodic Intervals for
details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by setting
the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled by setting the corresponding
bit in the Interrupt Enable Clear register (INTENCLR=1).
An interrupt request is generated when the interrupt flag is raised and the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled or the RTC is reset.
See the description of the INTFLAG registers for details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt
request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The user must read the INTFLAG
register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to the Nested Vector
Interrupt Controller for details.
23.5.5 Events
The RTC can generate the following output events:
• Overflow (OVF): Generated when the counter has reached its top value and wrapped to zero.
• Compare (CMP0-1): Indicates a match between the counter value and the compare register.
• Alarm (ALARM0): Indicates a match between the clock value and the alarm register.
• Period n (PER0-7): The corresponding bit in the prescaler has toggled. Refer to 23.5.8.1 Periodic Intervals for
details.
• Periodic Daily (PERD): Generated when the COUNT/CLOCK has incremented at a fixed period of time.
Setting the Event Output bit in the Event Control Register (EVCTRL.xxxEO=1) enables the corresponding output
event. Writing a zero to this bit disables the corresponding output event. Refer to the EVSYS - Event System for
details on configuring the event system.
When the device is in STANDBY sleep mode the DMA is not able to write the COUNT register. To write the COUNT
register with the DMA the device must be in Active mode or IDLE sleep mode.
23.5.7 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in Control A register, CTRLA.SWRST
• Enable bit in Control A register, CTRLA.ENABLE
• Count Read Synchronization bit in Control A register (CTRLA.COUNTSYNC)
• Clock Read Synchronization bit in Control A register (CTRLA.CLOCKSYNC)
The following registers are synchronized when written:
• Counter Value register, COUNT
• Clock Value register, CLOCK
• Counter Period register, PER
• Compare n Value registers, COMPn
• Alarm n Value registers, ALARM0
• Frequency Correction register, FREQCORR
• Alarm n Mask register, MASK0
• The General Purpose n registers (GP0, GP1)
The following registers are synchronized when read:
• The Counter Value register, COUNT, if the Counter Read Sync Enable bit in CTRLA (CTRLA.COUNTSYNC) is
'1'
• The Clock Value register, CLOCK, if the Clock Read Sync Enable bit in CTRLA (CTRLA.CLOCKSYNC) is '1'
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
PER0
PER1
PER2
PER3
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
COUNTSYNC PRESCALER[3:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MATCHCLR MODE[1:0] ENABLE SWRST
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 1 – ENABLE Enable
Due to synchronization there is a delay between writing CTRLA.ENABLE and until the peripheral is enabled/disabled.
The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy
register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value Description
0 The peripheral is disabled
1 The peripheral is enabled
Name: EVCTRL
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
OVFEO CMPEO0
Access R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTENCLR
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 15 14 13 12 11 10 9 8
OVF CMP0
Access R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTENSET
Offset: 0x0A
Reset: 0x0000
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 15 14 13 12 11 10 9 8
OVF CMP0
Access R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTFLAG
Offset: 0x0C
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
OVF CMP0
Access R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 – OVF Overflow
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be
generated if INTENCLR/SET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
Bit 8 – CMP0 Compare 0
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request
will be generated if INTENCLR/SET.COMP0 is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Compare 0 interrupt flag.
Name: DBGCTRL
Offset: 0x0E
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
COUNTSYNC
Access R
Reset 0
Bit 7 6 5 4 3 2 1 0
COMP0 COUNT FREQCORR ENABLE SWRST
Access R R R R R
Reset 0 0 0 0 0
Value Description
1 Write synchronization for CTRLA.SWRST bit is ongoing.
Name: FREQCORR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
SIGN VALUE[6:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: COUNT
Offset: 0x18
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit 31 30 29 28 27 26 25 24
COUNT[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
COUNT[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
COUNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
COUNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: COMP
Offset: 0x20
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
COMP[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
COMP[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
COMP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
COMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: GPn
Offset: 0x40 + n*0x04 [n=0..1]
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
GP[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
GP[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
GP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
COUNTSYNC PRESCALER[3:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MODE[1:0] ENABLE SWRST
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value Description
0 The peripheral is disabled
1 The peripheral is enabled
Name: EVCTRL
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
OVFEO CMPEO1 CMPEO0
Access R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTENCLR
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 15 14 13 12 11 10 9 8
OVF CMP1 CMP0
Access R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTENSET
Offset: 0x0A
Reset: 0x0000
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 15 14 13 12 11 10 9 8
OVF CMP1 CMP0
Access R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTFLAG
Offset: 0x0C
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
OVF CMP1 CMP0
Access R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 – OVF Overflow
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be
generated if INTENCLR/SET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
Name: DBGCTRL
Offset: 0x0E
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
GP1 GP0
Access R/W R/W
Reset 0 0
Bit 15 14 13 12 11 10 9 8
COUNTSYNC
Access R
Reset 0
Bit 7 6 5 4 3 2 1 0
COMP1 COMP0 PER COUNT FREQCORR ENABLE SWRST
Access R/W R/W R R R R R
Reset 0 0 0 0 0 0 0
Name: FREQCORR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
SIGN VALUE[6:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: COUNT
Offset: 0x18
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit 15 14 13 12 11 10 9 8
COUNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
COUNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PER
Offset: 0x1C
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
PER[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: COMP
Offset: 0x20 + n*0x02 [n=0..1]
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
COMP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
COMP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: GPn
Offset: 0x40 + n*0x04 [n=0..1]
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
GP[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
GP[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
GP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
CLOCKSYNC PRESCALER[3:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MATCHCLR CLKREP MODE[1:0] ENABLE SWRST
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Value Description
1 12 Hour (AM/PM)
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value Description
0 The peripheral is disabled
1 The peripheral is enabled
Name: EVCTRL
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
OVFEO ALARMEO0
Access R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTENCLR
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 15 14 13 12 11 10 9 8
OVF ALARM0
Access R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTENSET
Offset: 0x0A
Reset: 0x0000
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 15 14 13 12 11 10 9 8
OVF ALARM0
Access R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTFLAG
Offset: 0x0C
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
OVF ALARM0
Access R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 – OVF Overflow
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be
generated if INTENCLR/SET.OVF is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
Bit 8 – ALARM0 Alarm 0
This flag is cleared by writing a '1' to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request
will be generated if INTENCLR/SET.ALARM0 is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Alarm 0 interrupt flag.
Name: DBGCTRL
Offset: 0x0E
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
GP1 GP0
Access R/W R/W
Reset 0 0
Bit 15 14 13 12 11 10 9 8
CLOCKSYNC MASK0
Access R R
Reset 0 0
Bit 7 6 5 4 3 2 1 0
ALARM0 CLOCK FREQCORR ENABLE SWRST
Access R R R R R
Reset 0 0 0 0 0
Name: FREQCORR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
SIGN VALUE[6:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CLOCK
Offset: 0x18
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit 31 30 29 28 27 26 25 24
YEAR[5:0] MONTH[3:2]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
MONTH[1:0] DAY[4:0] HOUR[4]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
HOUR[3:0] MINUTE[5:2]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MINUTE[1:0] SECOND[5:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: ALARM
Offset: 0x20
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized
The 32-bit value of ALARM is continuously compared with the 32-bit CLOCK value, based on the masking set
by MASK.SEL. When a match occurs, the Alarm n interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.ALARM) is set on the next counter cycle, and the counter is cleared if CTRLA.MATCHCLR is '1'.
Bit 31 30 29 28 27 26 25 24
YEAR[5:0] MONTH[3:2]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
MONTH[1:0] DAY[4:0] HOUR[4]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
HOUR[3:0] MINUTE[5:2]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MINUTE[1:0] SECOND[5:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: MASK
Offset: 0x24
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
SEL[2:0]
Access R/W R/W R/W
Reset 0 0 0
Name: GPn
Offset: 0x40 + n*0x04 [n=0..1]
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
GP[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
GP[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
GP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
24.1 Overview
The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access engine and a Cyclic
Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus
off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up
CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication
modules.
The DMA part of the DMAC has several DMA channels which can receive different types of transfer triggers and
generate transfer requests from the DMA channels to the arbiter (Refer to the Block Diagram). The arbiter will select
one DMA channel at a time to act as the active channel. When an active channel has been selected, the fetch engine
of the DMAC will fetch a transfer descriptor from the SRAM and store it in the internal memory of the active channel,
which will then execute the data transmission.
An ongoing data transfer of an active channel can be interrupted by a higher prioritized DMA channel. The DMAC
will write back the updated transfer descriptor from the internal memory of the active channel to SRAM, and grant the
higher prioritized channel to start transfer as the new active channel. Once a DMA channel is done with its transfer,
interrupts and events can be generated optionally.
The DMAC has four bus interfaces:
• The data transfer bus is used for performing the actual DMA transfer.
• The AHB/APB Bridge bus is used when writing and reading the I/O registers of the DMAC.
• The descriptor fetch bus is used by the fetch engine to fetch transfer descriptors before data transfer can be
started or continued.
• The write-back bus is used to write the transfer descriptor back to SRAM.
All buses are AHB host interfaces except the AHB/APB Bridge bus, which is an APB client interface.
The CRC engine can be used by software to detect an accidental error in the transferred data and to take corrective
action, such as requesting the data to be sent again or simply not using the incorrect data.
24.2 Features
• Data transfer from:
– Peripheral-to-peripheral
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
• Transfer trigger sources
– Software
– Events from Event System
– Dedicated requests from peripherals
• SRAM-based transfer descriptors
– Single transfer using one descriptor
– Multi-buffer or circular buffer modes by linking multiple descriptors
• Up to 12 channels
– Enable 12 independent transfers
– Automatic descriptor fetch for each channel
– Suspend/resume operation support for each channel
• Flexible arbitration scheme
– 4 configurable priority levels for each channel
HIGH SPEED
BUS MATRIX
C SRAM
C H
Descriptor Fetch
Write-back
Data Transfer
AHB/APB
Bridge
DMAC
HOST
Fetch
DMA Channels Engine
Channel n
Interrupts
Channel 1
Transfer Active
Channel 0 Arbiter Interrupt /
Triggers n Channel Events Events
CRC
Engine
24.5.1.1 DMA
The DMAC can transfer data between memories and peripherals without interaction from the CPU. The data
transferred by the DMAC are called transactions, and these transactions can be split into smaller data transfers.
The following figure shows the relationship between the different transfer sizes:
Figure 24-2. DMA Transfer Sizes
Link Enabled Link Enabled Link Enabled
DMA transaction
• Beat transfer: The size of one data transfer bus access, and the size is selected by writing the Beat Size bit
group in the Block Transfer Control register (BTCTRL.BEATSIZE)
• Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k
beats. A block transfer can be interrupted.
• Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second
and so forth, as shown in the figure above. A DMA transaction is the complete transfer of all blocks within a
linked list.
A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must remain in SRAM.
For further details on the transfer descriptor refer to 24.5.2.3 Transfer Descriptors.
The figure above shows several block transfers linked together, which are called linked descriptors. For further
information about linked descriptors, refer to 24.5.3.1 Linked Descriptors.
A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be
configured to be either a software trigger, an event trigger, or one of the dedicated peripheral triggers. The transfer
trigger will result in a DMA transfer request from the specific channel to the arbiter. If there are several DMA channels
with pending transfer requests, the arbiter chooses which channel is granted access to become the active channel.
The DMA channel granted access as the active channel will carry out the transaction as configured in the transfer
descriptor. A current transaction can be interrupted by a higher prioritized channel, but will resume the block transfer
when the according DMA channel is granted access as the active channel again.
For each beat transfer, an optional output event can be generated. For each block transfer, optional interrupts and an
optional output event can be generated. When a transaction is completed, depending on the configuration, the DMA
channel will either be suspended or disabled.
24.5.1.2 CRC
The internal CRC engine supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE
802.3). It can be used on a selectable DMA channel, or on the I/O interface. Refer to 24.5.3.7 CRC Operation for
details.
24.5.2.1 Initialization
The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is
disabled (CTRL.DMAENABLE=0):
• Descriptor Base Memory Address register (BASEADDR)
• Write-Back Memory Base Address register (WRBADDR)
The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are
disabled (CTRL.DMAENABLE=0 and CTRL.CRCENABLE=0):
• Software Reset bit in Control register (CTRL.SWRST)
The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding
DMA channel is disabled (CHCTRLA.ENABLE=0):
• Channel Control B (CHCTRLB) register, except the Command bit (CHCTRLB.CMD) and the Channel Arbitration
Level bit (CHCTRLB.LVL)
The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA
channel is disabled:
• Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST)
The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled
(CTRL.CRCENABLE=0):
• CRC Control register (CRCCTRL)
• CRC Checksum register (CRCCHKSUM)
Enable-protection is denoted by the "Enable-Protected" property in the register description.
Before the DMAC is enabled it must be configured, as outlined by the following steps:
• The SRAM address of where the descriptor memory section is located must be written to the Description Base
Address (BASEADDR) register
• The SRAM address of where the write-back section should be located must be written to the Write-Back
Memory Base Address (WRBADDR) register
• Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control register
(CTRL.LVLENx=1)
Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be
configured, as outlined by the following steps:
• DMA channel configurations
– The channel number of the DMA channel to configure must be written to the Channel ID (CHID) register
– Trigger action must be selected by writing the Trigger Action bit group in the Channel Control B register
(CHCTRLB.TRIGACT)
– Trigger source must be selected by writing the Trigger Source bit group in the Channel Control B register
(CHCTRLB.TRIGSRC)
• Transfer Descriptor
– The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the
Block Transfer Control register (BTCTRL.BEATSIZE)
– The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control
register (BTCTRL.VALID)
– Number of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT)
register
– Source address for the block transfer must be selected by writing the Block Transfer Source Address
(SRCADDR) register
– Destination address for the block transfer must be selected by writing the Block Transfer Destination
Address (DSTADDR) register
If CRC calculation is needed, the CRC engine must be configured before it is enabled, as outlined by the following
steps:
• The CRC input source must selected by writing the CRC Input Source bit group in the CRC Control register
(CRCCTRL.CRCSRC)
• The type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the CRC Control
register (CRCCTRL.CRCPOLY)
• If I/O is selected as input source, the beat size must be selected by writing the CRC Beat Size bit group in the
CRC Control register (CRCCTRL.CRCBEATSIZE)
0x00000000
DSTADDR
DESCADDR Channel 0 – Last Descriptor
SRCADDR
BTCNT
BTCTRL
DESCADDR
DSTADDR
DESCADDR Channel 0 – Descriptor n-1
SRCADDR
BTCNT
BTCTRL
Descriptor Section
Channel n – First Descriptor
DESCADDR
Channel 2 – First Descriptor
Channel 1 – First Descriptor DSTADDR
BASEADDR Channel 0 – First Descriptor
SRCADDR
BTCNT
BTCTRL
Write-Back Section
Undefined
Channel n Ongoing Descriptor
Undefined
Channel 2 Ongoing Descriptor
Channel 1 Ongoing Descriptor
Undefined
WRBADDR Channel 0 Ongoing Descriptor
Undefined
Undefined
Device Memory Space
The size of the descriptor and write-back memory sections is dependent on the number of the most significant
enabled DMA channel m, as shown below:
Size = 128bits ⋅ m + 1
For memory optimization, it is recommended to always use the less significant DMA channels if not all channels are
required.
The descriptor and write-back memory sections can either be two separate memory sections, or they can share
memory section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same
transaction for a channel can be repeated without having to modify the first transfer descriptor. The benefit of having
descriptor memory and write-back memory in the same section is that it requires less SRAM. In addition, the latency
from fetching the first descriptor of a transaction to the first burst transfer is executed, is reduced.
24.5.2.4 Arbitration
If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request
to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of
channels having pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers
(PENDCH.PENDCHx) will be set. Depending on the arbitration scheme, the arbiter will choose which DMA channel
will be the next active channel. The active channel is the DMA channel being granted access to perform its
next burst transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding bit
PENDCH.PENDCHx will be cleared. See also the following figure.
If the upcoming burst transfer is the first for the transfer request, the corresponding Busy Channel x bit in the
Busy Channels register will be set (BUSYCH.BUSYCHx=1), and it will remain '1' for the subsequent granted burst
transfers.
When the channel has performed its granted burst transfer(s) it will be either fed into the queue of channels with
pending transfers, set to be waiting for a new transfer trigger, suspended, or disabled. This depends on the channel
and block transfer configuration. If the DMA channel is fed into the queue of channels with pending transfers, the
corresponding BUSYCH.BUSYCHx will remain '1'. If the DMA channel is set to wait for a new transfer trigger,
suspended, or disabled, the corresponding BUSYCH.BUSYCHx will be cleared.
If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending
channels, but the corresponding PENDCH.PENDCHx will remain set. When the same DMA channel is resumed, it
will be added to the queue of pending channels again.
If a DMA channel gets disabled (CHCTRLA.ENABLE=0) while it has a pending transfer, it will be removed from the
queue of pending channels, and the corresponding PENDCH.PENDCHx will be cleared.
Figure 24-4. Arbiter Overview
Arbiter
Channel Pending
Burst Done
Channel Pending Transfer Request Active
Channel Suspend
Channel Number Channel
Channel N
Channel Priority Level
Channel Burst Done
Active.LVLEXx
Level Enable
PRICTRLx.LVLPRI
CTRL.LVLENx
Priority Levels
When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in
the Active Channel and Levels register (ACTIVE.LVLEXx).
Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by writing to the
Channel Arbitration Level bit group in the Channel Control B register (CHCTRLB.LVL). As long as all priority levels
are enabled, a channel with a higher priority level number will have priority over a channel with a lower priority level
number. Each priority level x is enabled by setting the corresponding Priority Level x Enable bit in the Control register
(CTRL.LVLENx=1).
Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically:
Static Arbitration within a priority level is selected by writing a '0' to the Level x Round-Robin Scheduling Enable bit in
the Priority Control 0 register (PRICTRL0.RRLVLENx).
When static arbitration is selected, the arbiter will prioritize a low channel number over a high channel number as
shown in the figure below. When using the static arbitration there is a risk of high channel numbers never being
granted access as the active channel. This can be avoided using a dynamic arbitration scheme.
.
.
.
Channel x
Channel x+1
.
.
.
Channel 0 Channel 0
.
.
.
Channel x Lowest Priority Channel x
Channel x+1 Highest Priority Channel x+1 Lowest Priority
Channel x+2 Highest Priority
.
.
.
Channel N Channel N
Once the arbiter has granted a DMA channel access as the active channel (refer to DMA Block Diagram section) the
transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal
memory for the active channel. For a new block transfer, the transfer descriptor will be fetched from the descriptor
memory section (BASEADDR); For an ongoing block transfer, the descriptor will be fetched from the write-back
memory section (WRBADDR). By using the data transfer bus, the DMAC will read the data from the current source
address and write it to the current destination address. For further details on how the current source and destination
addresses are calculated, refer to the section on Addressing.
The arbitration procedure is performed after each burst transfer. If the current DMA channel is granted access again,
the block transfer counter (BTCNT) of the internal transfer descriptor will be decremented by the number of beats in a
burst transfer, the optional output event Beat will be generated if configured and enabled, and the active channel will
perform a new burst transfer. If a different DMA channel than the current active channel is granted access, the block
transfer counter value will be written to the write-back section before the transfer descriptor of the newly granted DMA
channel is fetched into the internal memory of the active channel.
When a block transfer has come to its end (BTCNT is zero), the Valid bit in the Block Transfer Control register will
be cleared (BTCTRL.VALID=0) before the entire transfer descriptor is written to the write-back memory. The optional
interrupts, Channel Transfer Complete and Channel Suspend, and the optional output event Block, will be generated
if configured and enabled. After the last block transfer in a transaction, the Next Descriptor Address register
(DESCADDR) will hold the value 0x00000000, and the DMA channel will either be suspended or disabled, depending
on the configuration in the Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT). If
the transaction has further block transfers pending, DESCADDR will hold the SRAM address to the next transfer
descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of the active channel and
write its content to the write-back section for the channel, before the arbiter gets to choose the next active channel.
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
If the trigger source generates a transfer request for a channel during an ongoing transfer, the new transfer request
will be kept pending (CHSTATUS.PEND=1), and the new transfer can start after the ongoing one is done. Only one
pending transfer can be kept per channel. If the trigger source generates more transfer requests while one is already
pending, the additional ones will be lost. All channels pending status flags are also available in the Pending Channels
register (PENDCH).
When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register
(CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All channel busy
status flags are also available in the Busy Channels register (BUSYCH) in DMAC.
24.5.2.7 Addressing
Each block transfer needs to have both a source address and a destination address defined. The source address
is set by writing the Transfer Source Address (SRCADDR) register, the destination address is set by writing the
Transfer Destination Address (SRCADDR) register.
The addressing of this DMAC module can be static or incremental, for either source or destination of a block transfer,
or both.
Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation
Enable bit in the Block Transfer Control register (BTCTRL.SRCINC=1). The step size of the incrementation
is configurable and can be chosen by writing the Step Selection bit in the Block Transfer Control register
(BTCTRL.STEPSEL=1) and writing the desired step size in the Address Increment Step Size bit group in the Block
Transfer Control register (BTCTRL.STEPSIZE). If BTCTRL.STEPSEL=0, the step size for the source incrementation
will be the size of one beat.
If BTCTRL.STEPSEL=0:
SRCADDR = SRCADDRSTART + BTCNT ⋅ BEATSIZE + 1
• SRCADDRSTART is the source address of the first beat transfer in the block transfer
• BTCNT is the initial number of beats remaining in the block transfer
• BEATSIZE is the configured number of bytes in a beat
• STEPSIZE is the configured number of beats for each incrementation
The following figure shows an example where DMA channel 0 is configured to increment the source address
by one beat after each beat transfer (BTCTRL.SRCINC=1), and DMA channel 1 is configured to increment the
source address by two beats (BTCTRL.SRCINC=1, BTCTRL.STEPSEL=1, and BTCTRL.STEPSIZE=0x1). As the
destination address for both channels are peripherals, destination incrementation is disabled (BTCTRL.DSTINC=0).
Figure 24-8. Source Address Increment
Incrementation for the destination address of a block transfer is enabled by setting the Destination Address
Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC=1). The step size of the
incrementation is configurable by clearing BTCTRL.STEPSEL=0 and writing BTCTRL.STEPSIZE to the desired step
size. If BTCTRL.STEPSEL=1, the step size for the destination incrementation will be the size of one beat.
When the destination address incrementation is configured (BTCTRL.DSTINC=1), DSTADDR must be set and
calculated as follows:
• DSTADDRSTART is the destination address of the first beat transfer in the block transfer
• BTCNT is the initial number of beats remaining in the block transfer
• BEATSIZE is the configured number of bytes in a beat
• STEPSIZE is the configured number of beats for each incrementation
The followiong figure shows an example where DMA channel 0 is configured to increment destination address
by one beat (BTCTRL.DSTINC=1) and DMA channel 1 is configured to increment destination address by two
beats (BTCTRL.DSTINC=1, BTCTRL.STEPSEL=0, and BTCTRL.STEPSIZE=0x1). As the source address for both
channels are peripherals, source incrementation is disabled (BTCTRL.SRCINC=0).
issued before the channel is suspended, the next suspend action is skipped and the channel continues the normal
operation.
Figure 24-10. Channel Suspend/Resume Operation
CHENn
Resume Command
Suspend skipped
Normal Transfer
The event input is used to trigger a beat or burst transfer on peripherals.
The event is acknowledged as soon as the event is received. When received, both the Channel Pending status bit
in the Channel Status register (CHSTATUS.PEND) and the corresponding Channel n bit in the Pending Channels
register (24.6.13 PENDCH.PENDCHn) are set. If the event is received while the channel is pending, the event
trigger is lost.
The figure below shows an example where beat transfers are enabled by internal events.
Peripheral Trigger
Trigger Lost
Event
PENDCHn
BUSYCHn
Event
Peripheral Trigger
PENDCHn
Block Transfer
Data Transfer
BEAT
Conditional Transfer
The event input is used to trigger a conditional transfer on peripherals with pending transfer requests. For example,
this type of event can be used for peripheral-to-peripheral transfers, where one peripheral is the source of event and
the second peripheral is the source of the trigger.
Each peripheral trigger is stored internally when the event is received. When the peripheral trigger is stored internally,
the Channel Pending status bit is set (CHSTATUS.PEND), the respective Pending Channel n Bit in the Pending
Channels register is set (24.6.13 PENDCH.PENDCHn), and the event is acknowledged. A software trigger will now
trigger a transfer.
The figure below shows an example where conditional event is enabled with peripheral beat trigger requests.
Event
Peripheral Trigger
PENDCHn
Block Transfer
Data Transfer
BEAT BEAT
Peripheral Trigger
PENDCHn
Channel Suspend
The event input is used to suspend an ongoing channel operation. The event is acknowledged when the current AHB
access is completed. For further details on Channel Suspend, refer to 24.5.3.2 Channel Suspend.
Channel Resume
The event input is used to resume a suspended channel operation. The event is acknowledged as soon as the
event is received and the Channel Suspend Interrupt Flag (CHINTFLAG.SUSP) is cleared. For further details refer to
24.5.3.2 Channel Suspend.
the Block Transfer Control register (BTCTRL.EVOSEL). It is possible to generate events after each block transfer
(BTCTRL.EVOSEL=0x1) or beat transfer (BTCTRL.EVOSEL=0x3). To enable an event being generated when a
transaction is complete, the block event selection must be set in the last transfer descriptor only.
Figure 24-15 shows an example where the event output generation is enabled in the first block transfer, and disabled
in the second block.
Figure 24-15. Event Output Generation
Beat Event Output
Event Output
Event Output
CRCDATAIN
CRCCTRL
8 16 8 32
CRC-16 CRC-32
crc32
CHECKSUM
bit-reverse +
complement
Checksum
read
CRC on CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once a
DMA DMA channel is selected as the source, the CRC engine will continuously generate the CRC on the data
data passing through the DMA channel. The checksum is available for readout once the DMA transaction is
completed or aborted. A CRC can also be generated on SRAM, Flash, or I/O memory by passing these
data through a DMA channel. If the latter is done, the destination register for the DMA data can be the
data input (CRCDATAIN) register in the CRC engine.
CRC using the I/O Before using the CRC engine with the I/O interface, the application must set the CRC Beat
interface Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE). 8/16/32-bit bus transfer
type can be selected.
CRC can be performed on any data by loading them into the CRC engine using the CPU and writing the data to
the CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU,
and CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the
CRC engine takes four cycles to calculate the CRC. The CRC complete is signaled by a set CRCBUSY bit in the
CRCSTATUS register. New data can be written only when CRCBUSY flag is not set.
24.5.4 Interrupts
The DMAC channels have the following interrupt sources:
• Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. Refer to
24.5.2.5 Data Transmission for details.
• Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid
descriptor has been fetched. Refer to 24.5.2.8 Error Handling for details.
• Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to
24.5.3.2 Channel Suspend and 24.5.2.5 Data Transmission for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt Flag Status
and Clear (CHINTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually
enabled by setting the corresponding bit in the Channel Interrupt Enable Set register (CHINTENSET=1), and
disabled by setting the corresponding bit in the Channel Interrupt Enable Clear register (CHINTENCLR=1).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or
the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear interrupt flags. All interrupt
requests are ORed together on system level to generate one combined interrupt request to the NVIC.
The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending
interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which
interrupt condition is present for the corresponding channel. It is also possible to read the Interrupt Pending register
(INTPEND), which provides the lowest channel number with pending interrupt and the respective interrupt flags.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
24.5.5 Events
The DMAC can generate the following output events:
• Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat
transfer within a block transfer for a given channel has been completed. Refer to 28. Event System (EVSYS) for
details.
Setting the Channel Event Output Enable bit (CHEVCTRLx.EVOE = 1) enables the corresponding output event
configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL).
Clearing CHEVCTRLx.EVOE = 0 disables the corresponding output event.
The DMAC can take the following actions on an input event:
• Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled
• Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled
• Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled
• Channel Suspend Operation (SUSPEND): suspend a channel operation
• Channel Resume Operation (RESUME): resume a suspended channel operation
• Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition
• Increase Priority (INCPRI): increase channel priority
Setting the Channel Event Input Enable bit (CHEVCTRLx.EVIE = 1) enables the corresponding action on input event.
Clearing this bit disables the corresponding action on input event. Note that several actions can be enabled for
incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of the
incoming events. For further details on event input actions, refer to Event Input Actions.
Note: Event input and outputs are not available for every channel. Refer to the Features section for more
information.
...........continued
0x3C
... Reserved
0x3E
0x3F CHID 7:0 ID[3:0]
0x40 CHCTRLA 7:0 RUNSTDBY ENABLE SWRST
0x41
... Reserved
0x43
7:0 LVL[1:0] EVOE EVIE EVACT[2:0]
15:8 TRIGSRC[5:0]
0x44 CHCTRLB
23:16 TRIGACT[1:0]
31:24 CMD[1:0]
0x48
... Reserved
0x4B
0x4C CHINTENCLR 7:0 SUSP TCMPL TERR
0x4D CHINTENSET 7:0 SUSP TCMPL TERR
0x4E CHINTFLAG 7:0 SUSP TCMPL TERR
0x4F CHSTATUS 7:0 FERR BUSY PEND
24.6.1 Control
Name: CTRL
Offset: 0x00
Reset: 0x00X0
Property: PAC Write-Protection, Enable-Protected Bits
Bit 15 14 13 12 11 10 9 8
LVLEN3 LVLEN2 LVLEN1 LVLEN0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CRCENABLE DMAENABLE SWRST
Access R/W R/W R/W
Reset 0 0 0
Name: CRCCTRL
Offset: 0x02
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit 15 14 13 12 11 10 9 8
CRCSRC[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CRCPOLY[1:0] CRCBEATSIZE[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CRCDATAIN
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
CRCDATAIN[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CRCDATAIN[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CRCDATAIN[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CRCDATAIN[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CRCCHKSUM
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. The register is reset to zero
by default, but it is possible to reset all bits to one by writing the CRCCHKSUM register directly. It is possible to write
this register only when the CRC module is disabled. If CRC-32 is selected and the CRC Status Busy flag is cleared
(i.e., CRC generation is completed or aborted), the bit reversed (bit 31 is swapped with bit 0, bit 30 with bit 1, etc.)
and complemented result will be read from CRCCHKSUM. If CRC-16 is selected or the CRC Status Busy flag is set
(i.e., CRC generation is ongoing), CRCCHKSUM will contain the actual content.
Bit 31 30 29 28 27 26 25 24
CRCCHKSUM[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CRCCHKSUM[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CRCCHKSUM[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CRCCHKSUM[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CRCSTATUS
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
CRCZERO CRCBUSY
Access R R/W
Reset 0 0
Name: DBGCTRL
Offset: 0x0D
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: QOSCTRL
Offset: 0x0E
Reset: 0x2A
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DQOS[1:0] FQOS[1:0] WRBQOS[1:0]
Access R/W R/W R/W R/W R/W R/W
Reset 1 0 1 0 1 0
Name: SWTRIGCTRL
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
SWTRIG11 SWTRIG10 SWTRIG9 SWTRIG8
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SWTRIG7 SWTRIG6 SWTRIG5 SWTRIG4 SWTRIG3 SWTRIG2 SWTRIG1 SWTRIG0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PRICTRL0
Offset: 0x14
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
RRLVLEN3 LVLPRI3[3:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
RRLVLEN2 LVLPRI2[3:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RRLVLEN1 LVLPRI1[3:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RRLVLEN0 LVLPRI0[3:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTPEND
Offset: 0x20
Reset: 0x0000
Property: -
This register allows the user to identify the lowest DMA channel with pending interrupt.
Bit 15 14 13 12 11 10 9 8
PEND BUSY FERR SUSP TCMPL TERR
Access R R R R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ID[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 – PEND Pending
This bit will read '1' when the channel selected by Channel ID field (ID) is pending.
Bit 14 – BUSY Busy
This bit will read '1' when the channel selected by Channel ID field (ID) is busy.
Name: INTSTATUS
Offset: 0x24
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
CHINT11 CHINT10 CHINT9 CHINT8
Access R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CHINT7 CHINT6 CHINT5 CHINT4 CHINT3 CHINT2 CHINT1 CHINT0
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: BUSYCH
Offset: 0x28
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
BUSYCH11 BUSYCH10 BUSYCH9 BUSYCH8
Access R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
BUSYCH7 BUSYCH6 BUSYCH5 BUSYCH4 BUSYCH3 BUSYCH2 BUSYCH1 BUSYCH0
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: PENDCH
Offset: 0x2C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
PENDCH11 PENDCH10 PENDCH9 PENDCH8
Access R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: ACTIVE
Offset: 0x30
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
BTCNT[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
BTCNT[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
ABUSY ID[4:0]
Access R R R R R R
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
LVLEX3 LVLEX2 LVLEX1 LVLEX0
Access R R R R
Reset 0 0 0 0
Name: BASEADDR
Offset: 0x34
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
BASEADDR[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
BASEADDR[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
BASEADDR[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
BASEADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: WRBADDR
Offset: 0x38
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
WRBADDR[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
WRBADDR[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
WRBADDR[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WRBADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
24.6.17 Channel ID
Name: CHID
Offset: 0x3F
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ID[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: CHCTRLA
Offset: 0x40
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected Bits
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit 7 6 5 4 3 2 1 0
RUNSTDBY ENABLE SWRST
Access R R/W R R R R R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CHCTRLB
Offset: 0x44
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit 31 30 29 28 27 26 25 24
CMD[1:0]
Access R/W R/W
Reset 0 0
Bit 23 22 21 20 19 18 17 16
TRIGACT[1:0]
Access R/W R/W
Reset 0 0
Bit 15 14 13 12 11 10 9 8
TRIGSRC[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
LVL[1:0] EVOE EVIE EVACT[2:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Name: CHINTENCLR
Offset: 0x4C
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register.
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit 7 6 5 4 3 2 1 0
SUSP TCMPL TERR
Access R/W R/W R/W
Reset 0 0 0
Name: CHINTENSET
Offset: 0x4D
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register.
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit 7 6 5 4 3 2 1 0
SUSP TCMPL TERR
Access R/W R/W R/W
Reset 0 0 0
Name: CHINTFLAG
Offset: 0x4E
Reset: 0x00
Property: -
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit 7 6 5 4 3 2 1 0
SUSP TCMPL TERR
Access R/W R/W R/W
Reset 0 0 0
Name: CHSTATUS
Offset: 0x4F
Reset: 0x00
Property: -
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit 7 6 5 4 3 2 1 0
FERR BUSY PEND
Access R R R
Reset 0 0 0
Name: BTCTRL
Offset: 0x00
Property: -
The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit 15 14 13 12 11 10 9 8
STEPSIZE[2:0] STEPSEL DSTINC SRCINC BEATSIZE[1:0]
Access
Reset
Bit 7 6 5 4 3 2 1 0
BLOCKACT[1:0] EVOSEL[1:0] VALID
Access
Reset
Name: BTCNT
Offset: 0x02
Property: -
The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit 15 14 13 12 11 10 9 8
BTCNT[15:8]
Access
Reset
Bit 7 6 5 4 3 2 1 0
BTCNT[7:0]
Access
Reset
Name: SRCADDR
Offset: 0x04
Property: -
The SRCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit 31 30 29 28 27 26 25 24
SRCADDR[31:24]
Access
Reset
Bit 23 22 21 20 19 18 17 16
SRCADDR[23:16]
Access
Reset
Bit 15 14 13 12 11 10 9 8
SRCADDR[15:8]
Access
Reset
Bit 7 6 5 4 3 2 1 0
SRCADDR[7:0]
Access
Reset
Name: DSTADDR
Offset: 0x08
Property: -
The DSTADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit 31 30 29 28 27 26 25 24
DSTADDR[31:24]
Access
Reset
Bit 23 22 21 20 19 18 17 16
DSTADDR[23:16]
Access
Reset
Bit 15 14 13 12 11 10 9 8
DSTADDR[15:8]
Access
Reset
Bit 7 6 5 4 3 2 1 0
DSTADDR[7:0]
Access
Reset
Name: DESCADDR
Offset: 0x0C
Property: -
The DESCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit 31 30 29 28 27 26 25 24
DESCADDR[31:24]
Access
Reset
Bit 23 22 21 20 19 18 17 16
DESCADDR[23:16]
Access
Reset
Bit 15 14 13 12 11 10 9 8
DESCADDR[15:8]
Access
Reset
Bit 7 6 5 4 3 2 1 0
DESCADDR[7:0]
Access
Reset
25.1 Overview
The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can
be individually masked and can generate an interrupt on rising, falling, or both edges, or on high or low levels. Each
external pin has a configurable filter to remove spikes. Each external pin can also be configured to be asynchronous
in order to wake up the device from sleep modes where all clocks have been disabled. External pins can also
generate an event.
A separate non-maskable interrupt (NMI) is also supported. It has properties similar to the other external interrupts,
but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode.
25.2 Features
• Up to 16 external pins (EXTINTx), plus one non-maskable pin (NMI)
• Dedicated, individually maskable interrupt for each pin
• Interrupt on rising, falling, or both edges
• Synchronous or asynchronous edge detection mode
• Interrupt pin debouncing
• Interrupt on high or low levels
• Asynchronous interrupts for sleep modes without clock
• Filtering of external pins
• Event generation from EXTINTx
FILTENx SENSEx[2:0]
intreq_extint
Interrupt
EXTINTx
inwake_extint
Edge/Level
Filter Wake
Detection
evt_extint
Event
NMIFILTEN NMISENSE[2:0]
intreq_nmi
Interrupt
NMI
Edge/Level
Filter
Detection
inwake_nmi
Wake
...........continued
Signal Name Type Description
NMI Digital Input Non-maskable interrupt pin
14-29:
EIC 0x40002800 3, NMI - Y 2 10 N - - Y
EXTINT0-15
25.6.2.1 Initialization
The EIC must be initialized in the following order:
1. Enable CLK_EIC_APB
2. If required, configure the NMI by writing the Non-Maskable Interrupt Control register (NMICTRL)
3. Enable GCLK_EIC or CLK_ULP32K when one of the following configuration is selected:
– The NMI uses edge detection or filtering.
– One or more EXTINT uses filtering.
– One or more EXTINT uses edge detection.
– One or more EXTINT uses debouncing.
GCLK_EIC is used when a frequency higher than 32.768 kHz is required for filtering.
CLK_ULP32K is recommended when power consumption is the priority. For CLK_ULP32K write a '1' to the
Clock Selection bit in the Control A register (CTRLA.CKSEL).
4. Configure the EIC input sense and filtering by writing the configuration register (CONFIG0 or CONFIG1).
5. Optionally, enable the asynchronous mode.
6. Optionally, enable the debouncer mode.
7. Enable the EIC by writing a ‘1’ to CTRLA.ENABLE.
The following bits are enable-protected, meaning that it can only be written when the EIC is disabled
(CTRLA.ENABLE=0):
• Clock Selection bit in Control A register (CTRLA.CKSEL)
The following registers are enable-protected:
• Event Control register (EVCTRL)
• Configuration register (CONFIGn).
• External Interrupt Asynchronous Mode register (25.7.9 ASYNCH)
• Debouncer Enable register (DEBOUNCEN)
When an external interrupt is configured for level detection and when filtering is disabled, detection is done
asynchronously. Level detection and asynchronous edge detection do not require GCLK_EIC or CLK_ULP32K and
can generate asynchronous interrupts and events.
If filtering, synchronous edge detection, or debouncing is enabled, the EIC automatically requests GCLK_EIC or
CLK_ULP32K to operate. The selection between these two clocks is done by writing the Clock Selection bits in the
Control A register (CTRLA.CKSEL). GCLK_EIC must be enabled in the GCLK module. In these modes the external
pin is sampled at the EIC clock rate, thus pulses with duration lower than two EIC clock periods may not be properly
detected.
CLK_EIC_APB
EXTINTx
intreq_extint[x]
(level detection / no filter)
intreq_extint[x] No interrupt
(level detection / filter)
intreq_extint[x]
(edge detection / no filter)
intreq_extint[x] No interrupt
(edge detection / filter)
clear INTFLAG.EXTINT[x]
Subsequent asynchronous edges will not generate events until Standby sleep mode is exited. Synchronous edge
detection will not exhibit this behavior.
25.6.5 Interrupts
The EIC has the following interrupt sources:
• External interrupt pins (EXTINTx). See 25.6.2 Basic Operation.
• Non-maskable interrupt pin (NMI). See 25.6.4 Additional Features.
Each interrupt source has an associated interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when an interrupt condition occurs (NMIFLAG for NMI). Each interrupt, except NMI, can
be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and
disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1). As both INTENSET
and INTENCLR always reflect the same value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the EIC is reset. See the
INTFLAG register for details on how to clear interrupt flags. The EIC has one interrupt request line for each external
interrupt (EXTINTx) and one line for NMI. The user must read the INTFLAG (or NMIFLAG) register to determine
which interrupt condition is present.
Notes:
1. Interrupts must be globally enabled for interrupt requests to be generated.
2. If an external interrupt (EXTINT) is common on two or more I/O pins, only one will be active (the first one
programmed).
25.6.6 Events
The EIC can generate the following output events:
• External event from pin (EXTINTx).
Setting an Event Output Control register (EVCTRL.EXTINTEO) enables the corresponding output event. Clearing this
bit disables the corresponding output event. Refer to Event System for details on configuring the Event System.
When the condition on pin EXTINTx matches the configuration in the CONFIGn.SENSEx bit field, the corresponding
event is generated, if enabled.
EXTINTx
intwake_extint[x]
intreq_extint[x]
25.6.8 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in control register (CTRLA.SWRST)
• Enable bit in control register (CTRLA.ENABLE)
25.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized Bits
Bit 7 6 5 4 3 2 1 0
CKSEL ENABLE SWRST
Access RW RW W
Reset 0 0 0
Bit 1 – ENABLE Enable
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
Value Description
0 The EIC is disabled.
1 The EIC is enabled.
Name: NMICTRL
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
NMIASYNCH NMIFILTEN NMISENSE[2:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: NMIFLAG
Offset: 0x02
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
NMI
Access RW
Reset 0
Name: SYNCBUSY
Offset: 0x04
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ENABLE SWRST
Access R R
Reset 0 0
Name: EVCTRL
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
EXTINTEO15 EXTINTEO14 EXTINTEO13 EXTINTEO12 EXTINTEO11 EXTINTEO10 EXTINTEO9 EXTINTEO8
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EXTINTEO7 EXTINTEO6 EXTINTEO5 EXTINTEO4 EXTINTEO3 EXTINTEO2 EXTINTEO1 EXTINTEO0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTEOx External Interrupt Event Output Enable [x = 15..0]
The bit x of EXTINTEO enables the event associated with the EXTINTx pin.
Value Description
0 Event from pin EXTINTx is disabled.
1 Event from pin EXTINTx is enabled and will be generated when EXTINTx pin matches the external
interrupt sensing configuration.
Name: INTENCLR
Offset: 0x0C
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTx External Interrupt Enable [x = 15..0]
The bit x of EXTINT disables the interrupt associated with the EXTINTx pin.
Writing a '0' to bit x has no effect.
Writing a '1' to bit x will clear the External Interrupt Enable bit x, which disables the external interrupt EXTINTx.
Value Description
0 The external interrupt x is disabled.
1 The external interrupt x is enabled.
Name: INTENSET
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTx External Interrupt Enable [x = 15..0]
The bit x of EXTINT enables the interrupt associated with the EXTINTx pin.
Writing a '0' to bit x has no effect.
Writing a '1' to bit x will set the External Interrupt Enable bit x, which enables the external interrupt EXTINTx.
Value Description
0 The external interrupt x is disabled.
1 The external interrupt x is enabled.
Name: INTFLAG
Offset: 0x14
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
EXTINT15 EXTINT14 EXTINT13 EXTINT12 EXTINT11 EXTINT10 EXTINT9 EXTINT8
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EXTINT7 EXTINT6 EXTINT5 EXTINT4 EXTINT3 EXTINT2 EXTINT1 EXTINT0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: ASYNCH
Offset: 0x18
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
ASYNCH15 ASYNCH14 ASYNCH13 ASYNCH12 ASYNCH11 ASYNCH10 ASYNCH9 ASYNCH8
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ASYNCH7 ASYNCH6 ASYNCH5 ASYNCH4 ASYNCH3 ASYNCH2 ASYNCH1 ASYNCH0
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – ASYNCH Asynchronous Edge Detection Mode [x = 15..0]
The bit x of ASYNCH set the Asynchronous Edge Detection Mode for the interrupt associated with the EXTINTx pin.
Value Description
0 The EXTINT x edge detection is synchronously operated.
1 The EXTINT x edge detection is asynchronously operated.
Name: CONFIGn
Offset: 0x1C + n*0x04 [n=0..1]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
FILTEN7 SENSE7[2:0] FILTEN6 SENSE6[2:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
FILTEN5 SENSE5[2:0] FILTEN4 SENSE4[2:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
FILTEN3 SENSE3[2:0] FILTEN2 SENSE2[2:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FILTEN1 SENSE1[2:0] FILTEN0 SENSE0[2:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bits 0:2, 4:6, 8:10, 12:14, 16:18, 20:22, 24:26, 28:30 – SENSEx Input Sense Configuration x [x = 7..0]
These bits define on which edge or level the interrupt or event for EXTINT[n*8+x] will be generated.
Value Name Description
0x0 NONE No detection
0x1 RISE Rising-edge detection
0x2 FALL Falling-edge detection
0x3 BOTH Both-edge detection
0x4 HIGH High-level detection
0x5 LOW Low-level detection
0x6 - - Reserved
0x7
26.1 Overview
Nonvolatile Memory (NVM) is a reprogrammable Flash memory that retains program and data storage even with
power off. It embeds a main array and a separate smaller Data Flash array, which can be programmed while reading
the main array. A size-configurable section at the beginning of the main array can be configured as write protected,
thus providing an immutable boot section. The NVM Controller (NVMCTRL) connects to the AHB and APB bus
interfaces for system access to the NVM block. The AHB interface is used for reads and writes to the NVM block,
while the APB interface is used for commands and configuration.
26.2 Features
• 32-bit AHB interface for reads and writes
• Data Flash
• All NVM sections are memory mapped to the AHB, including calibration and system configuration
• 32-bit APB interface for commands and control
• Programmable wait states
• 16 regions can be individually protected or unprotected against erase and writes
• Additional protection for bootloader against erase and writes
• Supports device protection through a security bit
• Supports permanent disabling of the Chip-Erase feature
• Interface to Power Manager for power-down of Flash blocks in sleep modes
• Can optionally wake up on exit from sleep or on first access
• Direct-mapped cache for the main array and the Data Flash section
NVM Block
NVMCTRL
Calibration and
NVM Interface
NVMCTRL 0x41004000 6 Y Y - 2 N - - - Y
26.5.1.1 Initialization
After power up, the NVM Controller goes through a power-up sequence. During this time, access to the NVM
Controller from the AHB bus is halted. Upon power-up completion, the NVM Controller is operational without any
need for user configuration.
The NVM block contains a calibration and auxiliary space, a Data Flash section, and a main array that is memory
mapped. Refer to the NVM Organization figure below for details.
The calibration and auxiliary space contains factory calibration and system configuration information. These spaces
can be read from the AHB bus in the same way as the main NVM main address space.
In addition, the lower rows in the NVM main address space can be allocated as a boot loader section. Its size is
configured thanks to the BOOTPROT fuses (refer to Table 26-2) in the user row. Once BOOTPROT is defined and
after the next reboot, the content of the section becomes write-protected from the debugger or the processor write
accesses.
0x0080A100
Calibration and
Auxillary Space
0x00800000
NVM Main
Address Space
0x00000000 + BOOTPROT Size
0x00000000
To temporarily lock or unlock a region, the Lock Region and Unlock Region commands are provided. Writing one of
these commands will temporarily lock/unlock the region containing the address loaded in the ADDR register. ADDR
can be written by software, or the automatically loaded value from a write operation can be used. The new setting will
stay in effect until the next Reset, or until the setting is changed again using the Lock and Unlock commands. The
current status of the lock can be determined by reading the LOCK register.
To change the default lock/unlock setting for a region, the user configuration section of the auxiliary space must be
written using the Write Auxiliary Page command. Writing to the auxiliary space will take effect after the next Reset.
Therefore, a boot of the device is needed for changes in the lock/unlock setting to take effect. Refer to the Physical
Memory Map for calibration and auxiliary space address mapping.
Notes:
1. The Data Flash is outside of the regions lock bits range, and consequently cannot be write protected.
2. The boot loader section is write protected by the BOOTPROT fuse and by the lock bit(s) corresponding to its
address space.
the Data Flash address space directly, while other operations such as manual page writes and row erases must be
performed by issuing commands through the NVM Controller.
To issue a command, the CTRLA.CMD bits must be written along with the CTRLA.CMDEX value. When a command
is issued, INTFLAG.READY will be cleared until the command has completed. Any commands written while
INTFLAG.READY is low will be ignored. Before entering any sleep mode, ensure any commands written to the
NVM controller have completed by confirming the INTFLAG.READY is '1'.
The CTRLB register must be used to control the power reduction mode, read wait states, and write mode.
1 Wait States
Data to be written to the NVM block are first written to and stored in an internal buffer called the page buffer. The
page buffer contains the same number of bytes as an NVM page. Writes to the page buffer must be 32 bits. 16-bit
and 8-bit writes to the page buffer are not allowed and will cause a system exception.
Internally, writes to the page buffer are on a 64-bit basis through the page buffer load data register (PBLDATA1 and
PBLDATA0). The PBLDATA register is a holding register for writes to the same 64-bit page buffer section. Data within
a 64-bit section can be written in any order. Crossing a 64-bit boundary will reset the PBLDATA register to all ones.
The following example assumes startup from reset where the current address is 0 and PBLDATA is all ones. Only 64
bits of the page buffer are written at a time, but 128 bits are shown for reference.
Sequential 32-bit Write Example:
• 32-bit 0x1 written to address 0
– Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, PBLDATA[63:32], 0x00000001}
– PBLDATA[63:0] = {PBLDATA[63:32], 0x00000001}
• 32-bit 0x2 written to address 1
– Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, 0x00000002, PBLDATA[31:0]}
– PBLDATA[63:0] = {0x00000002, PBLDATA[31:0]}
• 32-bit 0x3 written to address 2 (crosses 64-bit boundary)
– Page buffer[127:0] = 0xFFFFFFFF_00000003_00000002_00000001
– PBLDATA[63:0] = 0xFFFFFFFF_00000003
Random access writes to 32-bit words within the page buffer will overwrite the opposite word within the same 64-bit
section with ones. In the following example, notice that 0x00000001 is overwritten with 0xFFFFFFFF from the third
write due to the 64-bit boundary crossing. Only 64 bits of the page buffer are written at a time, but 128 bits are shown
for reference.
Random Access 32-bit Write Example:
• 32-bit 0x1 written to address 2
– Page buffer[127:0] = 0xFFFFFFFF_00000001_FFFFFFFF_FFFFFFFF
– PBLDATA[63:0] = 0xFFFFFFFF_00000001
• 32-bit 0x2 written to address 1
– Page buffer[127:0] = 0xFFFFFFFF_00000001_00000002_FFFFFFFF
– PBLDATA[63:0] = 0x00000002_FFFFFFFF
• 32-bit 0x3 written to address 3
– Page buffer[127:0] = 0x00000003_FFFFFFFF_00000002_FFFFFFFF
– PBLDATA[63:0] = 0x00000003_0xFFFFFFFF
Both the NVM main array and the Data Flash array share the same page buffer. Writing to the NVM block via
the AHB bus is performed by a load operation to the page buffer. For each AHB bus write, the address is stored
in the ADDR register. After the page buffer has been loaded with the required number of bytes, the page can be
written to the NVM main array or the Data Flash by setting CTRLA.CMD to 'Write Page' or 'Data Flash Write Page',
respectively, and setting the key value to CMDEX. The LOAD bit in the STATUS register indicates whether the page
buffer has been loaded or not. Before writing the page to memory, the accessed row must be erased.
Automatic page writes are enabled by writing the manual write bit to zero (CTRLB.MANW=0). This will trigger a write
operation to the page addressed by ADDR when the last location of the page is written.
Because the address is automatically stored in ADDR during the I/O bus write operation, the last given address will
be present in the ADDR register. There is no need to load the ADDR register manually, unless a different page in
memory is to be written.
Note:
1. Default value is 0x7.
26.5.7 Cache
The NVM Controller cache reduces the device power consumption and improves system performance when wait
states are required. The NVM main array and the Data Flash address spaces are cached. It is a direct-mapped cache
that implements 8 lines of 64 bits (i.e., 64 Bytes). NVM Controller cache can be enabled by writing a '0' to the Cache
Disable bit in the Control B register (CTRLB.CACHEDIS).
The cache can be configured to three different modes using the Read Mode bit group in the Control B register
(CTRLB.READMODE).
The INVALL command can be issued using the Command bits in the Control A register to invalidate all cache lines
(CTRLA.CMD = INVALL). Commands affecting NVM content automatically invalidate cache lines.
7:0 CMD[6:0]
0x00 CTRLA
15:8 CMDEX[7:0]
0x02
... Reserved
0x03
7:0 MANW RWS[3:0]
15:8 SLEEPPRM[1:0]
0x04 CTRLB
23:16 CACHEDIS[1:0] READMODE[1:0]
31:24
7:0 NVMP[7:0]
15:8 NVMP[15:8]
0x08 PARAM
23:16 DFP[3:0] PSZ[2:0]
31:24 DFP[11:4]
7:0 ERROR READY
15:8
0x0C INTENCLR
23:16
31:24
7:0 ERROR READY
15:8
0x10 INTENSET
23:16
31:24
7:0 ERROR READY
15:8
0x14 INTFLAG
23:16
31:24
7:0 NVME LOCKE PROGE LOAD PRM
0x18 STATUS
15:8 SB
0x1A
... Reserved
0x1B
7:0 ADDR[7:0]
15:8 ADDR[15:8]
0x1C ADDR
23:16 ADDR[21:16]
31:24
7:0 LOCK[7:0]
0x20 LOCK
15:8 LOCK[15:8]
0x22
... Reserved
0x27
7:0 PBLDATA[7:0]
15:8 PBLDATA[15:8]
0x28 PBLDATA0
23:16 PBLDATA[23:16]
31:24 PBLDATA[31:24]
7:0 PBLDATA[7:0]
15:8 PBLDATA[15:8]
0x2C PBLDATA1
23:16 PBLDATA[23:16]
31:24 PBLDATA[31:24]
26.6.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
CMDEX[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMD[6:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
...........continued
CMD[6:0] Group Description
Configuration
0x42 SPRM Sets the Power Reduction mode.
0x43 CPRM Clears the Power Reduction mode.
0x44 PBC Page Buffer Clear - Clears the page buffer.
0x45 SSB Set Security Bit - Sets the Security bit.
0x46 INVALL Invalidates all cache lines.
0x47-0x7E - Reserved
0x7F SCEHL Set Chip Erase Hard Lock. Sets the CEHL bit and permanently disables the
Chip-Erase feature. This command can only be issued once the Security Bit
has been set with the SSB command. Once set, it is not possible to erase it
anymore.
26.6.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000080
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
CACHEDIS[1:0] READMODE[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SLEEPPRM[1:0]
Access R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
MANW RWS[3:0]
Access R/W R/W R/W R/W R/W
Reset 1 0 0 0 0
Name: PARAM
Offset: 0x08
Reset: 0x000XXXXX
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
DFP[11:4]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DFP[3:0] PSZ[2:0]
Access R R R R R R R
Reset 0 0 0 0 x x x
Bit 15 14 13 12 11 10 9 8
NVMP[15:8]
Access R R R R R R R R
Reset x x x x x x x x
Bit 7 6 5 4 3 2 1 0
NVMP[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Name: INTENCLR
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ERROR READY
Access R/W R/W
Reset 0 0
Name: INTENSET
Offset: 0x10
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ERROR READY
Access R/W R/W
Reset 0 0
Name: INTFLAG
Offset: 0x14
Reset: 0x00
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ERROR READY
Access R/W R
Reset 0 0
Bit 1 – ERROR Error
This flag is set on the occurrence of an NVME, LOCKE or PROGE error.
This bit can be cleared by writing a '1' to its bit location.
Value Description
0 No errors have been received since the last clear.
1 At least one error has occurred since the last clear.
26.6.7 Status
Name: STATUS
Offset: 0x18
Reset: 0x0X00
Property: –
Bit 15 14 13 12 11 10 9 8
SB
Access R
Reset x
Bit 7 6 5 4 3 2 1 0
NVME LOCKE PROGE LOAD PRM
Access R/W R/W R/W R/W R
Reset 0 0 0 0 0
Important: Once set, this bit can only be cleared by a debugger chip erase.
Value Description
0 The Security bit is inactive.
1 The Security bit is active.
26.6.8 Address
Name: ADDR
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
ADDR[21:16]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
ADDR[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: LOCK
Offset: 0x20
Reset: X determined from NVM User Row
Property: –
Bit 15 14 13 12 11 10 9 8
LOCK[15:8]
Access R R R R R R R R
Reset x x x x x x x x
Bit 7 6 5 4 3 2 1 0
LOCK[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Name: PBLDATA0
Offset: 0x28
Reset: 0xFFFFFFFF
Property: -
Bit 31 30 29 28 27 26 25 24
PBLDATA[31:24]
Access R R R R R R R R
Reset 1 1 1 1 1 1 1 1
Bit 23 22 21 20 19 18 17 16
PBLDATA[23:16]
Access R R R R R R R R
Reset 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8
PBLDATA[15:8]
Access R R R R R R R R
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
PBLDATA[7:0]
Access R R R R R R R R
Reset 1 1 1 1 1 1 1 1
Name: PBLDATA1
Offset: 0x2C
Reset: 0xFFFFFFFF
Property: -
Bit 31 30 29 28 27 26 25 24
PBLDATA[31:24]
Access R R R R R R R R
Reset 1 1 1 1 1 1 1 1
Bit 23 22 21 20 19 18 17 16
PBLDATA[23:16]
Access R R R R R R R R
Reset 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8
PBLDATA[15:8]
Access R R R R R R R R
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
PBLDATA[7:0]
Access R R R R R R R R
Reset 1 1 1 1 1 1 1 1
27.1 Overview
The I/O Pin Controller (PORT) controls the I/O pins of the device. The I/O pins are organized in a series of groups,
collectively referred to as a PORT group. Each PORT group can have up to 32 pins that can be configured and
controlled individually or as a group. The number of PORT groups on a device may depend on the package/number
of pins. Each pin may either be used for general-purpose I/O under direct application control or be assigned to an
embedded device peripheral. When used for general-purpose I/O, each pin can be configured as input or output, with
highly configurable driver and pull settings.
All I/O pins have true read-modify-write functionality when used for general-purpose I/O; the direction or the output
value of one or more pins may be changed (set, reset or toggled) explicitly without unintentionally changing the state
of any other pins in the same port group by a single, atomic 8-, 16- or 32-bit write.
The PORT is connected to the high-speed bus matrix through an AHB/APB bridge. The Pin Direction, Data Output
Value and Data Input Value registers may also be accessed using the low-latency CPU local bus (IOBUS; ARM®
single-cycle I/O port).
27.2 Features
• Selectable Input and Output Configuration for Each Individual Pin
• Software-controlled Multiplexing of Peripheral Functions on I/O Pins
• Flexible Pin Configuration Through a Dedicated Pin Configuration Register
• Configurable Output Driver and Pull Settings:
– Totem-pole (push-pull)
– Pull configuration
– Driver strength
• Configurable Input Buffer and Pull Settings:
– Internal pull-up or pull-down
– Input sampling criteria
– Input buffer can be disabled if not needed for lower power consumption
– Read-Modify-Write support for output value (OUTCLR/OUTSET/OUTTGL) and pin direction (DIRCLR/
DIRSET/DIRTGL)
• Input Event:
– Up to four input event pins for each PORT group
– SET/CLEAR/TOGGLE event actions for each event input on output value of a pin
– Can be output to pin
PORT
Control
and Port Line
Bundles
Status
Pad Line
Bundles
PORTMUX
PERIPHERALS Analog Pad
Connections
Refer to the Pinout for details on the pin mapping for this peripheral. One signal can be mapped on several pins.
PORT PAD
PULLEN
PULLENx
DRIVE
DRIVEx
Pull
Resistor
OUT PG
OUTx PAD
VDD
APB Bus
OE NG
DIRx
INEN
INENx
INx IN
Q D Q D
R R
Synchronizer
Line Bundle
Periph Signal 0 0
Periph Signal 1 1
1
Peripheral Signals to
be muxed to Pad y
Periph Signal 15 15
The I/O pins of the device are controlled by PORT peripheral registers. Each port pin has a corresponding bit in the
Data Direction (DIR) and Data Output Value (OUT) registers to enable that pin as an output and to define the output
state.
The direction of each pin in a PORT group is configured by the DIR register. If a bit in DIR is set to '1', the
corresponding pin is configured as an output pin. If a bit in DIR is set to '0', the corresponding pin is configured as an
input pin.
When the direction is set as output, the corresponding bit in the OUT register will set the level of the pin. If bit y in
OUT is written to '1', pin y is driven HIGH. If bit y in OUT is written to '0', pin y is driven LOW. Pin configuration can be
set by Pin Configuration (PINCFGy) registers, with y=00, 01, ..31 representing the pin position within the group.
The Data Input Value (IN) is set as the input value of a port pin with resynchronization to the PORT clock. To reduce
power consumption, these input synchronizers can be clocked only when system requires reading the input value, as
specified in the SAMPLING field of the Control register (CTRL). The value of the pin can always be read, whether the
pin is configured as input or output. If the Input Enable bit in the Pin Configuration registers (PINCFGy.INEN) is '0',
the input value will not be sampled.
In PORT, the Peripheral Multiplexer Enable bit in the PINCFGy register (PINCFGy.PMUXEN) can be written to '1' to
enable the connection between peripheral functions and individual I/O pins. The Peripheral Multiplexing n (PMUXn)
registers select the peripheral function for the corresponding pin. This will override the connection between the PORT
and that I/O pin, and connect the selected peripheral signal to the particular I/O pin instead of the PORT line bundle.
27.6.2.1 Initialization
After reset, all standard function device I/O pads are connected to the PORT with outputs tri-stated and input buffers
disabled, even if there is no clock running.
However, specific pins, such as those used for connection to a debugger, may be configured differently, as required
by their special function.
27.6.2.2 Operation
Each I/O pin Pxy can be controlled by the registers in PORT. Each PORT group x has its own set of PORT registers,
with a base address at byte address (PORT + 0x80 * group index) (A corresponds to group index 0, B to 1, etc...).
Within that set of registers, the pin index is y, from 0 to 31.
Refer to the 4. Pinout and Packaging for details on available pin configuration and PORT groups.
The peripheral function can be selected by setting the PMUXO or PMUXE in the PMUXn register. The PMUXO/
PMUXE is at byte offset PMUX0 + (y/2). The chosen peripheral must also be configured and enabled.
DIR
OUT
IN
INEN
DIR
OUT
IN
INEN
Note: When pull is enabled, the pull value is defined by the OUT value.
DIR
OUT
IN
INEN
DIR
OUT
IN
INEN
DIR
OUT
IN
INEN
DIR
OUT
IN
INEN
27.6.4 Events
The PORT allows input events to control individual I/O pins. These input events are generated by the EVSYS module
and can originate from a different clock domain than the clock domain of the PORT module.
The PORT can perform the following actions:
• Output (OUT): I/O pin will be set when the incoming event has a high level ('1') and cleared when the incoming
event has a low-level ('0').
• Set (SET): I/O pin will be set when an incoming event is detected.
• Clear (CLR): I/O pin will be cleared when an incoming event is detected.
• Toggle (TGL): I/O pin will toggle when an incoming event is detected.
The OUTPUT event is sent to the pin without any internal latency. For SET, CLEAR and TOGGLE event actions, the
action will be executed up to three clock cycles after a rising edge.
The event actions can be configured with the Event Action m bit group in the Event Input Control
register( EVCTRL.EVACTm). Writing a '1' to a PORT Event Enable Input m of the Event Control register
(EVCTRL.PORTEIm) enables the corresponding action on input event. Writing '0' to this bit disables the
corresponding action on input event. Note that several actions can be enabled for incoming events. If several events
are connected to the peripheral, any enabled action will be taken for any of the incoming events. Refer to EVSYS –
Event System. for details on configuring the Event System.
Each event input can address one and only one I/O pin at a time. The selection of the pin is indicated by the
PORT Event Pin Identifier of the Event Input Control register (EVCTR.PIDn). On the other hand, one I/O pin can be
addressed by up to four different input events. To avoid action conflict on the output value of the register (OUT) of this
particular I/O pin, only one action is performed according to the table below.
Note that this truth table can be applied to any SET/CLR/TGL configuration from two to four active input events.
Table 27-3. Priority on Simultaneous SET/CLR/TGL Event Actions
Be careful when the event is output to pin. Due to the fact the events are received asynchronously, the I/O pin may
have unpredictable levels, depending on the timing of when the events are received. When several events are output
to the same pin, the lowest event line will get the access. All other events will be ignored.
2. APB
3. EVSYS input events, except for events with EVCTRL.EVACTx = OUT, where the output pin follows the event
input signal, independently of the OUT register value.
Note: One clock cycle latency can be observed on the APB access in case of concurrent PORT accesses.
For input events that require different actions on the same I/O pin, refer to 27.6.4 Events.
7:0 DIR[7:0]
15:8 DIR[15:8]
0x00 DIR
23:16 DIR[23:16]
31:24 DIR[31:24]
7:0 DIRCLR[7:0]
15:8 DIRCLR[15:8]
0x04 DIRCLR
23:16 DIRCLR[23:16]
31:24 DIRCLR[31:24]
7:0 DIRSET[7:0]
15:8 DIRSET[15:8]
0x08 DIRSET
23:16 DIRSET[23:16]
31:24 DIRSET[31:24]
7:0 DIRTGL[7:0]
15:8 DIRTGL[15:8]
0x0C DIRTGL
23:16 DIRTGL[23:16]
31:24 DIRTGL[31:24]
7:0 OUT[7:0]
15:8 OUT[15:8]
0x10 OUT
23:16 OUT[23:16]
31:24 OUT[31:24]
7:0 OUTCLR[7:0]
15:8 OUTCLR[15:8]
0x14 OUTCLR
23:16 OUTCLR[23:16]
31:24 OUTCLR[31:24]
7:0 OUTSET[7:0]
15:8 OUTSET[15:8]
0x18 OUTSET
23:16 OUTSET[23:16]
31:24 OUTSET[31:24]
7:0 OUTTGL[7:0]
15:8 OUTTGL[15:8]
0x1C OUTTGL
23:16 OUTTGL[23:16]
31:24 OUTTGL[31:24]
7:0 IN[7:0]
15:8 IN[15:8]
0x20 IN
23:16 IN[23:16]
31:24 IN[31:24]
7:0 SAMPLING[7:0]
15:8 SAMPLING[15:8]
0x24 CTRL
23:16 SAMPLING[23:16]
31:24 SAMPLING[31:24]
7:0 PINMASK[7:0]
15:8 PINMASK[15:8]
0x28 WRCONFIG
23:16 DRVSTR PULLEN INEN PMUXEN
31:24 HWSEL WRPINCFG WRPMUX PMUX[3:0]
7:0 PORTEI0 EVACT0[1:0] PID0[4:0]
15:8 PORTEI1 EVACT1[1:0] PID1[4:0]
0x2C EVCTRL
23:16 PORTEI2 EVACT2[1:0] PID2[4:0]
31:24 PORTEI3 EVACT3[1:0] PID3[4:0]
0x30 PMUX0 7:0 PMUXO[3:0] PMUXE[3:0]
...
0x3F PMUX15 7:0 PMUXO[3:0] PMUXE[3:0]
0x40 PINCFG0 7:0 DRVSTR PULLEN INEN PMUXEN
...........continued
...
0x5F PINCFG31 7:0 DRVSTR PULLEN INEN PMUXEN
Name: DIR
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to configure one or more I/O pins as an input or output. This register can be manipulated
without doing a read-modify-write operation by using the Data Direction Toggle (DIRTGL), Data Direction Clear
(DIRCLR) and Data Direction Set (DIRSET) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit 31 30 29 28 27 26 25 24
DIR[31:24]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIR[23:16]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DIR[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DIR[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: DIRCLR
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation.
Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data
Direction Set (DIRSET) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit 31 30 29 28 27 26 25 24
DIRCLR[31:24]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIRCLR[23:16]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DIRCLR[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DIRCLR[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: DIRSET
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write operation.
Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data
Direction Clear (DIRCLR) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit 31 30 29 28 27 26 25 24
DIRSET[31:24]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIRSET[23:16]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DIRSET[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DIRSET[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: DIRTGL
Offset: 0x0C
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Set (DIRSET) and
Data Direction Clear (DIRCLR) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit 31 30 29 28 27 26 25 24
DIRTGL[31:24]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIRTGL[23:16]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DIRTGL[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DIRTGL[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: OUT
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection
This register sets the data output drive value for the individual I/O pins in the PORT.
This register can be manipulated without doing a read-modify-write operation by using the Data Output Value Clear
(OUTCLR), Data Output Value Set (OUTSET), and Data Output Value Toggle (OUTTGL) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit 31 30 29 28 27 26 25 24
OUT[31:24]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
OUT[23:16]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
OUT[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OUT[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: OUTCLR
Offset: 0x14
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to set one or more output I/O pin drive levels low, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle
(OUTTGL) and Data Output Value Set (OUTSET) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit 31 30 29 28 27 26 25 24
OUTCLR[31:24]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
OUTCLR[23:16]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
OUTCLR[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OUTCLR[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: OUTSET
Offset: 0x18
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to set one or more output I/O pin drive levels high, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle
(OUTTGL) and Data Output Value Clear (OUTCLR) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit 31 30 29 28 27 26 25 24
OUTSET[31:24]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
OUTSET[23:16]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
OUTSET[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OUTSET[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: OUTTGL
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to toggle the drive level of one or more output I/O pins, without doing a read-modify-write
operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Set
(OUTSET) and Data Output Value Clear (OUTCLR) registers.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit 31 30 29 28 27 26 25 24
OUTTGL[31:24]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
OUTTGL[23:16]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
OUTTGL[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OUTTGL[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: IN
Offset: 0x20
Reset: 0x00000000
Property: -
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit 31 30 29 28 27 26 25 24
IN[31:24]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
IN[23:16]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
IN[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
IN[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
27.7.10 Control
Name: CTRL
Offset: 0x24
Reset: 0x00000000
Property: PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
Bit 31 30 29 28 27 26 25 24
SAMPLING[31:24]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
SAMPLING[23:16]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SAMPLING[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SAMPLING[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: WRCONFIG
Offset: 0x28
Reset: 0x00000000
Property: PAC Write-Protection, Write-Only
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
This write-only register is used to configure several pins simultaneously with the same configuration and peripheral
multiplexing.
In order to avoid side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading
this register always returns zero.
Bit 31 30 29 28 27 26 25 24
HWSEL WRPINCFG WRPMUX PMUX[3:0]
Access W W W W W W W
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DRVSTR PULLEN INEN PMUXEN
Access W W W W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
PINMASK[15:8]
Access W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PINMASK[7:0]
Access W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Value Description
1 The PINCFGy registers of the selected pins will be updated.
Name: EVCTRL
Offset: 0x2C
Reset: 0x00000000
Property: PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
There are up to four input event pins for each PORT group. Each byte of this register addresses one Event input pin.
Bit 31 30 29 28 27 26 25 24
PORTEI3 EVACT3[1:0] PID3[4:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
PORTEI2 EVACT2[1:0] PID2[4:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
PORTEI1 EVACT1[1:0] PID1[4:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PORTEI0 EVACT0[1:0] PID0[4:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bits 0:4, 8:12, 16:20, 24:28 – PIDx PORT Event Pin Identifier x [x = 3..0]
These bits define the I/O pin on which the event action will be performed, according to Table 27-5.
Table 27-4. PORT Event x Action ( x = [3..0] )
Name: PMUX
Offset: 0x30 + n*0x01 [n=0..15]
Reset: 0x00 except group 0 PMUX15 = 0x06
Property: PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
There are up to 16 Peripheral Multiplexing registers in each group, one for every set of two subsequent I/O lines. The
n denotes the number of the set of I/O lines.
Bit 7 6 5 4 3 2 1 0
PMUXO[3:0] PMUXE[3:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
...........continued
PMUXE[3:0] Name Description
0x9 J Peripheral function J selected
0xA-0xF - Reserved
Name: PINCFG
Offset: 0x40 + n*0x01 [n=0..31]
Reset: 0x00
Property: PAC Write-Protection
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists
of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0
(PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is
0x80.
There are up to 32 Pin Configuration registers in each PORT group, one for each I/O line.
Bit 7 6 5 4 3 2 1 0
DRVSTR PULLEN INEN PMUXEN
Access RW RW RW RW
Reset 0 0 0 0
28.1 Overview
The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals.
Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition
to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that
respond to events are called event users. Peripherals that generate events are called event generators. A peripheral
can have one or more event generators and can have one or more event users.
Communication is made without CPU intervention and without consuming system resources such as bus or SRAM
bandwidth. This reduces the load on the CPU and other system resources, compared to a traditional interrupt-based
system.
28.2 Features
• 12 configurable event channels, where each channel can:
– Be connected to any event generator
– Provide a pure asynchronous, resynchronized or synchronous path
• 88 event generators
• 47 event users
• Configurable edge detector
• Peripherals can be event generators, event users, or both
• SleepWalking and interrupt for operation in sleep modes
• Software event generation
• Each event user can choose which channel to respond to
Event Channel m
Event Channel 1 USER x+1
CHANNEL0.PATH
R R R
GCLK_EVSYS_0
28.5.3 Interrupts
The EVSYS has the following interrupt sources:
• Overrun Channel n interrupt (OVRn): for details, refer to 28.5.2.9 The Overrun Channel n Interrupt.
• Event Detected Channel n interrupt (EVDn): for details, refer to 28.5.2.10 The Event Detected Channel n
Interrupt.
These interrupts events are asynchronous wake-up sources. Refer to 16.5.3.3 Sleep Mode Controller. Each interrupt
source has an interrupt flag which is in the Interrupt Flag Status and Clear (INTFLAG) register. The flag is set
when the interrupt is issued. Each interrupt event can be individually enabled by setting a ‘1’ to the corresponding
bit in the Interrupt Enable Set (INTENSET) register, and disabled by setting a ‘1’ to the corresponding bit in the
Interrupt Enable Clear (INTENCLR) register. An interrupt event is generated when the interrupt flag is set and the
corresponding interrupt is enabled. The interrupt event is active until the interrupt flag is cleared, the interrupt is
disabled, or the Event System is reset. See 28.6.5 INTFLAG for details on how to clear interrupt flags.
All interrupt events from the peripheral are ORed together on system level to generate one combined interrupt
request to the NVIC. Refer to the 9.2 Nested Vector Interrupt Controller for details. The event user must read the
INTFLAG register to determine what the interrupt condition is.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
28.6.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
SWRST
Access W
Reset 0
Name: CHSTATUS
Offset: 0x0C
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
CHBUSY11 CHBUSY10 CHBUSY9 CHBUSY8
Access R R R R
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY4 CHBUSY3 CHBUSY2 CHBUSY1 CHBUSY0
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
USRRDY11 USRRDY10 USRRDY9 USRRDY8
Access R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 – CHBUSYx Channel Busy x [x = 11..0]
This bit is cleared when channel x is idle.
This bit is set if an event on channel x has not been handled by all event users connected to channel x.
Name: INTENCLR
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 31 30 29 28 27 26 25 24
EVD11 EVD10 EVD9 EVD8
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
OVR11 OVR10 OVR9 OVR8
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 – EVDx Event Detected Channel x Interrupt Enable [x = 11..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Event Detected Channel x Interrupt Enable bit, which disables the Event Detected
Channel x interrupt.
Value Description
0 The Event Detected Channel x interrupt is disabled.
1 The Event Detected Channel x interrupt is enabled.
Name: INTENSET
Offset: 0x14
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 31 30 29 28 27 26 25 24
EVD11 EVD10 EVD9 EVD8
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
OVR11 OVR10 OVR9 OVR8
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 – EVDx Event Detected Channel x Interrupt Enable [x = 11..0]
Writing '0' to this bit has no effect.
Writing '1' to this bit will set the Event Detected Channel x Interrupt Enable bit, which enables the Event Detected
Channel x interrupt.
Value Description
0 The Event Detected Channel x interrupt is disabled.
1 The Event Detected Channel x interrupt is enabled.
Name: INTFLAG
Offset: 0x18
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
EVD11 EVD10 EVD9 EVD8
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
OVR11 OVR10 OVR9 OVR8
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 – EVDx Event Detected Channel x [x = 11..0]
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an
interrupt request will be generated if INTENCLR/SET.EVDx is '1'.
When the event channel path is asynchronous, the EVDx interrupt flag will not be set.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Event Detected Channel x interrupt flag.
Name: SWEVT
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
CHANNEL11 CHANNEL10 CHANNEL9 CHANNEL8
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CHANNEL7 CHANNEL6 CHANNEL5 CHANNEL4 CHANNEL3 CHANNEL2 CHANNEL1 CHANNEL0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CHANNELn
Offset: 0x20 + n*0x04 [n=0..11]
Reset: 0x00008000
Property: PAC Write-Protection
This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the
configuration data.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
ONDEMAND RUNSTDBY EDGSEL[1:0] PATH[1:0]
Access R/W R/W R/W R/W R/W R/W
Reset 1 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EVGEN[6:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
...........continued
Value Event Generator Description
0x2F TCC2 OVF Overflow
0x30 TCC2 TRG Trig
0x31 TCC2 CNT Counter
0x32 TCC2 MC0 Match/Capture 0
0x33 TCC2 MC1 Match/Capture 1
0x34 TC0 OVF Overflow/Underflow
0x35 TC0 MC0 Match/Capture 0
0x36 TC0 MC1 Match/Capture 1
0x37 TC1 OVF Overflow/Underflow
0x38 TC1 MC0 Match/Capture 0
0x39 TC1 MC1 Match/Capture 1
0x3A TC2 OVF Overflow/Underflow
0x3B TC2 MC1 Match/Capture 0
0x3C TC2 MC0 Match/Capture 1
0x3D TC3 OVF Overflow/Underflow
0x3E TC3 MC0 Match/Capture 0
0x3F TC3 MC1 Match/Capture 1
0x40 TC4 OVF Overflow/Underflow
0x41 TC4 MC0 Match/Capture 0
0x42 TC4 MC1 Match/Capture 1
0x43 ADC0 RESRDY Result Ready
0x44 ADC0 WINMON Window Monitor
0x45 ADC1 RESRDY Result Ready
0x46 ADC1 WINMON Window Monitor
0x47 SDADC RESRDY Result Ready
0x48 SDADC WINMON Window Monitor
0x49 AC COMP0 Comparator 0
0x4A AC COMP1 Comparator 1
0x4B AC WIN0 Window 0
0x4C DAC EMPTY Data Buffer Empty
0x4D CCL LUTOUT0 CCL output
0x4E CCL LUTOUT1 CCL output
0x4F CCL LUTOUT2 CCL output
0x50 CCL LUTOUT3 CCL output
0x51 PAC ACCERR Access Error
0x52 - Reserved
0x53 PDEC_OVF PDEC Overflow
0x54 PDEC_ERR PDEC Error
0x55 PDEC_DIR PDEC Direction
0x56 PDEC_VLC PDEC VLC
0x57 PDEC_MC0 PDEC MC0
0x58 PDEC_MC1 PDEC MC1
0x59-0x7 Reserved Reserved
F
Name: USERm
Offset: 0x80 + m*0x04 [m=0..46]
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CHANNEL[4:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
...........continued
USERm User Multiplexer Description Path Type
m=6 DMAC CH1 Channel 1 Asynchronous, synchronous, and resynchronized paths
m=7 DMAC CH2 Channel 2 Asynchronous, synchronous, and resynchronized paths
m=8 DMAC CH3 Channel 3 Asynchronous, synchronous, and resynchronized paths
m=9 TCC0 EV0 Input Event 0 Asynchronous path only
m = 10 TCC0 EV1 Input Event 1 Asynchronous path only
m = 11 TCC0 MC0 Match/Capture 0 Asynchronous path only
m = 12 TCC0 MC1 Match/Capture 1 Asynchronous path only
m = 13 TCC0 MC2 Match/Capture 2 Asynchronous path only
m = 14 TCC0 MC3 Match/Capture 3 Asynchronous path only
m = 15 TCC1 EV0 Input Event 0 Asynchronous path only
m = 16 TCC1 EV1 Input Event 1 Asynchronous path only
m = 17 TCC1 MC0 Match/Capture 0 Asynchronous path only
m = 18 TCC1 MC1 Match/Capture 1 Asynchronous path only
m = 19 TCC2 EV0 Input Event 0 Asynchronous path only
m = 20 TCC2 EV1 Input Event 1 Asynchronous path only
m = 21 TCC2 MC0 Match/Capture 0 Asynchronous path only
m = 22 TCC2 MC1 Match/Capture 1 Asynchronous path only
m = 23 TC0EV Input Event Asynchronous path only, synchronous, and resynchronized
paths
m = 24 TC1EV Input Event Asynchronous, synchronous, and resynchronized paths
m = 25 TC2EV Input Event Asynchronous, synchronous, and resynchronized paths
m = 26 TC3EV Input Event Asynchronous, synchronous, and resynchronized paths
m = 27 TC4EV Input Event Asynchronous, synchronous, and resynchronized paths
m = 28 ADC0 START ADC start conversion Asynchronous path only
m = 29 ADC0 FLUSH Flush ADC Asynchronous path only
m = 30 ADC1 START ADC start conversion Asynchronous path only
m = 31 ADC1 FLUSH Flush ADC Asynchronous path only
m = 32 SDADC START ADC start Asynchronous path only
m = 33 SDADC FLUSH Flush ADC Asynchronous path only
m = 34 AC COMP0 Start comparator 0 Asynchronous path only
m = 35 AC COMP1 Start comparator 1 Asynchronous path only
m = 36 DAC START DAC start conversion Asynchronous path only
m = 37 CCL LUTIN 0 CCL input Asynchronous path only
m = 38 CCL LUTIN 1 CCL input Asynchronous path only
m = 39 CCL LUTIN 2 CCL input Asynchronous path only
m = 40 CCL LUTIN 3 CCL input Asynchronous path only
m = 41 Reserved - Reserved
m = 42 MTB START Micro Trace Buffer Start Asynchronous path only
m = 43 MTB STOP Micro Trace Buffer Stop Asynchronous path only
m = 44 PDEC EVU0 QDEC_EV0 Asynchronous path only
m = 45 PDEC EVU1 QDEC_EV1 Asynchronous path only
m = 46 PDEC EVU2 QDEC_EV2 Asynchronous path only
29.1 Overview
There are up to four instances of the serial communication interface (SERCOM) peripheral.
A SERCOM can be configured to support a number of modes: I2C, SPI, and USART. When an instance of SERCOM
is configured and enabled, all of the resources of that SERCOM instance will be dedicated to the selected mode.
The SERCOM serial engine consists of a transmitter and receiver, baud-rate generator and address matching
functionality. It can use the internal generic clock or an external clock. Using an external clock allows the SERCOM to
be operated in all Sleep modes.
29.2 Features
• Interface for configuring into one of the following:
– Inter-Integrated Circuit (I2C) Two-wire Serial Interface
– System Management Bus (SMBus™) compatible
– Serial Peripheral Interface (SPI)
– Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
• Single transmit buffer and double receive buffer
• Baud-rate generator
• Address match/mask logic
• Operational in all Sleep modes with an external clock source
• Can be used with DMA
For further information, see the following chapters:
• SERCOM SPI
• SERCOM USART
• SERCOM I2C
SERCOM
Register Interface
Mode n
Baud Rate
Mode 1 Transmitter Generator
PAD[3:0]
Mode 0
Receiver Address
Match
19: CORE 2: RX
SERCOM0 0x42000400 9 - N 1 N - - Y
18: SLOW 3: TX
20: CORE 4: RX
SERCOM1 0x42000800 10 - N 2 N - - Y
18: SLOW 5: TX
21: CORE 6: RX
SERCOM2 0x42000C00 11 - N 3 N - - Y
18: SLOW 7: TX
TX Shift Register
Receiver
RX Shift Register
Equal
Status RX Buffer
29.6.2.1 Initialization
The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control A register
(CTRLA.MODE). Refer to table SERCOM Modes for details.
Table 29-1. SERCOM Modes
CTRLA.MODE Description
0x0 USART with external clock
0x1 USART with internal clock
0x2 SPI in client operation
0x3 SPI in host operation
0x4 I2C client operation
0x5 I2C host operation
0x6-0x7 Reserved
For further initialization information, see the respective SERCOM mode chapters:
• SERCOM SPI
• SERCOM USART
• SERCOM I2C
CTRLA.MODE[0] /1 /2 /16
0 Tx Clk
1 CTRLA.MODE
1 Rx Clk
Clock
0
Recovery
Table 29-2 contains equations for the baud rate (in bits per second) and the BAUD register value for each operating
mode.
For asynchronous operation, the BAUD register value is 16 bits (0 to 65,535).
For synchronous operation, the BAUD register value is 8 bits (0 to 255).
Table 29-2. Baud Rate Equations
Operating Mode Condition Baud Rate (Bits Per Second) BAUD Register Value Calculation
Asynchronous fref fref f
Arithmetic fBAUD ≤ fBAUD = 1 − BAUD BAUD = 65536 ⋅ 1 − 16 ⋅ BAUD
16 16 65536 fref
BAUD Register Value Serial Engine CPF fBAUD at 48MHz Serial Engine Frequency (fREF)
0 – 406 160 3MHz
407 – 808 161 2.981MHz
809 – 1205 162 2.963MHz
... ... ...
65206 31775 15.11kHz
65207 31871 15.06kHz
65208 31969 15.01kHz
ADDR
Match
ADDRMASK ==
rx shift register
ADDR
==
==
ADDRMASK
29.6.5 Interrupts
Interrupt sources are mode-specific. See the respective SERCOM mode chapters for details.
• SERCOM SPI
• SERCOM USART
• SERCOM I2C
Each interrupt source has its own interrupt flag.
The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is
met.
Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
As both INTENSET and INTENCLR always reflect the same value, the status of interrupt enablement can be read
from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SERCOM is
reset. For details on clearing interrupt flags, refer to the INTFLAG register description.
The value of INTFLAG indicates which interrupt condition occurred. The user must read the INTFLAG register to
determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests.
For further information on Interrupts, refer to the NVIC.
29.6.7 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
30.1 Overview
The Universal Synchronous and Asynchronous Receiver and Transmitter (USART) is one of the available modes in
the 29. Serial Communication Interface (SERCOM).
The USART uses the SERCOM transmitter and receiver, see 30.3 Block Diagram. Labels in uppercase letters are
synchronous to CLK_SERCOMx_APB and accessible for CPU. Labels in lowercase letters can be programmed to
run on the internal generic clock or an external clock.
The transmitter consists of a single write buffer, a shift register, and control logic for different frame formats. The
write buffer support data transmission without any delay between frames. The receiver consists of a two-level receive
buffer and a shift register. Status information of the received data is available for error checking. Data and clock
recovery units ensure robust synchronization and noise filtering during asynchronous data reception.
CTRLA.MODE /1 - /2 - /16
XCK
CTRLA.MODE RX Shift Register RxD
Status RX Buffer
STATUS RX DATA
or the communication line can return to the idle (high) state. The figure below illustrates the possible frame formats.
Values inside brackets ([x]) denote optional bits.
Figure 30-2. Frame Formats
Frame
IDLE No frame is transferred on the communication line. Signal is always high in this state.
30.6.2.1 Initialization
The following registers are enable-protected, meaning they can only be written when the USART is disabled
(CTRL.ENABLE=0):
• Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits.
• Control B register (CTRLB), except the Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits.
• Baud register (BAUD)
When the USART is enabled or is being enabled (CTRLA.ENABLE=1), any writing attempt to these registers will be
discarded. If the peripheral is being disabled, writing to these registers will be executed after disabling is completed.
Enable-protection is denoted by the "Enable-Protection" property in the register description.
Before the USART is enabled, it must be configured by these steps:
1. Select either external (0x0) or internal clock (0x1) by writing the Operating Mode value in the CTRLA register
(CTRLA.MODE).
2. Select either asynchronous (0) or or synchronous (1) communication mode by writing the Communication
Mode bit in the CTRLA register (CTRLA.CMODE).
3. Select pin for receive data by writing the Receive Data Pinout value in the CTRLA register (CTRLA.RXPO).
4. Select pads for the transmitter and external clock by writing the Transmit Data Pinout bit in the CTRLA register
(CTRLA.TXPO).
5. Configure the Character Size field in the CTRLB register (CTRLB.CHSIZE) for character size.
6. Set the Data Order bit in the CTRLA register (CTRLA.DORD) to determine MSB- or LSB-first data
transmission.
7. To use parity mode:
7.1. Enable parity mode by writing 0x1 to the Frame Format field in the CTRLA register (CTRLA.FORM).
7.2. Configure the Parity Mode bit in the CTRLB register (CTRLB.PMODE) for even or odd parity.
8. Configure the number of stop bits in the Stop Bit Mode bit in the CTRLB register (CTRLB.SBMODE).
9. When using an internal clock, write the Baud register (BAUD) to generate the desired baud rate.
10. Enable the transmitter and receiver by writing '1' to the Receiver Enable and Transmitter Enable bits in the
CTRLB register (CTRLB.RXEN and CTRLB.TXEN).
The peripheral must be enabled (CTRLA.ENABLE = 1) before issuing the Software Reset.
Refer to the CTRLA register description for details.
0 Tx Clk
1
1 CTRLA.CMODE
XCK 0
1 Rx Clk
0
XCK
CTRLA.CPOL=1
RxD / TxD
Change Sample
XCK
CTRLA.CPOL=0
RxD / TxD
Sample
When the clock is provided through XCK (CTRLA.MODE=0x0), the shift registers operate directly on the XCK clock.
This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the
system frequency.
30.6.2.4 Data Register
The USART Transmit Data register (TxDATA) and USART Receive Data register (RxDATA) share the same I/O
address, referred to as the Data register (DATA). Writing the DATA register will update the TxDATA register. Reading
the DATA register will return the contents of the RxDATA register.
30.6.2.5 Data Transmission
Data transmission is initiated by writing the data to be sent into the DATA register. Then, the data in TxDATA will be
moved to the shift register when the shift register is empty and ready to send a new frame. After the shift register is
loaded with data, the data frame will be transmitted.
When the entire data frame including stop bit(s) has been transmitted and no new data was written to DATA, the
Transmit Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set, and the
optional interrupt will be generated.
The Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) indicates that the
register is empty and ready for new data. The DATA register should only be written to when INTFLAG.DRE is set.
30.6.2.5.1 Disabling the Transmitter
The transmitter is disabled by writing '0' to the Transmitter Enable bit in the CTRLB register (CTRLB.TXEN).
Disabling the transmitter will complete only after any ongoing and pending transmissions are completed, i.e., there is
no data in the transmit shift register and TxDATA to transmit.
30.6.2.6 Data Reception
The receiver accepts data when a valid Start bit is detected. Each bit following the Start bit will be sampled according
to the baud rate or XCK clock, and shifted into the receive shift register until the first Stop bit of a frame is received.
The second Stop bit will be ignored by the receiver.
When the first Stop bit is received and a complete serial frame is present in the Receive Shift register, the contents
of the Shift register will be moved into the two-level receive buffer. Then, the Receive Complete Interrupt flag in the
Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set, and the optional interrupt can be generated.
The received data can be read from the DATA register when the Receive Complete Interrupt flag is set.
30.6.2.6.1 Disabling the Receiver
Writing '0' to the Receiver Enable bit in the CTRLB register (CTRLB.RXEN) will disable the receiver, flush the
two-level receive buffer, and data from ongoing receptions will be lost.
30.6.2.6.2 Error Bits
The USART receiver has three error bits in the Status (STATUS) register: Frame Error (FERR), Buffer Overflow
(BUFOVF), and Parity Error (PERR). Once an error happens, the corresponding error bit will be set until it is cleared
by writing ‘1’ to it. These bits are also cleared automatically when the receiver is disabled.
There are two methods for buffer overflow notification, selected by the Immediate Buffer Overflow Notification bit in
the Control A register (CTRLA.IBON):
When CTRLA.IBON=1, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the
receive FIFO by reading RxDATA, until the Receiver Complete Interrupt flag (INTFLAG.RXC) is cleared.
When CTRLA.IBON=0, the Buffer Overflow condition is attending data through the receive FIFO. After the received
data is read, STATUS.BUFOVF and INTFLAG.ERROR will be set along with INTFLAG.RXC.
D RSLOW [%] RFAST [%] Max. total error [%] Recommended max. Rx error [%]
(Data bits+Parity)
5 94.12 107.69 +5.88/-7.69 ±2.5
6 94.92 106.67 +5.08/-6.67 ±2.0
7 95.52 105.88 +4.48/-5.88 ±2.0
8 96.00 105.26 +4.00/-5.26 ±2.0
9 96.39 104.76 +3.61/-4.76 ±1.5
10 96.70 104.35 +3.30/-4.35 ±1.5
The following equations calculate the ratio of the incoming data rate and internal receiver baud rate:
D+ 1 S D+ 2 S
RSLOW = , RFAST =
S − 1 + D ⋅ S + SF D + 1 S + SM
• RSLOW is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
• RFAST is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
• D is the sum of character size and parity size (D = 5 to 10 bits)
• S is the number of samples per bit (S = 16, 8 or 3)
• SF is the first sample number used for majority voting (SF = 7, 3, or 2) when CTRLA.SAMPA=0.
• SM is the middle sample number used for majority voting (SM = 8, 4, or 2) when CTRLA.SAMPA=0.
The recommended maximum Rx Error assumes that the receiver and transmitter equally divide the maximum total
error. Its connection to the SERCOM Receiver error acceptance is depicted in this figure:
Baud Rate
The recommendation values in the table above accommodate errors of the clock source and the baud generator. The
following figure gives an example for a baud rate of 3Mbps:
Figure 30-6. USART Rx Error Calculation Example
30.6.3.1 Parity
Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit field in the Control A
register (CTRLA.FORM).
If even parity is selected (CTRLB.PMODE=0), the parity bit of an outgoing frame is '1' if the data contains an odd
number of bits that are '1', making the total number of '1' even.
If odd parity is selected (CTRLB.PMODE=1), the parity bit of an outgoing frame is '1' if the data contains an even
number of bits that are '0', making the total number of '1' odd.
When parity checking is enabled, the parity checker calculates the parity of the data bits in incoming frames and
compares the result with the parity bit of the corresponding frame. If a parity error is detected, the Parity Error bit in
the Status register (STATUS.PERR) is set.
When the receiver is disabled or the receive FIFO is full, the receiver will drive the RTS pin high. This notifies
the remote device to stop transfer after the ongoing transmission. Enabling and disabling the receiver by writing to
CTRLB.RXEN will set/clear the RTS pin after a synchronization delay. When the receive FIFO goes full, RTS will be
set immediately and the frame being received will be stored in the shift register until the receive FIFO is no longer full.
Figure 30-8. Receiver Behavior when Operating with Hardware Handshaking
RXD
RXEN
RTS
Rx FIFO Full
The current CTS Status is in the STATUS register (STATUS.CTS). Character transmission will start only if
STATUS.CTS=0. When CTS is set, the transmitter will complete the ongoing transmission and stop transmitting.
Figure 30-9. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
TXD
Note: The polarity of the transmitter and receiver are opposite: During transmission, a '0' bit is transmitted as a '1'
pulse. During reception, an accepted '0' pulse is received as a '0' bit.
Example: The figure below illustrates reception where RXPL.RXPL is set to 19. This indicates that
the pulse width should be at least 20 SE clock cycles. When using BAUD = 0xE666 or 160 SE
cycles per bit, this corresponds to 2/16 baud clock as minimum pulse width required. In this case
the first bit is accepted as a '0', the second bit is a '1', and the third bit is also a '1'. A low pulse is
rejected since it does not meet the minimum requirement of 2/16 baud clock.
Figure 30-11. IrDA Receive Decoding
Baud clock 0 0.5 1 1.5 2 2.5
RXD
20 SE clock cycles
30.6.3.6 RS485
RS485 is available with the following configuration:
• USART frame format (CTRLA.FORM = 0x00 or 0x01)
• RS485 pinout (CTRLA.TXPO=0x3).
The RS485 feature enables control of an external line driver as shown in the figure below. While operating in RS485
mode, the transmit enable pin (TE) is driven high when the transmitter is active.
Figure 30-14. RS485 Bus Connection
USART
RXD
TXD Differential
Bus
TE
The TE pin will remain high for the complete frame including stop bit(s). If a Guard Time is programmed in the Control
C register (CTRLC.GTIME), the line will remain driven after the last character completion. The following figure shows
a transfer with one stop bit and CTRLC.GTIME=3.
Figure 30-15. Example of TE Drive with Guard Time
Start Data Stop GTIME=3
TXD
TE
The Transmit Complete interrupt flag (INTFLAG.TXC) will be raised after the guard time is complete and TE goes
low.
collision, the receiver and transmitter must be enabled (CTRLB.RXEN = 1 and CTRLB.TXEN = 1) and the peripheral
bus (APB) must operate at or above the SERCOMx GCLK frequency.
Collision detection is performed for each bit transmitted by comparing the received value with the transmit value, as
shown in the figure below. While the transmitter is idle (no transmission in progress), characters can be received on
RxD without triggering a collision.
Figure 30-16. Collision Checking
8-bit character, single stop bit
TXD
RXD
Collision checked
The figure below illustrates the conditions for a collision detection. In this case, the start bit and the first data bit
are received with the same value as transmitted. The second received data bit is found to be different than the
transmitted bit at the detection point, which indicates a collision.
Figure 30-17. Collision Detected
Collision checked and ok
Tri-state
TXD
RXD
TXEN
Collision detected
When a collision is detected, the USART follows these sequence:
1. Abort the current transfer.
2. Flush the transmit buffer.
3. Disable transmitter (CTRLB.TXEN = 0).
– This is done after a synchronization delay. The CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB)
will be set until this is complete.
– After disabling, the TxD pin will be tri-stated.
4. Set the Collision Detected bit (STATUS.COLL) along with the Error interrupt flag (INTFLAG.ERROR).
5. Set the Transmit Complete interrupt flag (INTFLAG.TXC), becasue the transmit buffer no longer contains data.
After a collision, software must manually enable the transmitter again before continuing, after assuring that the
CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) is not set.
If the Receive Start Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start
interrupt is generated immediately when a start is detected.
When using start-of-frame detection without the Receive Start interrupt, start detection will force the 8MHz Internal
Oscillator and USART clock active while the frame is being received. In this case, the CPU will not wake up until the
Receive Complete interrupt is generated.
Request
Condition
DMA Interrupt Event
Data Register Empty (DRE) Yes Yes NA
(request cleared when data is written)
30.6.4.2 Interrupts
The USART has the following interrupt sources. These are asynchronous interrupts, and can wake up the device
from any sleep mode:
• Data Register Empty (DRE)
• Receive Complete (RXC)
• Transmit Complete (TXC)
• Receive Start (RXS)
• Clear to Send Input Change (CTSIC)
• Received Break (RXBRK)
• Error (ERROR)
Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually enabled by writing
'1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). As both the INTENSET and INTENCLR
registers always reflect the same value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and if the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the USART is
reset. For details on clearing interrupt flags, refer to the INTFLAG register description.
The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for
interrupt requests. Refer to Nested Vector Interrupt Controller for details.
When the Data Register Empty (DRE) interrupt is enabled, it is necessary to write the DATA register before entering
standby mode.
30.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in the CTRLA register (CTRLA.SWRST)
• Enable bit in the CTRLA register (CTRLA.ENABLE)
• Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
• Transmitter Enable bit in the Control B register (CTRLB.TXEN)
Note: CTRLB.RXEN is write-synchronized somewhat differently. See also 30.7.2 CTRLB for details.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
30.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
Bit 31 30 29 28 27 26 25 24
DORD CPOL CMODE FORM[3:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
SAMPA[1:0] RXPO[1:0] TXPO[1:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SAMPR[2:0] IBON
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RUNSTDBY MODE[2:0] ENABLE SWRST
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
FORM[3:0] Description
0x0 USART frame
...........continued
FORM[3:0] Description
0x1 USART frame with parity
0x2 LIN Host - Break and sync generation. See LIN Command (CTRLB.LINCMD).
0x3 Reserved
0x4 Auto-baud (LIN Client) - break detection and auto-baud.
0x5 Auto-baud - break detection and auto-baud with parity
0x6-0xF Reserved
TXPO TxD Pin Location XCK Pin Location (When Applicable) RTS/TE CTS
0x0 SERCOM PAD[0] SERCOM PAD[1] N/A N/A
0x1 SERCOM PAD[2] SERCOM PAD[3] N/A N/A
0x2 SERCOM PAD[0] N/A SERCOM PAD[2] SERCOM PAD[3]
0x3 SERCOM_PAD[0] SERCOM_PAD[1] SERCOM_PAD[2] N/A
SAMPR[2:0] Description
0x0 16x over-sampling using arithmetic baud rate generation.
0x1 16x over-sampling using fractional baud rate generation.
0x2 8x over-sampling using arithmetic baud rate generation.
0x3 8x over-sampling using fractional baud rate generation.
0x4 3x over-sampling using arithmetic baud rate generation.
0x5-0x7 Reserved
Value Description
0 STATUS.BUFOVF is asserted when it occurs in the data stream.
1 STATUS.BUFOVF is asserted immediately upon buffer overflow.
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value Description
0 The peripheral is disabled or being disabled.
1 The peripheral is enabled or being enabled.
30.7.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
Bit 31 30 29 28 27 26 25 24
LINCMD[1:0]
Access R/W R/W
Reset 0 0
Bit 23 22 21 20 19 18 17 16
RXEN TXEN
Access R/W R/W
Reset 0 0
Bit 15 14 13 12 11 10 9 8
PMODE ENC SFDE COLDEN
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SBMODE CHSIZE[2:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Value Description
0 The receiver is disabled or being enabled.
1 The receiver is enabled or will be enabled when the USART is enabled.
Value Description
0 Collision detection is not enabled.
1 Collision detection is enabled.
CHSIZE[2:0] Description
0x0 8 bits
0x1 9 bits
0x2-0x4 Reserved
0x5 5 bits
0x6 6 bits
0x7 7 bits
30.7.3 Control C
Name: CTRLC
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
HDRDLY[1:0] BRKLEN[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GTIME[2:0]
Access R/W R/W R/W
Reset 0 0 0
30.7.4 Baud
Name: BAUD
Offset: 0x0C
Reset: 0x0000
Property: Enable-Protected, PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
BAUD[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
BAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: RXPL
Offset: 0x0E
Reset: 0x00
Property: Enable-Protected, PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
RXPL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
ERROR RXBRK CTSIC RXS RXC TXC DRE
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Value Description
0 Transmit Complete interrupt is disabled.
1 Transmit Complete interrupt is enabled.
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
ERROR RXBRK CTSIC RXS RXC TXC DRE
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Value Description
0 Transmit Complete interrupt is disabled.
1 Transmit Complete interrupt is enabled.
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ERROR RXBRK CTSIC RXS RXC TXC DRE
Access R/W R/W R/W R/W R R/W R
Reset 0 0 0 0 0 0 0
Bit 7 – ERROR Error
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS
register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.
The Frame Error (FERR) and Parity Error (PERR) error interrupts will not wake the device from Standby mode.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
30.7.9 Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
TXE COLL ISF CTS BUFOVF FERR PERR
Access R/W R/W R/W R R/W R/W R/W
Reset 0 0 0 0 0 0 0
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CTRLB ENABLE SWRST
Access R R R
Reset 0 0 0
30.7.11 Data
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
DATA[8]
Access R/W
Reset 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
31.1 Overview
The serial peripheral interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM).
The SPI uses the SERCOM transmitter and receiver configured as shown in 31.3 Block Diagram. Each side, host
and client, depicts a separate SPI containing a shift register, a transmit buffer and a two-level receive buffer. In
addition, the SPI host uses the SERCOM baud-rate generator, while the SPI client can use the SERCOM address
match logic. Labels in capital letters are synchronous to CLK_SERCOMx_APB and accessible by the CPU, while
labels in lowercase letters are synchronous to the SCK clock.
31.2 Features
SERCOM SPI includes the following features:
• Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
• One-level transmit buffer, two-level receive buffer
• Supports all four SPI modes of operation
• Single data direction operation allows alternate function on MISO or MOSI pin
• Selectable LSB- or MSB-first data transfer
• Can be used with DMA
• Host operation:
– Serial clock speed, fSCK=1/tSCK(1)
– 8-bit clock generator
– Hardware controlled SS
• Client Operation:
– Serial clock speed, fSCK=1/tSSCK(1)
– Optional 8-bit address match operation
– Operation in all sleep modes
– Wake on SS transition
1. For tSCK and tSSCK values, refer to the SPI Mode Electrical Specifications.
SS
baud rate generator shift register MISO shift register
MOSI
rx buffer rx buffer ==
Rx DATA Rx DATA Address Match
One signal can be mapped to one of several pins. For further information, refer to the Pinout Chapter.
_
SS
The SPI host must pull the SPI select line (SS) of the desired client low to initiate a transaction if multiple clients are
connected to the bus. The SPI select line can be wired low if there is only one SPI client on the bus. The host and
client prepare data to send via their respective Shift registers, and the host generates the serial clock on the SCK
line.
Data is always shifted from host to client on the Host Output Client Input line (MOSI); data is shifted from client to
host on the Host Input Client Output line (MISO).
Each time character is shifted out from the host, a character will be shifted out from the client simultaneously. To
signal the end of a transaction, the host will pull the SS line high.
31.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the SPI is disabled
(CTRL.ENABLE=0):
• Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST)
• Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN)
Note:
Leading edge is the first clock edge in a clock cycle.
Trailing edge is the second clock edge in a clock cycle.
Figure 31-3. SPI Transfer Modes
Mode 0
Mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
LSB first (DORD = 1) LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB
Mode 1
Mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB
LSB first (DORD = 1) LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB
31.6.2.6.1 Host
In host mode (CTRLA.MODE=0x3), when Host SPI Select Enable (CTRLB.MSSEN) is ‘1’, hardware will control the
SS line.
When Host SPI Select Enable (CTRLB.MSSEN) is '0', the SS line must be configured as an output. SS can be
assigned to any general purpose I/O pin. When the SPI is ready for a data transaction, software must pull the SS line
low.
When writing a character to the Data register (DATA), the character will be transferred to the shift register. Once the
content of TxDATA has been transferred to the shift register, the Data Register Empty flag in the Interrupt Flag Status
and Clear register (INTFLAG.DRE) will be set. And a new character can be written to DATA.
Each time one character is shifted out from the host, another character will be shifted in from the client
simultaneously. If the receiver is enabled (CTRLA.RXEN=1), the contents of the shift register will be transferred
to the two-level receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in. Then
the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The
received data can be retrieved by reading DATA.
When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt
flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. When the transaction is finished,
the host must pull the SS line high to notify the client. If Host SPI Select Enable (CTRLB.MSSEN) is set to '0', the
software must pull the SS line high.
31.6.2.6.2 Client
In client mode (CTRLA.MODE=0x2), the SPI interface will remain inactive with the MISO line tri-stated as long as the
SS pin is pulled high. Software may update the contents of DATA at any time as long as the Data Register Empty flag
in the Interrupt Status and Clear register (INTFLAG.DRE) is set.
When SS is pulled low and SCK is running, the client will sample and shift out data according to the transaction mode
set. When the content of TxDATA has been loaded into the shift register, INTFLAG.DRE will be set, and new data can
be written to DATA.
Similar to the host, the client will receive one character for each character transmitted. A character will be transferred
into the two-level receive buffer within the same clock cycle its last data bit is received. The received character can
be retrieved from DATA when the Receive Complete interrupt flag (INTFLAG.RXC) is set.
When the host pulls the SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt
Flag Status and Clear register (INTFLAG.TXC) will be set.
After DATA is written it takes up to three SCK clock cycles until the content of DATA is ready to be loaded into the
shift register on the next character boundary. As a consequence, the first character transferred in a SPI transaction
will not be the content of DATA. This can be avoided by using the preloading feature. Refer to Preloading of the Client
Shift Register.
When transmitting several characters in one SPI transaction, the data has to be written into DATA register with
at least three SCK clock cycles left in the current character transmission. If this criteria is not met, the previously
received character will be transmitted.
Once the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set.
SS synchronized
to system domain
SCK
Synchronization MISO to SCK
to system domain setup time
MOSI MOSI
shift register shift register
MISO MISO
SCK SCK
SS[0] SS SPI Client 0
SPI Host
SS[n-1] MOSI
shift register
MISO
SCK
SS SPI Client n-1
Another configuration is multiple clients in series, as in the following figure. In this configuration, all n attached clients
are connected in series. A common SS line is provided to all clients, enabling them simultaneously. The host must
shift n characters for a complete transaction. Depending on the Host SPI Select Enable bit (CTRLB.MSSEN), the SS
line can be controlled either by hardware or user software and normal GPIO.
Figure 31-6. Multiple Clients in Series
T T T T T
SS
SCK
T = 1 to 2 baud cycles
When CTRLB.MSSEN=0, the SS pin(s) is/are controlled by user software and normal GPIO.
31.6.3.6 SPI Select Low Detection
In client mode, the SPI can wake the CPU when the SPI select (SS) goes low. When the SPI Select Low Detect is
enabled (CTRLB.SSDE=1), a high-to-low transition will set the SPI Select Low interrupt flag (INTFLAG.SSL) and the
device will wake up if applicable.
Condition Request
DMA Interrupt Event
Data Register Empty (DRE) Yes Yes NA
(request cleared when data is written)
• Host operation, CTRLA.RUNSTDBY=1: The peripheral clock GCLK_SERCOM_CORE will continue to run in idle
sleep mode and in standby sleep mode. Any interrupt can wake up the device.
• Host operation, CTRLA.RUNSTDBY=0: GLK_SERCOMx_CORE will be disabled after the ongoing transaction is
finished. Any interrupt can wake up the device.
• Client operation, CTRLA.RUNSTDBY=1: The Receive Complete interrupt can wake up the device.
• Client operation, CTRLA.RUNSTDBY=0: All reception will be dropped, including the ongoing transaction.
31.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in the CTRLA register (CTRLA.SWRST)
• Enable bit in the CTRLA register (CTRLA.ENABLE)
• Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
Note: CTRLB.RXEN is write-synchronized somewhat differently. See the 31.7.2 CTRLB register for details.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
31.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
Bit 31 30 29 28 27 26 25 24
DORD CPOL CPHA FORM[3:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DIPO[1:0] DOPO[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
IBON
Access R/W
Reset 0
Bit 7 6 5 4 3 2 1 0
RUNSTDBY MODE[2:0] ENABLE SWRST
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Value Description
0 The data is sampled on a leading SCK edge and changed on a trailing SCK edge.
Value Description
1 The data is sampled on a trailing SCK edge and changed on a leading SCK edge.
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value Description
0 The peripheral is disabled or being disabled.
1 The peripheral is enabled or being enabled.
31.7.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
RXEN
Access R/W
Reset 0
Bit 15 14 13 12 11 10 9 8
AMODE[1:0] MSSEN SSDE
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PLOADEN CHSIZE[2:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Value Description
0 Hardware SS control is disabled.
1 Hardware SS control is enabled.
Name: BAUD
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
BAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will
also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
ERROR SSL RXC TXC DRE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will
also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
ERROR SSL RXC TXC DRE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ERROR SSL RXC TXC DRE
Access R/W R/W R R/W R
Reset 0 0 0 0 0
Bit 7 – ERROR Error
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS
register. The BUFOVF error will set this interrupt flag.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
31.7.7 Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: –
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
BUFOVF
Access R/W
Reset 0
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CTRLB ENABLE SWRST
Access R R R
Reset 0 0 0
31.7.9 Address
Name: ADDR
Offset: 0x24
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
ADDRMASK[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
31.7.10 Data
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: –
Bit 15 14 13 12 11 10 9 8
DATA[8]
Access R/W
Reset 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DBGCTRL
Offset: 0x30
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGSTOP
Access R/W
Reset 0
32.1 Overview
The inter-integrated circuit (I2C) interface is one of the available modes in the Serial Communication Interface
(SERCOM)..
The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 32-1. Labels in capital
letters are registers accessible by the CPU, while lowercase labels are internal to the SERCOM.
A SERCOM instance can be configured to be either an I2C host or an I2C client. Both host and client have an
interface containing a shift register, a transmit buffer and a receive buffer. In addition, the I2C host uses the SERCOM
baud-rate generator, while the I2C client uses the SERCOM address match logic.
32.2 Features
SERCOM I2C includes the following features:
• Host or client operation
• Can be used with DMA
• Philips I2C compatible
• SMBus™ compatible
• PMBus compatible
• Support of 100 kHz and 400 kHz, 1 MHz and 3.4 MHz I2C mode
• 4-Wire operation supported
• Physical interface includes:
– Slew-rate limited outputs
– Filtered inputs
• Client operation:
– Operation in all sleep modes
– Wake-up on address match
– 7-bit Address match in hardware for:
• Unique address and/or 7-bit general call address
• Address range
• Two unique addresses can be used with DMA
RxDATA RxDATA ==
A transaction starts with the I2C host sending the start condition, followed by a 7-bit address and a direction bit (read
or write to/from the client).
The addressed I2C client will then acknowledge (ACK) the address, and data packet transactions can begin. Every
9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the data was acknowledged or
not.
If a data packet is not acknowledged (NACK), whether by the I2C client or host, the I2C host takes action by either
terminating the transaction by sending the stop condition, or by sending a repeated start to transfer more data.
The following figure illustrates the possible transaction formats and explains the transaction symbols. These symbols
will be used in the following descriptions.
Figure 32-2. Transaction Diagram Symbols
Bus Driver Special Bus Conditions
'1' '0'
'0' '1'
Figure 32-3. Basic I2C Transaction Diagram
SDA
SCL
6..0 7..0 7..0
Direction
Transaction
32.6.2.1 Initialization
The following registers are enable-protected, meaning they can be written only when the I2C interface is disabled
(CTRLA.ENABLE is ‘0’):
• Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) bits
• Control B register (CTRLB), except Acknowledge Action (CTRLB.ACKACT) and Command (CTRLB.CMD) bits
• Baud register (BAUD)
• Address register (ADDR) in client operation.
When the I2C is enabled or is being enabled (CTRLA.ENABLE=1), writing to these registers will be discarded. If the
I2C is being disabled, writing to these registers will be completed after the disabling.
Enable-protection is denoted by the "Enable-Protection" property in the register description.
Before I2C is enabled it must be configured by the following these steps:
1. Select I2C Host or Client mode by writing 0x4 (Client mode) or 0x5 (Host mode) to the Operating Mode bits in
the CTRLA register (CTRLA.MODE).
2. If required, select the SDA Hold Time value in the CTRLA register (CTRLA.SDAHOLD).
3. If required, enable smart operation by setting the Smart Mode Enable bit in the CTRLB register
(CTRLB.SMEN).
4. If required, enable SCL low time-out by setting the SCL Low Time-Out bit in the Control A register
(CTRLA.LOWTOUTEN).
5. In Host mode:
5.1. Select the inactive bus time-out in the Inactive Time-Out bit group in the CTRLA register
(CTRLA.INACTOUT).
5.2. Write the Baud Rate register (BAUD) to generate the desired baud rate.
In Client mode:
5.1. Configure the address match configuration by writing the Address Mode value in the CTRLB register
(CTRLB.AMODE).
5.2. Set the Address and Address Mask value in the Address register (ADDR.ADDR and
ADDR.ADDRMASK) according to the address configuration.
RESET
UNKNOWN
(0b00)
Start Condition
IDLE BUSY
(0b01) Timeout or Stop Condition (0b11)
Start Condition
Repeated
Stop Condition
This diagram is used as reference for the description of the I2C host operation throughout the document.
Figure 32-5. I2C Host Behavioral Diagram (SCLSM=0)
APPLICATION Host Bus INTERRUPT + SCL HOLD
M1 M2 M3 M4
Wait for
SW R/W A SW P IDLE M2
IDLE
W A SW Sr M3 BUSY M4
SW DATA A/A
A/A
R A DATA
In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit, as in Host Behavioral Diagram
(SCLSM=1). This strategy can be used when it is not necessary to check DATA before acknowledging.
Note: I2C High-speed (Hs) mode requires CTRLA.SCLSM=1.
M1 M2 M3 M4
Wait for
SW R/W A SW P IDLE M2
IDLE
W A SW Sr M3 BUSY M4
SW DATA A/A
SW Software interaction
SW BUSY M4
R A DATA A/A
TRISE
P S TLOW Sr
SCL
THIGH
TBUF TFALL
SDA
When BAUD.BAUDLOW is zero, the BAUD.BAUD value is used to time both SCL high and SCL low. In this case the
following formula will give the SCL frequency:
fGCLK
fSCL =
10 + 2BAUD + fGCLK ⋅ TRISE
When BAUD.BAUDLOW is non-zero, the following formula determines the SCL frequency:
fGCLK
fSCL =
10 + BAUD + BAUDLOW + fGCLK ⋅ TRISE
The following formulas can determine the SCL TLOW and THIGH times:
TLOW = BAUDLOW + 5
fGCLK
THIGH = BAUD + 5
fGCLK
Note: The I2C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be
set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be non-zero.
Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when the DATA
register is written in smart mode. If a greater startup time is required due to long rise times, the time between DATA
write and IF clear must be controlled by software.
Note: When timing is controlled by user, the Smart Mode cannot be enabled.
If the I2C host receives an ACK from the I2C client, the I2C host proceeds to receive the next byte of data from the I2C
client. When the first data byte is received, the Client on Bus bit in the Interrupt Flag register (INTFLAG.SB) will be
set and STATUS.RXNACK will be cleared. The clock hold is active at this point, preventing further activity on the bus.
In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the
I2C operation to continue:
• Let the I2C host continue to read data by acknowledging the data received. ACK can be sent by software, or
automatically in smart mode.
• Transmit a new address packet.
• Terminate the transaction by issuing a stop condition.
Note: An ACK or NACK will be automatically transmitted if smart mode is enabled. The Acknowledge Action bit in
the Control B register (CTRLB.ACKACT) determines whether ACK or NACK should be sent.
Sr ADDRESS
Transmitting in High-speed mode requires the I2C host to be configured in High-speed mode (CTRLA.SPEED=0x2)
and the SCL clock stretch mode (CTRLA.SCLSM) bit set to '1'.
1
S
S 11110 addr[9:8] W A addr[7:0] A Sr 11110 addr[9:8] R A
W
This implies the following procedure for a 10-bit read operation:
1. Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit
(ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR).
2. Once the Host on Bus interrupt is asserted, Write ADDR[7:0] register to '11110 address[9:8] 1'.
ADDR.TENBITEN must be cleared (can be written simultaneously with ADDR).
3. Proceed to transmit data.
P S2
S1 S3 A S1 Sr S3
S S
S2 S ADDRESS R
W
A
W
DATA A/A
P S2
A S1 Sr S3
PREC INTERRUPT
S S
W A DATA A/A
W W
Interrupt on STOP S
Condition Enabled W
S
Software interaction
W
In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit is sent as shown in Client
Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check DATA before
acknowledging. For host reads, an address and data interrupt will be issued simultaneously after the address
acknowledge. However, for host writes, the first data interrupt will be seen after the first data byte has been received
by the client and the acknowledge bit has been sent to the host.
Note: For I2C High-speed mode (Hs), SCLSM=1 is required.
Figure 32-11. I2C Client Behavioral Diagram (SCLSM=1)
AMATCH INTERRUPT (+ DRDY INTERRUPT in Host Read mode) DRDY INTERRUPT
P S2
S1 S3 Sr S3
S
S2 S ADDRESS R A/A
W
DATA A/A
P S2
Sr S3
PREC INTERRUPT
S S
W A/A DATA A/A
W W
Interrupt on STOP S
Condition Enabled W
S
Software interaction
W
Command/Data
S ADDRESS 0 W A n Bytes A
ADDRESS 1 S S
Sr W A n Bytes A
(this client) W W
PREC INTERRUPT
Command/Data
S
Sr ADDRESS 2 W A n Bytes A P
W
32.6.3.1 SMBus
The I2C includes three hardware SCL low time-outs which allow a time-out to occur for SMBus SCL low time-out,
host extend time-out, and client extend time-out. This allows for SMBus functionality These time-outs are driven by
the GCLK_SERCOM_SLOW clock. The GCLK_SERCOM_SLOW clock is used to accurately time the time-out and
must be configured to use a 32.768 kHz oscillator. The I2C interface also allows for a SMBus compatible SDA hold
time.
• TTIMEOUT: SCL low time of 25..35ms – Measured for a single SCL low period. It is enabled by
CTRLA.LOWTOUTEN.
• TLOW:SEXT: Cumulative clock low extend time of 25 ms – Measured as the cumulative SCL low extend time by a
client device in a single message from the initial START to the STOP. It is enabled by CTRLA.SEXTTOEN.
• TLOW:MEXT: Cumulative clock low extend time of 10 ms – Measured as the cumulative SCL low extend time
by the host device within a single byte from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is enabled by
CTRLA.MEXTTOEN.
I2C SCL/SDA
Driver pad
SCL_IN/
SDA_IN
PINOUT
Condition Request
DMA Interrupt Event
Data needed for transmit (TX) (Client transmit mode) Yes NA
(request cleared when data is written)
Condition Request
DMA Interrupt Event
Data needed for transmit (TX) (Host transmit mode) Yes NA
(request cleared when data is written)
• Read data received (RX): The request is set when host read data is received. The request is cleared when
DATA is read.
• Write data needed for transmit (TX): The request is set when data is needed for a host write operation. The
request is cleared when DATA is written.
32.6.4.2 Interrupts
The I2C client has the following interrupt sources. These are asynchronous interrupts. The DRDY, AMATCH, AND
PREC will wake the device from any sleep mode.
• Error (ERROR)
• Data Ready (DRDY)
• Address Match (AMATCH)
• Stop Received (PREC)
The I2C host has the following interrupt sources. These are asynchronous interrupts. The SB and MB interrupts can
wake the device from any sleep mode.
• Error (ERROR)
• Client on Bus (SB)
• Host on Bus (MB)
Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG) will be set when the interrupt condition is meet. Each interrupt can be individually enabled by writing
‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing ‘1’ to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). As both INTENSET and INTENCLR always
reflect the same value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request active until the interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See the INTFLAG
register for details on how to clear interrupt flags.
The value of INTFLAG indicates which interrupt is executed. Note that interrupts must be globally enabled for
interrupt requests. Refer to the 9.2 Nested Vector Interrupt Controller for details.
32.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in the CTRLA register (CTRLA.SWRST)
• Enable bit in the CTRLA register (CTRLA.ENABLE)
• Command bits in CTRLB register (CTRLB.CMD)
• Write to Bus State bits in the Status register (STATUS.BUSSTATE)
• Address bits in the Address register (ADDR.ADDR) when in host operation.
The following registers are synchronized when written:
32.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
Bit 31 30 29 28 27 26 25 24
LOWTOUTEN SCLSM SPEED[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
SEXTTOEN SDAHOLD[1:0] PINOUT
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
RUNSTDBY MODE[2:0] ENABLE SWRST
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
interrupt flags set at the time of time-out will remain set. If the address was recognized, PREC will be set when a
STOP is received.
Note: This bit is enable-protected. This bit is not synchronized.
Value Description
0 Time-out disabled
1 Time-out enabled
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value Description
0 The peripheral is disabled or being disabled.
1 The peripheral is enabled.
Value Description
0 There is no reset operation ongoing.
1 The reset operation is ongoing.
32.7.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
ACKACT CMD[1:0]
Access R/W W W
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
AMODE[1:0] AACKEN GCMD SMEN
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Access
Reset
...........continued
CMD[1:0] DIR Action
0x3 Used in response to an address interrupt (AMATCH)
0 (Host write) Execute acknowledge action succeeded by reception of next byte
1 (Host read) Execute acknowledge action succeeded by client data interrupt
Used in response to a data interrupt (DRDY)
0 (Host write) Execute acknowledge action succeeded by reception of next byte
1 (Host read) Execute a byte read operation followed by ACK/NACK reception
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
ERROR DRDY AMATCH PREC
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
ERROR DRDY AMATCH PREC
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ERROR DRDY AMATCH PREC
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 – ERROR Error
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS
register. The corresponding bits in STATUS are SEXTTOUT, LOWTOUT, COLL, and BUSERR.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
32.7.6 Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
HS SEXTTOUT
Access R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR
Access R/W R/W R R R R/W R/W
Reset 0 0 0 0 0 0 0
Bit 10 – HS High-speed
This bit is set if the client detects a START followed by a Host Code transmission.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the status. However, this flag is automatically cleared when a STOP is received.
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ENABLE SWRST
Access R R
Reset 0 0
32.7.8 Address
Name: ADDR
Offset: 0x24
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
ADDRMASK[6:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ADDR[6:0] GENCEN
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
32.7.9 Data
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: Write-Synchronized, Read-Synchronized
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
32.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
Bit 31 30 29 28 27 26 25 24
LOWTOUTEN INACTOUT[1:0] SCLSM SPEED[1:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
SEXTTOEN MEXTTOEN SDAHOLD[1:0] PINOUT
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
RUNSTDBY MODE[2:0] ENABLE SWRST
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Value Description
1 SCL stretch only after ACK bit, Figure 32-6.
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value Description
0 The peripheral is disabled or being disabled.
1 The peripheral is enabled.
32.8.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
ACKACT CMD[1:0]
Access R/W W W
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
QCEN SMEN
Access R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
Access
Reset
...........continued
CMD[1:0] Direction Action
0x3 X Execute acknowledge action succeeded by issuing a stop condition
Name: BAUD
Offset: 0x0C
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
HSBAUDLOW[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
HSBAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
BAUDLOW[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
BAUD[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTENCLR
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
ERROR SB MB
Access R/W R/W R/W
Reset 0 0 0
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
ERROR SB MB
Access R/W R/W R/W
Reset 0 0 0
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
ERROR SB MB
Access R/W R/W R/W
Reset 0 0 0
Bit 7 – ERROR Error
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status bits in the STATUS
register. These status bits are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST, and BUSERR.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
32.8.7 Status
Name: STATUS
Offset: 0x1A
Reset: 0x0000
Property: Write-Synchronized
Bit 15 14 13 12 11 10 9 8
LENERR SEXTTOUT MEXTTOUT
Access R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
CLKHOLD LOWTOUT BUSSTATE[1:0] RXNACK ARBLOST BUSERR
Access R/W R/W R/W R/W R R/W R/W
Reset 0 0 0 0 0 0 0
Name: SYNCBUSY
Offset: 0x1C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
SYSOP ENABLE SWRST
Access R R R
Reset 0 0 0
32.8.9 Address
Name: ADDR
Offset: 0x24
Reset: 0x0000
Property: Write-Synchronized Bits
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
LEN[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TENBITEN HS LENEN ADDR[10:8]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
32.8.10 Data
Name: DATA
Offset: 0x28
Reset: 0x0000
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.SYSOP must be checked to ensure the DATA register
synchronization is complete.
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: DBGCTRL
Offset: 0x30
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGSTOP
Access R/W
Reset 0
33.1 Overview
There are up to five TC peripheral instances. Each TC consists of a counter, a prescaler, compare/capture channels
and control logic. The counter can be set to count events or clock pulses. The counter, together with the compare/
capture channels, can be configured to timestamp input events or I/O pin edges, allowing for capturing of frequency
and pulse width.
A TC can also perform waveform generation, such as frequency generation and pulse-width modulation.
33.2 Features
• Selectable configuration
– 8, 16, or 32-bit TC operation with compare/capture channels
• 2 compare/capture channels (CC) with:
– Double buffered timer period setting
– Double buffered compare channel
• Waveform generation
– Frequency generation
– Single-slope pulse-width modulation
• Input capture
– Event or I/O pin edge capture
– Frequency capture
– Pulse-width capture
– Time-stamp capture
– Minimum and maximum capture
• One input event
• Interrupts/output events on:
– Counter overflow or underflow
– Compare match or capture
• Internal prescaler
• DMA support
Base Counter
BUFV PERBUF
PER Prescaler
TOP
=
"event"
UPDATE
BOTTOM
=0
Compare/Capture
(Unit x = {0,1}
"capture"
BUFV CCBUFx Control Logic
WO[1]
CCx Waveform
Generation WO[0]
"match"
= MCx (INT/Event/DMA Req.)
Refer to 4. Pinout and Packaging for details on the pin mapping for this peripheral. One signal can be mapped on
several pins. TC2 and TC3 WO[1:0] signals are not available on the 32-pin variants.
Name Description
TOP The counter reaches TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be the same as Period (PER) or the
Compare Channel 0 (CC0) register value depending on the waveform generator
mode in 33.6.2.6.1 Waveform Output Operations.
ZERO The counter is ZERO when it contains all zeroes
MAX The counter reaches MAX when it contains all ones
UPDATE The timer/counter signals an update when it reaches ZERO or TOP, depending
on the direction settings.
Timer Increment / decrement / clear / reload steps are performed on each prescaled
clock cycle.
Counter Increment / decrement / clear / reload steps are performed on each detected
event.
CC For compare operations, the CC are referred to as “compare channels”
For capture operations, the CC are referred to as “capture channels.”
For optimized timing the CCx and CCBUFx registers share a common resource. When writing into CCBUFx, lock the
access to the corresponding CCx register (SYNCBUSY.CCX = 1) till the CCBUFx register value is not loaded into the
CCx register (BUFVx = 1). Each buffer register has a buffer valid (BUFV) flag that indicates when the buffer contains
a new value.
The Counter register (COUNT) and the Compare and Capture registers with buffers (CCx and CCBUFx) can be
configured as 8, 16, or 32-bit registers, with according MAX values. Mode settings (CTRLA.MODE) determine the
maximum range of the Counter register.
In 8-bit mode, a Period Value (PER) register and its Period Buffer Value (PERBUF) register are also available.
The counter range and the operating frequency determine the maximum time resolution achievable with the TC
peripheral.
The TC can be set to count up or down. Under normal operation, the counter value is continuously compared to the
TOP or ZERO value to determine whether the counter has reached that value. On a comparison match the TC can
request DMA transactions, or generate interrupts or events for the Event System.
In compare operation, the counter value is continuously compared to the values in the CCx registers. In case of a
match the TC can request DMA transactions, or generate interrupts or events for the Event System. In waveform
generator mode, these comparisons are used to set the waveform period or pulse width.
Capture operation can be enabled to perform input signal period and pulse width measurements, or to capture
selectable edges from an IO pin or internal event from Event System.
33.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the TC is disabled
(CTRLA.ENABLE = 0):
• Control A register (CTRLA), except the Enable (ENABLE) and Software Reset (SWRST) bits
• Drive Control register (DRVCTRL)
• Wave register (WAVE)
• Event Control register (EVCTRL)
Writing to Enable-Protected bits and setting the CTRLA.ENABLE bit can be performed in a single 32-bit access of
the CTRLA register. Writing to Enable-Protected bits and clearing the CTRLA.ENABLE bit cannot be performed in a
single 32-bit access.
Before enabling the TC, the peripheral must be configured by the following steps:
1. Enable the TC bus clock (CLK_TCx_APB).
2. Select 8, 16, or 32-bit counter mode through the TC Mode bit group in the Control A register (CTRLA.MODE).
The default mode is 16-bit.
3. Select one wave generation operation in the Waveform Generation Operation bit group in the WAVE register
(WAVE.WAVEGEN).
4. If required, the GCLK_TCx clock can be prescaled via the Prescaler bit group in the Control A register
(CTRLA.PRESCALER).
– If the prescaler is used, select a prescaler synchronization operation via the Prescaler and Counter
Synchronization bit group in the Control A register (CTRLA.PRESYNC).
5. If required, select one-shot operation by writing a '1' to the One-Shot bit in the Control B Set register
(CTRLBSET.ONESHOT).
6. If required, configure the counting direction 'down' (starting from the TOP value) by writing a '1' to the Counter
Direction bit in the Control B register (CTRLBSET.DIR).
7. For capture operation, enable the individual channels to capture in the Capture Channel x Enable bit group in
the Control A register (CTRLA.CAPTEN).
8. If required, enable inversion of the waveform output or IO pin input signal for individual channels via the Invert
Enable bit group in the Drive Control register (DRVCTRL.INVEN).
Note: Two instances of the TC may share a peripheral clock channel. In this case, they cannot be set to different
clock frequencies. Refer to the peripheral clock channel mapping of the Generic Clock Controller (GCLK.PCHTRLm)
to identify shared peripheral clocks.
set by CTRLBSET.DIR or CTRLBCLR.DIR), unless a different value has been written to it, or the TC has been
stopped at a value other than ZERO. The write access has higher priority than count, clear, or reload. The direction of
the counter can also be changed when the counter is running. See also the following figure.
Figure 33-3. Counter Operation
MAX
"reload" update
"clear" update
TOP
COUNT
ZERO
DIR
Due to asynchronous clock domains, the internal counter settings are written when the synchronization is complete.
Normal operation must be used when using the counter as timer base for the capture channels.
33.6.2.5.1 Stop Command and Event Action
A Stop command can be issued from software by using Command bits in the Control B Set register
(CTRLBSET.CMD = 0x2, STOP). When a Stop is detected while the counter is running, the counter will be loaded
with the starting value (ZERO or TOP, depending on direction set by CTRLBSET.DIR or CTRLBCLR.DIR). All
waveforms are cleared and the Stop bit in the Status register is set (STATUS.STOP).
33.6.2.5.2 Re-Trigger Command and Event Action
A re-trigger command can be issued from software by writing the Command bits in the Control B Set register
(CTRLBSET.CMD = 0x1, RETRIGGER), or from event when a re-trigger event action is configured in the Event
Control register (EVCTRL.EVACT = 0x1, RETRIGGER).
When the command is detected during counting operation, the counter will be reloaded or cleared, depending on the
counting direction (CTRLBSET.DIR or CTRLBCLR.DIR). When the re-trigger command is detected while the counter
is stopped, the counter will resume counting from the current value in the COUNT register.
Note: When a re-trigger event action is configured in the Event Action bits in the Event Control register
(EVCTRL.EVACT=0x1, RETRIGGER), enabling the counter will not start the counter. The counter will start on the
next incoming event and restart on corresponding following event.
33.6.2.5.3 Count Event Action
The TC can count events. When an event is received, the counter increases or decreases the value, depending on
direction settings (CTRLBSET.DIR or CTRLBCLR.DIR). The count event action can be selected by the Event Action
bit group in the Event Control register (EVCTRL.EVACT=0x2, COUNT).
Note: If this operation mode is selected, PWM generation is not supported.
33.6.2.5.4 Start Event Action
The TC can start counting operation on an event when previously stopped. In this configuration, the event has no
effect if the counter is already counting. When the peripheral is enabled, the counter operation starts when the event
is received or when a re-trigger software command is applied.
The Start TC on Event action can be selected by the Event Action bit group in the Event Control register
(EVCTRL.EVACT=0x3, START).
The Channel x Compare Buffer (CCBUFx) registers provide double buffer capability. The double buffering
synchronizes the update of the CCx register with the buffer value at the UPDATE condition or a forced update
command (CTRLBSET.CMD=UPDATE). For further details, refer to 33.6.2.7 Double Buffering. The synchronization
prevents the occurrence of odd-length, non-symmetrical pulses and ensures glitch-free output.
CCx
ZERO
WO[x]
Match Frequency Generation (MFRQ)
For Match Frequency Generation, the period time (T) is controlled by the CC0 register instead of PER or MAX. WO[0]
toggles on each update condition.
MAX
"reload" update
"clear" update
CC0
COUNT
ZERO
WO[0]
COUNT
CC1
ZERO
WO[1]
The table below shows the Update Counter and Overflow Event/Interrupt Generation conditions in different operation
modes.
CCBUFVx EN CCBUFx
EN CCx
UPDATE
COUNT
"match"
=
Both the registers (PER/CCx) and corresponding buffer registers (PERBUF/CCBUFx) are available in the I/O
register map, and the double buffering feature is not mandatory. The double buffering is disabled by writing a '1'
to CTRLBSET.LUPD.
Note: In NFRQ, MFRQ or PWM down-counting counter mode (CTRLBSET.DIR=1), when double buffering is
enabled (CTRLBCLR.LUPD=1), PERBUF register is continously copied into the PER independently of update
conditions.
Changing the Period
The counter period can be changed by writing a new TOP value to the Period register (PER or CC0, depending on
the waveform generation mode), which is available in 8-bit mode. Any period update on registers (PER or CCx) is
effective after the synchronization delay.
Counter Wraparound
MAX
"clear" update
"write"
COUNT
ZERO
A counter wraparound can occur in any operation mode when up-counting without buffering, see the following figure.
COUNT and TOP are continuously compared, so when a new TOP value that is lower than current COUNT is written
to TOP, COUNT will wrap before a compare match.
Figure 33-9. Unbuffered Single-Slope Down-Counting Operation
MAX
"reload" update
"write"
COUNT
ZERO
When double buffering is used, the buffer can be written at any time and the counter will still maintain correct
operation. The period register is always updated on the update condition, as shown in the following figure. This
prevents wraparound and the generation of odd waveforms.
Figure 33-10. Changing the Period Using Buffering
MAX
" clear" update
" write"
COUNT
ZERO
BV EN CCBx
IF EN CCx
"INT/DMA
request" data read
For input capture, the buffer register and the corresponding CCx act like a FIFO. When CCx is empty or read,
any content in CCBUFx is transferred to CCx. The buffer valid flag is passed to set the CCx interrupt flag (IF) and
generate the optional interrupt, event or DMA request. The CCBUFx register value can't be read, all captured data
must be read from CCx register.
events
TOP
COUNT
ZERO
The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the
Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
f= 1
T
tp
dutyCycle =
T
Figure 33-13. PWP Capture
Period (T)
events
MAX
"capture"
COUNT
ZERO
CC0 CC1 CC0 CC1
Selecting PWP in the Event Action bit group in the Event Control register (EVCTRL.EVACT) enables the TC to
perform one capture action on the rising edge and the other one on the falling edge. The period T will be captured
into CC1 and the pulse width tp in CC0. EVCTRL.EVACT=PPW (period and pulse-width) offers identical functionality,
but will capture T into CC0 and tp into CC1.
The TC Event Input Invert Enable bit in the Event Control register (EVCTRL.TCINV) is used to select whether
the wraparound should occur on the rising edge or the falling edge. If EVCTRL.TCINV=1, the wraparound will
happen on the falling edge. In case pin capture is enabled, this can also be achieved by modifying the value of the
DRVCTRL.INVENx bit.
The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the
Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
Note: The corresponding capture is working only if the channel is enabled in capture mode (CTRLA.CAPTENx=1).
If not, the capture action is ignored and the channel is enabled in compare mode of operation. Consequently, both
channels must be enabled in order to fully characterize the input.
events
MAX
"capture"
"restart"
COUNT
ZERO
CC0 CC0
The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the
Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
When a valid captured value is present in the capture channel register, the corresponding Capture Channel x
Interrupt Flag (INTFLAG.MCx) is set.
The timer/counter can detect capture overflow of the input capture channels: When a new capture event is detected
while the Capture Channel interrupt flag (INTFLAG.MCx) is still set, the new time-stamp will not be stored and
INTFLAG.ERR will be set.
Figure 33-15. Time-Stamp
Capture Events
MAX
TOP
"capture"
"overflow"
COUNT
ZERO
Figure 33-16. Maximum Capture Operation with CC0 Initialized with ZERO Value
TOP
"clear" update
COUNT CC0 "match"
ZERO
Input event
CC0 Event/
Interrupt
33.6.5 Interrupts
The TC has the following interrupt sources:
• Overflow/Underflow (OVF)
• Match or Capture Channel x (MCx)
• Capture Overflow Error (ERR)
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs.
Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register
(INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
As both INTENSET and INTENCLR always reflect the same value, the status of interrupt enablement can be read
from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the TC is reset.
See INTFLAG for details on how to clear interrupt flags.
The TC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register
to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to 9.2 Nested Vector
Interrupt Controller for details.
33.6.6 Events
The TC can generate the following output events:
• Overflow/Underflow (OVF)
• Match or Capture Channel x (MCx)
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.MCEOx) enables the corresponding output
event. The output event is disabled by writing EVCTRL.MCEOx=0.
One of the following event actions can be selected by the Event Action bit group in the Event Control register
(EVCTRL.EVACT):
• Disable event action (OFF)
• Start TC (START)
• Re-trigger TC (RETRIGGER)
– If a re-trigger event occurs exactly at the time a Channel Compare Match occurs, the next waveform will
be corrupted. To avoid this issue, use two channels to store two successive CC register values (n and n+1)
and combine the related waveform outputs to provide signal redundancy.
• Count on event (COUNT)
• Capture time stamp (STAMP)
• Capture Period (PPW and PWP)
• Capture Pulse Width (PW)
Writing a '1' to the TC Event Input bit in the Event Control register (EVCTRL.TCEI) enables input events (EVU) to
the TC. Writing a '0' to this bit disables input events to the TC. The TC requires only asynchronous event inputs. For
additional information on how configuring the asynchronous events, refer to the 28. Event System (EVSYS).
33.6.9 Synchronization
Some registers (or bit fields within a register) require synchronization when read and/or written.
Synchronization is denoted by the "Read-Synchronized" (or "Read-Synchronized Bits”) and/or "Write-Synchronized"
(or "Write-Synchronized Bits”) property in each individual register description.
For more details, refer to Register Synchronization.
33.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized Bits, Enable-Protected Bits
Bit 31 30 29 28 27 26 25 24
CAPTMODE1[1:0] CAPTMODE0[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
COPEN1 COPEN0 CAPTEN1 CAPTEN0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
ALOCK PRESCALER[2:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY PRESCSYNC[1:0] MODE[1:0] ENABLE SWRST
Access R/W R/W R/W R/W R/W R/W R/W W
Reset 0 0 0 0 0 0 0 0
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable protected.
Value Description
0 The peripheral is disabled.
1 The peripheral is enabled.
Name: CTRLBCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set register (CTRLBSET).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBCLR register synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CMD[2:0] ONESHOT LUPD DIR
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: CTRLBSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Clear register (CTRLBCLR).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBSET register synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CMD[2:0] ONESHOT LUPD DIR
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Important: This command requires synchronization before being executed. A valid sequence is:
• Issue CMD command (CTRLBSET.CMD = command)
• Wait for CMD synchronization (SYNCBUSY.CTRLB = 0)
• Wait for CMD read back as zero (CTRLBSET.CMD = 0)
Value Description
1 The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on
hardware update condition.
Name: EVCTRL
Offset: 0x06
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit 15 14 13 12 11 10 9 8
MCEO1 MCEO0 OVFEO
Access R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
TCEI TCINV EVACT[2:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTENCLR
Offset: 0x08
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
MC1 MC0 ERR OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTENSET
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
MC1 MC0 ERR OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTFLAG
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
MC1 MC0 ERR OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
33.7.8 Status
Name: STATUS
Offset: 0x0B
Reset: 0x01
Property: Read-Synchronized, Write-Synchronized
Note: This register is read- and write-synchronized: SYNCBUSY.STATUS must be checked to ensure the STATUS
register synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CCBUFV1 CCBUFV0 PERBUFV SLAVE STOP
Access R/W R/W R/W R/W R
Reset 0 0 0 0 1
Name: WAVE
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
WAVEGEN[1:0]
Access R/W R/W
Reset 0 0
1) This depends on the TC mode: In 8-bit mode, the top value is the Period Value register (PER). In 16- and 32-bit
mode it is the respective MAX value.
Name: DRVCTRL
Offset: 0x0D
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
INVEN1 INVEN0
Access R/W R/W
Reset 0 0
Name: DBGCTRL
Offset: 0x0F
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CC1 CC0 PER COUNT STATUS CTRLB ENABLE SWRST
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: COUNT
Offset: 0x14
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Notes:
1. This register is read-synchronized: Prior to any read access, this register must be synchronized by user by
writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
2. This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
COUNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PER
Offset: 0x1B
Reset: 0xFF
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.PER must be checked to ensure the PER register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
PER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: CCx
Offset: 0x1C + x*0x01 [x=0..1]
Reset: 0x00
Property: Write-Synchronized, Read-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CC[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: PERBUF
Offset: 0x2F
Reset: 0xFF
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.PER must be checked to ensure the PER register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
PERBUF[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: CCBUFx
Offset: 0x30 + x*0x01 [x=0..1]
Reset: 0x00
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CCBUF[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
33.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized Bits, Enable-Protected Bits
Bit 31 30 29 28 27 26 25 24
CAPTMODE1[1:0] CAPTMODE0[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
COPEN1 COPEN0 CAPTEN1 CAPTEN0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
ALOCK PRESCALER[2:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY PRESCSYNC[1:0] MODE[1:0] ENABLE SWRST
Access R/W R/W R/W R/W R/W R/W R/W W
Reset 0 0 0 0 0 0 0 0
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable protected.
Value Description
0 The peripheral is disabled.
1 The peripheral is enabled.
Name: CTRLBCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set register (CTRLBSET).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBCLR register synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CMD[2:0] ONESHOT LUPD DIR
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: CTRLBSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Clear register (CTRLBCLR).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBSET register synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CMD[2:0] ONESHOT LUPD DIR
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Important: This command requires synchronization before being executed. A valid sequence is:
• Issue CMD command (CTRLBSET.CMD = command)
• Wait for CMD synchronization (SYNCBUSY.CTRLB = 0)
• Wait for CMD read back as zero (CTRLBSET.CMD = 0)
Value Description
1 The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on
hardware update condition.
Name: EVCTRL
Offset: 0x06
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit 15 14 13 12 11 10 9 8
MCEO1 MCEO0 OVFEO
Access R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
TCEI TCINV EVACT[2:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTENCLR
Offset: 0x08
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
MC1 MC0 ERR OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTENSET
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
MC1 MC0 ERR OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTFLAG
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
MC1 MC0 ERR OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
33.8.8 Status
Name: STATUS
Offset: 0x0B
Reset: 0x01
Property: Read-Synchronized, Write-Synchronized
Note: This register is read- and write-synchronized: SYNCBUSY.STATUS must be checked to ensure the STATUS
register synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CCBUFV1 CCBUFV0 SLAVE STOP
Access R/W R/W R/W R
Reset 0 0 0 1
Name: WAVE
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
WAVEGEN[1:0]
Access R/W R/W
Reset 0 0
1) This depends on the TC mode: In 8-bit mode, the top value is the Period Value register (PER). In 16-bit and 32-bit
mode it is the respective Max. value.
Name: DRVCTRL
Offset: 0x0D
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
INVEN1 INVEN0
Access R/W R/W
Reset 0 0
Name: DBGCTRL
Offset: 0x0F
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CC1 CC0 COUNT STATUS CTRLB ENABLE SWRST
Access R R R R R R R
Reset 0 0 0 0 0 0 0
Name: COUNT
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Notes:
1. This register is read-synchronized: prior to any read access, this register must be synchronized by user by
writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
2. This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register
synchronization is complete.
Bit 15 14 13 12 11 10 9 8
COUNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
COUNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CCx
Offset: 0x1C + x*0x02 [x=0..1]
Reset: 0x0000
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit 15 14 13 12 11 10 9 8
CC[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CC[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CCBUFx
Offset: 0x30 + x*0x02 [x=0..1]
Reset: 0x0000
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit 15 14 13 12 11 10 9 8
CCBUF[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CCBUF[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
33.9.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized Bits, Enable-Protected Bits
Bit 31 30 29 28 27 26 25 24
CAPTMODE1[1:0] CAPTMODE0[1:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
COPEN1 COPEN0 CAPTEN1 CAPTEN0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
ALOCK PRESCALER[2:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY PRESCSYNC[1:0] MODE[1:0] ENABLE SWRST
Access R/W R/W R/W R/W R/W R/W R/W W
Reset 0 0 0 0 0 0 0 0
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable protected.
Value Description
0 The peripheral is disabled.
1 The peripheral is enabled.
Name: CTRLBCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set register (CTRLBSET).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBCLR register synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CMD[2:0] ONESHOT LUPD DIR
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: CTRLBSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Clear register (CTRLBCLR).
Note: This register is read- and write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the
CTRLBSET register synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CMD[2:0] ONESHOT LUPD DIR
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Important: This command requires synchronization before being executed. A valid sequence is:
• Issue CMD command (CTRLBSET.CMD = command)
• Wait for CMD synchronization (SYNCBUSY.CTRLB = 0)
• Wait for CMD read back as zero (CTRLBSET.CMD = 0)
Value Description
1 The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on
hardware update condition.
Name: EVCTRL
Offset: 0x06
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit 15 14 13 12 11 10 9 8
MCEO1 MCEO0 OVFEO
Access R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
TCEI TCINV EVACT[2:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: INTENCLR
Offset: 0x08
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
MC1 MC0 ERR OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTENSET
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
MC1 MC0 ERR OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTFLAG
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
MC1 MC0 ERR OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
33.9.8 Status
Name: STATUS
Offset: 0x0B
Reset: 0x01
Property: Read-Synchronized, Write-Synchronized
Note: This register is read- and write-synchronized: SYNCBUSY.STATUS must be checked to ensure the STATUS
register synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CCBUFV1 CCBUFV0 SLAVE STOP
Access R/W R/W R/W R
Reset 0 0 0 1
Name: WAVE
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
WAVEGEN[1:0]
Access R/W R/W
Reset 0 0
1) This depends on the TC mode: In 8-bit mode, the top value is the Period Value register (PER). In 16-bit and 32-bit
mode it is the respective Max. value.
Name: DRVCTRL
Offset: 0x0D
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
INVEN1 INVEN0
Access R/W R/W
Reset 0 0
Name: DBGCTRL
Offset: 0x0F
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CC1 CC0 COUNT STATUS CTRLB ENABLE SWRST
Access R R R R R R R
Reset 0 0 0 0 0 0 0
Name: COUNT
Offset: 0x14
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Notes:
1. This register is read-synchronized: prior to any read access, this register must be synchronized by user by
writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
2. This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register
synchronization is complete.
Bit 31 30 29 28 27 26 25 24
COUNT[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
COUNT[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
COUNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
COUNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CCx
Offset: 0x1C + x*0x04 [x=0..1]
Reset: 0x00000000
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit 31 30 29 28 27 26 25 24
CC[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CC[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CC[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CC[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: CCBUFx
Offset: 0x30 + x*0x04 [x=0..1]
Reset: 0x00000000
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit 31 30 29 28 27 26 25 24
CCBUF[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CCBUF[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CCBUF[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CCBUF[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
34.1 Overview
The device provides three instances of the Timer/Counter for Control (TCC) applications peripheral, TCC[2:0].
Each TCC instance consists of a counter, a prescaler, compare/capture channels and control logic. The counter can
be set to count events or clock pulses. The counter together with the compare/capture channels can be configured
to time stamp input events, allowing capture of frequency and pulse-width. It can also perform waveform generation,
such as frequency generation and pulse-width modulation.
Waveform extensions are featured for motor control, ballast, LED, H-bridge, power converters, and other types of
power control applications. They allow for low-side and high-side output with optional dead-time insertion. Waveform
extensions can also generate a synchronized bit pattern across the waveform output pins. The fault options enable
fault protection for safe and deterministic handling, disabling and/or shut down of external drivers.
Note: The TCC configurations, such as channel numbers and features, may be reduced for some of the TCC
instances.
34.2 Features
• Up to four compare/capture channels (CC) with:
– Double buffered period setting
– Double buffered compare or capture channel
– Circular buffer on period and compare channel registers
• Waveform generation:
– Frequency generation
– Single-slope pulse-width modulation (PWM)
– Dual-slope PWM with half-cycle reload capability
• Input capture:
– Event capture
– Frequency capture
– Pulse-width capture
• Waveform extensions:
– Configurable distribution of compare channels outputs across port pins
– Low-side and high-side output with programmable dead-time insertion
– Waveform swap option with double buffer support
– Pattern generation with double buffer support
– Dithering support
• Fault protection for safe disabling of drivers:
– Two recoverable fault sources
– Two non-recoverable fault sources
– Debugger can be a source of non-recoverable fault
• Input events:
– Two input events (EVx) for counter
– One input event (MCx) for each channel
• Output events:
– Three output events (Count, Re-Trigger and Overflow) are available for counter
– One Compare Match/Input Capture event output for each channel
• Interrupts:
– Overflow and Re-Trigger interrupt
TCC# Channels Waveform Counter size Fault Dithering Output Dead Time SWAP Pattern
(CC_NUM) Output matrix Insertion generation
(WO_NUM) (DTI)
2 2 2 16-bit Yes
Note: The number of CC registers (CC_NUM) for each TCC corresponds to the number of compare/capture
channels, therefore a TCC can have more Waveform Outputs (WO_NUM) than CC registers.
BV PERBUFx
PER Prescaler
"count"
Counter OVF (INT/Event/DMA Req.)
"clear"
ERR (INT Req.)
"load"
COUNT Control Logic
"direction"
"TCCx_EV0" (TCE0)
"TCCx_EV1" (TCE1)
TOP
UPDATE
= "TCCx_MCx" Event
"event"
System
BOTTOM
=0
WO[7]
WO[6]
Compare/Capture
(Unit x = {0,1,…,3})
WO[5]
Non-recoverable
Generation
WO[4]
Pattern
Faults
SWAP
Output
Matrix
"capture" WO[3]
BV CCBUFx Control Logic
WO[2]
Dead-Time
Insertion
WO[1]
Recoverable
CCx
Faults
Waveform
Generation
WO[0]
"match"
= MCx (INT/Event/DMA Req.)
...........continued
Pin Name Type Description
TCCx/WO[1] Digital output Compare channel 1 waveform output
… ... ...
TCCx/WO[WO_NUM-1] Digital output Compare channel n waveform output
Refer to the 4. Pinout and Packaging for details on the pin mapping for this peripheral. One signal can be mapped on
several pins.
35: OVF
9-10: EV0-1 10: OVF
36: TRG
TCC0 0x42002400 13 - N 23 9 N Y
37: NT
11-14: MC0-3 11-14: MC0-3
38-41: MC0-3
42: OVF
15-16: EV0-1 15: OVF
43: TRG
TCC1 0x42002800 14 - N 23 10 N Y
44:CNT
17-18: MC0-1 16-17: MC0-1
45-46: MC0-1
47: OVF
19-20: EV0-1 18: OVF
48: TRG
TCC2 0x42002C00 15 - N 24 11 N Y
49: CNT
21-22: MC0-1 19-20: MC0-1
50-51 MC0-1
Name Description
TOP The counter reaches TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be the same as Period (PER) or the
Compare Channel 0 (CC0) register value depending on the waveform generator
mode in 34.6.2.5.1 Waveform Output Generation Operations.
ZERO The counter reaches ZERO when it contains all zeroes.
MAX The counter reaches maximum when it contains all ones.
UPDATE The timer/counter signals an update when it reaches ZERO or TOP, depending
on the direction settings.
...........continued
Name Description
Timer Increment / decrement / clear / reload steps are done on each prescaled clock.
Counter Increment / decrement / clear / reload steps is done on each detected events.
CC For compare operations, the CC are referred to as "compare channels."
For capture operations, the CC are referred to as "capture channels."
Note: MCE0 and MCE1 can also be used as non-recoverable event source.
If the filter options are not used, the non-recoverable faults provide an immediate asynchronous action on waveform
output, even for cases where the clock is not present. For further details on how to configure asynchronous events
routing, refer to section EVSYS – Event System.
34.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the TCC is
disabled(CTRLA.ENABLE=0):
• Control A (CTRLA) register, except Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset
(SWRST) bits
• Recoverable Fault n Control registers (FCTRLA and FCTRLB)
• Waveform Extension Control register (WEXCTRL)
• Drive Control register (DRVCTRL)
• Event Control register (EVCTRL)
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1',
but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the “Enable-Protected”
property in the register description.
Before the TCC is enabled, it must be configured as outlined by the following steps:
1. Enable the TCC bus clock (CLK_TCCx_APB).
2. If Capture mode is required, enable the channel in capture mode by writing a '1' to the Capture Enable bit in
the Control A register (CTRLA.CPTEN).
Optionally, the following configurations can be set before enabling TCC:
1. Select PRESCALER setting in the Control A register (CTRLA.PRESCALER).
2. Select Prescaler Synchronization setting in Control A register (CTRLA.PRESCSYNC).
3. If down-counting operation is desired, write the Counter Direction bit in the Control B Set register
(CTRLBSET.DIR) to '1'.
4. Select the Waveform Generation operation in the WAVE register (WAVE.WAVEGEN).
5. Select the Waveform Output Polarity in the WAVE register (WAVE.POL).
6. The waveform output can be inverted for the individual channels using the Waveform Output Invert Enable bit
group in the Driver register (DRVCTRL.INVEN).
Note: Two instances of the TCC (TCC0 and TCC1) may share a peripheral clock channel. In this case, they cannot
be set to different clock frequencies. Refer to the peripheral clock channel mapping of the Generic Clock Controller
(GCLK.PCHTRLm) to identify shared peripheral clocks.
Prescaler outputs from 1 to 1/1024 are available. For a complete list of available prescaler outputs, see the register
description for the Prescaler bit group in the Control A register (CTRLA.PRESCALER).
Note: When counting events, the prescaler is bypassed.
The joint stream of prescaler ticks and event action ticks is called CLK_TCC_COUNT.
Figure 34-2. Prescaler
GCLK_TCC PRESCALER
GCLK_TCC / COUNT
{1,2,4,8,64,256,1024 } TCCx EV0/1 CLK_TCC_COUNT
MAX
"reload" update
"clear" update
TOP
COUNT
ZERO
DIR
It is possible to change the counter value (by writing directly in the COUNT register) even when the counter
is running. The COUNT value will always be ZERO or TOP, depending on direction set by CTRLBSET.DIR or
CTRLBCLR.DIR, when starting the TCC, unless a different value has been written to it, or the TCC has been stopped
at a value other than ZERO. The write access has higher priority than count, clear, or reload. The direction of the
counter can also be changed during normal operation. See the figure 34-3 above for further information.
Stop Command
A stop command can be issued from software by using TCC Command bits in Control B Set register
(CTRLBSET.CMD=0x2, STOP).
When a stop is detected while the counter is running, the counter will maintain its current value. If the waveform
generation (WG) is used, all waveforms are set to a state defined in Non-Recoverable State x Output Enable bit and
Non- Recoverable State x Output Value bit in the Driver Control register (DRVCTRL.NREx and DRVCTRL.NRVx),
and the Stop bit in the Status register is set (STATUS.STOP).
The decrement event action can be selected in the Event Control register (EVCTRL.EVACT1=0x4, DEC) and can
change the counter state when an event is received. When the TCE1 (TCCx_EV1) event is received, the counter
decrements, whatever the direction setting (CTRLBSET.DIR or CTRLBCLR.DIR) is.
Non-recoverable Fault Event Action
Non-recoverable fault actions can be selected in the Event Control register (EVCTRL.EVACTx=0x7, FAULT). When
received, the counter will be stopped and the output of the compare channels is overridden according to the
Driver Control register settings (DRVCTRL.NREx and DRVCTRL.NRVx). TCE0 and TCE1 must be configured as
asynchronous events.
Event Action Off
If the event action is disabled (EVCTRL.EVACTx=0x0, OFF), enabling the counter will also start the counter.
34.6.2.5 Compare Operations
By default, the Compare/Capture channel is configured for compare operations. To perform capture operations, it
must be re-configured.
When using the TCC with the Compare/Capture Value registers (CCx) for compare operations, the counter value is
continuously compared to the values in the CCx registers. This can be used for timer or for waveform operation.
The Channel x Compare/Capture Buffer Value (CCBUFx) registers provide double buffer capability. The double
buffering synchronizes the update of the CCx register with the buffer value at the UPDATE condition or a force
update command (CTRLBSET.CMD=0x3, UPDATE). For further details, refer to 34.6.2.6 Double Buffering. The
synchronization prevents the occurrence of odd-length, non-symmetrical pulses and ensures glitch-free output.
34.6.2.5.1 Waveform Output Generation Operations
The compare channels can be used for waveform generation on output port pins. To make the waveform available on
the connected pin, the following requirements must be fulfilled:
1. Choose a waveform generation mode in the Waveform Generation Operation bit in Waveform register
(WAVE.WAVEGEN).
2. Optionally invert the waveform output WO[x] by writing the corresponding Waveform Output x Inversion bit in
the Driver Control register (DRVCTRL.INVENx).
3. Configure the pins with the I/O Pin Controller. Refer to the PORT - I/O Pin Controller for details.
Note: Event MCx must not be used when the compare channel is set in waveform output operating mode, except
when used as non-recoverable fault input.
The counter value is continuously compared with each CCx value. On a comparison match, the Match or Capture
Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set on the next zero-to-one
transition of CLK_TCC_COUNT (see Normal Frequency Operation). An interrupt and/or event can be generated on
the same condition if Match/Capture occurs, i.e. INTENSET.MCx and/or EVCTRL.MCEOx is '1'. Both interrupt and
event can be generated simultaneously. The same condition generates a DMA request.
There are seven waveform configurations for the Waveform Generation Operation bit group in the Waveform register
(WAVE.WAVEGEN). This will influence how the waveform is generated and impose restrictions on the top value. The
configurations are:
• Normal Frequency (NFRQ)
• Match Frequency (MFRQ)
• Normal Pulse-Width Modulation (NPWM)
• Dual-slope, interrupt/event at TOP (DSTOP)
• Dual-slope, interrupt/event at ZERO (DSBOTTOM)
• Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
• Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
When using MFRQ configuration, the TOP value is defined by the CC0 register value. For the other waveform
operations, the TOP value is defined by the Period (PER) register value.
For dual-slope waveform operations, the update time occurs when the counter reaches ZERO. For the other
waveforms generation modes, the update time occurs on counter wraparound, on overflow, underflow, or re-trigger.
The table below shows the update counter and overflow event/interrupt generation conditions in different operation
modes.
1. The UPDATE condition on TOP only will occur when circular buffer is enabled for the channel.
CCx
ZERO
WO[x]
MAX
"reload" update
"clear" update
CC0
COUNT
ZERO
WO[0]
34.6.2.5.4 Normal Pulse-Width Modulation (NPWM)
NPWM uses single-slope PWM generation.
COUNT
CCx
ZERO
WO[x]
The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform:
log(TOP+1)
RPWM_SS =
log(2)
The PWM frequency depends on the Period register value (PER) and the peripheral clock frequency (fGCLK_TCC), and
can be calculated by the following equation:
fGCLK_TCC
fPWM_SS =
N(TOP+1)
Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).
CCx
TOP
COUNT
ZERO
WO[x]
Using dual-slope PWM results in a lower maximum operation frequency compared to single-slope PWM generation.
The period (TOP) defines the PWM resolution. The minimum resolution is 1 bit (TOP=0x00000001).
The following equation calculates the exact resolution for dual-slope PWM (RPWM_DS):
log(TOP+1)
RPWM_DS = .
log(2)
The PWM frequency fPWM_DS depends on the period setting (TOP) and the peripheral clock frequency fGCLK_TCC, and
can be calculated by the following equation (outside of DSBOTH mode):
fGCLK_TCC
fPWM_DS =
2N ⋅ TOP
N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the TCC
clock frequency (fGCLK_TCC) when TOP is set to 0x00000001 and no prescaling is used.
The pulse width (PPWM_DS) depends on the compare channel (CCx) register value and the peripheral clock frequency
(fGCLK_TCC), and can be calculated by the following equation:
2N ⋅ TOP − CCx
PPWM_DS =
fGCLK_TCC
TOP
COUNT
ZERO
WO[x]
In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform output.
BV EN CCBUFx
EN CCx
UPDATE
COUNT
"match"
=
Both the registers (PATT/PER/CCx) and corresponding Buffer registers (PATTBUF/PERBUF/CCBUFx) are available
in the I/O register map, and the double buffering feature is not mandatory. The double buffering is disabled by writing
a '1' to CTRLSET.LUPD.
Note: When NFRQ, MFRQ or PWM down-counting counter mode (CTRLBSET.DIR=1), is enabled and double
buffering is enabled (CTRLBCLR.LUPD=1), PERBUF register is continuously copied into the PER independently of
update conditions.
MAX
"clear" update
"write"
COUNT
ZERO
MAX
"reload" update
"write"
COUNT
ZERO
MAX
"reload" update
"write"
COUNT
ZERO
MAX
"reload" update
"write"
COUNT
ZERO
events
MAX
COUNT
ZERO
For input capture, the buffer register and the corresponding CCx act like a FIFO. When CCx is empty or read,
any content in CCBUFx is transferred to CCx. The buffer valid flag is passed to set the CCx interrupt flag (IF) and
generate the optional interrupt, event or DMA request. CCBUFx register value can't be read, all captured data must
be read from CCx register.
Figure 34-15. Capture Double Buffering
"capture" COUNT
BUFV EN CCBUFx
IF EN CCx
"INT/DMA
request" data read
The TCC can detect capture overflow of the input capture channels: When a new capture event is detected while the
Capture Buffer Valid flag (STATUS.CCBUFV) is still set, the new timestamp will not be stored and INTFLAG.ERR will
be set.
Period and Pulse-Width (PPW) Capture Action
The TCC can perform two input captures and restart the counter on one of the edges. This enables the TCC to
measure the pulse-width and period and to characterize the frequency f and dutyCycle of an input signal:
tp
f= 1 , dutyCycle =
T T
Figure 34-16. PWP Capture
Period (T)
external
signal /event
capture times
MAX
"capture"
COUNT
ZERO
CC0 CC1 CC0 CC1
Selecting PWP or PPW in the Timer/Counter Event Input 1 Action bit group in the Event Control register
(EVCTRL.EVACT1) enables the TCC to perform one capture action on the rising edge and the other one on the
falling edge. When using PPW (period and pulse-width) event action, period T will be captured into CC0 and the
pulse-width tp into CC1. The PWP (Pulse-width and Period) event action offers the same functionality, but T will be
captured into CC1 and tp into CC0.
The Timer/Counter Event x Invert Enable bit in Event Control register (EVCTRL.TCEINVx) is used for event source
x to select whether the wraparound should occur on the rising edge or the falling edge. If EVCTRL.TCEINVx=1, the
wraparound will happen on the falling edge.
The corresponding capture is done only if the channel is enabled in capture mode (CTRLA.CPTENx=1). If not, the
capture action will be ignored and the channel will be enabled in compare mode of operation. When only one of these
channel is required, the other channel can be used for other purposes.
The TCC can detect capture overflow of the input capture channels: When a new capture event is detected while the
INTFLAG.MCx is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
Note: When up-counting (CTRLBSET.DIR=0), counter values lower than 1 cannot be captured in Capture Minimum
mode (FCTRLn.CAPTURE=CAPTMIN). To capture the full range including value 0, the TCC must be configured in
down-counting mode (CTRLBSET.DIR=0).
Note: In dual-slope PWM operation, and when TOP is lower than MAX/2, the CCx MSB captures the CTRLB.DIR
state to identify the ramp on which the capture has been done. For rising ramps CCx[MSB] is zero, for falling ramps
CCx[MSB]=1.
UPDATE
BUFV EN CCBUF0
CIRCC0EN
EN CC0
UPDATE
COUNT
"ma tch"
=
34.6.3.3 Dithering Operation
The TCC supports dithering on Pulse-width or Period on a 16, 32 or 64 PWM cycles frame. The TCC does not
support dithering with any RAMP2 operation.
Dithering consists in adding some extra clocks cycles in a frame of several PWM cycles, and can improve the
accuracy of the average output pulse width and period. The extra clock cycles are added on some of the compare
match signals, one at a time, through a "blue noise" process that minimizes the flickering on the resulting dither
patterns. The use of dithering with an external retrigger event (EVCTRL.EVACTx) is not possible as the event can
lead to unexpected stretch of right aligned pulses, or shrinking of left aligned pulses.
Dithering is enabled by writing the corresponding configuration in the Enhanced Resolution bits in CTRLA register
(CTRLA.RESOLUTION):
• DITH4 enable dithering every 16 PWM frames
• DITH5 enable dithering every 32 PWM frames
• DITH6 enable dithering every 64 PWM frames
The DITHERCY bits of COUNT, PER and CCx define the dithercy increment value and so the number of extra cycles
to add into the frame (DITHERCY bits from the respective COUNT, PER or CCx registers). The remaining bits of
COUNT, PER, CCx define the compare value itself.
The pseudo code, giving the extra cycles insertion regarding the cycle is:
Dithering on Period
Writing DITHERCY in PER will lead to an average PWM period configured by the following formulas.
DITH4 mode:
Note: If DITH4 mode is enabled, the last 4 significant bits from PER/CCx register correspond to the DITHERCY
value (the last 4 significant bits from COUNT are always read as 0), rest of the bits corresponds to PER/CCx or
COUNT value.
DITH5 mode:
DITH6 mode:
DITH5 mode:
DITH6 mode:
RAMP1 Operation
This is the default PWM operation, described in Single-Slope PWM Generation.
RAMP2 Operation
These operation modes are dedicated for power factor correction (PFC), Half-Bridge and Push-Pull SMPS
topologies, where two consecutive timer/counter cycles are interleaved. In cycle A, odd channel output is disabled,
and in cycle B, even channel output is disabled. The ramp index changes after each update, but can be software
modified using the Ramp index command bits in Control B Set register (CTRLBSET.IDXCMD). All RAMP2 operations
only support counting up mode (CTRLB.DIR = 0).
ZERO
WO[0] POL0 = 1
FaultA input
FaultB input
ZERO
WO[0]
Keep on FaultB POL0 = 1
WO[1]
FaultA input
FaultB input
ZERO
WO[0] POL2 = 1
FaultA input
FaultB input
ZERO
WO[0] POL0 = 0
FaultA input
FaultB input
Fault Inputs
The first two channel input events (TCCxMC0 and TCCxMC1) can be used as Fault A and Fault B inputs,
respectively. Event system channels connected to these fault inputs must be configured as asynchronous. The TCC
must work in a PWM mode.
Fault Filtering
There are three filters available for each input Fault A and Fault B. They are configured by the corresponding
Recoverable Fault n Configuration registers (FCTRLA and FCTRLB). The three filters can either be used
independently or in any combination.
Input By default, the event detection is asynchronous. When the event occurs, the fault system will
Filtering immediately and asynchronously perform the selected fault action on the compare channel output,
also in device power modes where the clock is not available. To avoid false fault detection on external
events (e.g. due to a glitch on an I/O port) a digital filter can be enabled and configured by the Fault
B Filter Value bits in the Fault n Configuration registers (FCTRLn.FILTERVAL). If the event width is
less than FILTERVAL (in clock cycles), the event will be discarded. A valid event will be delayed by
FILTERVAL clock cycles.
Fault This ignores any fault input for a certain time just after a selected waveform output edge. This can be
Blanking used to prevent false fault triggering due to signal bouncing, as shown in the figure below. Blanking
can be enabled by writing an edge triggering configuration to the Fault n Blanking Mode bits in the
Recoverable Fault n Configuration register (FCTRLn.BLANK). The desired duration of the blanking
must be written to the Fault n Blanking Time bits (FCTRLn.BLANKVAL).
The blanking time, tb is calculated by
tb = 1 + BLANKVAL
fGCLK_TCCx_PRESC
Where,
fGCLK_TCCx_PRESC is the frequency of the prescaled peripheral clock frequency fGCLK_TCCx. The
prescaler is enabled by writing '1' to the Fault n Blanking Prescaler bit (FCTRLn.BLANKPRESC).
When disabled, fGCLK_TCCx_PRESC=fGCLK_TCCx. When enabled, fGCLK_TCCx_PRESC=fGCLK_TCCx/64.
The maximum blanking time (FCTRLn.BLANKVAL=
255) at fGCLK_TCCx=96MHz is 2.67µs (no prescaler) or 170µs (prescaling). For fGCLK_TCCx=1MHz, the
maximum blanking time is either 170µs (no prescaling) or 10.9ms (prescaling enabled).
ZERO
CMP0
FaultA Blanking - -
x xxx
FaultA Input
WO[0]
Fault This is enabled by writing a '1' to the Fault n Qualification bit in the Recoverable Fault n
Qualification Configuration register (FCTRLn.QUAL). When the recoverable fault qualification is enabled
(FCTRLn.QUAL=1), the fault input is disabled all the time the corresponding channel output
has an inactive level, as shown in the figures below.
"Fault discarded"
ZERO
Fault Input A
Fault Input B
ZERO
Fault Input A
Fault Input B
Fault Actions
Different fault actions can be configured individually for Fault A and Fault B. Most fault actions are not mutually
exclusive; therefore two or more actions can be enabled at the same time to achieve a result that is a combination of
fault actions.
Keep This is enabled by writing the Fault n Keeper bit in the Recoverable Fault n Configuration register
Action (FCTRLn.KEEP) to '1'. When enabled, the corresponding channel output will be clamped to zero as
long as the fault condition is present. The clamp will be released on the start of the first cycle after the
fault condition is no longer present, see next Figure.
"Fault discarded"
ZERO
Fault Input A
Restart This is enabled by writing the Fault n Restart bit in Recoverable Fault n Configuration register
Action (FCTRLn.RESTART) to '1'. When enabled, the timer/counter will be restarted as soon as the
corresponding fault condition is present. The ongoing cycle is stopped and the timer/counter starts a
new cycle, see the following figures. In Ramp 1 mode, when the new cycle starts, the compare outputs
will be clamped to inactive level as long as the fault condition is present.
Note: For RAMP2 operation, when a new timer/counter cycle starts the cycle index will change
automatically, see the following figures. Fault A and Fault B are qualified only during the cycle A and
cycle B respectively: Fault A is disabled during cycle B, and Fault B is disabled during cycle A.
CC0
COUNT
CC1
ZERO
Restart Restart
Fault Input A
WO[0]
WO[1]
Figure 34-27. Waveform Generation in RAMP2 mode with Restart Action
Cycle
"clear" update
CCx=ZERO CCx=TOP "match"
MAX
TOP
COUNT
CC0/CC1
ZERO
No fault A action
in cycle B Restart
Fault Input A
WO[0]
WO[1]
Capture Several capture actions can be selected by writing the Fault n Capture Action bits in the Fault n Control
Action register (FCTRLn.CAPTURE). When one of the capture operations is selected, the counter value is
captured when the fault occurs. These capture operations are available:
• CAPT - The equivalent to a standard capture operation, for further details refer to 34.6.2.7 Capture
Operations
• CAPTMIN - Gets the minimum time stamped value: on each new local minimum captured value, an
event or interrupt is issued.
• CAPTMAX - Gets the maximum time stamped value: on each new local maximum captured value,
an event or interrupt (IT) is issued. For additional information, refer to the following figure Capture
Action “CAPTMAX”.
• LOCMIN - Notifies by event or interrupt when a local minimum captured value is detected.
• LOCMAX - Notifies by event or interrupt when a local maximum captured value is detected.
• DERIV0 - Notifies by event or interrupt when a local extreme captured value is detected, For more
information, reference the following figure Capture Action “DERIV0”.
CCx Content:
In CAPTMIN and CAPTMAX operations, CCx keeps the respective extreme captured values, For
more information, reference the following figure Capture Action “CAPTMAX”. In LOCMIN, LOCMAX
or DERIV0 operation, CCx follows the counter value at fault time, For more information, reference the
following figure Capture Action “DERIV0”.
Before enabling CAPTMIN or CAPTMAX mode of capture, the user must initialize the corresponding
CCx register value to a value different from zero (for CAPTMIN) or top (for CAPTMAX). If the CCx
register initial value is zero (for CAPTMIN) or top (for CAPTMAX), no captures will be performed using
the corresponding channel.
When using advanced capture functions like CAPTMIN, CAPTMAX, LOCMIN, LOCMAX and DERIV0,
standard capture functions (CAPT) must be assigned to the lower CCx channels when used. See the
example below.
Example: CC[0] = CAPT, CC[1] = CAPT, CC[2] = CAPTMIN, CC[3] = CAPTMAX.
MCx Behaviour:
In LOCMIN and LOCMAX operation, capture is performed on each capture event. The MCx interrupt
flag is set only when the captured value is above or equal (for LOCMIN) or below or equal (for
LOCMAX) to the previous captured value. So interrupt flag is set when a new relative local Minimum
(for CAPTMIN) or Maximum (for CAPTMAX) value has been detected. DERIV0 is equivalent to an OR
function of (LOCMIN, LOCMAX).
In CAPT operation, capture is performed on each capture event. The MCx interrupt flag is set on each
new capture.
In CAPTMIN and CAPTMAX operation, capture is performed only when on capture event time, the
counter value is lower (for CAPTMIN) or higher (for CAPMAX) than the last captured value. The MCx
interrupt flag is set only when on capture event time, the counter value is higher or equal (for CAPTMIN)
or lower or equal (for CAPTMAX) to the value captured on the previous event. So interrupt flag is
set when a new absolute local Minimum (for CAPTMIN) or Maximum (for CAPTMAX) value has been
detected.
Interrupt Generation
In CAPT mode, an interrupt is generated on each filtered Fault n and each dedicated CCx channel
capture counter value. In other modes, an interrupt is only generated on an extreme captured value.
TOP
"clear" update
COUNT CC0
ZERO
FaultA Input
CC0 Event/
Interrupt
TOP
"update"
COUNT CC0 "match"
ZERO
WO[0]
FaultA Input
CC0 Event/
Interrupt
Hardware This is configured by writing 0x1 to the Fault n Halt mode bits in the Recoverable Fault n
Halt Action Configuration register (FCTRLn.HALT). When enabled, the timer/counter is halted and the cycle is
extended as long as the corresponding fault is present.
The next figure ('Waveform Generation with Halt and Restart Actions') shows an example where
both restart action and hardware halt action are enabled for Fault A. The compare channel 0 output
is clamped to inactive level as long as the timer/counter is halted. The timer/counter resumes the
counting operation as soon as the fault condition is no longer present. As the restart action is enabled
in this example, the timer/counter is restarted after the fault condition is no longer present.
The figure after that ('Waveform Generation with Fault Qualification, Halt, and Restart Actions') shows
a similar example, but with additionally enabled fault qualification. Here, counting is resumed after the
fault condition is no longer present.
Note that in RAMP2 and RAMP2A operations, when a new timer/counter cycle starts, the cycle index
will automatically change.
Figure 34-30. Waveform Generation with Halt and Restart Actions
MAX
"clear" update
TOP
"match"
CC0
COUNT
HALT
ZERO
Restart Restart
Fault Input A
WO[0]
Figure 34-31. Waveform Generation with Fault Qualification, Halt, and Restart Actions
MAX
"update"
TOP
"match"
COUNT CC0
HALT
ZERO
Resume
Fault Input A
WO[0] KEEP
Software This is configured by writing 0x2 to the Fault n Halt mode bits in the Recoverable Fault n
Halt Action configuration register (FCTRLn.HALT). Software halt action is similar to hardware halt action, but
in order to restart the timer/counter, the corresponding fault condition must not be present anymore,
and the corresponding FAULT n bit in the STATUS register must be cleared by software.
Figure 34-32. Waveform Generation with Software Halt, Fault Qualification, Keep and Restart Actions
MAX
"update"
TOP
"match"
COUNT CC0
HALT
ZERO
Restart Restart
Fault Input A
Software Clear
NO
WO[0] KEEP
KEEP
FCTRLA.KEEP = 1 FCTRLA.KEEP = 0
In RAMP2, RAMP2A, or DSBOTH operation, when the Lock Update bit in the Control B register is set by writing
CTRLBSET.LUPD=1 and the ramp index or counter direction changes, a non-recoverable Update Fault State and the
respective interrupt (UFS) are generated.
OTMX[x+WO_NUM/2] PGV[x+WO_NUM/2]
P[x+WO_NUM/2]
LS
PGO[x+WO_NUM/2] INV[x+WO_NUM/2]
OTMX DTIx DTIxEN SWAPx
PGO[x] INV[x]
HS
P[x]
OTMX[x] PGV[x]
The output matrix (OTMX) unit distributes compare channels, according to the selectable configurations in the table
below.
Table 34-5. Output Matrix Channel Pin Routing Configuration
Value OTMX[x]
0x0 CC3 CC2 CC1 CC0 CC3 CC2 CC1 CC0
0x1 CC1 CC0 CC1 CC0 CC1 CC0 CC1 CC0
0x2 CC0 CC0 CC0 CC0 CC0 CC0 CC0 CC0
0x3 CC1 CC1 CC1 CC1 CC1 CC1 CC1 CC0
The following comments provide an explanation for each of the four Output Matrix Chanel Pin Routing
Configurations.
:
• Configuration 0x0 is the default configuration. The channel location is the default one, and channels are
distributed on outputs modulo the number of channels. Channel 0 is routed to the Output matrix output
OTMX[0], and Channel 1 to OTMX[1]. If there are more outputs than channels, then channel 0 is duplicated
to the Output matrix output OTMX[CC_NUM], channel 1 to OTMX[CC_NUM+1] and so on.
• Configuration 0x1 distributes the channels on output modulo half the number of channels. This assigns twice the
number of output locations to the lower channels than the default configuration. This can be used, for example,
to control the four transistors of a full bridge using only two compare channels.
Using pattern generation, some of these four outputs can be overwritten by a constant level, enabling flexible
drive of a full bridge in all quadrant configurations.
• Configuration 0x2 distributes compare channel 0 (CC0) to all port pins. With pattern generation, this
configuration can control a stepper motor.
• Configuration 0x3 distributes the compare channel CC0 to the first output, and the channel CC1 to all other
outputs. Together with pattern generation and the fault extension, this configuration can control up to seven LED
strings, with a boost stage.
Table
• 34-6. Example: four compare channels on four outputs
The dead-time insertion (DTI) unit generates OFF time with the non-inverted low side (LS) and inverted high side
(HS) of the wave generator output forced at low level. This OFF time is called dead time. Dead-time insertion ensures
that the LS and HS will never switch simultaneously.
The DTI stage consists of four equal dead-time insertion generators; one for each of the first four compare channels.
Figure 34-34 shows the block diagram of one DTI generator. The four channels have a common register which
controls the dead time, which is independent of high side and low side setting.
Figure 34-34. Dead-Time Generator Block Diagram
DTLS DTHS
LOAD
Counter
EN
=0
"DTLS"
OTMX output D Q (To PORT)
"DTHS"
Edge Detect (To PORT)
As shown in Figure 34-35, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle until it
reaches zero. A non-zero counter value will force both the low side and high side outputs into their OFF state. When
the output matrix (OTMX) output changes, the dead-time counter is reloaded according to the edge of the input.
When the output changes from low to high (positive edge) it initiates a counter reload of the DTLS register. When the
output changes from high to low (negative edge) it reloads the DTHS register.
"dti_cnt"
T
tP
tDTILS t DTIHS
"OTMX output"
"DTLS"
"DTHS"
The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to. The pattern
generation features are primarily intended for handling the commutation sequence in brushless DC motors (BLDC),
stepper motors, and full bridge control. See also Figure 34-36.
Figure 34-36. Pattern Generator Block Diagram
COUNT
UPDATE
EN PGE[7:0] EN PGV[7:0]
WOx[7:0]
As with other double-buffered timer/counter registers, the register update is synchronized to the UPDATE condition
set by the timer/counter waveform generation operation. If synchronization is not required by the application, the
software can simply access directly the PATT.PGE, PATT.PGV bits registers.
...........continued
Condition Interrupt Event Event input DMA DMA request is cleared
request output request
Channel Compare Match or Yes Yes Yes(2) Yes(3) For circular buffering: on
Capture DMA acknowledge
For capture channel:
when CCx register is
read
Notes:
1. DMA request set on overflow, underflow or re-trigger conditions.
2. Can perform capture or generate recoverable fault on an event input.
3. In capture or circular modes.
4. On event input, either action can be executed:
– Re-trigger counter
– Control counter direction
– Stop the counter
– Decrement the counter
– Perform period and pulse width capture
– Generate non-recoverable fault
5. On event input, either action can be executed:
– Re-trigger counter
– Increment or decrement counter depending on direction
– Start the counter
– Increment or decrement counter based on direction
– Increment counter regardless of direction
– Generate non-recoverable fault
Counter If the Ones-shot Trigger mode in the control A register (CTRLA.DMAOS) is written to '0', the
overflow TCC generates a DMA request on each cycle when an update condition (overflow, underflow or
(OVF) re-trigger) is detected.
When an update condition (overflow, underflow or re-trigger) is detected while CTRLA.DMAOS=1,
the TCC generates a DMA trigger on the cycle following the DMA One-Shot Command written to
the Control B register (CTRLBSET.CMD=DMAOS).
In both cases, the request is cleared by hardware on DMA acknowledge.
Channel A DMA request is set only on a compare match if CTRLA.DMAOS=0. The request is cleared by
Match (MCx) hardware on DMA acknowledge.
Channel For a capture channel, the request is set when valid data is present in the CCx register, and cleared
Capture once the CCx register is read.
(MCx) In this operation mode, the CTRLA.DMAOS bit value is ignored.
Ramp A B A B A B
"update"
COUNT
ZERO
STATUS.IDX
DMA_CCx_req
DMA Channel i
Update ramp A
DMA_OVF_req DMA Channel j
Update ramp B
DMA Operation with Circular Buffer in DSBOTH Mode
When a CC channel is selected as a circular buffer, the related DMA request is not set on a compare match
detection, but on start of down-counting phase.
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of up-counting phase
with an effective DMA transfer on previous down-counting phase (DMA acknowledge).
When up-counting, all circular buffer values can be updated through a DMA channel triggered by MC trigger. When
down-counting, all circular buffer values can be updated through a second DMA channel, triggered by the OVF DMA
request.
Figure 34-38. DMA Triggers in DSBOTH Operation Mode and Circular Buffer Enabled
Cycle
N-2 N-1 N
Old Parameter Set New Parameter Set
"update"
COUNT
ZERO
CTRLB.DIR
Update Rising
DMA_OVF_req
DMA Channel j
Update Rising
34.6.5.2 Interrupts
The TCC has the following interrupt sources:
• Overflow/Underflow (OVF)
• Retrigger (TRG)
• Count (CNT), also refer to the description of EVCTRL.CNTSEL.
• Capture Overflow Error (ERR)
• Non-Recoverable Update Fault (UFS)
• Debug Fault State (DFS)
• Recoverable Faults (FAULTn)
• Non-recoverable Faults (FAULTx)
• Compare Match or Capture Channels (MCx)
These interrupts are asynchronous wake-up sources. See Sleep Mode Entry and Exit Table in PM/Sleep Mode
Controller section for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt
flag is cleared, the interrupt is disabled, or the TCC is reset. See 34.7.12 INTFLAG for details on how to clear
interrupt flags. The TCC has one common interrupt request line for all the interrupt sources. The user must read the
INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for more details.
34.6.5.3 Events
The TCC can generate the following output events:
• Overflow/Underflow (OVF)
• Trigger (TRG)
• Counter (CNT) For additional information, refer to EVCTRL.CNTSEL description.
• Compare Match or Capture on compare/capture channels: MCx
Writing a '1' ('0') to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables (disables) the
corresponding output event. For further information, refer to the EVSYS – Event System.
The TCC can take the following actions on a channel input event (MCx):
• Capture event
34.6.8 Synchronization
Some registers (or bit fields within a register) require synchronization when read and/or written. Synchronization
is denoted by the "Read-Synchronized" (or Read-Synchronized Bits) and/or "Write-Synchronized" (or Write-
Synchronized Bits) property in each individual register description. For more details, refer to Register
Synchronization.
...........continued
7:0 COUNT[7:0]
15:8 COUNT[15:8]
0x34 COUNT
23:16 COUNT[23:16]
31:24
7:0 PGE7 PGE6 PGE5 PGE4 PGE3 PGE2 PGE1 PGE0
0x38 PATT
15:8 PGV7 PGV6 PGV5 PGV4 PGV3 PGV2 PGV1 PGV0
0x3A
... Reserved
0x3B
7:0 CIPEREN RAMP[1:0] WAVEGEN[2:0]
15:8 CICCEN3 CICCEN2 CICCEN1 CICCEN0
0x3C WAVE
23:16 POL3 POL2 POL1 POL0
31:24 SWAP3 SWAP2 SWAP1 SWAP0
7:0 PER[1:0] DITHER[5:0]
15:8 PER[9:2]
0x40 PER
23:16 PER[17:10]
31:24
7:0 CC[1:0] DITHER[5:0]
15:8 CC[9:2]
0x44 CC0
23:16 CC[17:10]
31:24
7:0 CC[1:0] DITHER[5:0]
15:8 CC[9:2]
0x48 CC1
23:16 CC[17:10]
31:24
7:0 CC[1:0] DITHER[5:0]
15:8 CC[9:2]
0x4C CC2
23:16 CC[17:10]
31:24
7:0 CC[1:0] DITHER[5:0]
15:8 CC[9:2]
0x50 CC3
23:16 CC[17:10]
31:24
0x54
... Reserved
0x63
7:0 PGEB7 PGEB6 PGEB5 PGEB4 PGEB3 PGEB2 PGEB1 PGEB0
0x64 PATTBUF
15:8 PGVB7 PGVB6 PGVB5 PGVB4 PGVB3 PGVB2 PGVB1 PGVB0
0x66
... Reserved
0x6B
7:0 PERBUF[1:0] DITHERBUF[5:0]
15:8 PERBUF[9:2]
0x6C PERBUF
23:16 PERBUF[17:10]
31:24
7:0 CCBUF[1:0] DITHERBUF[5:0]
15:8 CCBUF[9:2]
0x70 CCBUF0
23:16 CCBUF[17:10]
31:24
7:0 CCBUF[1:0] DITHERBUF[5:0]
15:8 CCBUF[9:2]
0x74 CCBUF1
23:16 CCBUF[17:10]
31:24
7:0 CCBUF[1:0] DITHERBUF[5:0]
15:8 CCBUF[9:2]
0x78 CCBUF2
23:16 CCBUF[17:10]
31:24
...........continued
34.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized (ENABLE, SWRST)
Bit 31 30 29 28 27 26 25 24
CPTEN3 CPTEN2 CPTEN1 CPTEN0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DMAOS
Access R/W
Reset 0
Bit 15 14 13 12 11 10 9 8
MSYNC PRESCSYNC[1:0] RUNSTDBY PRESCALER[2:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RESOLUTION[1:0] ENABLE SWRST
Access R/W R/W R/W R/W
Reset 0 0 0 0
...........continued
Value Name Description
Counter Reloaded Prescaler
0x1 PRESC Reload or reset Counter on next -
prescaler clock
0x2 RESYNC Reload or reset Counter on next GCLK Reset prescaler counter
0x3 Reserved
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value Description
0 The peripheral is disabled.
1 The peripheral is enabled.
Value Description
0 There is no reset operation ongoing.
1 The reset operation is ongoing.
Name: CTRLBCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Set (CTRLBSET) register.
Bit 7 6 5 4 3 2 1 0
CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 2 – ONESHOT One-Shot
This bit controls one-shot operation of the TCC. When one-shot operation is enabled, the TCC will stop counting on
the next overflow/underflow condition or on a stop command.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable the one-shot operation.
Value Description
0 The TCC will update the counter value on overflow/underflow condition and continue operation.
1 The TCC will stop counting on the next underflow/overflow condition.
Name: CTRLBSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Clear (CTRLBCLR) register.
Bit 7 6 5 4 3 2 1 0
CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Important: This command requires synchronization before being executed. A valid sequence is:
• Issue CMD command (CTRLBSET.CMD = command)
• Wait for CMD synchronization (SYNCBUSY.CTRLB = 0)
• Wait for CMD read back as zero (CTRLBSET.CMD = 0)
Bit 2 – ONESHOT One-Shot
This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the next
overflow/underflow condition or a stop command.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable the one-shot operation.
Value Description
0 The TCC will count continuously.
1 The TCC will stop counting on the next underflow/overflow condition.
Name: SYNCBUSY
Offset: 0x08
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
CC3 CC2 CC1 CC0
Access R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PER WAVE PATT COUNT STATUS CTRLB ENABLE SWRST
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24
FILTERVAL[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
BLANKVAL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
BLANKPRESC CAPTURE[2:0] CHSEL[1:0] HALT[1:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RESTART BLANK[1:0] QUAL KEEP SRC[1:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
...........continued
Value Name Description
0x2 CAPTMIN On rising edge of a valid recoverable Fault n, capture counter value on channel selected
by CHSEL[1:0], if COUNT value is lower than the last stored capture value (CC).
INTFLAG.FAULTn flag rises on each local minimum detection.
0x3 CAPTMAX On rising edge of a valid recoverable Fault n, capture counter value on channel selected
by CHSEL[1:0], if COUNT value is higher than the last stored capture value (CC).
INTFLAG.FAULTn flag rises on each local maximun detection.
0x4 LOCMIN On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local minimum value detection.
0x5 LOCMAX On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun detection.
0x6 DERIV0 On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun or minimum detection.
0x7 CAPTMARK Capture with ramp index as MSB value.
Value Description
1 The Fault n state is released at the end of TCC cycle.
Name: WEXCTRL
Offset: 0x14
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
DTHS[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DTLS[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DTIEN3 DTIEN2 DTIEN1 DTIEN0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OTMX[1:0]
Access R/W R/W
Reset 0 0
Name: DRVCTRL
Offset: 0x18
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
FILTERVAL1[3:0] FILTERVAL0[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
INVEN7 INVEN6 INVEN5 INVEN4 INVEN3 INVEN2 INVEN1 INVEN0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
NRV7 NRV6 NRV5 NRV4 NRV3 NRV2 NRV1 NRV0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
NRE7 NRE6 NRE5 NRE4 NRE3 NRE2 NRE1 NRE0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 16, 17, 18, 19, 20, 21, 22, 23 – INVEN Waveform Output x Inversion
These bits are used to select inversion on the output of channel x.
Writing a '1' to INVENx inverts output from WO[x].
Writing a '0' to INVENx disables inversion of output from WO[x].
Bits 8, 9, 10, 11, 12, 13, 14, 15 – NRV NRVx Non-Recoverable State x Output Value
These bits define the value of the enabled override outputs, under non-recoverable fault condition.
Name: DBGCTRL
Offset: 0x1E
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
FDDBD DBGRUN
Access R/W R/W
Reset 0 0
Name: EVCTRL
Offset: 0x20
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
MCEO3 MCEO2 MCEO1 MCEO0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
MCEI3 MCEI2 MCEI1 MCEI0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TCEI1 TCEI0 TCINV1 TCINV0 CNTEO TRGEO OVFEO
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CNTSEL[1:0] EVACT1[2:0] EVACT0[2:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 24, 25, 26, 27 – MCEO Match or Capture Channel x Event Output Enable
These bits control if the match/capture event on channel x is enabled and will be generated for every match or
capture.
Value Description
0 Match/capture x event is disabled and will not be generated.
1 Match/capture x event is enabled and will be generated for every compare/capture on channel x.
Bits 16, 17, 18, 19 – MCEI Match or Capture Channel x Event Input Enable
These bits indicate if the match/capture x incoming event is enabled
These bits are used to enable match or capture input events to the CCx channel of TCC.
Value Description
0 Incoming events are disabled.
1 Incoming events are enabled.
Value Description
0 Counter cycle output event is disabled and will not be generated.
1 Counter cycle output event is enabled and will be generated depend of CNTSEL[1:0] value.
Name: INTENCLR
Offset: 0x24
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
MC3 MC2 MC1 MC0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
FAULT1 FAULT0 FAULTB FAULTA DFS UFS
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ERR CNT TRG OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Writing a '1' to this bit will clear the Recoverable Fault B Interrupt Disable/Enable bit, which disables the Recoverable
Fault B interrupt.
Value Description
0 The Recoverable Fault B interrupt is disabled.
1 The Recoverable Fault B interrupt is enabled.
Value Description
0 The Overflow interrupt is disabled.
1 The Overflow interrupt is enabled.
Name: INTENSET
Offset: 0x28
Reset: 0x00000000
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
MC3 MC2 MC1 MC0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
FAULT1 FAULT0 FAULTB FAULTA DFS UFS
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ERR CNT TRG OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
Writing a '1' to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the Recoverable
Fault B interrupt.
Value Description
0 The Recoverable Fault B interrupt is disabled.
1 The Recoverable Fault B interrupt is enabled.
Value Description
1 The Overflow interrupt is enabled.
Name: INTFLAG
Offset: 0x2C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
MC3 MC2 MC1 MC0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
FAULT1 FAULT0 FAULTB FAULTA DFS UFS
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ERR CNT TRG OVF
Access R/W R/W R/W R/W
Reset 0 0 0 0
34.7.13 Status
Name: STATUS
Offset: 0x30
Reset: 0x00000001
Property: -
When writing the STATUS register ensure only 32-bit writes are made.
Bit 31 30 29 28 27 26 25 24
CMP3 CMP2 CMP1 CMP0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CCBUFV3 CCBUFV2 CCBUFV1 CCBUFV0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
FAULT1 FAULT0 FAULTB FAULTA FAULT1IN FAULT0IN FAULTBIN FAULTAIN
Access R/W R/W R/W R/W R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PERBUFV PATTBUFV SLAVE DFS UFS IDX STOP
Access R/W R/W R R/W R/W R R
Reset 0 0 0 0 0 0 1
Bit 4 – SLAVE Client
This bit is set when TCC is set in Client mode. This bit follows the CTRLA.MSYNC bit state.
Bit 0 – STOP Stop
This bit is set when the TCC is disabled either on a STOP command or on an UPDATE condition when One-Shot
operation mode is enabled (CTRLBSET.ONESHOT=1).
This bit is clear on the next incoming counter increment or decrement.
Value Description
0 Counter is running.
1 Counter is stopped.
Name: COUNT
Offset: 0x34
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Note: Prior to any read access, this register must be synchronized by user by writing the according TCC Command
value to the Control B Set register (CTRLBSET.CMD=READSYNC).
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
COUNT[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
COUNT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
COUNT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
34.7.15 Pattern
Name: PATT
Offset: 0x38
Reset: 0x0000
Property: Write-Synchronized
Bit 15 14 13 12 11 10 9 8
PGV7 PGV6 PGV5 PGV4 PGV3 PGV2 PGV1 PGV0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PGE7 PGE6 PGE5 PGE4 PGE3 PGE2 PGE1 PGE0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PGV Pattern Generation Output Value
This register holds the values of pattern for each waveform output.
34.7.16 Waveform
Name: WAVE
Offset: 0x3C
Reset: 0x00000000
Property: Write-Synchronized
Bit 31 30 29 28 27 26 25 24
SWAP3 SWAP2 SWAP1 SWAP0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 23 22 21 20 19 18 17 16
POL3 POL2 POL1 POL0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CICCEN3 CICCEN2 CICCEN1 CICCEN0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CIPEREN RAMP[1:0] WAVEGEN[2:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
0x0 NFRQ Normal Frequency PER TOP/Zero Toggle Stable TOP Zero
0x1 MFRQ Match Frequency CC0 TOP/Zero Toggle Stable TOP Zero
0x2 NPWM Normal PWM PER TOP/Zero Set Clear TOP Zero
0x3 Reserved - - - - - TOP -
0x4 DSCRITICAL Dual-slope PWM PER Zero ~DIR Stable – Zero
0x5 DSBOTTOM Dual-slope PWM PER Zero ~DIR Stable – Zero
0x6 DSBOTH Dual-slope PWM PER TOP & Zero ~DIR Stable TOP Zero
0x7 DSTOP Dual-slope PWM PER Zero ~DIR Stable TOP –
Name: PER
Offset: 0x40
Reset: 0xFFFFFFFF
Property: Write-Synchronized
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
PER[17:10]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8
PER[9:2]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
PER[1:0] DITHER[5:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: CC
Offset: 0x44 + n*0x04 [n=0..3]
Reset: 0x00000000
Property: Write-Synchronized, Read-Synchronized
The CCx register represents the 16-, 24- bit value, CCx. The register has two functions, depending of the mode of
operation.
For capture operation, this register represents the second buffer level and access point for the CPU and DMA.
For compare operation, this register is continuously compared to the counter value. Normally, the output form the
comparator is then used for generating waveforms.
CCx register is updated with the buffer value from their corresponding CCBUFx register when an UPDATE condition
occurs.
In addition, in match frequency operation, the CC0 register controls the counter period.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
CC[17:10]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CC[9:2]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CC[1:0] DITHER[5:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
Name: PATTBUF
Offset: 0x64
Reset: 0x0000
Property: Write-Synchronized, Read-Synchronized
Bit 15 14 13 12 11 10 9 8
PGVB7 PGVB6 PGVB5 PGVB4 PGVB3 PGVB2 PGVB1 PGVB0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PGEB7 PGEB6 PGEB5 PGEB4 PGEB3 PGEB2 PGEB1 PGEB0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PGVB Pattern Generation Output Value Buffer
This register is the buffer for the PGV register. If double buffering is used, valid content in this register is copied to the
PGV register on an UPDATE condition.
Name: PERBUF
Offset: 0x6C
Reset: 0xFFFFFFFF
Property: Write-Synchronized, Read-Synchronized
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
PERBUF[17:10]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8
PERBUF[9:2]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
PERBUF[1:0] DITHERBUF[5:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 1 1 1 1 1 1
Name: CCBUF
Offset: 0x70 + n*0x04 [n=0..3]
Reset: 0x00000000
Property: Write-Synchronized, Read-Synchronized
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
CCBUF[17:10]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CCBUF[9:2]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CCBUF[1:0] DITHERBUF[5:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
35.1 Overview
The Configurable Custom Logic (CCL) is a programmable logic peripheral which can be connected to the device
pins, events, or other internal peripherals. This enables the user to eliminate logic gates for simple glue logic
functions on the PCB.
Each LookUp Table (LUT) consists of three inputs: a truth table, an optional synchronizer/filter, and an optional edge
detector. Each LUT can generate an output as a user programmable logic expression with three inputs. Inputs can be
individually masked.
The output can be combinatorially generated from the inputs, and can be filtered to remove spikes. Optional
sequential logic can be used. The inputs of the sequential module are individually controlled by two independent,
adjacent LUT (LUT0/LUT1, LUT2/LUT3 and so on) outputs, enabling complex waveform generation.
35.2 Features
• Glue logic for general purpose PCB design
• Up to 4 programmable LookUp Tables (LUTs)
• Combinatorial logic functions:
AND, NAND, OR, NOR, XOR, XNOR, NOT
• Sequential logic functions:
Gated D Flip-Flop, JK Flip-Flop, gated D Latch, RS Latch
• Flexible LUT inputs selection:
– I/Os
– Events
– Internal peripherals
– Subsequent LUT output
• Output can be connected to the I/O pins or the Event System
• Optional synchronizer, filter, or edge detector available on each LUT output
LUTCTRL0 LUT0
(INSEL)
Internal
LUTCTRL0 LUTCTRL0
Events (FILTSEL) (EDGESEL) SEQCTRL CTRL
(SEQSEL0) (ENABLE)
Event System
I/O
Truth Table 8 OUT0
Filter / Synch Edge Detector
CLR CLR Sequential I/O
Peripherals CLR
LUTCTRL0
(ENABLE)
D Q
CLK_CCL_APB
GCLK_CCL
LUTCTRL1 LUT1
(INSEL)
Internal
LUTCTRL1 LUTCTRL1
Events (FILTSEL) (EDGESEL) CTRL
(ENABLE)
Event System
I/O
Truth Table 8 OUT1
Filter / Synch Edge Detector
CLR CLR I/O
Peripherals
LUTCTRL1
(ENABLE)
D Q
CLK_CCL_APB
GCLK_CCL
UNIT 0
Event System
.
OUT2x-1
.
...
UNIT x I/O
37-40: 77-80:
CCL 0x42005C00 - - N 32 23 N - Y
LUTIN0-3 LUTOUT0-3
help the designer overcome challenging real-time constrains by combining core independent peripherals in clever
ways to handle the most time critical parts of the application independent of the CPU.
35.6.2 Operation
35.6.2.1 Initialization
The CCL bus clock (CLK_CCL_APB) is required to access the CCL registers. This clock can be enabled in the MCLK
- Main Clock module.
A generic clock (GCLK_CCL) is optionally required to clock the CCL. This clock must be configured and enabled in
the GCLK - Generic Clock Controller before using input events, filter, edge detection or sequential logic.
The following bits are enable-protected, meaning that they can only be written when the CCL module is disabled
(CTRL.ENABLE=0):
• Sequential Selection bits in the Sequential Control x (SEQCTRLx.SEQSEL) register
• LUT Control n (LUTCTRLn) register, except the ENABLE bit
Enable-protected bits in the LUTCTRLn registers can be written at the same time as LUTCTRLn.ENABLE is written
to '1', but not at the same time as LUTCTRLn.ENABLE is written to '0'.
Enable-protection is denoted by the Enable-Protected property in the register description.
IN[2:0]
Table 35-1. Truth Table of LUT
...........continued
IN[2] IN[1] IN[0] OUT
0 1 0 TRUTH[2]
0 1 1 TRUTH[3]
1 0 0 TRUTH[4]
1 0 1 TRUTH[5]
1 1 0 TRUTH[6]
1 1 1 TRUTH[7]
Input Overview
The inputs can be individually:
• Masked
• Driven by peripherals:
– Analog comparator output (AC)
– Timer/Counters waveform outputs (TC)
– Serial Communication output transmit interface (SERCOM)
– Timer/Counters for Control Applications waveform outputs (TCC)
• Driven by internal events from Event System
• Driven by other CCL sub-modules
The Input Selection for each input y of LUT n is configured by writing the Input x Source Selection bit in the LUT n
Control register (LUTCTRLn.INSELx).
IN 2n+1 x = SEQ n
With n representing the sequencer number and x=0,1,2 representing the LUT input index.
Figure 35-4. Feedback Input Selection
LUT0 SEQ 0
CTRL
(ENABLE)
LUT1
LUT2 SEQ 1
CTRL
(ENABLE)
LUT3
LUT(2n – 2) SEQ n
CTRL
(ENABLE)
LUT(2n-1)
FILTSEL
Input
OUT
G
D Q D Q D Q D Q
R R R R
GCLK_CCL
CLR
TC0
(default) WO[0]
TC1
(alternative) WO[0]
TC4
WO[0]
(second alternative)
35.6.2.5 Filter
By default, the LUT output is a combinatorial function of the LUT inputs. This may cause some short glitches when
the inputs change value. These glitches can be removed by clocking through filters, if demanded by application
needs.
The Filter Selection bits in LUT Control register (LUTCTRLn.FILTSEL) define the synchronizer or digital filter options.
When a filter is enabled, the OUT output will be delayed by two to five GCLK cycles. One APB clock after the
corresponding LUT is disabled, all internal filter logic is cleared.
Note: Events used as LUT input will also be filtered, if the filter is enabled.
Figure 35-12. Filter
FILTSEL
Input
OUT
G
D Q D Q D Q D Q
R R R R
GCLK_CCL
CLR
When the even LUT is disabled (LUTCTRL0.ENABLE=0 / LUTCTRL2.ENABLE=0), the flip-flop is asynchronously
cleared. The reset command (R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT)
is refreshed on rising edge of the GCLK_CCL, as shown in Table 35-2.
Table 35-2. DFF Characteristics
R G D OUT
1 X X Clear
0 1 1 Set
0 Clear
0 X Hold state (no change)
JK Flip-Flop (JK)
When this configuration is selected, the J-input is driven by the even LUT output (LUT0 and LUT2), and the K-input is
driven by the odd LUT output (LUT1 and LUT3), as shown in Figure 35-15.
Figure 35-15. JK Flip Flop
When the even LUT is disabled (LUTCTRL0.ENABLE=0 / LUTCTRL2.ENABLE=0), the flip-flop is asynchronously
cleared. The reset command (R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT)
is refreshed on rising edge of the GCLK_CCL, as shown in Table 35-3.
Table 35-3. JK Characteristics
R J K OUT
1 X X Clear
0 0 0 Hold state (no change)
0 0 1 Clear
0 1 0 Set
0 1 1 Toggle
Figure 35-16. D-Latch
odd LUT G
When the even LUT is disabled (LUTCTRL0.ENABLE=0 /
LUTCTRL2.ENABLE=0), the latch output will be cleared. The G-input is forced enabled for one more APB clock
cycle, and the D-input to zero. In all other cases, the latch output (OUT) is refreshed as shown in Table 35-4.
Table 35-4. D-Latch Characteristics
G D OUT
0 X Hold state (no change)
1 0 Clear
1 1 Set
RS Latch (RS)
When this configuration is selected, the S-input is driven by the even LUT output (LUT0 and LUT2), and the R-input
is driven by the odd LUT output (LUT1 and LUT3), as shown in Figure 35-17.
Figure 35-17. RS-Latch
odd LUT R
When the even LUT is disabled LUTCTRL0.ENABLE=0 / LUTCTRL2.ENABLE=0), the latch output will be cleared.
The R-input is forced enabled for one more APB clock cycle and S-input to zero. In all other cases, the latch output
(OUT) is refreshed as shown in Table 35-5.
Table 35-5. RS-Latch Characteristics
S R OUT
0 0 Hold state (no change)
0 1 Clear
1 0 Set
1 1 Forbidden state
35.6.3 Events
The CCL can generate the following output events:
• OUTn: Lookup Table Output Value
Writing a '1' to the LUT Control Event Output Enable bit (LUTCTRLn.LUTEO) enables the corresponding output
event. Writing a '0' to this bit disables the corresponding output event.
The CCL can take the following actions on an input event:
• INSELx: The event is used as input for the TRUTH table.
Writing a '1' to the LUT Control Event Input Enable bit (LUTCTRLn.LUTEI) enables the corresponding action on input
event. Writing a '0' to this bit disables the corresponding action on input event.
For further information, refer to the 28. Event System (EVSYS).
35.7.1 Control
Name: CTRL
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection
Note: CTRL register (except the bits ENABLE & SWRST) is Enable Protected when CCL.CTRL.ENABLE = 1.
Bit 7 6 5 4 3 2 1 0
RUNSTDBY ENABLE SWRST
Access R/W R/W W
Reset 0 0 0
Value Description
0 Generic clock is not required in standby sleep mode.
1 Generic clock is required in standby sleep mode.
Bit 1 – ENABLE Enable
Value Description
0 The peripheral is disabled.
1 The peripheral is enabled.
Name: SEQCTRL
Offset: 0x04 + n*0x01 [n=0..1]
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
SEQSEL[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: LUTCTRLn
Offset: 0x08 + n*0x04 [n=0..3]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-protected
Bit 31 30 29 28 27 26 25 24
TRUTH[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
LUTEO LUTEI INVEI INSEL2[3:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
INSEL1[3:0] INSEL0[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EDGESEL FILTSEL[1:0] ENABLE
Access R/W R/W R/W R/W
Reset 0 0 0 0
36.1 Overview
The Analog-to-Digital Converter (ADC) converts analog signals to digital values. The ADC has up to 12-bit resolution,
and is capable of a sampling rate of up to 1 Msps. The input selection is flexible, and both differential and single-
ended measurements can be performed. In addition, several internal signal inputs are available. The ADC can
provide both signed and unsigned results.
ADC measurements can be started by either application software or an incoming event from another peripheral in the
device. ADC measurements can be started with predictable timing and without software intervention.
Both internal and external reference voltages can be used.
The INTREF voltage reference (supplied by the bandgap), as well as the scaled I/O and core voltages, can be
measured by the ADC.
The ADC has a compare function for accurate monitoring of user-defined thresholds, with minimum software
intervention required. The ADC can be configured for 8, 10, or 12-bit results. ADC conversion results are provided
left- or right-adjusted, which eases calculation when the result is represented as a signed value. It is possible to use
DMA to move ADC results directly to memory or peripherals when conversions are done.
The device has two ADC instances, ADC0 and ADC1. The two inputs can be sampled simultaneously, as each ADC
includes a dedicated sample and hold circuit.
36.2 Features
• Two Analog-to-Digital Converters (ADC): ADC0 and ADC1
• 8-bit, 10-bit, or 12-bit resolution
• Up to 1,000,000 samples per second (1 MSPS)
• Differential and single-ended inputs
– Up to 14 analog inputs on ADC
Up to 12 external analog inputs and 3 internal inputs
• Internal inputs:
– INTREF voltage reference, supplied by the bandgap
– Scaled core supply
– Scaled I/O supply
– DAC
• Single, continuous, and sequencing options
• Windowing monitor with selectable channel
• Conversion range: Vref = [2.0V to VDDANA ]
• Built-in internal reference and external reference options
• Event-triggered conversion for accurate timing (one event input)
• Optional DMA transfer of conversion settings or result
• Hardware gain and offset compensation
• Averaging and oversampling with decimation to support up to 16-bit result
• Selectable sampling time
• Flexible Power or Throughput rate management
CTRLB SEQCTRL
AVGCTRL WINLT
SAMPCTRL WINUT
INPUTCTRL
EVCTRL OFFSETCORR
SWTRIG GAINCORR
AIN0
...
AINn
INT.SIG
ADC POST
PROCESSING
RESULT
AIN0
...
AINn
INTREF
INTVCC0
INTVCC1 CTRLA SEQSTATUS
VREFA
DAC
INTVCC2
PRESCALER
REFCTRL
...........continued
AHB CLK APB CLK Generic CLK PAC Events DMA
Sleep
Peripheral Base Address IRQ Enabled at Enabled at Prot at
Index Index User Generator Index Walking
reset reset reset
36.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the ADC is disabled
(CTRLA.ENABLE=0):
• Control B register (CTRLB)
• Reference Control register (REFCTRL)
• Event Control register (EVCTRL)
• Calibration register (CALIB)
Enable-protection is denoted by the "Enable-Protected" property in the register description.
36.6.2.3 Operation
In the most basic configuration, the ADC samples values from the configured internal or external sources
(INPUTCTRL register). The rate of the conversion depends on the combination of the GCLK_ADCx frequency and
the clock prescaler.
To convert analog values to digital values, the ADC needs to be initialized first, as described in the Initialization
section. Data conversion can be started either manually by setting the Start bit in the Software Trigger register
(SWTRIG.START=1), or automatically by configuring an automatic trigger to initiate the conversions. The ADC starts
sampling the input only after the start of conversion is triggered. This means that even after the MUX selection
is made, sample and hold (S&H) operation starts only on the conversion trigger. Free-running mode can be used
to continuously convert an input channel. When using free-running mode, conversions will start after the ADC is
enabled.
The ADC starts sampling the input only after the start of a conversion is triggered. This means that even after the
MUX selection is made, sample and hold operation starts only on the conversion trigger.
The result of the conversion is stored in the Result register (RESULT) overwriting the result from the previous
conversion.
To avoid data loss, if more than one channel is enabled, the conversion result must be read as soon as it is available
(INTFLAG.RESRDY). Failing to do so will result in an overrun error condition, indicated by the OVERRUN bit in the
Interrupt Flag Status and Clear register (INTFLAG.OVERRUN).
To enable one of the available interrupts sources, the corresponding bit in the Interrupt Enable Set register
(INTENSET) must be written to '1'.
DIV128
DIV256
DIV16
DIV32
DIV64
DIV2
DIV4
CTRLB.PRESCALER[2:0] DIV8
CLK_ADCx
Note: The minimum prescaling factor is DIV2.
START
INT
The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control
register (SAMPCTRL.SAMPLEN). As example, the next figure is showing the timing conversion with sampling time
increased to six CLK_ADC cycles.
Figure 36-4. ADC Timing for One Conversion with Increased Sampling Time, 12-bit
CLK_ADC
START
INT
The ADC can also provide compensation, as shown in the following figure. The offset compensation is enabled by
the Offset Compensation bit in the Sampling Control register (SAMPCTRL.OFFCOMP).
Note: ADC sampling time is fixed to 4 ADC Clock cycles when offset compensation (OFFCOMP=1) is used.
In free running mode, the sampling rate RS is calculated by
RS = fCLK_ADC / ( nSAMPLING + nOFFCOMP + nDATA)
Here, nSAMPLING is the sampling duration in CLK_ADC cycles, nOFFCOMP is the offset compensation duration in clock
cycles, and nDATA is the bit resolution. fCLK_ADC is the ADC clock frequency from the internal prescaler: fCLK_ADC =
fGCLK_ADC / 2^(1 + CTRLB.PRESCALER)
Figure 36-5. ADC Timing for One Conversion with Offset Compensation, 12-bit
CLK_ADC
START
INT
The impact of resolution on the sampling rate is seen in the next two figures, where free-running sampling in 12-bit
and 8-bit resolution are compared.
Figure 36-6. ADC Timing for Free Running in 12-bit Resolution
CLK_ADC
CONVERT
INT
CLK_ADC
CONVERT
STATE LSB SAMPLING MSB 6 5 4 3 2 1 LSB SAMPLING MSB 6 5 4 3 2 1 LSB SAMPLING MSB
INT
PropagationDelay = 1 + Resolution
fADC
Example. In order to obtain 1 MSPS in 12-bit resolution with a sampling time length of four
CLK_ADC cycles, fCLK_ADC must be 1 MSPS * (4 + 12) = 16 MHz. As the minimal division factor of
the prescaler is 2, GCLK_ADC must be 32 MHz.
36.6.2.9 Accumulation
The result from multiple consecutive conversions can be accumulated. The number of samples to be accumulated is
specified by the Sample Number field in the Average Control register (AVGCTRL.SAMPLENUM). When accumulating
more than 16 samples, the result will be too large to match the 16-bit RESULT register size. To avoid overflow, the
result is right shifted automatically to fit within the available register size. The number of automatic right shifts is
specified in the table below.
Note: To perform the accumulation of two or more samples, the Conversion Result Resolution field in the Control C
register (CTRLC.RESSEL) must be set depending on the final result precision. For resolutions strictly higher than 12
bits, RESSEL must be set to 16 bits.
Table 36-1. Accumulation
36.6.2.10 Averaging
Averaging is a feature that increases the sample accuracy, at the cost of a reduced sampling rate. This feature is
suitable when operating in noisy conditions.
Averaging is done by accumulating m samples, as described in 36.6.2.9 Accumulation, then dividing the result by m.
The averaged result is available in the RESULT register. The number of samples to be accumulated is specified by
writing to AVGCTRL.SAMPLENUM as shown in Table 36-2.
The division is obtained by a combination of the automatic right shift described above, and an additional right shift
that must be specified by writing to the Adjusting Result/Division Coefficient field in AVGCTRL (AVGCTRL.ADJRES),
as described in Table 36-2.
Note: To perform the averaging of two or more samples, the Conversion Result Resolution field in the Control C
register (CTRLC.RESSEL) must be set.
Averaging AVGCTRL.SAMPLENUM samples will reduce the un-averaged sampling rate by a factor
1 .
AVGCTRL.SAMPLENUM
When the averaged result is available, the INTFLAG.RESRDY bit will be set.
Table 36-2. Averaging
Number of AVGCTRL. Intermediate Number of Division AVGCTRL.ADJRES Total Final Result Automatic
Accumulated SAMPLENUM Result Automatic Factor Number Precision Division
Samples Precision Right Shifts of Right Factor
Shifts
...........continued
Result Number of AVGCTRL.SAMPLENUM[3:0] Number of AVGCTRL.ADJRES[2:0]
Resolution Samples to Automatic
Average Right Shifts
15 bits 43 = 64 0x6 2 0x1
16 bits 44 = 256 0x8 4 0x0
ADC0.SEQCTRL
ADC0.AVGCTRL ADC0.WINLT
ADC0.SAMPCTRL ADC0.WINUT
ADC0.EVCTRL ADC0.OFFSETCORR
ADC0.SWTRIG ADC0.GAINCORR
ADC0_AIN0
...
ADC0_AINn
INT.SIG
ADC0.RESULT
ADC0.INPUTCTRL ADC 0 POST
PROCESSING
ADC0.SEQSTATUS
ADC0_AIN0
...
ADC0_AINn
INTREF ADC0.CTRLA
INTVCC0
INTVCC1 ADC0.CTRLB
VREFA
DAC
INTVCC2
PRESCALER
ADC0.REFCTRL
ADC1_AIN0
...
ADC1_AINn
INT.SIG
ADC1.RESULT
ADC 1
POST
ADC1.INPUTCTRL
PROCESSING
ADC1.SEQSTATUS
ADC1_AIN0
...
ADC1_AINn
INTREF
INTVCC0 ADC1.CTRLA ADC1.GAINCORR
INTVCC1 SLAVEEN
VREFA
DAC ADC1.AVGCTRL ADC1.OFFSETCORR
INTVCC2
ADC1.SAMPCTRL ADC1.WINUT
ADC1.REFCTRL
ADC1.SWTRIG ADC1.WINLT
ADC1.SEQCTRL
In this mode of operation, the client ADC is enabled by accessing the CTRLA register of host ADC. In the same way,
the host ADC event inputs will be automatically routed to the client ADC, meaning that the input events configuration
must be done in the host ADC (ADC0.EVCTRL).
ADC measurements can be started simultaneously on both ADC’s or interleaved. The trigger mode selection is
available in the host ADC Control C register (ADC0.CTRLC.DUALSEL).
Start Trigger
(Software or Event)
ADC0 Start Conversion ADC1 Start Conversion ADC0 Start Conversion ADC1 Start Conversion ADC0 Start Conversion
36.6.5 Interrupts
The ADC has the following interrupt sources:
• Result Conversion Ready: RESRDY
• Window Monitor: WINMON
• Overrun: OVERRUN
These interrupts, except the OVERRUN interrupt, are asynchronous wake-up sources. Refer to 16.5.3.3 Sleep Mode
Controller for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to
the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when
the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the
interrupt flag is cleared, the interrupt is disabled, or the ADC is reset. See INTFLAG register for details on how to
clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one
combined interrupt request to the NVIC. Refer to 9.2 Nested Vector Interrupt Controller for details. The user must
read the 13.6.3 INTFLAG register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
36.6.6 Events
The ADC can generate the following output events:
• Result Ready (RESRDY): Generated when the conversion is complete and the result is available. Refer to
36.7.4 EVCTRL for details.
• Window Monitor (WINMON): Generated when the window monitor condition match. Refer to 36.7.10 CTRLC for
details.
Setting an Event Output bit in the Event Control Register (EVCTRL.xxEO=1) enables the corresponding output event.
Clearing this bit disables the corresponding output event. Refer to the Event System chapter for details on configuring
the event system.
The ADC can take the following actions on an input event:
• Start conversion (START): Start a conversion. Refer to 36.7.17 SWTRIG for details.
• Conversion flush (FLUSH): Flush the conversion. Refer to 36.7.17 SWTRIG for details.
Setting an Event Input bit in the Event Control register (EVCTRL.xxEI=1) enables the corresponding action on input
event. Clearing this bit disables the corresponding action on input event.
The ADC uses only asynchronous events, so the asynchronous Event System channel path must be configured. By
default, the ADC will detect a rising edge on the incoming event. If the ADC action must be performed on the falling
edge of the incoming event, the event line must be inverted first. This is done by setting the corresponding Event
Invert Enable bit in Event Control register (EVCTRL.xINV=1).
Note: If several events are connected to the ADC, the enabled action will be taken on any of the incoming events. If
FLUSH and START events are available at the same time, the FLUSH event has priority.
For further information, refer to the 28. Event System (EVSYS).
36.6.8 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in Control A register (CTRLA.SWRST)
• Enable bit in Control A register (CTRLA.ENABLE)
The following registers are synchronized when written:
• Input Control register (INPUTCTRL)
• Control C register (CTRLC)
• Average control register (AVGCTRL)
• Sampling time control register (SAMPCTRL)
• Window Monitor Lower Threshold register (WINLT)
• Window Monitor Upper Threshold register (WINUT)
• Gain correction register (GAINCORR)
• Offset Correction register (OFFSETCORR)
• Software Trigger register (SWTRIG)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
36.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized Bits
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY SLAVEEN ENABLE SWRST
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 1 – ENABLE Enable
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE.
For the client ADC, this bit has no effect when the SLAVEEN bit is set (CTRLA.SLAVEEN= 1).
Value Description
0 The ADC is disabled.
1 The ADC is enabled.
36.7.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
PRESCALER[2:0]
Access R/W R/W R/W
Reset 0 0 0
Name: REFCTRL
Offset: 0x02
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
REFCOMP REFSEL[3:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Name: EVCTRL
Offset: 0x03
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
WINMONEO RESRDYEO STARTINV FLUSHINV STARTEI FLUSHEI
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: INTENCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 7 6 5 4 3 2 1 0
WINMON OVERRUN RESRDY
Access R/W R/W R/W
Reset 0 0 0
Name: INTENSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 7 6 5 4 3 2 1 0
WINMON OVERRUN RESRDY
Access R/W R/W R/W
Reset 0 0 0
Name: INTFLAG
Offset: 0x06
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
WINMON OVERRUN RESRDY
Access R/W R/W R/W
Reset 0 0 0
Bit 1 – OVERRUN Overrun
This flag is cleared by writing a '1' to the flag.
This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt request will be
generated if INTENCLR/SET.OVERRUN=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overrun interrupt flag.
Name: SEQSTATUS
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SEQBUSY SEQSTATE[4:0]
Access R R R R R R
Reset 0 0 0 0 0 0
Name: INPUTCTRL
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.INPUTCTRL must be checked to ensure the INPUTCTRL
register synchronization is complete.
Bit 15 14 13 12 11 10 9 8
MUXNEG[4:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MUXPOS[4:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
36.7.10 Control C
Name: CTRLC
Offset: 0x0A
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CTRLC must be checked to ensure the CTRLC register
synchronization is complete.
Bit 15 14 13 12 11 10 9 8
DUALSEL[1:0] WINMODE[2:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
R2R RESSEL[1:0] CORREN FREERUN LEFTADJ DIFFMODE
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Value Description
0 Disable the digital result correction.
1 Enable the digital result correction. The ADC conversion result in the RESULT register is then
corrected for gain and offset based on the values in the GAINCORR and OFFSETCORR registers.
Conversion time will be increased by 13 cycles according to the value in the Offset Correction Value bit
group in the Offset Correction register.
Name: AVGCTRL
Offset: 0x0C
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.AVGCTRL must be checked to ensure the AVGCTRL register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
ADJRES[2:0] SAMPLENUM[3:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Name: SAMPCTRL
Offset: 0x0D
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.SAMPCTRL must be checked to ensure the SAMPCTRL
register synchronization is complete.
Bit 7 6 5 4 3 2 1 0
OFFCOMP SAMPLEN[5:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Name: WINLT
Offset: 0x0E
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.WINLT must be checked to ensure the WINLT register
synchronization is complete.
Bit 15 14 13 12 11 10 9 8
WINLT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINLT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: WINUT
Offset: 0x10
Reset: 0x0000
Property: PAV Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.WINUT must be checked to ensure the WINUT register
synchronization is complete.
Bit 15 14 13 12 11 10 9 8
WINUT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINUT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: GAINCORR
Offset: 0x12
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.GAINCORR must be checked to ensure the GAINCORR
register synchronization is complete.
Bit 15 14 13 12 11 10 9 8
GAINCORR[11:8]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GAINCORR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OFFSETCORR
Offset: 0x14
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
OFFSETCORR[11:8]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OFFSETCORR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: SWTRIG
Offset: 0x18
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.SWTRIG must be checked to ensure the SWTRIG register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
START FLUSH
Access W W
Reset 0 0
Name: DBGCTRL
Offset: 0x1C
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: SYNCBUSY
Offset: 0x20
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
SWTRIG OFFSETCORR GAINCORR
Access R R R
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
WINUT WINLT SAMPCTRL AVGCTRL CTRLC INPUTCTRL ENABLE SWRST
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
36.7.20 Result
Name: RESULT
Offset: 0x24
Reset: 0x0000
Property: -
Bit 15 14 13 12 11 10 9 8
RESULT[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RESULT[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: SEQCTRL
Offset: 0x28
Reset: 0x00000000
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
SEQEN[31:24]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
SEQEN[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SEQEN[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SEQEN[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
36.7.22 Calibration
Name: CALIB
Offset: 0x2C
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit 15 14 13 12 11 10 9 8
BIASREFBUF[2:0]
Access R/W R/W R/W
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
BIASCOMP[2:0]
Access R/W R/W R/W
Reset 0 0 0
37.1 Overview
The Sigma-Delta Analog-to-Digital Converter (SDADC) converts analog signals to digital values. The SDADC has
16-bit resolution, and is capable of converting up to 1.5 Msps divided by the data over sampling ratio (OSR). The
input selection is up to three differential analog channels. The SDADC provides signed results.
SDADC measurements can be started by either application software or an incoming event from another peripheral in
the device. SDADC measurements can be started with predictable timing and without software intervention.
The SDADC also integrates Sleep mode and a conversion sequencer. These features reduce power consumption
and processor intervention.
A set of reference voltages is generated internally.
37.2 Features
• 16-bit resolution
• Up to 1,500,000 divided by Over Sampling Ratio (OSR) samples per second
• Three analog differential inputs
– Up to 2 external analog differential pairs.
• Conversion Range:
– Differential mode: -VREF to +VREF
• Event-triggered conversion (one event input)
• Optional DMA transfer of conversion settings or result
• Single, continuous, and sequencing options
• Hardware gain, offset, and shift compensation
• Windowing monitor
• Chopper mode (offset reduction)
CTRLB
CTRLC
SAMPCTRL
SEQCTRL
INPUTCTRL
EVCTRL
WINLT
SWTRIG
WINUT
AINN0
...
AINNn
SDADC POST
PROCESSING
RESULT
AINP0
...
AINPn
SEQSTATUS
INTREF CTRLA
VREFB
SHIFTCORR
DAC
VDDANA
PRESCALER OFFSETCORR
GAINCORR
REFCTRL
ANACTRL
37.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the SDADC is disabled
(CTRLA.ENABLE is zero):
• CTRLA ONEDEMAND and RUNSTDBY bits
• CTRLB
• CTRLC
• EVCTRL
• ANACTRL
Enable-protection is denoted by the Enable-Protected property in the register description.
37.6.2.3 Operation
In the most basic configuration, the SDADC sample values from the configured external sources (input ctrl register).
The rate of the conversion depends on the combination of the GCLK_SDADC frequency, the clock prescaler from
CTRLB.PRESCALER and the Over Sampling Ratio from CTRLB.OSR.
To convert analog values to digital values, the SDADC needs to be initialized first, as described in
37.6.2.1 Initialization . Data conversion can be started either manually, by writing a one to the Start bit in the
Software Trigger register (SWTRIG.START), or automatically, by configuring an automatic trigger to initiate the
conversions. A free-running mode could be used to continuously convert an input channel. There is no need for a
trigger to start the conversion. It will start automatically at the end of previous conversion.
The first valid sample starts from the third sample onward. It can skip the first few samples by programming the
SKPCNT[3:0] in CTRLB register. The result of the conversion is stored in the Result register (RESULT) overwriting
the result from the previous conversion.
To avoid data loss the conversion result must be read as soon as it is available (INTFLAG.RESRDY). Failing to do so
will result in an overrun error condition, indicated by the OVERRUN bit in the Interrupt Flag Status and Clear register
(INTFLAG.OVERRUN).
To use an interrupt handler, the corresponding bit in the Interrupt Enable Set register (INTENSET) must be written to
one.
DIV510
DIV512
DIV10
DIV2
DIV4
DIV6
DIV8
...
CTRLB.PRESCALER[7:0]
CLK_SDADC
The INTFLAG.WINMON interrupt flag will be set if the conversion result matches the window monitor condition.
37.6.3.1 Description
The Analog-to-Digital Converter filters and decimates the sigma-delta ADC output bitstream. Its output is defined on
16bits unsigned format with the following programmable output rates: CLK_SDADC_FS/64, CLK_SDADC_FS/128,
CLK_SDADC_FS/256, CLK_SDADC_FS/512 and CLK_SDADC_FS/1024, where CLK_SDADC_FS is the sigma-
delta ADC’s sampling frequency: CLK_SDADC_FS = CLK_SDADC_PRESCALER/4, the reduction comes from the
phase generator between the prescaler and the SDADC.
The filtering and the decimation is performed by a SINC-based filter whose zeros are placed in order to minimize
aliasing effects of the decimation.
1 OSR+ − 1 3
H z = i=0 z−i
OSR3
Where,
OSR is the Over Sampling Ratio which can be modified to change the output data rate (See CTRLC for the setting of
this parameter).
The DC gain of this filter is unity and does not depend on its OSR. However, as it generates a 3rd order zero at
(CLK_SDADC_FS / OSR) frequency multiples, its frequency response depends on the OSR parameter. See next
section for frequency plots.
Figure 37-3. Spectral Mask of an OSR = 64, CLK_SDADC_FS = 1 MHz, 3rd Order Sinc Filter Overall Response
(Continuous Line) and 0–1600Hz Bandwidth Response (Dashed Line)
frequency (Hz), base band
0 200 400 600 800 1000 1200 1400 1600
0 0
-24 -0.1
gain (dB), overall mask
-48 -0.2
-72 -0.3
-96 -0.4
-120 -0.5
0 Fs/16 2*Fs/16 3*Fs/16 4*Fs/16 5*Fs/16 6*Fs/16 7*Fs/16 8*Fs/16
frequency (Hz), overall mask
Figure 37-4. Spectral Mask of an OSR = 128, CLK_SDADC_FS = 1 MHz, 3rd Order Sinc Filter Overall
Response (Continuous Line) and 0–1600 Hz Bandwidth Response (Dashed Line)
frequency (Hz), base band
0 200 400 600 800 1000 1200 1400 1600
0 0
-24 -0.4
-72 -1.2
-96 -1.6
-120 -2
0 Fs/16 2*Fs/16 3*Fs/16 4*Fs/16 5*Fs/16 6*Fs/16 7*Fs/16 8*Fs/16
frequency (Hz), overall mask
-24 -2.4
gain (dB), overall mask
-72 -7.2
-96 -9.6
-120 -12
0 Fs/16 2*Fs/16 3*Fs/16 4*Fs/16 5*Fs/16 6*Fs/16 7*Fs/16 8*Fs/16
frequency (Hz), overall mask
Where:
Data0 is an unsigned integer defined on 16 bits. It is the output of the decimation filter.
OFFSET is a signed integer defined on 24 bits (OFFSETCORR register).
GAIN is an unsigned integer defined on 14 bits (GAINCORR register).
SHIFT is an unsigned integer defined on 4 bits (SHIFTCORR register).
The result of the operation is then saturated to be within [0:216-1] and the 16 LSBs of this saturation operation are
sent to the controller as the result of the SDADC conversion.
Offset error can be compensated by setting the Chopper mode ON, refer to the 37.7.21 ANACTRL.ONCHOP bit.
37.6.5 Interrupts
The SDADC has the following interrupt sources:
• Result Conversion Ready: RESRDY
• Window Monitor: WINMON
• Overrun: OVERRUN
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and
Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by
writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a
one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated
when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until
the interrupt flag is cleared, the interrupt is disabled, or the SDADC is reset. See 37.7.7 INTFLAG for details on
how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate
one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt
condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
37.6.6 Events
The SDADC can generate the following output events:
• Result Ready (RESRDY): Generated when the conversion is complete and the result is available. Refer to
EVCTRL for details.
• Window Monitor (WINMON): Generated when the window monitor condition match. Refer to WINCTRL register
for details.
Writing a one to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables the corresponding output
event. Writing a zero to this bit disables the corresponding output event. Refer to the Event System chapter for details
on configuring the event system.
The SDADC can take the following actions on an input event:
• Start conversion (START): Start a conversion. Refer to SWTRIG for details.
• Conversion flush (FLUSH): Flush the conversion. Refer to SWTRIG for details.
Writing a one to an Event Input bit into the Event Control register (EVCTRL.xxEI) enables the corresponding action
on input event. Writing a zero to this bit disables the corresponding action on input event.
The SDADC uses only asynchronous events and asynchronous Event System channel path must be configured. By
default, the SDADC will detect a rising edge on the incoming event. If the SDADC action must be performed on the
falling edge of the incoming event, the event line must be inverted first, by writing to one the corresponding Event
Invert Enable bit in Event Control register (EVCTRL.xINV).
Note: If FLUSH and START events are available simultaneously, the FLUSH event has higher priority.
When the device is in STANDBY sleep mode the DMA is not able to write the SWTRIG register. To write the SWTRIG
register with the DMA the device must be in Active mode or IDLE sleep mode.
37.6.8 Synchronization
Due to the asynchronicity between CLK_SDADC_APB and CLK_GEN_SDADC some registers must be synchronized
when accessed. A register can require:
• Synchronization when written
• Synchronization when read
• Synchronization when written and read
• No synchronization
When executing an operation that requires synchronization, the corresponding synchronization bit is set in
Synchronization Busy register (SYNCBUSY) and cleared when synchronization is complete.
If an operation that require synchronization is executed while its busy bit is on, the operation is discarded and a bus
error is generated.
The following bits need synchronization when written:
• Software Reset bit in Control A register (CTRLA.SWRST)
• Enable bit in Control A register (CTRLA.ENABLE)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
The following registers need synchronization when written:
• Input Control register (INPUTCTRL)
• Reference Control register (REFCTRL)
• Control C register (CTRLC)
• Window Monitor Lower Threshold register (WINLT)
• Window Monitor Upper Threshold register (WINUT)
• Offset correction register (OFFSETCORR)
• Gain correction register (GAINCORR)
• Shift correction register (SHIFTCORR)
• Software Trigger register (SWTRIG)
• Analog Control Register (ANACTRL)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
37.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized (ENABLE, SWRST)
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY ENABLE SWRST
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value Description
0 The SDADC is disabled.
1 The SDADC is enabled.
Name: REFCTRL
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
ONREFBUF REFSEL[1:0]
Access R/W R/W R/W
Reset 0 0 0
37.7.3 Control B
Name: CTRLB
Offset: 0x02
Reset: 0x2000
Property: PAC Write-Protection, Enable-Protected
Bit 15 14 13 12 11 10 9 8
SKPCNT[3:0] OSR[2:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PRESCALER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: EVCTRL
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
WINMONEO RESRDYEO STARTINV FLUSHINV STARTEI FLUSHEI
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: INTENCLR
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 7 6 5 4 3 2 1 0
WINMON OVERRUN RESRDY
Access R/W R/W R/W
Reset 0 0 0
Name: INTENSET
Offset: 0x06
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 7 6 5 4 3 2 1 0
WINMON OVERRUN RESRDY
Access R/W R/W R/W
Reset 0 0 0
Name: INTFLAG
Offset: 0x07
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
WINMON OVERRUN RESRDY
Access R/W R/W R/W
Reset 0 0 0
Bit 1 – OVERRUN Overrun
This flag is cleared by writing a one to the flag.
This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt request will be
generated if INTENCLR/SET.OVERRUN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overrun interrupt flag.
Name: SEQSTATUS
Offset: 0x08
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SEQBUSY SEQSTATE[3:0]
Access R R R R R
Reset 0 0 0 0 0
Name: INPUTCTRL
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
MUXSEL[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
37.7.10 Control C
Name: CTRLC
Offset: 0x0A
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
FREERUN
Access R/W
Reset 0
Name: WINCTRL
Offset: 0x0B
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
WINMODE[2:0]
Access R/W R/W R/W
Reset 0 0 0
Name: WINLT
Offset: 0x0C
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
WINLT[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
WINLT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINLT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: WINUT
Offset: 0x10
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
WINUT[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
WINUT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINUT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: OFFSETCORR
Offset: 0x14
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
OFFSETCORR[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
OFFSETCORR[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OFFSETCORR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: GAINCORR
Offset: 0x18
Reset: 0x0001
Property: PAC Write-Protection, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
GAINCORR[13:8]
Access R R R R R R
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GAINCORR[7:0]
Access R R R R R R R R
Reset 1 0 0 0 0 0 0 0
Name: SHIFTCORR
Offset: 0x1A
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
SHIFTCORR[3:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: SWTRIG
Offset: 0x1C
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
START FLUSH
Access W W
Reset 0 0
Name: SYNCBUSY
Offset: 0x20
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
ANACTRL SWTRIG SHIFTCORR GAINCORR
Access R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OFFSETCORR WINUT WINLT WINCTRL MUXCTRL CTRLC ENABLE SWRST
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
37.7.19 Result
Name: RESULT
Offset: 0x24
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
RESULT[23:16]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RESULT[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RESULT[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: SEQCTRL
Offset: 0x28
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
SEQENn[2:0]
Access R/W R/W R/W
Reset 0 0 0
Name: ANACTRL
Offset: 0x2C
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized.
Bit 7 6 5 4 3 2 1 0
BUFTEST ONCHOP CTLSDADC[4:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 6 – ONCHOP ONCHOP
Value Description
0 No Chopper at SDADC input
1 Chopper at SDADC input
Name: DBGCTRL
Offset: 0x2E
Reset: 0x00
Property: PAC Write-Protectedion
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
38.1 Overview
The Analog Comparator (AC) supports multiple individual comparators. Each comparator (COMP) compares the
voltage levels on two inputs, and provides a digital output based on this comparison. Each comparator may be
configured to generate interrupt requests and peripheral events upon several combinations of input change.
Hysteresis and propagation delay can be adjusted to achieve optimal operation for each application.
The input selection includes four shared analog port pins and several internal signals. Each Comparator Output state
can also be output on a pin for use by external devices.
The comparators are grouped in pairs on each port. The AC peripheral implements one pair of comparators and one
stand alone comparator. These are called Comparator 0 (COMP0) and Comparator 1 (COMP1). The pair can be set
in Window mode to compare a signal to a voltage range instead of a single voltage level.
38.2 Features
• Two individual comparators
• Selectable propagation delay versus current consumption
• Hysteresis: On or Off
• Analog comparator outputs available on pins
– Asynchronous or synchronous
• Flexible input selection:
– Four pins selectable for positive or negative inputs
– Ground (for zero crossing)
– INTREF reference voltage, supplied by the bandgap
– 64-level programmable VDD scaler per comparator
– DAC (if available)
• Interrupt generation on:
– Rising or falling edge
– Toggle
– End of comparison
• Window function interrupt generation on:
– Signal above window
– Signal inside window
– Signal below window
– Signal outside window
• Event generation on:
– Comparator output
– Window function inside/outside window
• Optional digital filter on comparator output
• Low-power option
– Single-shot support
AIN0
+
CMP0
COMP0
AIN1
- HYSTERESIS
VDD
INTERRUPTS
SCALER
ENABLE INTERRUPT
INTERRUPT MODE SENSITIVITY
DAC CONTROL
COMPCTRLn WINCTRL & EVENTS
WINDOW
ENABLE FUNCTION GCLK_AC
INTREF
HYSTERESIS
AIN2 +
CMP1
COMP1
AIN3
-
Refer to the Pinout for details on the pin mapping for this peripheral. One signal can be mapped on several pins.
73-74:
34-35: COMP0-1
AC 0x42005000 23 - N 33 20 N - Y
SOC0-1
75: WIN0
of-comparison interrupt can be used with the single-shot mode to chain further events in the system, regardless of
the state of the comparator outputs. The interrupt mode is set by the Interrupt Selection bit group in the Comparator
Control register (COMPCTRLx.INTSEL). Events are generated using the comparator output state, regardless of
whether the interrupt is enabled or not.
tSTARTUP
STATUSB.READYx
Sampled
Comparator Output
For low-power operation, comparisons can be performed during sleep modes without a clock. The comparator is
enabled continuously, and changes of the comparator state are detected asynchronously. When a toggle occurs, the
Power Manager will start GCLK_AC to register the appropriate peripheral events and interrupts. The GCLK_AC clock
is then disabled again automatically, unless configured to wake up the system from sleep.
38.6.2.4.2 Single-Shot
Single-shot operation is selected by writing COMPCTRLx.SINGLE to '1'. During single-shot operation, the
comparator is normally idle. The user starts a single comparison by writing '1' to the respective Start Comparison
bit in the write-only Control B register (CTRLB.STARTx). The comparator is enabled, and after the start-up time has
passed, a single comparison is done and STATUSA.STATEx is updated. Appropriate peripheral events and interrupts
are also generated. No new comparisons will be performed.
Writing '1' to CTRLB.STARTx also clears the Comparator x Ready bit in the Status B register (STATUSB.READYx).
STATUSB.READYx is set automatically by hardware after the single comparison has completed.
A single-shot measurement can also be triggered by the Event System. Setting the Comparator x Event Input bit in
the Event Control Register (EVCTRL.COMPEIx) enables triggering on incoming peripheral events. Each comparator
can be triggered independently by separate events. Event-triggered operation is similar to user-triggered operation;
the difference is that a peripheral event from another hardware module causes the hardware to automatically start the
comparison and clear STATUSB.READYx.
To detect an edge of the comparator output in single-shot operation for the purpose of interrupts, the result of the
current measurement is compared with the result of the previous measurement (one sampling period earlier). An
example of single-shot operation is shown in Figure 38-3.
Figure 38-3. Single-Shot Example
GCLK_AC
Write ‘1’ Write ‘1’
CTRLB.STARTx 2-3 cycles 2-3 cycles
tSTARTUP tSTARTUP
STATUSB.READYx
Sampled
Comparator Output
For low-power operation, event-triggered measurements can be performed during sleep modes. When the event
occurs, the Power Manager will start GCLK_AC. The comparator is enabled, and after the startup time has passed,
a comparison is done and appropriate peripheral events and interrupts are also generated. The comparator and
GCLK_AC are then disabled again automatically, unless configured to wake up the system from sleep.
STATE0
COMP0
INTERRUPT
SENSITIVITY
INTERRUPTS
CONTROL
INPUT SIGNAL &
WINDOW
FUNCTION EVENTS
STATE1
COMP1
COMPCTRLx.MUXNEG == 5 SCALERx.
OR VALUE
COMPCTRLx.MUXPOS == 4
6
to
COMPx
38.6.8 Filtering
The output of the comparators can be filtered digitally to reduce noise. The filtering is determined by the Filter Length
bits in the Comparator Control x register (COMPCTRLx.FLEN), and is independent for each comparator. Filtering is
selectable from none, 3-bit majority (N=3) or 5-bit majority (N=5) functions. Any change in the comparator output is
considered valid only if N/2+1 out of the last N samples agree. The filter sampling rate is the GCLK_AC frequency.
Note that filtering creates an additional delay of N-1 sampling cycles from when a comparison is started until the
comparator output is validated. For continuous mode, the first valid output will occur when the required number of
filter samples is taken. Subsequent outputs will be generated every cycle based on the current sample plus the
previous N-1 samples, as shown in Figure 38-6. For single-shot mode, the comparison completes after the Nth filter
sample, as shown in Figure 38-7.
Figure 38-6. Continuous Mode Filtering
Sampling Clock
Sampled
Comparator Output
3-bit Majority
Filter Output
5-bit Majority
Filter Output
Start
tSTARTUP
3-bit Sampled
Comparator Output
3-bit Majority
Filter Output
5-bit Sampled
Comparator Output
5-bit Majority
Filter Output
During sleep modes, filtering is supported only for single-shot measurements. Filtering must be disabled if continuous
measurements will be done during sleep modes, or the resulting interrupt/event may be generated incorrectly.
comparator input offset voltage. As part of the input selection, COMPCTRLx.SWAP can be changed only while the
comparator is disabled.
Figure 38-8. Input Swapping for Offset Compensation
MUXPOS
COMPx CMPx
- HYSTERESIS
ENABLE
SWAP
SWAP
MUXNEG COMPCTRLx
38.6.11 Interrupts
The AC has the following interrupt sources:
• Comparator (COMP0 and COMP1): Indicates a change in comparator status.
• Window (WIN0): Indicates a change in the window status.
Comparator interrupts are generated based on the conditions selected by the Interrupt Selection bit group in the
Comparator Control registers (COMPCTRLx.INTSEL). Window interrupts are generated based on the conditions
selected by the Window Interrupt Selection bit group in the Window Control register (WINCTRL.WINTSEL[1:0]).
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and
Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by
writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a
one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated
when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until
the interrupt flag is cleared, the interrupt is disabled, or the AC is reset. See the INTFLAG register for details on
how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate
one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt
condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
38.6.12 Events
The AC can generate the following output events:
• Comparator (COMP0 and COMP1): Generated as a copy of the comparator status
• Window (WIN0): Generated as a copy of the window inside/outside status
Writing a one to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables the corresponding output
event. Writing a zero to this bit disables the corresponding output event. Refer to the Event System chapter for details
on configuring the event system.
The AC can take the following action on an input event:
• Start comparison (START0 and START1): Start a comparison.
Writing a one to an Event Input bit into the Event Control register (EVCTRL.COMPEIx) enables the corresponding
action on input event. Writing a zero to this bit disables the corresponding action on input event. Note that if several
events are connected to the AC, the enabled action will be taken on any of the incoming events. Refer to the Event
System chapter for details on configuring the event system.
When EVCTRL.COMPEIx is one, the event will start a comparison on COMPx after the start-up time delay. In
normal mode, each comparator responds to its corresponding input event independently. For a pair of comparators in
window mode, either comparator event will trigger a comparison on both comparators simultaneously.
tSTARTUP
STATUSB.READYx
Sampled
Comparator Output
tSTARTUP tSTARTUP
Input Event
Comparator
Output or Event
38.6.14 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
38.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized Bits
Bit 7 6 5 4 3 2 1 0
ENABLE SWRST
Access R/W W
Reset 0 0
Bit 1 – ENABLE Enable
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
Value Description
0 The AC is disabled.
1 The AC is enabled. Each comparator must also be enabled individually by the Enable bit in the
Comparator Control register (COMPCTRLn.ENABLE).
38.7.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
START1 START0
Access R/W R/W
Reset 0 0
Name: EVCTRL
Offset: 0x02
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit 15 14 13 12 11 10 9 8
INVEI1 INVEI0 COMPEI1 COMPEI0
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINEO0 COMPEO1 COMPEO0
Access R/W R/W R/W
Reset 0 0 0
Name: INTENCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
WIN0 COMP1 COMP0
Access R/W R/W R/W
Reset 0 0 0
Name: INTENSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
WIN0 COMP1 COMP0
Access R/W R/W R/W
Reset 0 0 0
Name: INTFLAG
Offset: 0x06
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
WIN0 COMP1 COMP0
Access R/W R/W R/W
Reset 0 0 0
Bits 0, 1 – COMPx Comparator x
Reading this bit returns the status of the Comparator x interrupt flag. If comparator x is not implemented, COMPx
always reads as zero.
This flag is set according to the Interrupt Selection bit group in the Comparator x Control register
(COMPCTRLx.INTSEL) and will generate an interrupt if INTENCLR/SET.COMPx is also one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Comparator x interrupt flag.
38.7.7 Status A
Name: STATUSA
Offset: 0x07
Reset: 0x00
Property: Read-Only
Bit 7 6 5 4 3 2 1 0
WSTATE0[1:0] STATE1 STATE0
Access R R R R
Reset 0 0 0 0
38.7.8 Status B
Name: STATUSB
Offset: 0x08
Reset: 0x00
Property: Read-Only
Bit 7 6 5 4 3 2 1 0
READY1 READY0
Access R R
Reset 0 0
Name: DBGCTRL
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
Name: WINCTRL
Offset: 0x0A
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.WINCTRL must be checked to ensure the WINCTRL register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
WINTSEL0[1:0] WEN0
Access R/W R/W R/W
Reset 0 0 0
38.7.11 Scaler n
Name: SCALERn
Offset: 0x0C + n*0x01 [n=0..1]
Reset: 0x00
Property: Write-Protected
Bit 7 6 5 4 3 2 1 0
VALUE[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: COMPCTRL
Offset: 0x10 + n*0x04 [n=0..1]
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
OUT[1:0] FLEN[2:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
HYSTEN SPEED[1:0]
Access R/W R/W R/W
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
SWAP MUXPOS[2:0] MUXNEG[2:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RUNSTDBY INTSEL[1:0] SINGLE ENABLE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 1 – ENABLE Enable
Writing a zero to this bit disables comparator n.
Writing a one to this bit enables comparator n.
Due to synchronization, there is delay from updating the register until the comparator is enabled/disabled. The value
written to COMPCTRLn.ENABLE will read back immediately after being written. SYNCBUSY.COMPCTRLn is set.
SYNCBUSY.COMPCTRLn is cleared when the peripheral is enabled/disabled.
Writing a one to COMPCTRLn.ENABLE will prevent further changes to the other bits in COMPCTRLn. These bits
remain protected until COMPCTRLn.ENABLE is written to zero and the write is synchronized.
Name: SYNCBUSY
Offset: 0x20
Reset: 0x00000000
Property: Read-Only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
COMPCTRL1 COMPCTRL0 WINCTRL ENABLE SWRST
Access R R R R R
Reset 0 0 0 0 0
39.1 Overview
The Digital-to-Analog Converter (DAC) converts a digital value to a voltage. The DAC has one channel with 10-bit
resolution, and it is capable of converting up to 350,000 samples per second (350 ksps).
39.2 Features
• DAC with 10-bit resolution
• Up to 350 ksps conversion rate
• Hardware support for 14-bit using dithering
• Multiple trigger sources
• High-drive capabilities
• Output can be used as input to the Analog Comparator (AC), SDADC, or ADC
• DMA support
DATABUF
Internal input
Output
DATA DAC10 Buffer VOUT
VREFA
DAC Controller VDDANA
INTREF
For each Start Conversion event, DATABUF is transferred into DATA and the conversion starts. When DATABUF
is empty, the DAC generates the DMA request for new data. As DATABUF is initially empty, a DMA request is
generated whenever the DAC is enabled.
If the CPU accesses the registers that are the source of a DMA request set/clear condition, the DMA request can be
lost or the DMA transfer can be corrupted, if enabled.
39.6.4 Interrupts
The DAC Controller has the following interrupt sources:
• Data Buffer Empty (EMPTY): Indicates that the internal data buffer of the DAC is empty.
• Underrun (UNDERRUN): Indicates that the internal data buffer of the DAC is empty and a DAC start of
conversion event occurred. Refer to 39.6.5 Events for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a one to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to
the corresponding bit in the Interrupt Enable Clear register (INTENCLR). As both INTENSET and INTENCLR always
reflect the same value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the DAC is reset. See
INTFLAG register for details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt
request to the 9.2 Nested Vector Interrupt Controller. The user must read the INTFLAG register to determine which
interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
39.6.5 Events
The DAC Controller can generate the following output events:
• Data Buffer Empty (EMPTY): Generated when the internal data buffer of the DAC is empty. Refer to
39.6.3 DMA Operation for details.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.EMPTYEO) enables the corresponding
output event. Writing a '0' to this bit disables the corresponding output event.
The DAC can take the following action on an input event:
• Start Conversion (START): DATABUF value is transferred into DATA as soon as the DAC is ready for the next
conversion, and then conversion is started. START is considered as asynchronous to GCLK_DAC thus it is
resynchronized in DAC Controller. Refer to 39.6.2.4 Digital-to-Analog Conversion (DAC) for details.
Writing a '1' to an Event Input bit in the Event Control register (EVCTRL.STARTEI) enables the corresponding action
on an input event. Writing a '0' to this bit disables the corresponding action on input event.
Note: When several events are connected to the DAC Controller, the enabled action will be taken on any of the
incoming events.
By default, DAC Controller detects rising edge events. Falling edge detection can be enabled by writing a '1' to
EVCTRL.INVEIx.
For further information, refer to the 28. Event System (EVSYS).
39.6.7 Synchronization
Due to the asynchronicity between main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read. A register can require:
• Synchronization when written
• Synchronization when read
• Synchronization when written and read
• No synchronization
When executing an operation that requires synchronization, the corresponding status bit in the Synchronization Busy
register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while its busy bit is one, the operation is discarded and an
error is generated.
The following bits need synchronization when written:
• Software Reset bit in the Control A register (CTRLA.SWRST)
• Enable bit in the Control A register (CTRLA.ENABLE)
• All bits in the Data register (DATA)
• All bits in the Data Buffer register (DATABUF)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
No bits need synchronization when read.
To use the dithering feature, EVSYS is used for generating a periodic STARTEI. And the STARTEI event must be
configured (EVCTRL.STARTEI = 1) to generate 16 events for each DATA[13:0] conversion, and DATABUFx must be
loaded every 16 DAC conversions. EMPTYx event and DMA request are therefore generated every 16 DATABUF
to DATA transfers. Using the DMA with dithering is optional. If the DMA is not used, it is required to poll the
INTFLAG.EMTPY flag, or use an interrupt on EMPTY to add a new value in DATABUF.
Note that the input value for DAC is positioned in the DATA register based on CTRLB.LEFTADJ as shown in
the following figure. Refer to 41.8.8 DATA register description for further details. If LEFTADJ = 0: the user writes
DATA[13:4], and the dithering function will take care of bit DATA[3:0] during the 16 sub-conversions.
If LEFTADJ = 1: the user writes DATA[15:6], and the dithering function will take care of bit DATA[5:2] during the 16
sub-conversions.
Following timing diagram shows examples with DATA[15:0] = 0x1210 then DATA[15:0] = 0x12E0 and
CTRLB.LEFTADJ=1.
Figure 39-2. DAC Conversions in Dithering Mode (CTRLB.LEFTADJ=1)
DATA [15:0]
0x1300
0x12E0
0x12C0
VOUT0
0x1240
0x1200 0x1210
sub-conversion 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
39.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized Bits
Bit 7 6 5 4 3 2 1 0
RUNSTDBY ENABLE SWRST
Access R/W R/W R/W
Reset 0 0 0
39.7.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection, Enable-Protected
Bit 7 6 5 4 3 2 1 0
REFSEL[1:0] DITHER VPD LEFTADJ IOEN EOEN
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Name: EVCTRL
Offset: 0x02
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
INVEI EMPTYEO STARTEI
Access R/W R/W R/W
Reset 0 0 0
Name: INTENCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit 7 6 5 4 3 2 1 0
EMPTY UNDERRUN
Access R/W R/W
Reset 0 0
Name: INTENSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Bit 7 6 5 4 3 2 1 0
EMPTY UNDERRUN
Access R/W R/W
Reset 0 0
Name: INTFLAG
Offset: 0x06
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
EMPTY UNDERRUN
Access R/W R/W
Reset 0 0
Bit 0 – UNDERRUN Underrun
This flag is cleared by writing a '1' to it.
This flag is set when a start conversion event occurs when DATABUF is empty, and will generate an interrupt request
if INTENCLR/SET.UNDERRUN is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Underrun interrupt flag.
39.7.7 Status
Name: STATUS
Offset: 0x07
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
READY
Access R
Reset 0
Name: DATA
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.DATA must be checked to ensure the DATA register
synchronization is complete.
Bit 15 14 13 12 11 10 9 8
DATA[15:8]
Access W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Name: DATABUF
Offset: 0x0C
Reset: 0x0000
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.DATABUF must be checked to ensure the DATABUF register
synchronization is complete.
Bit 15 14 13 12 11 10 9 8
DATABUF[15:8]
Access W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DATABUF[7:0]
Access W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
DATABUF DATA ENABLE SWRST
Access R R R R
Reset 0 0 0 0
Bit 2 – DATA Data
This bit is set when DATA register is written.
This bit is cleared when DATA synchronization is completed.
Value Description
0 No ongoing synchronized access.
1 Synchronized access is ongoing.
Name: DBGCTRL
Offset: 0x14
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access
Reset 0
40.1 Overview
The TSENS can be used to measure the operating temperature of the device.
40.2 Features
• Measures temperature
• A selectable reference clock source
GAIN
FCAL ENABLE
OFFSET
START INTFLAG
VALUE
TSENS 0x40003000 5 - N 5 12 N - - - -
Notes:
• The values of GAIN and OFFSET are factory programmed to give a specific temperature slope when using the
undivided internal 48 MHz oscillator (OSC48M) as the GCLK_TSENS source. Other frequencies/sources may
be used, but the GAIN setting and/or expected slope will need to be scaled accordingly.
• The calibration value should be copied and written into the GAIN and OFFSET registers to get the specified
accuracy.
40.5.2.1 Initialization
The generic clocks (GCLK_TSENS) should be configured and enabled. Refer to the Generic Clock Controller chapter
for details.
The following bits are enable-protected, meaning that they can only be written when the TSENS is disabled
(40.6.1 CTRLA.ENABLE is zero):
• Run in Standby bit in Control A register (40.6.1 CTRLA.RUNSTDBY)
The following registers are enable-protected:
• Control C (40.6.3 CTRLC)
• Event Control (40.6.4 EVCTRL)
• Window Monitor Lower Threhold (40.6.11 WINLT)
• Window Monitor Upper Threshold (40.6.12 WINUT)
• Gain Correction (40.6.13 GAIN)
• Offset Correction (40.6.14 OFFSET)
• Calibration (40.6.15 CAL)
Enable-protection is denoted by the Enable-Protected property in the register description.
40.5.2.3 Measurement
After the TSENS is enabled, a measurement can be started either manually, by writing a one to the START bit in
Control B register (CTRLB.START), or automatically by configuring an event input. A free-running mode can be used
to continuously measure the temperature. When the Free running bit in the Control C register (CTRLC.FREERUN) is
written to one, there is no need for a trigger to start the measurement. It will start automatically at the end of previous
measurement.
The result of the measurement is stored in the Value register (VALUE), overwriting the result from the previous
measurement and setting the Result Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.RESRDY).
To avoid data loss, the conversion result must be read as soon as it is available. Failing to do so will result
in an overrun error condition, indicated by the OVERRUN bit in the Interrupt Flag Status and Clear register
(INTFLAG.OVERRUN).
To use an interrupt handler, the corresponding bit in the Interrupt Enable Set register (INTENSET) must be written to
one.
To prevent any discrepancies in the temperature measurement, an average on 10 measurements is recommended.
40.5.4 Interrupts
The TSENS has the following interrupt sources:
• Result Ready (RESRDY): Indicates when a measurement result is available.
• Window Monitor (WINMON): Generated when the measurement result matches the window monitor condition.
Refer to 40.6.3 CTRLC for details.
• Overrun (OVERRUN): Indicates that a new result is ready before the previous result has been read.
• Overflow (OVF): Indicates that the result is invalid because the result required more than 16 bits and overflowed
the VALUE register.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and
Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by
writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a
one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated
when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until
the interrupt flag is cleared, the interrupt is disabled, or the TSENS is reset. See 40.6.7 INTFLAG for details on
how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate
one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt
condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
40.5.5 Events
The TSENS can generate the following output event:
• Window Monitor (WINMON): Generated when the measurement results matches the window monitor condition.
Refer to 40.6.3 CTRLC for details.
Writing a one to an Event Output bit in the Event Control Register (EVCTRL.WINEO) enables the corresponding
output event. Writing a zero to this bit disables the corresponding output event. Refer to the Event System chapter for
details on configuring the event system.
The TSENS can take the following action on an input event:
• Start measurement (START): Start a measurement. Refer to 40.6.2 CTRLB for details.
Writing a one to an Event Input bit into the Event Control register (EVCTRL.STARTEI) enables the corresponding
action on input event. Writing a zero to this bit disables the corresponding action on input event. Refer to the Event
System chapter for details. By default, the TSENS will detect a rising edge on the incoming event. If the TSENS
action must be performed on the falling edge of the incoming event, the event line must be inverted first, by writing to
one the corresponding Event Invert Enable bit in Event Control register (EVCTRL.STARTINV).
40.5.7 Synchronization
Due to the asynchronicity between the main clock domain (CLK_TSENS_APB) and the peripheral clock domain
(GCLK_TSENS) some registers are synchronized when written. When a write-synchronized register is written,
the corresponding bit in the Synchronization Busy register (SYNCBUSY) is set immediately. When the write-
synchronization is complete, this bit is cleared. Reading a write-synchronized register while the synchronization
is ongoing will return the value written, and not the current value in the peripheral clock domain. To read the current
value in the peripheral clock domain after writing a register, the user must wait for the corresponding SYNCBUSY bit
to be cleared before reading the value.
If an operation that require synchronization is executed while its busy bit is on, the operation is discarded and a bus
error is generated.
The following bits need synchronization when written:
• Software Reset bit in Control A register (40.6.1 CTRLA.SWRST)
• Enable bit in Control A register (40.6.1 CTRLA.ENABLE)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
40.6.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized (ENABLE, SWRST)
Bit 7 6 5 4 3 2 1 0
RUNSTDBY ENABLE SWRST
Access R/W R/W R/W
Reset 0 0 0
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value
written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the Synchronization Busy register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
This bit is not enable-protected.
Value Description
0 The peripheral is disabled.
1 The peripheral is enabled.
40.6.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: PAC Write-Protection
Note: PAC write protection will prevent the CTRLB register from write access, but will not trigger a PAC interrupt.
Bit 7 6 5 4 3 2 1 0
START
Access W
Reset 0
40.6.3 Control C
Name: CTRLC
Offset: 0x02
Reset: 0x00
Property: PAC Write-Protection, Enable-protected
Bit 7 6 5 4 3 2 1 0
FREERUN WINMODE[2:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: EVCTRL
Offset: 0x03
Reset: 0x00
Property: PAC Write-Protection, Enable-protected
Bit 7 6 5 4 3 2 1 0
WINEO STARTINV STARTEI
Access R/W R/W R/W
Reset 0 0 0
Name: INTENCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 7 6 5 4 3 2 1 0
OVF WINMON OVERRUN RESRDY
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTENSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 7 6 5 4 3 2 1 0
OVF WINMON OVERRUN RESRDY
Access R/W R/W R/W R/W
Reset 0 0 0 0
Name: INTFLAG
Offset: 0x06
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
OVF WINMON OVERRUN RESRDY
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 3 – OVF Overflow
This flag is cleared by writing a one to the flag.
This flag is set when the conversion result requires more than 24 bits and overflows the VALUE register, and an
interrupt request will be generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
Bit 1 – OVERRUN Overrun
This flag is cleared by writing a one to the flag.
This flag is set if a valid VALUE is updated before the previous valid value has been read by the CPU, and an
interrupt will be generated if INTENCLR/SET.OVERRUN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overrun interrupt flag.
40.6.8 Status
Name: STATUS
Offset: 0x07
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
OVF
Access R
Reset 0
Name: SYNCBUSY
Offset: 0x08
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ENABLE SWRST
Access R R
Reset 0 0
40.6.10 Value
Name: VALUE
Offset: 0x0C
Reset: 0x0000
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
VALUE[23:16]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
VALUE[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
VALUE[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Temperature VALUE
T = 25°C 2500 = 0x09C4
T = -25°C -2500 = 0xFFF63C
Name: WINLT
Offset: 0x10
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
WINLT[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
WINLT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINLT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: WINUT
Offset: 0x14
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
WINUT[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
WINUT[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
WINUT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
40.6.13 Gain
Name: GAIN
Offset: 0x18
Reset: 0x0000
Property: Enable-Protected, PAC Write-Protection, not reset by a software reset
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
GAIN[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
GAIN[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
GAIN[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
40.6.14 Offset
Name: OFFSET
Offset: 0x1C
Reset: 0x0000
Property: Enable-Protected, PAC Write-Protection, not reset by a software reset
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
OFFSETC[23:16]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
OFFSETC[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OFFSETC[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
40.6.15 Calibration
Name: CAL
Offset: 0x20
Reset: 0x00000000
Property: Enable-Protected, PAC Write-Protection, not reset by a software reset
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
TCAL[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FCAL[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Name: DBGCTRL
Offset: 0x24
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access R/W
Reset 0
41.1 Overview
The Frequency Meter (FREQM) can be used to accurately measure the frequency of a clock by comparing it to a
known reference clock.
41.2 Features
• Ratio can be measured with 24-bit accuracy
• Accurately measures the frequency of an input clock with respect to a reference clock
• Reference clock can be selected from the available GCLK_FREQM_REF sources
• Measured clock can be selected from the available GCLK_FREQM_MSR sources
CLK_MSR
GCLK_FREQM_MSR EN COUNTER VALUE
START
CLK_REF DONE
GCLK_FREQM_REF EN TIMER
ENABLE
REFNUM INTFLAG
3: Measure
FREQM 0x40002C00 4 - Y 11 N - - - -
4: Reference
register (VALUE.VALUE). REFNUM is the number of Reference clock cycles selected in the Configuration A register
(CFGA.REFNUM).
The frequency of the measured clock, fCLK_MSR, is calculated by
VALUE f
fCLK_MSR =
REFNUM CLK_REF
41.5.2.1 Initialization
Before enabling FREQM, the device and peripheral must be configured:
• Each of the generic clocks (GCLK_FREQM_REF and GCLK_FREQM_MSR) must be configured and enabled.
Find CLK_FREQM_REF and GCLK_FREQM_MSR values listed in Table 12-9. PCHCTRLm Mapping.
Important: The reference clock must be slower than the measurement clock.
• Write the number of Reference clock cycles for which the measurement is to be done in the Configuration A
register (CFGA.REFNUM). This must be a non-zero number.
The following register is enable-protected, that is it can only be written when the FREQM is disabled:
(CTRLA.ENABLE=0):The Configuration A register (CFGA)
Enable-protection is denoted by the "Enable-Protected" property in the register description.
41.5.2.3 Measurement
In the Configuration A register, the Number of Reference Clock Cycles field (CFGA.REFNUM) selects the duration of
the measurement. The measurement is given in number of GCLK_FREQM_REF periods.
Note: The REFNUM field must be written before the FREQM is enabled.
After the FREQM is enabled, writing a '1' to the START bit in the Control B register (CTRLB.START) starts the
measurement. The BUSY bit in Status register (STATUS.BUSY) is set when the measurement starts, and cleared
when the measurement is complete.
There is also an interrupt request for Measurement Done: When the Measurement Done bit in Interrupt Enable Set
register (INTENSET.DONE) is '1' and a measurement is finished, the Measurement Done bit in the Interrupt Flag
Status and Clear register (INTFLAG.DONE) will be set and an interrupt request is generated.
The result of the measurement can be read from the Value register (VALUE.VALUE). The frequency of the measured
clock GCLK_FREQM_MSR is then:
VALUE f
fCLK_MSR =
REFNUM CLK_REF
Note: In order to make sure the measurement result (VALUE.VALUE[23:0]) is valid, the overflow status
(STATUS.OVF) should be checked.
In case an overflow condition occurred, indicated by the Overflow bit in the STATUS register (STATUS.OVF), either
the number of reference clock cycles must be reduced (CFGA.REFNUM), or a faster reference clock must be
configured. Once the configuration is adjusted, clear the overflow status by writing a '1' to STATUS.OVF. Then
another measurement can be started by writing a '1' to CTRLB.START.
41.5.3 Interrupts
The FREQM has one interrupt source:
• DONE: A frequency measurement is done.
The interrupt flag in the Interrupt Flag Status and Clear (41.6.6 INTFLAG) register is set when the interrupt
condition occurs. The interrupt can be enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set
(41.6.5 INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear
(41.6.4 INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the FREQM is reset. See
41.6.6 INTFLAG for details on how to clear interrupt flags.
This interrupt is a synchronous wake-up source.
Note that interrupts must be globally enabled for interrupt requests to be generated.
41.5.5 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits and registers are write-synchronized:
• Software Reset bit in Control A register (CTRLA.SWRST)
• Enable bit in Control A register (CTRLA.ENABLE)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description
For more information, refer to 11.3 Register Synchronization.
41.6.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized Bits
Bit 7 6 5 4 3 2 1 0
ENABLE SWRST
Access R/W R/W
Reset 0 0
Bit 1 – ENABLE Enable
Note: This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
Value Description
0 The peripheral is disabled.
1 The peripheral is enabled.
41.6.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
START
Access W
Reset 0
41.6.3 Configuration A
Name: CFGA
Offset: 0x02
Reset: 0x0000
Property: PAC Write-Protection, Enable-protected
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
REFNUM[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Name: INTENCLR
Offset: 0x08
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DONE
Access R/W
Reset 0
Name: INTENSET
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DONE
Access R/W
Reset 0
Name: INTFLAG
Offset: 0x0A
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
DONE
Access R/W
Reset 0
41.6.7 Status
Name: STATUS
Offset: 0x0B
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
OVF BUSY
Access R/W R
Reset 0 0
Name: SYNCBUSY
Offset: 0x0C
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ENABLE SWRST
Access R R
Reset 0 0
Bit 1 – ENABLE Enable
This bit is cleared when the synchronization of CTRLA.ENABLE is complete.
This bit is set when the synchronization of CTRLA.ENABLE is started.
41.6.9 Value
Name: VALUE
Offset: 0x10
Reset: 0x00000000
Property: –
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
VALUE[23:16]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
VALUE[15:8]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
VALUE[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
42.1 Overview
The PDEC consists of a Quadrature / Hall decoder, followed by a counter, with two compare channels. The counter
can be split into two parts to report the angular position and the number of revolutions. If the quadrature decoder
feature is not suitable for specific applications, the PDEC module can be used as an additional time base.
42.2 Features
• Internal prescaler
• Selectable mode of operation:
– QDEC, HALL or COUNTER
• QDEC
– Angular and revolution counts
– Synchronous and asynchronous velocity measurements
– Direction change detection
– Check valid quadrature transitions
– Check index position versus angular position
– Auto correction mode
• HALL
– Window validation of Hall transitions
– Hall code detection
– Direction change detection
– Check valid Hall transitions
– Programmable event generation delay after a Hall transition
• COUNTER
– 16-bit counter with two compare channels
– One of the compare channels can be configured with period settings
– Counter overflow interrupt and event generation option
– Compare match interrupt and event generation option
EVEI
EVINV
PDEC_EV[0]
Signal 0 CC1 MC1 (Interrupt or Event)
sync
PINEN
CC0 MC0 (Interrupt or Event)
PINVE
PDEC[0]
0
EVEI
EVINV
PDEC_EV[1]
Signal 1
PINEN
sync
Control
Filter
Logic
PINVE
PDEC[1]
0
VLC (Interrupt or Event)
EVEI
EVINV
sync
PDEC[2]
83: OVF
44: EVU0
84: ERR
85: DIR
PDEC 0x42006800 26 - N 34 26 N 45: EVU1 - Y
86: VLC
87:MC0
46:EVU2
88: MC1
42.6.2.1 Initialization
The following PDEC registers are enable-protected, meaning they can only be written when the PDEC is disabled
(CTRLA.ENABLE is zero):
• Event Control register (EVCTRL)
Enable-protection is denoted by the 'Enable-Protected' property in the register description.
The following register bits are enable-protected, meaning that they can only be written when the PDEC is disabled
(CTRLA.ENABLE=0):
• Maximum Consecutive Missing Pulses bits in Control A register (CTRLA.MAXCMP[3:0])
• Angular Counter Length bits in Control A register (CTRLA.ANGULAR[2:0])
• I/O Pin x Invert Enable bits in Control A register (CTRLA.PINVEN[2:0])
• PDEC Input From Pin x Enable bits in Control A register (CTRLA.PINEN[2:0])
• Period Enable bit in Control A register (CTRLA.PEREN)
• PDEC Phase A and B Swap bit in Control A register (CTRLA.SWAP)
• Auto Lock bit in Control A register (CTRLA.ALOCK)
• PDEC Configuration bits in Control A register (CTRLA.CONF[2:0])
• Run in Standby bit in Control A register (CTRLA.RUNSTDBY)
• Operation Mode bits in Control A register (CTRLA.MODE[1:0])
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but
not at the same time as CTRLA.ENABLE is written to '0'.
The PDEC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The PDEC is
disabled by writing a '0' to CTRLA.ENABLE.
In QDEC or HALL operation modes, PDEC decoding is enabled writing a START command in the Control B Set
register (CTRLBSET.CMD=START). The PDEC decoding is disabled writing a STOP command in the Control B Set
register (CTRLBSET.CMD=STOP).
The PDEC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in
the PDEC, except DBGCTRL, will be reset to their initial state, and the PDEC will be disabled.
The PDEC should be disabled before the PDEC is reset to avoid undefined behavior.
PRESC EVACT
GCLK_PDEC Prescaler
GCLK_PDEC / COUNT
{1,2,4,8,64,256,1024 } EVENT CLK_PDEC
Prescaled Clock
Filter Out
Only the first two input signals can be swapped by writing to the SWAP bit in the Control A register (CTRLA.SWAP).
of operation. In X4 mode, a simultaneous transition on Phase A and Phase B will cause a QDEC error detection
(STATUS.QERR).
Figure 42-4. QDEC Block Diagram
sync
Signal 0
Count
CC0 MC0 (Interrupt or Event)
Quadrature
Position Direction OVF (Interrupt or Event)
Decoder
Phase B Filter DIR Reset Counter (n-bits) Counter (16/32-n-bits)
sync
– The first valid Index detection after the module is enabled, will reload the counter with ZERO value
– Any other valid Index detection which does not match the Angular counter overflow or underflow,
will set the Index Error flag in Status register (STATUS.IDXERR). The Error Interrupt Flag is set
(INTFLAG.ERR)and an optional interrupt can be generated.
The Revolution counter will count up or down, depending on the counting direction and configuration modes:
• In X2 and X4 confirmation operating mode:
– If the Index is enabled, the counter is incremented (or decremented depending on counting direction) on
each index detection
– If the Index is disabled, the counter is incremented (or decremented depending on counting direction) on
each Angular counter overflow/underflow
• In X2S and X4S confirmation operating mode, the counter is incremented (or decremented depending on
counting direction) on each Angular counter overflow/underflow
– If the Index is not detected after one Angular counter revolution, the Index Error flag in Status register
(STATUS.IDXERR) is set. The Error Interrupt Flag is set (INTFLAG.ERR) and an optional interrupt can be
generated.
When counting-up and its TOP value is reached, the Channel 0 Compare Match Interrupt Flag in the Interrupt
Flag Status and Clear register (INTFLAG.MC0) will be set. When counting-down and ZERO is reached, the
INTFLAG.MC0 will be set. The Channel 0 Compare Match condition can be enabled as source of interrupt or event
generation.
Figure 42-5. Position and Rotation Measurement
PhaseA
PhaseB
Index
DIR Event
Angle OVF
ERR
CC0 (LSB)
CC1 (LSB)
Anglular
Counter
CC1 (MSB)
Revolution
Counter
MC1 Event
In X4 and X4S configuration, a valid index is detected when the three inputs (PhaseA, PhaseB and Index) are at low
level.
In X2 and X2S configuration, a valid index is detected when the two inputs (Count and Index) are at low level.
In X2 and X4 configuration, depending on current detected direction, Index will reset or reload the Angular counter
and increment or decrement the Revolution counter.
In X2S and X4S configuration, the Angular counter is reset on the first Index occurrence after the PDEC decoding
is enabled. When any next Index occurrence does not match an Angular counter overflow or underflow, the Index
Error flag in Status register is set (STATUS.IDXERR). The Error Interrupt Flag is set (INTFLAG.ERR) and an optional
interrupt can be generated.
An Index Error is also generated after the PDEC decoding is enabled and no Index has been detected after one
Angular counter revolution.
Missing Angular Step Missing Index
First error detection is ignored Detection Extra Index Detection Detection
Phase A
Phase B
Index
ERR
Match Angular
Max Value
Angular
Counter
Revolution
Counter
PhaseA
PhaseB
Anglular
Counter
DIR Event
DIRCHG Interrupt
VLC Event
To avoid spurious interrupts when coding wheel is stopped, the direction change condition is reported as an interrupt,
only on the second edge confirming the direction change.
Velocity output event is generated on each QDEC transition except when the direction changes.
MC1
EV TCk MC0
OVF
There is no autocorrection if both phase signals are affected at the same location on the input signals, because the
autocorrection requires a valid phase signal to detect contamination on the other phase signal.
If the quadrature source is undamaged, the number of pulses counted for a predefined period of time must be the
same with or without detection and auto-correction. Therefore, if the measurement results differ, a contamination
exists on the source producing the quadrature signals. This does not substitute the measurements of the number
of pulses between two index pulses (if available) but provides an additional method to detect damaged quadrature
sources.
When the source providing quadrature signals is strongly damaged, potentially leading to a number of consecutive
missing pulses greater than 1, the quadrature decoder processing may be affected.
The Maximum Consecutive Missing Pulses bits in Control A register (CTRLA.MAXCMP) define the maximum
acceptable number of consecutive missing pulses. If the limit is reached, the Missing Pulse Error flag in Status
register (STATUS.MPERR) is set. The Error Interrupt flag is set (INTFLAG.ERR) and an optional interrupt can be
generated.
Note: When the MAXCMP value is zero, the MPERR error flag is never set.
CC1(MSB) CC1[2:0]
Phase A (Unused) MC1 (Interrupt/Event)
sync
Window Max
Signal 0
CC0(MSB) CC0[2:0]
Window Min Hall Code Trigger MC0 (Interrupt/Event)
COUNT(MSB) COUNT(LSB)
Decoder
Phase B
Hall
Delay Counter
sync
Window Counter
Signal 1
Velocity Clock
VLC (Interrupt/Event)
Direction Change Detection
Phase C DIR (Interrupt/Event)
sync
When positive rotation is detected, the DIR status bit is set (STATUS.DIR = 1). When a negative rotation sequence is
detected, the DIR status bit is set (STATUS.DIR = 0).
CC1(MSB)
CC0(MSB)
Counter(MSB)
ERR
VLC Event
MC0 Event
OVF Event
DIR Event
DIR Interrupt
42.6.4 Interrupts
The PDEC has the following interrupt sources:
• Overflow/Underflow: OVF
• Compare Channels: COMPx
• Error: ERR
• Velocity: VLC. This interrupt is available only in QDEC and HALL operation modes.
• Direction: DIR. This interrupt is available only in QDEC and HALL operation modes.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing
a '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a '1' to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). As both INTENSET and INTENCLR always
reflect the same value, the status of interrupt enablement can be read from either register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the PDEC is reset. See
the INTFLAG register description for details on how to clear interrupt flags.
The user must read the INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. See the Nested Vector Interrupt
Controller.
42.6.5 Events
The PDEC can generate the following output events:
• Overflow/Underflow: OVF
• Channel x Compare Match: MCx
• Error: ERR
• Velocity: VLC. This interrupt is available only in QDEC and HALL operation modes.
• Direction: DIR. This interrupt is available only in QDEC and HALL operation modes.
Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.MCEO) enables the corresponding output
event. Writing a '0' to this bit disables the corresponding output event.
In counter mode the PDEC can take action on an input event. PDEC counter event input are available for each of the
three PDEC channels.
• Retrigger: Restart/retrigger on event
See the EVSYS for further information.
42.6.7 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
• Software Reset bit in the Control A register (CTRLA.SWRST)
• Enable bit in the Control A register (CTRLA.ENABLE)
The following registers need synchronization when written:
• Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
• Status register (STATUS)
• Prescaler and Prescaler Buffer registers (PRESC and PRESCBUF)
• Compare Value x and Compare Value x Buffer registers (CCx and CCBUFx)
• Filter Value and Filter Buffer Value registers (FILTER and FILTERBUF)
• Counter Value register (COUNT)
Required write synchronization is denoted by the "Write-Synchronized" property in the register description.
The following registers are synchronized when read:
• Counter Value register (COUNT): the synchronization is done on demand through READSYNC software
command (CTRLBSET.CMD)
Required read synchronization is denoted by the "Read-Synchronized" property in the register description.
42.7.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits
Bit 31 30 29 28 27 26 25 24
MAXCMP[3:0] ANGULAR[2:0]
Access RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
PINVEN2 PINVEN1 PINVEN0 PINEN2 PINEN1 PINEN0
Access RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
PEREN SWAP ALOCK CONF[2:0]
Access RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RUNSTDBY MODE[1:0] ENABLE SWRST
Access RW RW RW RW W
Reset 0 0 0 0 0
Bit 1 – ENABLE Enable
Notes:
1. This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE
synchronization is complete.
2. This bit is not enable-protected.
Value Description
0 The peripheral is disabled.
1 The peripheral is enabled.
Name: CTRLBCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Set (CTRLBSET) register.
Note: This register is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLBCLR register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CMD[2:0] LUPD
Access RW RW RW RW
Reset 0 0 0 0
Name: CTRLBSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Clear (CTRLBCLR) register.
Note: This register is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLBSET register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
CMD[2:0] LUPD
Access RW RW RW RW
Reset 0 0 0 0
Name: EVCTRL
Offset: 0x06
Reset: 0x0000
Property: Enable-Protected, PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
MCEO1 MCEO0 VLCEO DIREO ERREO OVFEO
Access RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EVEI[2:0] EVINV[2:0] EVACT[1:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Value Description
1 Incoming events are enabled.
Name: INTENCLR
Offset: 0x08
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit 7 6 5 4 3 2 1 0
MC1 MC0 VLC DIR ERR OVF
Access RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Name: INTENSET
Offset: 0x09
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit 7 6 5 4 3 2 1 0
MC1 MC0 VLC DIR ERR OVF
Access RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Name: INTFLAG
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
MC1 MC0 VLC DIR ERR OVF
Access RW RW RW RW RW RW
Reset 0 0 0 0 0 0
Bit 3 – VLC Velocity
This flag is set if a velocity transition occurs, and will generate an interrupt request if the Velocity Interrupt Enable bit
in Interrupt Enable Set register (INTENSET.VLC) is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Velocity transition interrupt flag.
This flag is never set when COUNTER operation mode is selected.
Bit 1 – ERR Error
This flag is set when an error condition is detected, and will generate an interrupt request if the Error Interrupt Enable
bit in the Interrupt Enable Set register (INTENSET.ERR) is '1'. The error source can be identified by reading the
Status (STATUS) register.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Error interrupt flag.
Bit 0 – OVF Overflow/Underflow
This flag is set on the next CLK_TC_CNT cycle after an overflow condition occurs, and will generate an interrupt
request if the Overflow Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.OVF) is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
42.7.8 Status
Name: STATUS
Offset: 0x0C
Reset: 0x0040
Property: Read-Synchronized, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.STATUS must be checked to ensure the STATUS register
synchronization is complete.
Bit 15 14 13 12 11 10 9 8
CCBUFV1 CCBUFV0 FILTERBUFV PRESCBUFV
Access R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DIR STOP HERR WINERR MPERR IDXERR QERR
Access R R RW RW RW RW RW
Reset 0 1 0 0 0 0 0
Bit 6 – STOP Stop
This bit reflects the HALL/QDEC decoding status.
In COUNTER mode, this bits is always read '0'.
Value Description
0 PDEC/HALL decoding is running.
1 PDEC/HALL decoding is stopped.
Name: DBGCTRL
Offset: 0x0F
Reset: 0x00
Property: PAC Write-Protection
Bit 7 6 5 4 3 2 1 0
DBGRUN
Access RW
Reset 0
Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: Read-Only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
CC1
Access R
Reset 0
Bit 7 6 5 4 3 2 1 0
CC0 COUNT FILTER PRESC STATUS CTRLB ENABLE SWRST
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Name: PRESC
Offset: 0x14
Reset: 0x00
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.PRESC must be checked to ensure the PRESC register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
PRESC[3:0]
Access RW RW RW RW
Reset 0 0 0 0
Name: FILTER
Offset: 0x15
Reset: 0x00
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.FILTER must be checked to ensure the FILTER register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
FILTER[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: PRESCBUF
Offset: 0x18
Reset: 0x00
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.PRESC must be checked to ensure the PRESC register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
PRESCBUF[3:0]
Access RW RW RW RW
Reset 0 0 0 0
Name: FILTERBUF
Offset: 0x19
Reset: 0x00
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.FILTER must be checked to ensure the FILTERBUF register
synchronization is complete.
Bit 7 6 5 4 3 2 1 0
FILTERBUF[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: COUNT
Offset: 0x1C
Reset: 0x00000000
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.COUNT must be checked to ensure the COUNT register
synchronization is complete.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
COUNT[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
COUNT[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: CCx
Offset: 0x20 + x*0x04 [x=0..1]
Reset: 0x00000000
Property: Read-Synchronized, Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCx register
synchronization is complete.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
CC[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CC[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Name: CCBUFx
Offset: 0x30 + x*0x04 [x=0..1]
Reset: 0x00000000
Property: Write-Synchronized
Note: This register is write-synchronized: SYNCBUSY.CCx must be checked to ensure the CCBUFx register
synchronization is complete.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
CCBUF[15:8]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CCBUF[7:0]
Access RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions, above those
indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2. Maximum allowable current is a function of device maximum power dissipation.
Param. No. VDDIO, VDDIN, VDDANA Range Temp. Range (in °C) Max CPU Frequency Comments
DC_5 2.7 to 5.5V(1,2,3) -40°C to +85°C 48 Mhz Industrial
Notes:
1. With BODVDD disabled.
2. The same voltage must be applied to VDDIN and VDDANA. This common voltage is referred to as VDD in the
data sheet. VDDIO should be lower or equal to VDD = VDDIN = VDDANA.
3. Some I/Os are in the VDDIO cluster, but can be multiplexed as analog functions (inputs or outputs). In such
a case, VDDANA is used to power the I/O. Using this configuration may result in an electrical conflict if the
VDDIO voltage is lower than VDD = VDDIN = VDDANA.
Note:
1. See Absolute Maximum Ratings.
Table 43-4. Thermal Packaging Characteristics
Note:
1. Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise
DC CHARACTERISTICS stated)
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise
DC CHARACTERISTICS stated)
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
DC calibrated output
REG_39 VDDCORE 1.08 1.23 1.32 V —
voltage
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise
DC CHARACTERISTICS stated)
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
VDDIO Power- up or
VDDIO/VDD Falling Power-down (See Param
REG_45B VPOR- 1.64 — 1.92 V
Power-on Reset REG_43, VDDIO/VDD
Ramp Rate)
(Default Setting)
2.74 2.80 2.86 V LEVEL[5:0] = 0x8 (3)
HYST[0] = 0x0
(Default Setting)
2.74 2.86 2.91 V LEVEL[5:0] = 0x8 (3,4)
REG_47 VBODVDD VDDIO BOD (All modes) HYST[0] = 0x1
Notes:
1. In single power supply configuration, only one bulk capacitor (REG_4 or REG_7) is enough for both VDDIN and VDDIO. In dual-power supply configuration,
two bulk capacitors are needed: REG_4 for VDDIO and REG_7 for VDDIN.
2. VDDIN and VDDANA must be at the same voltage level. VDDIO should be lower or equal to VDDIN/ VDDANA. The common voltage is referred to as VDD in
the data sheet. Some I/O are in the VDDIO cluster, but can be multiplexed as analog inputs or outputs (e.g. TCC[n] pads). In such a case, VDDANA is used to
power the I/O. Using this configuration may result in an electrical conflict if the VDDIO voltage is lower than the VDDIN/VDDANA.
3. VBODVDD-(min) = 2.372 + (BODVDD.LEVEL[5:0]) * 0.047
4. VBODVDDHYST_STEP Graph:
VBODVDD(max)@BODVDD.HYST[0] =1 = VBODVDD(max)@BODVDD.HYST[0] = 0 + VBODVDDHYST_STEP
5. Shared between VDDIO, VDDIN, and VDDANA in case of a common power supply VDD = VDDIO = VDDIN = VDDANA.
6. Shared between VDDIO, VDDIN, and VDDANA in case of a common power supply VDD = VDDIO = VDDIN = VDDANA. Else, shared between VDDIN =
VDDANA.
7. If the VREF is not used, then the caps are not needed.
VDDANA = VDDIO = 5V
APWR_1 99.6 112.9 µA/MHz
XOSC32K at 32.768 kHz as reference of FDPLL (2)
FDPLL 48MHz
VDDANA = VDDIO = 3.3V
APWR_3 97.3 110 µA/MHz
XOSC32K at 32.768 kHz as reference of FDPLL (2)
IDD_ACTIVE MCU IDD in active mode
VDDANA = VDDIO = 5V
APWR_5 97.8 110.4 µA/MHz
XOSC32K Off (2)
OSC48M 48MHz
VDDANA = VDDIO = 3.3V
APWR_7 95.5 107.9 µA/MHz
XOSC32K Off (2)
Notes:
1. Typical values at 25°C only.
2. Conditions:
– No peripheral modules are operating (i.e., all peripherals inactive)
– APB clocks not needed are masked: except MCLK and NVMCTRL
– MCLK.AHBMASK = 0x000005FF
– All I/O pins configured as input pins pulled down or tied to GND
– WDT, RTC, CFD Clock Fail Detect disabled
– RESET = VDDIO
– CPU is running on Flash with 2 Wait States
– NVMCTRL cache enabled
– BODVDD disabled
Figure 43-1. Power Consumption over Temperature in Active Mode (Typical values for guidance only, not
tested in manufacturing)
6000
VDD = 5,5V
5000 VDD = 2,7V
4000
ICC[µA]
3000
2000
1000
0
‐40 ‐30 ‐20 ‐10 0 10 20 30 40 50 60 70 80 90 100 110 120
Temperature [°C]
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
VDDANA = VDDIO = 5V
IPWR_1 19.1 25 µA/MHz
XOSC32K at 32.768 kHz as reference of FDPLL(2)
FDPLL 48MHz
VDDANA = VDDIO = 3.3V
IPWR_3 19 24.8 µA/MHz
XOSC32K at 32.768 kHz as reference of FDPLL(2)
IDD_IDLE CPU IDD in IDLE mode
VDDANA = VDDIO = 5V
IPWR_5 17.3 22.2 µA/MHz
XOSC32K Off(2)
OSC48M 48MHz
VDDANA = VDDIO = 3.3V
IPWR_7 17.2 22 µA/MHz
XOSC32K Off(2)
Notes:
1. Typical values at 25°C only.
2. Conditions:
– No peripheral modules are operating (That is, all peripherals inactive)
– All clock sources disabled unless otherwise specified. (that is, XOSC32 = Off)
– GCLK clock generators 1 to 8 stopped (GENCTRL[8:1].GENEN = 0)
– AHB/APB clocks not needed are masked: AHBMASK = 0x70, APB (A/B/C/D) MASK = 0x0
– CPU stopped and AHB clocks undivided
– All I/O pins configured as input pins pulled down or tied to GND
– WDT, RTC, CFD Clock Fail Detect disabled
– RESET = VDDIO
– NVMCTRL cache enabled
– BODVDD disabled
Figure 43-2. Power Consumption at Over Temperature in IDLE Mode (typical Values for guidance only, not
characterized over process / voltage)
1600
1400
VDD = 5,5V
1200 VDD = 2,7V
1000
ICC[µA]
800
600
400
200
0
‐40 ‐30 ‐20 ‐10 0 10 20 30 40 50 60 70 80 90 100 110 120
Temperature [°C]
Operation Conditions
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
VDD =
Param. No. Symbol Characteristics Typ.(1) Max. Units Conditions
VDDIO
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
VDD =
Param. No. Symbol Characteristics Typ.(1) Max. Units Conditions
VDDIO
Notes:
1. Typical values at 25°C only.
2. Conditions:
– System in standby mode
– No SleepWalking (except RTC when indicated)
– Peripheral modules are inactive (except RTC when indicated)
– All clocks stopped (CPU, AHB, APB, Main, GCLK, except RTC running at 1 KHz from XOSC32K when indicated)
– All clock generation sources disabled except XOSC32K running with external 32 kHz crystal when indicated
– All I/O pins configured as input pins pulled down or tied to GND
– WDT, CFD Clock Fail Detect disabled
– BODVDD disabled
– RESET = VDDIO.
Figure 43-3. Power Consumption Over Temperature in Standby Sleep Mode with RTC
700
PERFORMANCE ‐ VDD = 5V
600
PERFORMANCE ‐ VDD = 3,3V
500
400
ICC[µA]
100
0
‐40 ‐30 ‐20 ‐10 0 10 20 30 40 50 60 70 80 90 100 110 120
Temperature [°C]
Operating Conditions:
• VDD = VDDIO = 5.0V
PAI_30 IBOD50 BOD50 Active current Continuous mode, VDDANA = VDDIO = 5.0V
...........continued
Standard Operating Conditions: VDDIO = VDDANA 2.7V to 5.5V (unless
DC CHARACTERISTICS otherwise stated)
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
PAI_33 IEVSYS EVSYS Active current One channel operating, Synchronous mode
PAI_36 ICCL CCL Active current All LUT Active, Filter Enabled
PAI_50 IEIC EIC/NMI Active current One EIC line operating, Filter Enabled
PAI_65 ITC4 TC Active current (1 of 2) Normal Frequency mode, Counter in 16bits mode
PAI_70 IAC AC Active current COMP0 and COMP1 operating in low speed, Vscaler0 = Vscaler1 = VDDANA
PAI_100 ITC0/1/2/3 TC Active current (2 of 2) Normal Frequency mode, Counter in 16bits mode
PAI_120 IDAC DAC Active current VREF = VDDANA, DAC DATA = 0x3FF (2)
...........continued
Standard Operating Conditions: VDDIO = VDDANA 2.7V to 5.5V (unless
DC CHARACTERISTICS otherwise stated)
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
PAI_150 IFREQM FREQM Active current Reference running at 48MHz and Measure clock running at 96 MHz (3)
PAI_200 IADC ADC Active current Free-Running, 1 Msps, VDDANA = VREF = 5,5V (4)
PAI_203 IDMA DMA Active current RAM-to-RAM transfer, one channel operating
...........continued
Standard Operating Conditions: VDDIO = VDDANA 2.7V to 5.5V (unless
DC CHARACTERISTICS otherwise stated)
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Notes:
1. Conditions:
– Only mentioned peripheral module is operating (that is, rest of the peripherals are inactive)
– MCLK all APB clock masked except MCLK and NVMCTRL and selected peripheral
– MCLK.AHBMASK = 0x00005FF
– All clock generation sources disabled unless otherwise specified. (that is, XOSC32 = OFF)
– All clock sources disabled except XOSC32K running with external 32kHz crystal and FDPLL96M using XOSC32K as reference and running at 96MHz
divided by 2 on GCLK0
– GCLK clock generators 1 to 8 stopped (GENCTRL[8:1].GENEN = 0)
– CPU and AHB clocks undivided
– All I/O pins configured as input pins pulled down or tied to GND
– WDT, RTCC, CFD Clock Fail Detect disabled
– RESET = VDDIO
– CPU is running on Flash with 2 Wait States
– NVMCTRL cache enabled
– BODVDD disabled
– Measure is differential between active and inactive module in those conditions
2. Conditions:
– Same Conditions as Note 1
– GCLK1 running on FDPLL96M at 96 MHz divided by 96
– Measure is differential between active and inactive module in those conditions
3. Conditions:
– Same Conditions as Note 1
– GCLK1 running on FDPLL96M at 96 MHz not divided
– Measure is differential between active and inactive module in those conditions
4. Conditions:
– Same Conditions as Note 1
– GCLK1 running on FDPLL96M at 96 MHz divided by 6
– Measure is differential between active and inactive module in those conditions
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Note:
1. – VDD = VDDIO = 5.0V
– CPU clock = 8 MHz from OSC48M
– 0 wait states
– Flash in WAKEUPINSTANT mode (NVMCTRL.CTRLB.SLEEPRM=1)
– Cache enabled/disabled
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Notes:
1. VIL source < (GND - 0.3). Characterized but not tested.
2. 5.5V < VIH source ≤ 5.8V. Characterized but not tested.
3. If the sum of all injection currents are > | ∑IICT | it can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDDIO + 0.3) or VIL source <
(GND - 0.3)).
4. Any number and/or the combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the “absolute instantaneous” sum of the
input injection currents from all pins do not exceed the specified ∑IICT limit. To limit the injection current the user must insert a resistor in series RSERIES, (i.e.
RS), between input source voltage and device pin. The resistor value is calculated according to:
– For negative Input voltages less than (GND-0.3): RS ≥ absolute value of | ((VIL source - (GND - 0.3)) / IICL) |
– For positive input voltages greater than (VDDIO + 0.3): RS ≥ absolute value of | ((VIH source - (VDDIO + 0.3)) / IICH) |
– For Vpin voltages >VDDIO +0.3 and <GND-0.3 then RS = the larger of the values calculated above.
5. The following pins are High Sink pins and have different properties than standard pins: PA10, PA11, PB10, PB11.
6. The following pins are TWIHS pins and have the same properties as standard pins when not used as SERCOM I2C pins: PA08, PA09, PA12, PA13, PA16,
PA17, PA22, PA23. When used in SERCOM I2C mode, refer to I2CM_5/7 and I2CS_5/7 parameters.
Param. No. Symbol Characteristics Min. Typical (1) Max. Units Conditions
VR_27 VDRIFT Internal Voltage Reference Voltage Drift -0.111 - 0.252 %/V Over full operating voltage range
Notes:
1. Typical values at 25°C only.
2. ADC, DAC, SDADC Internal Voltage Reference voltage 2.4V ≤ IREF ≤ VDDANA.
3. ADC, DAC, SDADC reference voltages < 2.4V, (i.e. < 500µV/step), is not practical and peripheral performance is not guaranteed.
4. Comparator Ref voltage cannot exceed (VIN(max)-VIOFF(max)-200mV) ≥ CMP VREF ≥ (VIN(min)+VIOFF(min)+200mV) (i.e. VIN = Parameter CMP_4,
VIOFF = Parameter CMP_1).
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
XOSC Crystal
Stabilisation Time(3) CL = 20pF,
XOSC_2 XOSC_ST — 12300 — TOSC
XOSC Crystal FOSC = XOSC.GAIN = 0,1,2,3,4
2 - 32 MHz
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Notes:
1. This is for guidance only. A major component of crystal start-up time is based on the second party crystal MFG parasitics that are outside the scope of this
specification. If this is a major concern the customer would need to characterize this based on their design choices.
2. CRYSTAL LOAD CAPACITOR CALCULATION GIVEN:
– Standard PCB trace capacitance = 1.5 pf per 12.5 mm (0.5 inches) (i.e., PCB STD TRACE W = 0.175 mm, H = 36 μm, T=113 μm)
– Xtal PCB capacitance typical therefore ~= 2.5 pF for a tight PCB xtal layout
– For CXIN and CXOUT within 4 pF of each other, Assume CXTAL_EFF = ((CXIN+CXOUT) / 2)
Note: Averaging CXIN and CXOUT will effect final calculated CLOAD value by less than 0.25 pF.
EQUATION 1:
MFG CLOAD Spec = {( [CXIN + C1] * [CXOUT + C2] ) / [CXIN + C1 + C2 + CXOUT] } + estimated oscillator PCB stray capacitance
– Assuming C1 = C2 and CXIN ~= CXOUT, the formula can be further simplified and restated to solve for C1 and C2 by:
EXAMPLE ONLY:
Figure 43-4. XTAL
C2
MCU XIN
XTAL
MCU XOUT
RS
C1
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
XOSC32 XIN32
XOSC32_3 CXIN32 parasitic pin — 3 — pF —
capacitance
XOSC32 XOUT32
XOSC32_5 CXOUT32 parasitic pin — 3.1 — pF —
capacitance
XOSC32K.XTALEN = 1
32.768 kz Crystal
XOSC32_13 ESR_X32 — — 70 kΩ XOSC32K.ENABLE = 1
ESR
CLOAD = 12.5 pF
See parameter
TOSC32 = 1/
XOSC32_15 TOSC32 — 30.5176 — us XOSC32_1 for
FOSC_XOSC32
FOSC_XOSC32 value
XOSC32 Crystal
XOSC32_17 XOSC32_ST — 16000 (3) TOSC32 32.768 kHz Crystal (1)
Stabilization Time
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Notes:
1. This is for guidance only. A major component of crystal start-up time is based on the Second party crystal MFG parasitics that are outside the scope of this
specification. If this is a major concern the customer would need to characterize this based on their design choices.
2. CRYSTAL LOAD CAPACITOR CALCULATION GIVEN:
– Standard PCB trace capacitance = 1.5 pF per 12.5 mm (0.5 inches) (i.e. PCB STD TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
– Xtal PCB capacitance typical therefore ~= 2.5 pF for a tight PCB xtal layout
– For CXIN and CXOUT within 4pF of each other, Assume CXTAL_EFF = ((CXIN+CXOUT) / 2)
Note: Averaging CXIN and CXOUT will effect final calculated CLOAD value by less than 0.25 pF.
EQUATION 1:
MFG CLOAD Spec = {( [CXIN + C1] * [CXOUT + C2] ) / [CXIN + C1 + C2 + CXOUT] } + estimated oscillator PCB stray capacitance
– Assuming C1 = C2 and CXIN ~= CXOUT, the formula can be further simplified and restated to solve for C1 and C2 by:
EXAMPLE ONLY:
C1 = C2 = (24 - 5.5 - 5)
Figure 43-5. XTAL
C2
MCU XIN32
XTAL
MCU XOUT32
RS
C1
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
OSC48M_1 FOSC48M OSC48M Oscillator Frequency 46.6 — 49.5 MHz -40 to 85°C
Notes:
1. 25°C, VDD = VDDIO = 5.0V.
2. An option for more accurate RC can be available upon request. Contact your local Microchip Sales office for additional information.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
fOUT = 48 MHz
FDPLL_5
VDD = VDDIO = 5.0v,
1 — 8.6 % fIN = 32.768 kHz from XOSC32K,
fOUT = 96 MHz
FDPLL_Jitter FDPLL96M Period Jitter Pk-to-Pk (1,2)
VDD = VDDIO = 5.0v,
1.4 — 3.9 % fIN = 2 MHz from XOSC,
fOUT = 48 MHz
FDPLL_7
VDD = VDDIO = 5.0v,
1 — 6.8 % fIN = 2 MHz from XOSC,
fOUT = 96 MHz
fOUT = 96 MHz
FDPLL_11 FDPLL_SRT FDPLL96M Start-Up/Lock Time Time (1)
VDD = VDDIO = 5.0v,
— 25 — µs fIN = 2 MHz from XOSC,
fOUT = 96 MHz
Notes:
1. REFCLK for FDPLL96M is XOSC or XOSC32K.
2. The provided jitter performance will be the best achieved on the device. Digital activity can increase jitter but is highly dependent on the application use model.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Internal connection to
GNDANA — VREF V another module (for
example, AC) (No buffer)
VDDANA
CTRLB.REFSEL = VDDANA V —
0x1
DAC
VREFA pin
Reference
DAC_9 VREF (1,2) CTRLB.REFSEL = 2.4V (1,2) — VDDANA - 0.6V V VDDANA ≥ VREF + 0.6V
Input Option
(1,2) 0x2
INTREF
CTRLB.REFSEL = 2.4V (1,2) VR_1 VDDANA - 0.6V V See parameter VR_1
0x0
CTRLB.REFSEL = 0x1
-1.2 — 1.2 LSB VREF = VDDANA = 5.0V
CTRLB.REFSEL = 0x2
SDAC_19 INL(4) Integral Non Linearity
VDDANA = 5.0V
CTRLB.REFSEL = 0x1
-1.4 — 1.4 LSB VREF = VDDANA = 5.0V
CTRLB.REFSEL = 0x2
SDAC_21 DNL(4) Differential Non Linearity
VDDANA = 5.0V
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
CTRLB.REFSEL = 0x1
DAC reference =
-5.4 — 5.4 LSB VDDANA = 5.0V
CTRLB.REFSEL = 0x1
DAC reference =
-3.4 — 3.4 LSB VDDANA = 5.0V
Notes:
1. DAC Internal Bandgap Reference voltage 4.096V when used.
2. DAC functional device operation with either internal or external VREF<2.4v is guaranteed, but not characterized. DAC will function, but with degraded
performance. DAC accuracy is limited by users application noise/accuracy on VDDANA, GNDANA and VREF accuracy/drift.
3. 10-bit mode.
4. Over VOUT range defined by DAC_7 parameter.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Device Supply
Reference Inputs
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
VREF = VDDANA
2.7 (1) VDDANA V
(REFCTRL.REFSEL = 0x5)
CTRLA.ENABLE = 1 or
ADC_11 TSETTLING ADC Stabilization Time — 10 — µs
CTRLA.ONDEMAND = 1
Note:
1. ADC functional device operation with either internal or external VREF < 2.4V is functional, but not characterized. ADC will function, but with degraded
accuracy of approximately ~((0.06 * 2n) / VREF), where "n" = #bits. ADC accuracy is limited by internal VREF accuracy + drift, MCU generated noise plus
users application noise/accuracy on VDDANA, GNDANA.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Notes:
1. Characterized with an analog input sine wave = (FTP(max) / 100). For example, FTP(max)=1Msps/100 = 10kHz sine wave.
2. Sine wave peak amplitude = 96% ADC Full Scale amplitude input with 12bit resolution.
3. Spec values collected under the following additional conditions:
3.1. 12bit resolution mode.
3.2. All registers at reset default value otherwise not mentioned.
4. Value taken over 7 harmonics.
5. SAMPCTRL.OFFCOMP = 0, SAMPCTRL.SAMPLEN = [5:0] = 3.
6. SAMPCTRL.OFFCOMP = 0 and REFCTRL.REFCOMP = 0 , SAMPCTRL.SAMPLEN = [5:0] = 3.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Notes:
1. Characterized with an analog input sine wave = (FTP(max) / 100). Example: FTP(max)=1Msps/100 = 10Khz sine wave.
2. Sinewave peak amplitude = 96% ADC_ Full Scale amplitude input with 12bit resolution c) 12bit resolution mode.
3. Spec values collected under the following additional conditions:
– 12bit resolution mode
– All registers at reset default value otherwise not mentioned
4. Value taken over 7 harmonics.
5. SAMPCTRL.OFFCOMP=1.
6. SAMPCTRL.OFFCOMP=1 and REFCTRL.REFCOMP=1.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise
AC CHARACTERISTICS stated)
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Notes:
1. ADC Sample time = ((SAMPCTRL.SAMPLEN + 1) * TAD) and SAMPCTRL.OFFCOMP=0.
2. ADC HDW forces sample time to 4*TAD when SAMPCTRL.OFFCOMP=1, user SAMPCTRL.SAMPLEN is ignored.
3. ADC Throughput Rate FTP = ((1 / ((TSAMP + TCNV) * TAD)) / (# of user active analog inputs in use on specific target ADC module)).
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
12 12-bit resolution
9 8-bit resolution
TCNV
12 12-bit resolution
8 8-bit resolution
Notes:
1. When SAMPCTRL.OFFCOMP = 0:
– TSAMP = (((RSAMPLE + RSOURCE) * CSAMPLE * ((#Bits Resolution+2) * ln(2)))) / TAD)+1 rounded down to nearest whole integer
– User SAMPCTRL.SAMPLEN = (TSAMP - 1)
2. When SAMPCTRL.OFFCOMP = 1:
– TSAMP = 4 (Forced by HDW)
– User SAMPCTRL.SAMPLEN = (n/a, Ignored by HDW)
3. ADC Throughput Rate FTP = ((1 / ((TSAMP + TCNV) * TAD)) / (# of user active analog inputs in use on specific target ADC module)).
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Device Supply
Reference Inputs
VREF = VDDANA
2.7 VDDANA V
(REFCTRL.REFSEL = 0x3)
VREF ≤ VDDANA
VREF = INTREF
SDADC_3 VREF(2) ADC Reference Voltage — (REFCTRL.REFSEL = 0x0)
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
VREF<VDDANA-0.3V, Gaincorr
SDADC_7 Full-Scale Analog Input GNDANA — +VREF V
= 0x1
Signal Range (Single-
SDADC_8 Ended (1)) GNDANA — +0.7 * VREF V
VREF> = VDDANA-0.3V,
Gaincorr = 0x1
AFS
VREF<VDDANA-0.3V, Gaincorr
SDADC_9 Full-Scale Analog -VREF — +VREF V
= 0x1
Input Signal Range
(Differential) VREF> = VDDANA-0.3V,
SDADC_10 -0.7*VREF — +0.7 * VREF V
Gaincorr = 0x1
Notes:
1. This mode corresponds to a differential mode where the selected AINx pin is externally grounded.
2. SDADC functional device operation with either internal or external VREF < 2.4V is functional, but not characterized. SDADC will function, but with degraded
accuracy of approximately ~((0.06 * 2n) /VREF). Where "n" = #bits. SDADC accuracy is limited by internal VREF accuracy + drift, MCU generated noise plus
users application noise or accuracy on VDDANA, GNDANA.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
DSDADC_51 SNR (1,2,3,6) Signal to Noise ratio 85.0 — — FTP(max), REFCTRL.REFSEL = 0x3 = VDDANA
dB
VREF = VDDANA = 5.0V
DSDADC_53 DR (1,2,3,6) Dynamic Range 78.0 — —
Notes:
1. Characterized with an analog input sine wave at 500Hz with OSR = 256.
2. Sinewave peak amplitude = -3dB SDADC_ Full Scale amplitude input with 16bit resolution.
3. Spec values collected under the following additional conditions:
– All registers at reset default value otherwise not mentioned
4. Value taken over 7 harmonics.
5. Differential input mode, OSR = 256, SDADC Clock Period=166.7 ns (6 MHz), Chopper OFF (ANACTRL.ONCHOP = 0).
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Note:
1. SDADC Throughput Rate FTP is divided by # of user active analog inputs in use on specific target SDADC module.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
register bits:
SDADC_63 SKPCNT skip count (1) 2 — 15 TAD
CTRLB.SKPCNT[3:0]
Notes:
1. Number of skip samples before retrieve the first valid sample. The first valid sample starts from the (SKPCNT+1)th sample onward.
2. External anti-alias filter must be placed in front of each SDADC input to ensure high-frequency signals to not alias into measurement bandwidth. Use
capacitors of X5R type for DC measurement, or capacitors of COG or NPO type for AC measurement.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
COMPCTRLx.HYST = 0x0
VIOFF_00 -26 — 26 mV
COMPCTRLx.SPEED = 0x0
COMPCTRLx.HYST = 0x1
VIOFF_01 -32 — 32 mV
COMPCTRLx.SPEED = 0x0
CMP_1 Input Offset Voltage
COMPCTRLx.HYST = 0x0
VIOFF_02 -14 — 14 mV
COMPCTRLx.SPEED = 0x3
COMPCTRLx.HYST = 0x1
VIOFF_03 -16 — 16 mV
COMPCTRLx.SPEED = 0x3
CMP_4 VIN Input Voltage Range GNDANA — VDDANA V With respect to GND and VDDANA
COMPCTRLx.HYST = 0x1
VHYST_00 Input Hysteresis Voltage 25 — 161 mV
COMPCTRLx.SPEED = 0x0
CMP_5
COMPCTRLx.HYST = 0x1
VHYST_01 Input Hysteresis Voltage 50 — 141 mV
COMPCTRLx.SPEED = 0x3
COMPCTRL.SPEED = 0x0
COMPCTRLx.SPEED = 0x3
Comparator Internal Band Gap (3) (3) (3) See ACIREF Spec Parameters:
CMP_21 ACIREF V
Voltage Reference VR_9-VR_13
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Notes:
1. Values in TYPICAL column are taken at 25°C.
2. Comparator Ref voltage cannot exceed (VIN(max) - VIOFF(max) - (CMP_5(max) + 50mV)) ≥ CMP VREF ≥ (VIN(min) + VIOFF(min) + (CMP_5(max) +
50mV)).
3. See Internal Voltage Ref Spec Parameters: VR_9-VR_13.
4. TRESP is measured from Vin transition to ACOUT (AC direct output) toggle. It takes into account only analog propagation delay.
SCK MSP_13
CPOL=0
SCK
CPOL=1
MSP_15 MSP_17 MSP_3
MISO
(HOST Data In) MSB ●●●● ●●●● LSB
MOSI
(Host Data Out) MSB ●●●● ●●●● LSB
MSP_11
SCK MSP_13
CPOL=0
SCK
CPOL=1
MSP_3
MSP_15 MSP_17
MISO
(Host Data In)
MSB ●●●● ●●●● LSB
MOSI
(Host Data Out) MSB ●●●● ●●●● LSB
MSP_11
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
MSP_7 TSCF SCK & MOSI Output Fall Time — — DI_27 ns See parameter DI_27 I/O spec
MSP_9 TSCR SCK & MOSI Output Rise Time — — DI_25 ns See parameter DI_25 I/O spec
Note:
1. Assumes VDDIO = 2.7V and 30 pF external load on all SPIx pins unless otherwise noted.
SCK SSP_13
CPOL=0
SCK
CPOL=1
SSP_15 SSP_17 SSP_3
MISO
(Host Data In) MSB ●●●● ●●●● LSB
MOSI
(Host Data Out) MSB ●●●● ●●●● LSB
SSP_11
SSP_21
SSP_19
__
SS
SCK SSP_13
CPOL=0
SCK
CPOL=1
SSP_3
SSP_15 SSP_17
MISO
MSB ●●●● ●●●● LSB
(Host Data In)
MOSI
(Host Data Out)
MSB ●●●● ●●●● LSB
SSP_21
SSP_11
SSP_19
__
SS
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
SSP_7 TSCF SCK & MISO Output Fall Time — — DI_27 ns See parameter DI_27 I/O spec
SSP_9 TSCR SCK & MISO Output Rise Time — — DI_25 ns See parameter DI_25 I/O spec
SSP_17 TSIH MOSI Hold Time of Data Input to SCK 8.49 — — ns VDDIO = 2.7V, CLOAD= 30 pF (MIN)
Note:
1. Assumes VDDIO = 2.7V and 30 pF external load on all SPIx pins unless otherwise noted.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Note:
1. These parameters are characterized, but not tested in manufacturing.
SCLx
I2Cx_15
I2Cx_19
I2Cx_17
I2Cx_13
SDAx
SCLx
I2Cx_13 I2Cx_11
I2Cx_17
I2Cx_15 I2Cx_9
SDAx
In
I2Cx_23
I2Cx_21
I2Cx_21
SDAx
Out
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS_
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
I2CM_1 TL0:SCL Host Clock Low Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 0.5 — µs
CLOAD = 550 pF
I2CM_3 THI:SCL Host Clock High Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 0.5 — µs
CLOAD= 550 pF
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS_
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
I2CM_5 TF:SCL SDAx and SCLx Fall Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode — 250 ns
CLOAD = 550 pF
I2CM_7 TR:SCL SDAx and SCLx Rise Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode — 120 ns
CLOAD = 550 pF
I2CM_9 TSU:DAT Data Input Setup Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 104 — ns
CLOAD = 550 pF
I2CM_11 THD:DAT Data Input Hold Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 9 — ns
CLOAD = 550 pF
I2CM_13 TSU:STA Start Condition Setup Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 507 — ns
CLOAD = 550 pF
I2CM_15 THD:STA Start Condition Hold Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 491 — ns
CLOAD = 550 pF
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS_
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
I2CM_17 TSU:ST0 Stop Condition Setup Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 509 — ns
CLOAD = 550 pF
I2CM_19 THD:ST0 Stop Condition Hold Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 21 — ns
CLOAD = 550 pF
I2CM_21 TAA:SCL 0utput Valid from Clock VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode — 170 ns
CLOAD = 550 pF
I2CM_23 TBF:SDA Bus Free Time (1) VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 500 — ns
CLOAD = 550 pF
Note:
1. The amount of time the bus must be free before a new transmission can start (STOP condition to START condition).
SCLx
I2Cx_15
I2Cx_19
I2Cx_17
I2Cx_13
SDAx
SCLx
I2Cx_13 I2Cx_11
I2Cx_17
I2Cx_15 I2Cx_9
SDAx
In
I2Cx_23
I2Cx_21
I2Cx_21
SDAx
Out
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTI2CS_
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
I2CS_1 TL0:SCL Client Clock Low Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 500 — ns
CLOAD = 550 pF
I2CS_3 THI:SCL Client Clock High Time VDDIO = 5.0V, IPULL-UP = 20ma,
1 MHz mode 500 — ns
CLOAD=550pF
I2CS_5 TF:SCL SDAx and SCLx Fall Time VDDIO = 5.0V, IPULL-UP = 20ma,
1 MHz mode — 250 ns
CLOAD=550pF
I2CS_7 TR:SCL SDAx and SCLx Rise Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode — 120 ns
CLOAD = 550 pF
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTI2CS_
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
I2CS_9 TSU:DAT Data Input Setup Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 51 — ns
CLOAD = 550 pF
I2CS_11 THD:DAT Data Input Hold Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 71 — ns
CLOAD = 550 pF
I2CS_13 TSU:STA Start Condition Setup Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 108 — ns
CLOAD = 550 pF
I2CS_15 THD:STA Start Condition Hold Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 70 — ns
CLOAD = 550 pF
I2CS_17 TSU:ST0 Stop Condition Setup Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 108 — ns
CLOAD = 550 pF
I2CS_19 THD:ST0 Stop Condition Hold Time VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 70 — ns
CLOAD = 550 pF
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTI2CS_
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
I2CS_21 TAA:SCL Output Valid from Clock VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode — 182 ns
CLOAD = 550 pF
I2CS_23 TBF:SDA Bus Free Time (1) VDDIO = 5.0V, IPULL-UP = 20 ma,
1 MHz mode 500 — ns
CLOAD = 550 pF
Note:
1. The amount of time the bus must be free before a new transmission can start (STOP condition to START condition).
TCx WO[y]
TC1 TC3
TC5
TCx WO[y]
TC7 TC9
TC11
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
TC_1 TCINLOW Capture TCx Input Low Time 2/fGLK_TCx — — ns VDDIO = 2.7V and meet TC_5 spec
TC_3 TCINHIGH Capture TCx Input High Time 2/fGLK_TCx — — ns VDDIO = 2.7V and meet TC_5 spec
TC_7 TCOUTLOW Compare TCx Output Low Time 33 — — ns VDDIO = 2.7V and meet TC_11 spec
TC_9 TCOUTHIGH Compare TCx Output High Time 33 — — ns VDDIO = 2.7V and meet TC_11 spec
TCCx WO[y]
TC1 TC3
TC5
TCCx WO[y]
TC7 TC9
TC11
TCC17
FAULTx In
TCC15
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
TCC_1 TCCINLOW Capture TCCx Input Low Time 2/fGLK_TCCx — — ns VDDIO = 2.7V and meet TCC_5 spec
TCC_3 TCCINHIGH Capture TCCx Input High Time 2/fGLK_TCCx — — ns VDDIO = 2.7V and meet TCC_5 spec
TCC_7 TCCOUTLOW Compare TCCx Output Low Time 33 — — ns VDDIO = 2.7V and meet TCC_11 spec
TCC_9 TCCOUTHIGH Compare TCCx Output High Time 33 — — ns VDDIO = 2.7V and meet TCC_11 spec
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
TCC_19 TCCINLOW Capture TCC2 Input Low Time 2/fGLK_TCC2 — — ns VDDIO = 2.7V and meet TCC_23 spec
TCC_21 TCCINHIGH Capture TCC2 Input High Time 2/fGLK_TCC2 — — ns VDDIO = 2.7V and meet TCC_23 spec
TCC_25 TCCOUTLOW Compare TCC2 Output Low Time 33 — — ns VDDIO = 2.7V and meet TCC_29 spec
TCC_27 TCCOUTHIGH Compare TCC2 Output High Time 33 — — ns VDDIO = 2.7V and meet TCC_29 spec
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
VDDIO = 2.7V
FM_7 fGCLK_FREQM_REF FREQM Reference — — FCLK_17 MHz See parameter FCLK_17 in
VDDIO = 2.7V
FM_9 fGCLK_FREQM_MSR FREQM Measure — — FCLK_15 MHz See parameter FCLK_15 in
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise
AC CHARACTERISTICS
stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
0 Wait States — — 23
2 Wait States — — 48
NVM_5 FREAD Flash Read
0 Wait States — — 22
2 Wait States — — 48
Note:
1. Maximum FLASH operating frequencies are given in the table above, but are limited by the Embedded Flash access time when the processor is fetching code
out of it. Theses tables provide the device maximum operating frequency defined by the field RWS of the NVMCTRL CTRLA register. This field defines the
number of Wait states required to access the Embedded Flash Memory.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial
Note:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions, above those
indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
Characteristic VDDIOx, VDDANA Range Temp. Range (in °C) Max CPU Frequency Comments
DC5 2.7 to 5.5V -40°C to +125°C 48 MHz Extended Temp
Note:
1. See Absolute Maximum Ratings.
Param. No. Symbol Characteristics Clock/Freq Typ (1) Max. Units Conditions
VDDANA = VDDIO = 5V
APWR_1 99.6 131.2 µa/MHz XOSC32K @ 32.768 kHz as
reference of FDPLL (2)
FDPLL 48MHz
VDDANA = VDDIO = 3.3V
APWR_3 97.3 127.9 µa/MHz XOSC32K @ 32.768 kHz as
MCU IDD in Active mode w/LDO
IDD_ACTIVE (2,3) reference of FDPLL (2)
mode selected
VDDANA = VDDIO = 5V
APWR_5 97.8 127 µa/MHz
XOSC32K Off (2)
RC 48MHz
VDDANA = VDDIO = 3.3V
APWR_7 95.5 124.1 µa/MHz
XOSC32K Off (2)
Notes:
1. Typical values at 25°C only.
2. Conditions:
– No peripheral modules are operating (i.e. all peripherals inactive)
– All clock generation sources disabled unless otherwise specified (i.e., XOSC32 = Off)
– GCLK clock generators 1 to 8 stopped (GENCTRL[8:1].GENEN = 0)
– AHB/APB clocks not needed are masked: AHBMASK = 0x70, APB (A/B/C/D)MASK = 0x0
– CPU and AHB clocks undivided
– I/Os are inactive input mode with input trigger disabled
– WDT, RTC, CFD Clock Fail Detect disabled
– RESET = VDDIOx
– MCU is running on Flash with xx Wait States
– NVMCTRL cache enabled
– BODVDD disabled
Param. No. Symbol Characteristics Clock/Freq Typ (1) Max. Units Conditions
VDDANA = VDDIO = 5V
IPWR_1 19.1 43.4 µa/MHz XOSC32K @ 32.768 kHz as reference
of FDPLL(2)
FDPLL 48MHz
VDDANA = VDDIO = 3.3V
IPWR_3 19 43.2 µa/Mhz XOSC32K @ 32.768 kHz as reference
CPU IDD in IDLE mode w/LDO mode
IDD_IDLE (2) of FDPLL(2)
selected
VDDANA = VDDIO = 5V
IPWR_5 17.3 40 µa/Mhz
XOSC32K Off (2)
RC 48MHz
VDDANA = VDDIO = 3.3V
IPWR_7 17.2 39.8 µa/Mhz
XOSC32K Off (2)
Notes:
1. Typical values at 25°C only.
2. Conditions:
– No peripheral modules are operating (i.e., all peripherals inactive)
– All clock generation sources disabled unless otherwise specified. (i.e., XOSC32 = Off)
– GCLK clock generators 1 to 8 stopped (GENCTRL[8:1].GENEN = 0)
– AHB/APB clocks not needed are masked: AHBMASK=0x70, APB(A/B/C/D)MASK = 0x0
– MCU and AHB clocks undivided
– I/Os are inactive input mode with input trigger disabled
– WDT, RTC, CFD Clock Fail Detect disabled
– RESET = VDDIOx
– NVMCTRL cache enabled
– BODVDD disabled
Param. No. Symbol Characteristics VDDIOx Typ (1) Max. Units Conditions
Notes:
1. Typical values at 25°C only.
2. Conditions :
– System in standby mode
– No SleepWalking (except RTC when indicated)
– Peripheral modules are inactive (except RTC when indicated)
– All clocks stopped (CPU, AHB, APB, Main, GCLK, except RTC running at 1kHz from XOSC32K when indicated)
– All clock generation sources disabled except XOSC32K running with external 32 kHz crystal when indicated
– All I/O pins configured as input pins pulled down or tied to GND
– WDT, CFD Clock Fail Detect disabled
– BODVDD disabled
– RESET = VDDIO
PAI_65 ITC4 TC Active current (1 of 2) Normal Frequency mode, Counter in 16 bits mode
PAI_100 ITC0/1/2/3 TC Active current (2 of 2) Normal Frequency mode, Counter in 16bits mode
PAI_120 IDAC DAC Active current VREF = VDDANA, DAC DATA = 0x3FF (2)
...........continued
Standard Operating Conditions: VDDIO = VDDANA _2.7V to 5.5V (unless
DC CHARACTERISTICS otherwise stated)
Operating temperature: -40°C ≤ TA ≤ +125°C for Extended Temp
Notes:
1. Conditions:
– Only mentioned peripheral modules is operating (i.e., rest of the peripherals are inactive)
– MCLK all APB clock masked except MCLK and NVMCTRL and selected peripheral
– MCLK.AHBMASK = 0x00C00FFF
– All clock generation sources disabled unless otherwise specified. (i.e., XOSC32 = Off)
– All clock sources disabled except XOSC32K running with external 32kHz crystal and FDPLL96M using XOSC32K as reference and running at 96MHz
divided by 2 on GCLK0
– GCLK clock generators 1 to 8 stopped (GENCTRL[8:1].GENEN = 0)
– AHB/APB clocks not needed are masked: AHBMASK = 0x70, APB(A/B/C/D)MASK = 0x0
– CPU and AHB clocks undivided
– All I/O pins configured as input pins pulled down or tied to GND
– WDT, RTCC, CFD Clock Fail Detect disabled
– RESET = VDDIOx
– CPU is running on Flash with 3 Wait States
– NVMCTRL cache enabled
– BODVDD disabled
– Measure is differential between active and inactive module in those conditions
2. Conditions:
– Same Conditions than Note 1
– GCLK1 running on FDPLL96M at 96 MHz divided by 96
– Measure is differential between active and inactive module in those conditions
3. Conditions:
– Same Conditions than Note 1
– GCLK1 running on FDPLL96M at 96 MHz not divided
– Measure is differential between active and inactive module in those conditions
4. Conditions:
– Same Conditions than Note 1
– GCLK1 running on FDPLL96M at 96 MHz divided by 6
– Measure is differential between active and inactive module in those conditions
Standard Operating Conditions: VDD & VDDIO 2.7V to 5.5V (unless otherwise stated)
AC - DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
...........continued
Standard Operating Conditions: VDD & VDDIO 2.7V to 5.5V (unless otherwise stated)
AC - DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
Notes:
1. Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the “absolute instantaneous” sum of the input
injection currents from all pins do not exceed the specified ∑IICT limit. To limit the injection current the user must insert a resistor in series RSERIES (i.e., RS),
between input source voltage and device pin. The resistor value is calculated according to:
– For negative Input voltages less than (GND-0.3): RS ≥ absolute value of | ((VIL source - (GND - 0.3)) / IICL) |
– For positive input voltages greater than (VDDIO +0.3): RS ≥ ((VIH source - (VDDIO +0.3))/ IICH)
– For Vpin voltages > VDDIO +0.3 and <GND-0.3 then RS = the larger of the values calculated above
2. The following pins are High-Sink pins and have different properties than standard pins: PA10, PA11, PB10, PB11.
3. The following pins are TWIHS pins and have the same properties as standard pins when not used as SERCOM I2C pins: PA08, PA09, PA12, PA13, PA16,
PA17, PA22, PA23. When used in SERCOM I2C mode, refer to I2CM_5/7 and I2CS_5/7 parameters.
VR_25 TDRIFT Internal Voltage Reference Temperature Drift -0.007 — 0.011 %/°C Over [+25, +125]°C
VR_27 VDRIFT Internal Voltage Reference Voltage Drift -0.124 — 0.264 %/V Over full operating voltage range
TA = 25°C,
OSC32K_3a -1.5 — 1.5 %
VDDANA = 5.0V
TA = 25°C,
OSC32K_3b OSC32K_ACC Accuracy -12 — 12 %
2.7V ≤ VDDANA ≤ 5.5V
-40°C ≤ TA ≤ +125°C,
OSC32K_3c -26 — 16 %
2.7V ≤ VDDANA ≤ 5.5V
Note:
1. 25°C, VDD = VDDIO = 5.0V
-40°C ≤ TA ≤ +125°C
ULPRC32K_3 ULPRC32K_ACC Accuracy -25 — 25 %
VDD and VDDIO 2.7V to 5.5V
Standard Operating Conditions: VDD & VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
Notes:
1. REFCLK for FDPLL96M is XOSC or XOSC32K.
2. The provided jitter performance will be the best achieved on the device. Digital activity can increase jitter but is highly dependent on the application use model.
Standard Operating Conditions: VDD & VDDIO 2.7V to 5,5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
CTRLB.REFSEL = 0x1
-1.2 — 1.2 LSB VREF = VDDANA = 5.0V w/
CLOAD & RLOAD
SDAC_19 INL(6) Integral Non Linearity
CTRLB.REFSEL = 0x2
-1.2 — 1.2 LSB VDDANA = 5.0V VREF = VREFA
pin = 3.0V w/ CLOAD & RLOAD
CTRLB.REFSEL = 0x1
-1.5 — 1.5 LSB VREF = VDDANA = 5.0V w/
CLOAD & RLOAD
SDAC_21 DNL(6) Differential Non Linearity
CTRLB.REFSEL = 0x2
-1.5 — 1.5 LSB VDDANA = 5.0V VREF = VREFA
pin = 3.0V w/ CLOAD & RLOAD
CTRLB.REFSEL = 0x1
-6.0 — 6.0 LSB DAC reference = VDDANA =
5.0V w/ CLOAD & RLOAD
...........continued
Standard Operating Conditions: VDD & VDDIO 2.7V to 5,5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
CTRLB.REFSEL = 0x1
-4.1 — 4.1 LSB DAC reference = VDDANA =
5.0V w/ CLOAD & RLOAD
Notes:
1. DAC Internal Bandgap Reference voltage 4.096V when used.
2. DAC reference voltages < 2.4V is not practical and peripheral performance is not guaranteed.
3. DAC functional device operation with either internal or external VREF <2.4V is guaranteed, but not characterized. DAC will function, but with degraded
performance. DAC accuracy is limited by users application noise/accuracy on VDDANA, GNDANA and VREF accuracy/drift.
4. Value taken over 7 harmonics.
5. 10-bit mode.
6. Over VOUT range defined by DAC_7 parameter.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
Notes:
1. Spec values collected under the following additional conditions:
– 12 bit resolution mode
– All registers at reset default value otherwise not mentioned
2. SAMPCTRL.OFFCOMP = 0, SAMPCTRL.SAMPLEN = [5:0] = 3.
3. SAMPCTRL.OFFCOMP = 0 and REFCTRL.REFCOMP = 0 , SAMPCTRL.SAMPLEN = [5:0] = 3.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
...........continued
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
Notes:
1. Characterized with an analog input sine wave = (FTP(max)/100). For example, FTP(max) = 1Msps/100 = 10 KHz sine wave.
2. Sine wave peak amplitude = 96% ADC_ Full Scale amplitude input with 12bit resolution.
3. Spec values collected under the following additional conditions:
– 12 bit resolution mode
– All registers at reset default value otherwise not mentioned
4. ADC functional device operation with either internal or external VREF <2.4v is functional, but not characterized. ADC will function, but with degraded accuracy
of approximately ~((0.06 * 2n) /VREF), where "n" = #bits. ADC accuracy is limited by internal VREF accuracy + drift, MCU generated noise plus users
application noise/accuracy on VDDANA, GNDANA.
5. Value taken over 7 harmonics.
6. SAMPCTRL.OFFCOMP = 1.
7. SAMPCTRL.OFFCOMP = 1 and REFCTRL.REFCOMP = 1.
Standard Operating Conditions: VDD and VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
Notes:
1. Spec values collected under the following additional conditions:
– All registers at reset default value otherwise not mentioned
2. Differential input mode, OSR = 256, SDADC Clock Period = 166.7ns (6 MHz), Chopper OFF (ANACTRL.ONCHOP = 0), REFRANGE[1:0] = 0x3.
Standard Operating Conditions: VDD & VDDIO 2.7V to 5,5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
COMPCTRLx.HYST = 0x0
VIOFF_00 -33 — 33 mV
COMPCTRLx.SPEED = 0x0
COMPCTRLx.HYST = 0x1
VIOFF_01 -39 — 39 mV
COMPCTRLx.SPEED = 0x0
CMP_1 Input Offset Voltage
COMPCTRLx.HYST = 0x0
VIOFF_02 -17 — 17 mV
COMPCTRLx.SPEED = 0x3
COMPCTRLx.HYST = 0x1
VIOFF_03 -19 — 19 mV
COMPCTRLx.SPEED = 0x3
COMPCTRLx.HYST = 0x1
VHYST_00 Input Hysteresis Voltage 25 — 179 mV
COMPCTRLx.SPEED = 0x0
CMP_5
COMPCTRLx.HYST = 0x1
VHYST_01 Input Hysteresis Voltage 43 — 145 mV
COMPCTRLx.SPEED = 0x3
COMPCTRL.SPEED = 0x0
COMPCTRLx.SPEED = 0x3
...........continued
Standard Operating Conditions: VDD & VDDIO 2.7V to 5,5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
Notes:
1. Values in TYPICAL column are taken at 25°C .
2. Comparator Ref voltage cannot exceed: (VIN(max) - VIOFF(max) - CMP_5(max) - 50mV) ≥ CMP VREF ≥ (VIN(min) + VIOFF(min) + CMP_5(max) + 50mV).
3. See Internal Voltage Ref Spec Parameters: VR_9-VR_13.
4. TRESP is measured from Vin transition to ACOUT (AC direct output) toggle. It takes into account only analog propagation delay.
Standard Operating Conditions: VDD & VDDIO 2.7V to 5.5V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +125°C for Extended Temp
NVM_1 FRETEN Flash Data Retention 15 — — Yrs Under all conditions less
Cell Endurance (Flash Erase and than Absolute Maximum
NVM_3 EP 25000 — — Cycles Ratings specifications
Write Operation)
0 Wait States — — 21
2 Wait States — — 48
NVM_5 FREAD Flash Read
0 Wait States — — 20
2 Wait States — — 48
Note:
1. Maximum Flash operating frequencies are given in the table above, but are limited by the Embedded Flash access time when the processor is fetching code
out of it. Theses tables provide the device maximum operating frequency defined by the field RWS of the NVM_CTRL CTRLA register. This field defines the
number of Wait states required to access the Embedded Flash Memory.
XXXXXX
XXXXXXX
YYWWNNN
Where:
• "Y" or "YY": Manufacturing Year (last OR two last digit(s))
• "WW": Manufacturing Week
• "NNN": Internal Code
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1 D
2 2
E1
2
A B
E
E1
A A
NOTE 1 E
2
N
N/4 TIPS
0.20 C A-B D
1 2 3
e 0.20 C A-B D 4X
2
TOP VIEW
C
A A2
SEATING
PLANE 48X
48X b 0.08 C
A1
0.08 C A-B D
SIDE VIEW
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ϴ2
ϴ1
H R2
R1
c
ϴ2 ϴ
L
(L1)
SECTION A-A
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 48
Pitch e 0.50 BSC
Overall Height A - - 1.20
Standoff A1 0.05 - 0.15
Molded Package Thickness A2 0.95 1.00 1.05
Overall Length D 9.00 BSC
Molded Package Length D1 7.00 BSC
Overall Width E 9.00 BSC
Molded Package Width E1 7.00 BSC
Terminal Width b 0.17 0.22 0.27
Terminal Thickness c 0.09 - 0.16
Terminal Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Lead Bend Radius R1 0.08 - -
Lead Bend Radius R2 0.08 - 0.20
Foot Angle ϴ 0° 3.5° 7°
Lead Angle ϴ1 0° - -
Mold Draft Angle ϴ2 11° 12° 13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
C2 G
SILK SCREEN
48
Y1
1 2
X1
E
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.50 BSC
Contact Pad Spacing C1 8.40
Contact Pad Spacing C2 8.40
Contact Pad Width (X48) X1 0.30
Contact Pad Length (X48) Y1 1.50
Distance Between Pads G 0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Table 45-1. Device
© 2018 and Package
Microchip Technology Inc. Maximum Weight
140 mg
48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN]
With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
48X
0.08 C
D A
D 0.10 C
4 B
N
E 1
4
2
NOTE 1
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
0.10 C
TOP VIEW A1
0.10 C A B
(A3)
D2
A
SEATING
C
0.10 C A B PLANE
DETAIL A
SIDE VIEW
A A
E2 A4
e
2
2 D3
1
SECTION A-A
N (K)
L 48X b
e 0.10 C A B
0.05 C
BOTTOM VIEW
48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN]
With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 48
Pitch e 0.50 BSC
Overall Height A 0,80 0.85 0.90
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.203 REF
Overall Length D 7.00 BSC
Exposed Pad Length D2 5.05 5.15 5.25
Overall Width E 7.00 BSC
Exposed Pad Width E2 5.05 5.15 5.25
Terminal Width b 0.20 0.25 0.30
Terminal Length L 0.35 0.40 0.45
Terminal-to-Exposed-Pad K 0.53 REF
Wettable Flank Step Length D3 - - 0.085
Wettable Flank Step Height A4 0.10 - 0.19
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
48-Lead Very Thin Plastic Quad Flat, No Lead Package (U5B) - 7x7 mm Body [VQFN]
With 5.15 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZLH
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
48
1
ØV
2
G2
C2 Y2
EV
G1
Y1
X1
SILK SCREEN E
Note: The exposed die attach pad is not connected electrically inside the device.
© 2018 Microchip Technology Inc.
140 mg
D1
D
32X TIPS
0.20 C A-B D
A B
E1 E
A A
NOTE 1 1 2 4X
0.20 H A-B D
32X b
0.20 C A-B D
e
TOP VIEW
0.10 C
C
SEATING A A2 32X
PLANE 0.10 C
A1
SIDE VIEW
L
(L1)
SECTION A-A
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 32
Lead Pitch e 0.80 BSC
Overall Height A - - 1.20
Standoff A1 0.05 - 0.15
Molded Package Thickness A2 0.95 1.00 1.05
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle 0° - 7°
Overall Width E 9.00 BSC
Overall Length D 9.00 BSC
Molded Package Width E1 7.00 BSC
Molded Package Length D1 7.00 BSC
Lead Width b 0.30 0.37 0.45
Mold Draft Angle Top 11° - 13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
C1
C2
SILK SCREEN X
E
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.80 BSC
Contact Pad Spacing C1 8.40
Contact Pad Spacing C2 8.40
Contact Pad Width (Xnn) X 0.55
Contact Pad Length (Xnn) Y 1.55
Contact Pad to Contact Pad (Xnn) G 0.25
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN]
With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBS
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D A B
NOTE 1 N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
0.10 C TOP VIEW
0.10 C A1
C
A
SEATING
PLANE 32X
(A3) 0.08 C
SIDE VIEW
0.10 C A B
D2
A4
DETAIL A
D3 PARTIALLY
PLATED
A A E2 SECTION A–A
e K
2
2
0.10 C A B
1
NOTE 1 N
L 32X b
e 0.10 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-21391 RevE Sheet 1 of 2
32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN]
With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBS
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 32
Pitch e 0.50 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.035 0.05
Terminal Thickness A3 0.203 REF
Overall Length D 5.00 BSC
Exposed Pad Length D2 3.50 3.60 3.70
Overall Width E 5.00 BSC
Exposed Pad Width E2 3.50 3.60 3.70
Terminal Width b 0.20 0.25 0.30
Terminal Length L 0.35 0.40 0.45
Terminal-to-Exposed-Pad K 0.20 - -
Wettable Flank Step Cut Width D3 - - 0.085
Wettable Flank Step Cut Depth A4 0.10 - 0.19
Dimensions D3 and A4 above apply to all new products released after
November 1, and all products shipped after January 1, 2019, and supersede
dimensions D3 and A4 below.
No physical changes are being made to any package; this update is to align
cosmetic and tolerance variations from existing suppliers.
Wettable Flank Step Length D3 0.035 0.06 0.085
Wettable Flank Step Height A4 0.10 - 0.19
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
32-Lead Very Thin Plastic Quad Flat, No Lead Package (RTB) - 5x5 mm Body [VQFN]
With 3.6x3.6 mm Exposed Pad and Stepped Wettable Flanks; Atmel Legacy ZBS
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
32
G1
1
2 ØV
CH
C2 Y2
G2
EV
X1
X1
SILK SCREEN E
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
46.1 Introduction
This chapter describes a common checklist which should be used when starting and reviewing the schematics for a
PIC32CM MC design. This chapter illustrates the recommended power supply connections, how to connect external
analog references, programmer, debugger, oscillator and crystal.
Close to device
2.7V - 5.5V
(for every pin)
VDDANA
10μF 100nF
VDDIO
100nF
VDDIN
100nF
VDDCORE
10μF
1μF 100nF
GND
GNDANA
IO Supply VDDANA
(2.7V - 5.5V)
10μF 100nF
VDDIO
100nF
VDDIN
100nF
VDDCORE
10μF 10μF
1μF 100nF
GND
GNDANA
GND Ground
GNDANA Ground for the analog power domain
3. An inductor should be added between the external power and the VDD for power filtering.
4. A ferrite bead has better filtering performance compared to standard inductor at high frequencies. A ferrite bead
can be added between the main power supply (VDD) and VDDANA to prevent digital noise from entering the analog
power domain. The bead should provide enough impedance (e.g. 50Ω at 20MHz and 220Ω at 100MHz) to separate
the digital and analog power domains. Make sure to select a ferrite bead designed for filtering applications with a low
DC resistance to avoid a large voltage drop across the ferrite bead.
Close to device
(for every pin)
VREFA
EXTERNAL
4.7μF 100nF
REFERENCE 1 GND
VREFB
EXTERNAL
4.7μF 100nF
REFERENCE 2 GND
Close to device
(for every pin)
VREFA
EXTERNAL
4.7μF 100nF
REFERENCE GND
VREFB
GND
Close to device
(for every pin)
VREFB
EXTERNAL
4.7μF 100nF
REFERENCE GND
GND Ground
Notes:
1. Refer to Power Supply Electrical Specifications from the Electrical Characteristics chapter.
2. Refer to the Electrical Characteristics chapter for the intended peripheral to be used with VREFx to determine
suggested operational conditions. These peripherals include ADC, DAC, AC, and SDADC.
3. Decoupling capacitor must be placed close to the device for each supply pin pair in the signal group.
VDD
(1)
100kΩ
39Ω RESET
4.7nF
GND
The following reset circuit is intended to improve EFT immunity but does not filter low frequency glitches which makes
it unsuitable as an example for applications requiring debouncing on a reset button.
Figure 46-6. External Reset Circuit Schematic (EFT Immunity Enhancement) (2)
VDD
2.2k Ω 100pF
RESET
330Ω
GND
Notes:
1. The device features an internal pull-up resistor on the RESET pin; therefore, an external pull-up is optional.
2. These values are only given as a typical example. Reference the Power Supply Electrical Characteristics to
determine proper values given system parameters to meet reset timing requirements (TRST).
External
Clock
XIN
XOUT/GPIO
NC/GPIO
C1 XIN
XOUT
C2
The crystal should be located as close to the device as possible. Long signal lines may cause too high of a load to
operate the crystal, and cause crosstalk to other parts of the system.
Note: Crystal selection must be done using both the crystal data sheet and the crystal oscillator parameters given in
the XOSC Electrical Specifications from Electrical Characteristics chapter.
Table 46-4. Crystal Oscillator Checklist
Notes:
1. The capacitors should be placed close to the device.
2. Crystal Load Capacitors Calculation is given in the XOSC Electrical Specifications.
External
Clock
XIN32
XOUT32
NC/ GPIO
C1 XIN32
C2
XOUT32
Note: 32.768 kHz crystal selection must be done using both the crystal data sheet and the crystal oscillator
parameters given in the “XOSC32K Electrical Specifications” from the “Electrical Characteristics” chapter.
Table 46-6. 32.768 kHz Crystal Oscillator Checklist
Notes:
1. The capacitors must be placed close to the device.
2. Crystal Load Capacitors Calculation is given in the XOSC32K Electrical Characteristics.
1kΩ
SWCLK
VDD
Cortex Debug Connector
(10-pin)
VTref SWDIO
1
GND SWDCLK RESET
GND
NC
SWCLK
NC NC
RESET
NC
SWDIO
GND
VDD
20-pin IDC JTAG Connector
VCC NC
1
GND RESET
NC
GND
NC
SWDIO GND SWCLK
SWDCLK GND
NC GND SWDIO
NC GND*
RESET GND* GND
NC GND*
NC GND*
47. Appendix
PCB HDW
SW Non-
FEATURE SAMC21N/J/G/E PIC32CMxxxxMC00048/32 Non- Comments
Compatible
Compatible
Max Frequency
48 48 -- -- --
(MHz)
--
32.768 kHz crystal oscillator
(XOSC32K) 32.768 kHz crystal oscillator (XOSC32K) --
0.4-32 MHz crystal oscillator (XOSC) 0.4-32 MHz crystal oscillator (XOSC)
--
32.768 kHz internal oscillator 32.768 kHz internal oscillator (OSC32K)
(OSC32K) --
32.768 kHz ultra low-power internal oscillator
Oscillators/Clock
32.768 kHz ultra low-power internal (OSCULP32K) -- -- --
Sources
oscillator (OSCULP32K)
48 MHz high-accuracy internal oscillator --
48 MHz high-accuracy internal (OSC48M)
oscillator (OSC48M) --
96 MHz Fractional Digital Phased Locked Loop
96 MHz Fractional Digital Phased (FDPLL96M) --
Locked Loop (FDPLL96M)
--
TC Instances 8/5 5 -- -- --
ALOCK function
TCC Instances 3 3 -- X not available for
PIC32CM MC00
Waveform Output
(TCC0/TCC1/ 8/6/4 8/6/4 -- -- --
TCC2)
EVSYS 12 12 -- -- --
DMA Channels 12 12 -- -- --
CAN module
CAN Interface 2 0 X X not available on
PIC32CM MC00
CCL 4 4 -- -- --
...........continued
PCB HDW
SW Non-
FEATURE SAMC21N/J/G/E PIC32CMxxxxMC00048/32 Non- Comments
Compatible
Compatible
SERCOM
-- -- --
Instances
The DBGCTRL
register is not
USART -- X
available for
8/6/6/4 4 PIC32CM MC00
SPI -- -- --
SDADC
3 3 -- -- --
Channels
AC 4/2/2/2 2 -- -- --
DAC 1 1 -- -- --
TSENS 1 1 -- -- --
RTC Alarms 1 1 -- -- --
RTC Compare
One 32-bit value or two 16-bit values One 32-bit value or two 16-bit values -- -- --
values
Section Updates
5-Volt, 128-KB Flash, Addition of AEC-Q100 Grade qualifications
16-KB SRAM with
Advanced Analog
Configuration Summary Removed a redundant table
Ordering Information Added a note for AEC-Q100 Qualification
PDEC • Updated the equation for Filtering in Input Selection and Filtering
• Added SYNBUSY.STATUS verbiage to the STATUS register for the following bit
fields:
– HERR
– WINERR
– MPERR
– IDXERR
– QERR
Electrical Specifications • Updated the Conditions column for the last two rows of the table in I/O Pin Electrical
at 85℃ Specifications
• Removed the Minimum Specification for XOSC_35 in External Crystal Oscillator and
Clock (XOSC) Electrical Specifications
• Removed the Min. and Max. Specifications for XOSC32_19 in External 32 kHz
Crystal Oscillator (XOSC32K) Electrical Specifications
• Updated the Min. and Max. Specifications for OSC48M_1 in Internal 48 MHz RC
Oscillator (OSC48M)
• Removed a Redundant table from Fractional Digital Phase Locked Loop
(FDPLL96M)
• Updated the Min., Max and Units Specifications for SDAC_23 and SDAC_25 in
Digital-to-Analog Converter (DAC) Electrical Specifications
• Added a note to Temperature Sensor (TSENS) Electrical Specifications
Electrical Specifications • Updated the Min. and Max. Specifications for OSC48M_1 in the table in Internal 48
at 125℃ MHz RC Oscillator (OSC48M)
• Updated the Min., Max. and Units specifications for SDAC_23 and SDAC_25 in DAC
Module Electrical Specifications
Section Updates
General Throughout the entire document all references of “Master” were changed to “Host,” and
“Slave” was changed to “Client,” where applicable.
Electrical • Updated the Absolute Maximum Ratings table with new specifications for VDD and
Specifications at VDDIO
85℃ • Updated Power Supply table with new specifications for REG_4, REG_5, REG_9,
REG_11, REG_38, and REG_39
• Updated the CPU Active Power table with the addition of APWR_5 and APWR_7
• Updated the note of the CPU Idle Power table
• Updated Peripheral Active Current with a new table
• Updated the table in the I/O Pin Electrical Specifications with new max value for DI_21,
and new data for Note 1, Note 2, and Note 4
• Updated VR_27 min and max values in Internal Voltage Reference Specifications
• Updated the notes in External Crystal Oscillator and Clock (XOSC) Electrical
Specifications
• Update the notes in External 32kHz Crystal Oscillator (XOSC32K) Electrical
Specifications
• Updated Internal 32.768 kHz RC Oscillator (OSC32K) with new min and max values for
OSC32K_3b
• Updated the min and max values for OSC48M_1 in Internal 48MHz RC Oscillator
(OSC48M)
• Removed erroneous reference to PPM<100 from the “Fractional Digital Phase Locked
Loop (FDPLL96M) Electrical Specifications” table in Fractional Digital Phase Locked
Loop (FDPLL96M)
• Updated the min and max specifications for SADC_31a, SADC_31b, SADC_31c,
SADC_31d, SADC_37a, SADC_37b, SADC_37c, SADC_37d, DADC+31a,
DADC_31b, DADC_31c, DADC_31d, DADC_37a, DADC_37b, DADC_37c, and
DADC_37d in Analog to Digital Converter (ADC) Electrical Specifications
• Updated the Min. and max. specifications for DSDADC_31 and DSDADC_37 in Sigma-
Delta Analog to Digital Converter (SDADC) Electrical Specifications
• Updated the minimum specifications in the table for Frequency Meter (FREQM)
Electrical Specifications
• Updated the minimum specifications in the table for Position Decoder (PDEC) Electrical
Specifications
Section Updates
Pinout • Updated the 32-pin VQFN diagrams with proper pin numbering. Updated Note 1 in the
Pinout table.
• Updated the 48-pin VQFN diagrams with proper pin numbering. Updated Note 1 in the
Pinout table.
General For each chapter the topic “Product Dependencies” was renamed to “Peripheral Dependencies”
and the content was condensed into a table.
...........continued
Section Updates
Power Supply Removed redundant images from Typical Powering Schematics and added a cross reference to
and Start-Up the proper schematics.
Considerations
Processor and New verbiage was added to the SysTick section of Cortex-M0+ Peripherals.
Architecture
Product Mapping Updated the diagram with a new section for PORT, DIVAS, and Reserved off the IOBUS
section.
NVM User Row Updated the BODCORE calibration with a new Production Setting.
Mapping
Clock System Updated the Diagram in On-Demand, Clock Requests changing CLKEN to CHEN.
GCLK Added new information about the Peripheral channel to the second line item in Initialization.
OSCCTRL • Added new verbiage regarding the XOSC Register to External Multipurpose Crystal
Oscillator (XOSC) Operation
• Added new Verbiage to the Clock Failure detection section of Clock Failure Detection
Operation
• Added new verbiage for OSC48M Operation at the end of 48 MHz Internal Oscillator
(OSC48M) Operation
• New verbiage for configuration was added to Loop Divider Ratio Rates
• The following register was updated with new verbiage to notes and/or bitfields:
– OSC48MDIV
OSC32KCTRL • Updated 32.768 kHz External Crystal Oscillator (XOSC32K) Operation with new verbiage
regarding disabling the XOSC32K bit
• Updated Clock Failure Detection Operation with new verbiage at the end of the Clock
Failure Detection Section
SUPC Added content for the SDADC to the SEL bitfield of the VREF register
DSU Updated the REVISION bit of the DID Register with new text for device revision.
PM Updated verbiage for the SysTick Overflow Interrupt in SRAM Automatic Low-Power Mode.
PAC • Removed erroneous text from the Interrupts section
• Added new notes to the PERID bit of the WRCTRL Register
• Removed the TSENS bit from the INTFLAGA and STATUSA Registers
RTC • Added verbiage for STANDBY Sleep Mode to Sleep Mode Operation
• Updated the following registers with new verbiage for the bitfield COUNT:
– COUNT32
– COUNT16
• Added a new note to the CLOCK register
EIC Updated Asynchronous Edge detection Mode with new verbiage for asynchronous edge
detection.
NVMCTRL Updated Command and Data Interface with verbiage for confirming INTFLAG.READY is ‘1’.
PORT Updated PORT Access Priority with new verbiage about IOBUS writes.
...........continued
Section Updates
EVSYS • Added new verbiage to Event System Channel for the busy bit
• Updated Channel Path with new verbiage regarding 2.5 GCLK_EVSYS periods
• Added new verbiage to The Overrun Channel n Interrupt regarding the GCLK
• Added new verbiage to Software Event for channels with a resynchronized path
• Updated the User Multiplexer Number table in the USERm Register
SERCOM USART • Updated Collision Detection with verbiage for the Peripheral Bus (APB)
• Updated Interrupts with new verbiage for the Data Register Empty interrupt
• Updated Sleep Mode Operation with new verbiage for the FERR, PERR, and STANDBY
power consumption
• Removed erroneous DBGCTRL register
• Updated the following registers with new FERR and PERR information:
– INTENSET
– INTFLAG
SERCOM SPI • Updated Preloading of the Client Shift Register to avoid the Preload function
• Updated Interrupts with new verbiage for the Data Register Empty interrupt
• Updated the following registers with new verbiage:
– CTRLB
– DBGCTRL
SERCOM I2C • Updated 10-Bit Addressing to show it is not available in Client mode
• Updated Quick Command with new verbiage for the Quick Command mode
• Updated Client DMA with new verbiage for transaction length of data
• Updated Interrupts with new verbiage for the DRDY, AMATCH, PREC, SB, and MB
interrupts
• Updated the STATUS Register with new verbiage for the SEXTOUT, CLKHOLD,
LOWTOUT, COLL, and BUSERR bits
• Removed the TENBITEN bit from the ADDR Register and updated the ADDRMASK and
ADDR bits with new bit lengths
TC • Updated Double Buffering with new verbiage for the STATUS Register
• Updated Sleep Mode Operation with information about STANDBY Sleep mode
• Updated the following 8 bit registers with new verbiage:
– STATUS
– DBGCTRL
• Updated the following 16 bit registers with new verbiage:
– STATUS
– DBGCTRL
– SYNCBUSY
• Updated the following 32 bit registers with new verbiage:
– STATUS
– DBGCTRL
...........continued
Section Updates
TCC • Updated the Configuration Summary to display a 16-bit Counter Size for TCC#1
• Updated Double Buffering with new verbiage for clearing the STATUS bits twice
• Updated Dithering Operation with verbiage regarding avoiding an external retrigger event
• Updated RAMP2 Operation in Ramp Operation with verbiage for supporting counting up
mode
• Added new verbiage to the Counter Re-trigger sections of Events detailing the non-
support of dithering or if RAMP2 operation is used with a prescaler
• Added new verbiage to Sleep Mode Operation detailing STANDBY Sleep mode
• Updated the following registers:
– CTRLA - Removed the ALOCK bit
– CTRLBCLR - new verbiage to the IDXCMD bit
– DBGCTRL - new verbiage for the DBGRUN bit
– EVCTRL - Updated the EVACT1 and EVACT0 bit descriptions
– STATUS - Removed the WAVEBUFV bit and added new text to the register
description
ADC • Updated Offset and Gain Correction with new verbiage to not use it for 8 and 10-bit
conversion resolution
• Updated Reference Buffer Compensation Offset with new information regarding discarding
conversions of the ADC
• Removed the DAC from the Diagram in Host/Client Operation
• Updated Sleep Mode Operation with new information for STANDBY Sleep mode
• Updated the following registers:
– REFCTRL - New verbiage for discarding ADC conversions
– INPUTCTRL - Removal of DAC reference from the MUXPOS bit
– OFFSETCORR - Updated text for not using Offset correction for 8-bit and 10-bit
conversion resolution
– DBGCTRL - New verbiage for DBGRUN bit
AC Updated the DBGCTRL register with new verbiage for the DBGRUN bit.
DAC • Updated Sleep Mode Operation with new verbiage for STANDBY
• Updated the INTFLAG register with new verbiage for the EMPTY bit
• Updated the DBGCTRL Register with new verbiage for the DBGRUN bit
...........continued
Section Updates
FREQM Updated the CTRLB Register with a new note.
PDEC • Updated Prescaler Selection to remove erroneous text
• In Position and Rotation Measurement all references starting with Q, such as Q4, Q4S, etc
were changed to read X4, and X4S etc
• Removed the Count Event Action topic
• Removed The description for “Count” from the bulleted item list in Events
• Updates were done to the following registers:
– EVCTRL - Updated verbiage for the EVE, EVEI, EVINV, and EVACT1 bits
Electrical Updates to formatting, notes, min, typ and max specs were made to the tables and content of
Characteristics the following topics:
• Operating Frequencies and Thermal Limitations
• Power Supply
• CPU Active Power
• CPU Idle Power
• CPU Standby Power
• Peripheral Active Current
• Wake-up Timing
• I/O Pin Electrical Specifications
• Internal Voltage Reference Specifications
• Maximum Clock Frequencies Electrical Specifications
• XOSC Electrical Specifications
• XOSC32K Electrical Specifications
• Internal 32.768 kHz RC Oscillator (OSC32K)
• Internal 48MHz RC Oscillator (OSC48M)
• Ultra Low Power internal 32kHz RC Oscillator (OSCULP32K)
• Frequency Digital Phase Locked Loop (FDPLL96M)
• Digital-to-Analog Converter (DAC) Module
• ADC Electrical Specifications
• SDADC Electrical Specifications
• Temperature Sensor (TSENS) Electrical Specifications
• Analog Comparator (AC) Electrical Specifications
• SERCOM SPIx Mode Electrical Specifications
• SERCOM USART Electrical Specifications
• SERCOM I2C Electrical Specifications
• TC Input Module Electrical Specifications
• TCC Module Electrical Specifications
• FREQM Electrical Specifications
• Flash NVM Electrical Specifications
• Position Decoder (PDEC) Electrical Specifications
...........continued
Section Updates
Packaging Removed the Packaging table for moisture sensitivity from the following packages:
• 48-pin TQFP
• 48-pin VQFN
• 32-pin TQFP
Added in packaging tables for the following package:
• 32-pin VQFN
Updated the Package Marking Information, and removed the Thermal Considerations topics.
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ISBN: 978-1-5224-8349-6