PIC16F18854
PIC16F18854
PIC16F18854
Description
PIC16(L)F18854 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,
combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.
The family will feature the CRC/SCAN, Hardware Limit Timer (HLT) and Windowed Watchdog Timer (WWDT) to support
customers looking to add safety to their application. Additionally, this family includes up to 7 KB of Flash memory, along
with a 10-bit ADC with Computation (ADC2) extensions for automated signal analysis to reduce the complexity of the
application.
Analog Peripherals
• Analog-to-Digital Converter with Computation
(ADC2):
- 10-bit with up to 24 external channels
- Automated post-processing
- Automates math functions on input signals:
averaging, filter calculations, oversampling
and threshold comparison
- Operates in Sleep
• Two Comparators (COMP):
- Fixed Voltage Reference at (non) inverting
input(s)
- Comparator outputs externally accessible
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
Memory (Words)
CCP/10-Bit PWM
Watchdog Timer
EUSART/I2C/SPI
8-Bit (with HLT)/
Program Flash
Program Flash
16-Bit Timers
Memory (KB)
Comparator
Data SRAM
Windowed
I/O Pins(1)
Disable
5-Bit DAC
EEPROM
(bytes)
(bytes)
CWG
DSM
NCO
SMT
CLC
Device
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
TABLE 1: PACKAGES
QFN UQFN QFN UQFN
Packages (S)PDIP SOIC SSOP TQFP
(6x6) (4x4) (8x8) (5x5)
PIC16(L)F18854
PIN DIAGRAMS
VPP/MCLR/RE3 1 28 RB7
RA0 2 27 RB6
RA1 3 26 RB5
RA2 4 25 RB4
RA3 5 24 RB3
RA4 6 23 RB2
RA5 7 PIC16(L)F18854 22 RB1
VSS 8 21 RB0
RA7 9 20 VDD
RA6 10 19 VSS
RC0 11 18 RC7
RC1 12 17 RC6
RC2 13 16 RC5
RC3 14 15 RC4
RE3/MCLR/VPP
RA1
RA0
RB7
RB6
RB5
RB4
28
27
26
24
23
22
25
RA2 1 21 RB3
RA3 2 20 RB2
RA4 3 19 RB1
RA5 PIC16(L)F18854
4 18 RB0
VSS 5 17 VDD
RA7 6 16 VSS
RA6 7 15 RC7
RC2 10
RC4 12
RC5 13
RC6 14
RC3 11
RC0 8
Note 1: RC1 9
See Table 2 for location of all peripheral functions.
2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
3: The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.
PIC16(L)F18854
TABLE 2: 28-PIN ALLOCATION TABLE (PIC16(L)F18854)
28-Pin SPDIP/SOIC/SSOP
Interrupt-on-Change
Zero-Cross Detect
Voltage Reference
MSSP (SPI/I2C)
Comparators
Timers/SMT
EUSART
Basic
CWG
DSM
NCO
ADC
DAC
CLC
I/O
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTX pins. Refer to Table 13-1 for details on which port pins may be
used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTX pin options as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I2C specific or SMbus input buffer thresholds.
TABLE 2: 28-PIN ALLOCATION TABLE (PIC16(L)F18854) (CONTINUED)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
28-Pin SPDIP/SOIC/SSOP
Interrupt-on-Change
Zero-Cross Detect
Voltage Reference
MSSP (SPI/I2C)
Comparators
Timers/SMT
EUSART
Basic
CWG
DSM
NCO
ADC
DAC
CLC
I/O
VSS 8, 5, — — — — — — — — — — — — — — — —
19 16
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTX pins. Refer to Table 13-1 for details on which port pins may be
used for this signal.
DS40001826C-page 7
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTX pin options as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I2C specific or SMbus input buffer thresholds.
TABLE 2: 28-PIN ALLOCATION TABLE (PIC16(L)F18854) (CONTINUED)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
28-Pin SPDIP/SOIC/SSOP
Interrupt-on-Change
Zero-Cross Detect
Voltage Reference
MSSP (SPI/I2C)
Comparators
Timers/SMT
EUSART
Basic
CWG
DSM
NCO
ADC
DAC
CLC
I/O
OUT(2) — — ADGRDA — — C1OUT — SDO1 TX/ DSM TMR0 CCP1 CWG1A CLC1OUT NCO CLKR — —
ADGRDB C2OUT SCK1 CK(3) CCP2 CWG1B CLC2OUT
SDO2 DT(3) CCP3 CWG1C CLC3OUT
SCK2 CCP4 CWG1D CLC4OUT
CCP5 CWG2A
PWM6OUT CWG2B
PWM7OUT CWG2C
CWG2D
CWG3A
CWG3B
CWG3C
CWG3D
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTX pins. Refer to Table 13-1 for details on which port pins may be
used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTX pin options as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I2C specific or SMbus input buffer thresholds.
DS40001826C-page 8
PIC16(L)F18854
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 21
3.0 Memory Organization ................................................................................................................................................................. 23
4.0 Device Configuration .................................................................................................................................................................. 73
5.0 Resets ........................................................................................................................................................................................ 82
6.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 91
7.0 Interrupts .................................................................................................................................................................................. 110
8.0 Power-Saving Operation Modes .............................................................................................................................................. 136
9.0 Windowed Watchdog Timer (WWDT) ...................................................................................................................................... 143
10.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 151
11.0 Cyclic Redundancy Check (CRC) Module ............................................................................................................................... 169
12.0 I/O Ports ................................................................................................................................................................................... 181
13.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 204
14.0 Peripheral Module Disable ....................................................................................................................................................... 214
15.0 Interrupt-On-Change ................................................................................................................................................................ 221
16.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 229
17.0 Temperature Indicator Module ................................................................................................................................................. 232
18.0 Comparator Module.................................................................................................................................................................. 234
19.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 244
20.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 251
21.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 275
22.0 Configurable Logic Cell (CLC).................................................................................................................................................. 281
23.0 Analog-to-Digital Converter With Computation (ADC2) Module............................................................................................... 298
24.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 336
25.0 5-Bit Digital-to-Analog Converter (DAC1) Module.................................................................................................................... 346
26.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 351
27.0 Timer0 Module ......................................................................................................................................................................... 364
28.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 370
29.0 Timer2/4/6 Module ................................................................................................................................................................... 384
30.0 Capture/Compare/PWM Modules ............................................................................................................................................ 405
31.0 Master Synchronous Serial Port (MSSP) Modules .................................................................................................................. 418
32.0 Signal Measurement Timer (SMT) ........................................................................................................................................... 469
33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 514
34.0 Reference Clock Output Module .............................................................................................................................................. 542
35.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 546
36.0 Instruction Set Summary .......................................................................................................................................................... 548
37.0 Electrical Specifications............................................................................................................................................................ 562
38.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 592
39.0 Development Support............................................................................................................................................................... 608
40.0 Packaging Information.............................................................................................................................................................. 612
Appendix A: Data Sheet Revision History ......................................................................................................................................... 626
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Website; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
PIC16(L)F18854
sheet. The PIC16(L)F18854 devices are available in
28-pin SPDIP, SSOP, SOIC, and UQFN packages.
Figure 1-1 shows a block diagram of the Peripheral
PIC16(L)F18854 devices. Table 1-2 shows the pinout
descriptions.
Reference Table 1-1 for peripherals available per device. Timers
Timer0 ●
TABLE 1-1: DEVICE PERIPHERAL Timer1 ●
SUMMARY Timer2 ●
Timer3 ●
PIC16(L)F18854
Timer4 ●
Timer5 ●
Peripheral
Timer6 ●
PIC16(L)F18854
Rev. 10-000039K
Program 11/20/2015
Flash Memory
RAM
PORTA
CLKOUT
/OSC2 Timing PORTB
Generation
CPU
CLKIN/
OSC1 INTRC PORTC
Oscillator
(Note 3)
MCLR
PORTE
Temp ADC
TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 CRC Scanner DSM C2 C1 DAC FVR
Indicator 10-bit
CWG1 CWG2 CWG3 SMT2 SMT1 NCO1 EUSART MSSP2 MSSP1 CLC4 CLC3 CLC2 CLC1 ZCD1 PWM6/7 CCPs(5)
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
RE3/IOCE3/MCLR/VPP RE3 TTL/ST — General purpose input only (when MCLR is disabled by the
Configuration bit).
IOCE3 TTL/ST — Interrupt-on-change input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I2C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I2C specific or SMBus input buffer thresholds.
15
Configuration 15 8
Data Bus
Program Counter
MUX
Nonvolatile
Memory 16-Level
8 Level Stack
Stack
RAM
(13-bit)
(15-bit)
Program
14 Program Memory 12 RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction
Instruction Reg
reg
Indirect
Direct Addr 7 Addr
5 12 12
15 BSR
FSR Reg
reg
FSR0reg
FSR Reg
FSR1 Reg
FSR reg
15 STATUS Reg
STATUS reg
8
3 MUX
Power-up
Timer
Instruction Oscillator
Decodeand
Decode & Start-up Timer
ALU
Control
OSC1/CLKIN Power-on
Reset 8
Timing Watchdog
OSC2/CLKOUT Generation Timer W reg
Brown-out
Reset
Internal
Oscillator
Block
VDD VSS
Unimplemented
3FFFh
4000h
7FFFh
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
6Fh
70h
Common RAM
(16 bytes)
7Fh
PIC16(L)F18854
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch ADRESL 10Ch ADCNT 18Ch SSP1BUF 20Ch TMR1L 28Ch T2TMR 30Ch CCPR1L 38Ch PWM6DCL
00Dh PORTB 08Dh ADRESH 10Dh ADRPT 18Dh SSP1ADD 20Dh TMR1H 28Dh T2PR 30Dh CCPR1H 38Dh PWM6DCH
00Eh PORTC 08Eh ADPREVL 10Eh ADLTHL 18Eh SSP1MSK 20Eh T1CON 28Eh T2CON 30Eh CCP1CON 38Eh PWM6CON
00Fh — 08Fh ADPREVH 10Fh ADLTHH 18Fh SSP1STAT 20Fh T1GCON 28Fh T2HLT 30Fh CCP1CAP 38Fh —
010h PORTE 090h ADACCL 110h ADUTHL 190h SSP1CON1 210h T1GATE 290h T2CLKCON 310h CCPR2L 390h PWM7DCL
011h TRISA 091h ADACCH 111h ADUTHH 191h SSP1CON2 211h T1CLK 291h T2RST 311h CCPR2H 391h PWM7DCH
012h TRISB 092h — 112h ADSTPTL 192h SSP1CON3 212h TMR3L 292h T4TMR 312h CCP2CON 392h PWM7CON
013h TRISC 093h ADCON0 113h ADSTPTH 193h — 213h TMR3H 293h T4PR 313h CCP2CAP 393h —
014h — 094h ADCON1 114h ADFLTRL 194h — 214h T3CON 294h T4CON 314h CCPR3L 394h —
015h — 095h ADCON2 115h ADFLTRH 195h — 215h T3GCON 295h T4HLT 315h CCPR3H 395h —
016h LATA 096h ADCON3 116h ADERRL 196h SSP2BUF 216h T3GATE 296h T4CLKCON 316h CCP3CON 396h —
017h LATB 097h ADSTAT 117h ADERRH 197h SSP2ADD 217h T3CLK 297h T4RST 317h CCP3CAP 397h —
018h LATC 098h ADCLK 118h — 198h SSP2MSK 218h TMR5L 298h T6TMR 318h CCPR4L 398h —
019h — 099h ADACT 119h RC1REG 199h SSP2STAT 219h TMR5H 299h T6PR 319h CCPR4H 399h —
01Ah — 09Ah ADREF 11Ah TX1REG 19Ah SSP2CON1 21Ah T5CON 29Ah T6CON 31Ah CCP4CON 39Ah —
01Bh — 09Bh ADCAP 11Bh SP1BRGL 19Bh SSP2CON2 21Bh T5GCON 29Bh T6HLT 31Bh CCP4CAP 39Bh —
01Ch TMR0L 09Ch ADPRE 11Ch SP1BRGH 19Ch SSP2CON3 21Ch T5GATE 29Ch T6CLKCON 31Ch CCPR5L 39Ch —
01Dh TMR0H 09Dh ADACQ 11Dh RC1STA 19Dh — 21Dh T5CLK 29Dh T6RST 31Dh CCPR5H 39Dh —
01Eh T0CON0 09Eh ADPCH 11Eh TX1STA 19Eh — 21Eh CCPTMRS0 29Eh — 31Eh CCP5CON 39Eh —
01Fh T0CON1 09Fh — 11Fh BAUD1CON 19Fh — 21Fh CCPTMRS1 29Fh — 31Fh CCP5CAP 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h
General Purpose
Register
General General General General General 32Fh 48 Bytes
Purpose Purpose Purpose Purpose Purpose Unimplemented
General Register Register Register Register Register 330h Read as ‘0’
Purpose 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes Unimplemented
Register Read as ‘0’
96 Bytes
0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
0F0h Common RAM 170h Common RAM 1F0h Common RAM 270h Common RAM 2F0h Common RAM 370h Common RAM 3F0h Common RAM
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
07Fh 0FFh 70h – 7Fh) 17Fh 70h – 7Fh) 1FFh 70h – 7Fh) 27Fh 70h – 7Fh) 2FFh 70h – 7Fh) 37Fh 70h – 7Fh) 3FFh 70h – 7Fh)
PIC16(L)F18854
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h 480h 500h 580h 600h 680h 700h 780h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
40Bh 48Bh 50Bh 58Bh 60Bh 68Bh 70Bh 78Bh
40Ch SCANLADRL 48Ch SMT1TMRL 50Ch SMT2TMRL 58Ch NCO1ACCL 60Ch CWG1CLKCON 68Ch CWG3CLKCON 70Ch PIR0 78Ch —
40Dh SCANLADRH 48Dh SMT1TMRH 50Dh SMT2TMRH 58Dh NCO1ACCH 60Dh CWG1ISM 68Dh CWG3ISM 70Dh PIR1 78Dh —
40Eh SCANHADRL 48Eh SMT1TMRU 50Eh SMT2TMRU 58Eh NCO1ACCU 60Eh CWG1DBR 68Eh CWG3DBR 70Eh PIR2 78Eh —
40Fh SCANHADRH 48Fh SMT1CPRL 50Fh SMT2CPRL 58Fh NCO1INCL 60Fh CWG1DBF 68Fh CWG3DBF 70Fh PIR3 78Fh —
410h SCANCON0 490h SMT1CPRH 510h SMT2CPRH 590h NCO1INCH 610h CWG1CON0 690h CWG3CON0 710h PIR4 790h —
411h SCANTRIG 491h SMT1CPRU 511h SMT2CPRU 591h NCO1INCU 611h CWG1CON1 691h CWG3CON1 711h PIR5 791h —
412h — 492h SMT1CPWL 512h SMT2CPWL 592h NCO1CON 612h CWG1AS0 692h CWG3AS0 712h PIR6 792h —
413h — 493h SMT1CPWH 513h SMT2CPWH 593h NCO1CLK 613h CWG1AS1 693h CWG3AS1 713h PIR7 793h —
414h — 494h SMT1CPWU 514h SMT2CPWU 594h — 614h CWG1STR 694h CWG3STR 714h PIR8 794h —
415h — 495h SMT1PRL 515h SMT2PRL 595h — 615h — 695h — 715h — 795h —
416h CRCDATL 496h SMT1PRH 516h SMT2PRH 596h — 616h CWG2CLKCON 696h — 716h PIE0 796h PMD0
417h CRCDATH 497h SMT1PRU 517h SMT2PRU 597h — 617h CWG2ISM 697h — 717h PIE1 797h PMD1
418h CRCACCL 498h SMT1CON0 518h SMT2CON0 598h — 618h CWG2DBR 698h — 718h PIE2 798h PMD2
419h CRCACCH 499h SMT1CON1 519h SMT2CON1 599h — 619h CWG2DBF 699h — 719h PIE3 799h PMD3
41Ah CRCSHIFTL 49Ah SMT1STAT 51Ah SMT2STAT 59Ah — 61Ah CWG2CON0 69Ah — 71Ah PIE4 79Ah PMD4
41Bh CRCSHIFTH 49Bh SMT1CLK 51Bh SMT2CLK 59Bh — 61Bh CWG2CON1 69Bh — 71Bh PIE5 79Bh PMD5
41Ch CRCXORL 49Ch SMT1SIG 51Ch SMT2SIG 59Ch — 61Ch CWG2AS0 69Ch — 71Ch PIE6 79Ch —
41Dh CRCXORH 49Dh SMT1WIN 51Dh SMT2WIN 59Dh — 61Dh CWG2AS1 69Dh — 71Dh PIE7 79Dh —
41Eh CRCCON0 49Eh — 51Eh — 59Eh — 61Eh CWG2STR 69Eh — 71Eh PIE8 79Eh —
41Fh CRCCON1 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh —
420h 4A0h 520h 5A0h 620h 6A0h 720h 7A0h
PIC16(L)F18854
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h 880h 900h 980h A00h A80h B00h B80h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2 ) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh
80Ch WDTCON0 88Ch CPUDOZE 90Ch FVRCON 98Ch — A0Ch A8Ch B0Ch B8Ch
80Dh WDTCON1 88Dh OSCCON1 90Dh — 98Dh —
80Eh WDTPSL 88Eh OSCCON2 90Eh DAC1CON0 98Eh —
80Fh WDTPSH 88Fh OSCCON3 90Fh DAC1CON1 98Fh CMOUT
810h WDTTMR 890h OSCSTAT 910h — 990h CM1CON0
811h BORCON 891h OSCEN 911h — 991h CM1CON1
812h VREGCON(1) 892h OSCTUNE 912h — 992h CM1NSEL
813h PCON0 893h OSCFRQ 913h — 993h CM1PSEL
814h —(2) 894h — 914h — 994h CM2CON0
815h — 895h CLKRCON 915h — 995h CM2CON1
816h — 896h CLKRCLK 916h — 996h CM2NSEL
817h — 897h MDCON0 917h — 997h CM2PSEL Unimplemented Unimplemented Unimplemented Unimplemented
818h — 898h MDCON1 918h — 998h — Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
819h — 899h MDSRC 919h — 999h —
81Ah NVMADRL 89Ah MDCARL 91Ah — 99Ah —
81Bh NVMADRH 89Bh MDCARH 91Bh — 99Bh —
81Ch NVMDATL 89Ch — 91Ch — 99Ch —
81Dh NVMDATH 89Dh — 91Dh — 99Dh —
81Eh NVMCON1 89Eh — 91Eh — 99Eh —
81Fh NVMCON2 89Fh — 91Fh ZCDCON 99Fh —
820h 8A0h 920h 9A0h
Unimplemented Unimplemented Unimplemented Unimplemented
Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h Common RAM 8F0h Common RAM 970h Common RAM 9F0h Common RAM A70h Common RAM AF0h Common RAM B70h Common RAM BF0h Common RAM
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
87Fh 70h – 7Fh 8FFh 70h – 7Fh 97Fh 70h – 7Fh 9FFh 70h – 7Fh A7Fh 70h – 7Fh AFFh 70h – 7Fh B7Fh 70h – 7Fh BFFh 70h – 7Fh
PIC16(L)F18854
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h C80h D00h D80h E00h E80h F00h F80h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh F8Bh
C0Ch C8Ch D0Ch D8Ch E0Ch E8Ch F0Ch F8Ch
Unimplemented
Read as ‘0’
See Table 3-7 for See Table 3-8 for See Tables 3-9
Unimplemented Unimplemented Unimplemented Unimplemented
register mapping register mapping for register
Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
details details mapping details FE3h
FE4h STATUS_SHAD
FE5h WREG_SHAD
FE6h BSR_SHAD
FE7h PCLATH_SHAD
FE8h FSR0L_SHAD
FE9h FSR0H_SHAD
FEAh FSR1L_SHAD
FEBh FSR1H_SHAD
FECh —
FEDh STKPTR
FEEh TOSL
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh TOSH
C70h CF0h D70h DF0h E70h EF0h F70h FF0h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
C7Fh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
DS40001826C-page 31
PIC16(L)F18854
TABLE 3-7: PIC16(L)F18854 MEMORY MAP, BANK 28
Bank 28
Bank 28
E0Ch —
E2Eh CLC4CON
E0Dh —
E2Fh CLC4POL
E0Eh —
E30h CLC4SEL0
E0Fh CLCDATA
E31h CLC4SEL1
E10h CLC1CON
E32h CLC4SEL2
E11h CLC1POL
E33h CLC4SEL3
E12h CLC1SEL0
E34h CLC4GLS0
E13h CLC1SEL1
E35h CLC4GLS1
E14h CLC1SEL2
E36h CLC4GLS2
E15h CLC1SEL3
E37h CLC4GLS3
E16h CLC1GLS0
E38h
E17h CLC1GLS1
—
E18h CLC1GLS2
E6Fh
E19h CLC1GLS3
E1Ah CLC2CON
E1Bh CLC2POL
E1Ch CLC2SEL0
E1Dh CLC2SEL1
E1Eh CLC2SEL2
E1Fh CLC2SEL3
E20h CLC2GLS0
E21h CLC2GLS1
E22h CLC2GLS2
E23h CLC2GLS3
E24h CLC3CON
E25h CLC3POL
E26h CLC3SEL0
E27h CLC3SEL1
E28h CLC3SEL2
E29h CLC3SEL3
E2Ah CLC3GLS0
E2Bh CLC3GLS1
E2Ch CLC3GLS2
E2Dh CLC3GLS3
E9Bh — EC0h —
E9Ch T2AINPPS EC1h —
EA8h — ECDh
EA9h SMT1WINPPS —
EACh SMT2SIGPPS
EADh —
EAEh —
EAFh —
EB0h —
PIC16(L)F18854
TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 0
00Ch PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx xxxx xxxx
00Dh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx xxxx xxxx
00Eh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx
00Fh — Unimplemented — —
011h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
012h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
013h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
014h — Unimplemented — —
015h — Unimplemented — —
016h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx uuuu uuuu
017h LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx uuuu uuuu
018h LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu
019h — Unimplemented — —
01Ah — Unimplemented — —
01Bh — Unimplemented — —
01Ch TMR0L Holding Register for the Least Significant Byte of the 16-bit TMR0 Register 0000 0000 0000 0000
01Dh TMR0H Holding Register for the Most Significant Byte of the 16-bit TMR0 Register 1111 1111 1111 1111
01Eh T0CON0 T0EN — T0OUT T016BIT T0OUTPS<3:0> 0-00 0000 0-00 0000
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
DS40001826C-page 36
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 1
092h — Unimplemented — —
093h ADCON0 ADON ADCONT — ADCS — ADFRM0 — ADGO 00-0 -0-0 00-0 -0-0
094h ADCON1 ADPPOL ADIPEN ADGPOL — — — — ADDSEN 000- ---0 000- ---0
095h ADCON2 ADPSIS ADCRS<2:0> ADACLR ADMD<2:0> 0000 0000 0000 0000
097h ADSTAT ADAOV ADUTHR ADLTHR ADMATH — ADSTAT<2:0> 0000 -000 0000 -000
09Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 37
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 2
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 3
18Fh SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
190h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
191h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
192h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
193h — Unimplemented — —
194h — Unimplemented — —
195h — Unimplemented — —
199h SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
19Ah SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
19Bh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
19Ch SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
19Dh — Unimplemented — —
19Eh — Unimplemented — —
19Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 39
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 4
20Ch TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 0000 0000 uuuu uuuu
20Dh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 0000 0000 uuuu uuuu
20Fh T1GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 0000 0x-- uuuu ux--
212h TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register 0000 0000 uuuu uuuu
213h TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register 0000 0000 uuuu uuuu
215h T3GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 0000 0x-- uuuu ux--
218h TMR5L Holding Register for the Least Significant Byte of the 16-bit TMR5 Register 0000 0000 uuuu uuuu
219h TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register 0000 0000 uuuu uuuu
21Bh T5GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 0000 0x-- uuuu ux--
21Eh CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 0101 0101 0101 0101
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 40
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 5
28Ch T2TMR Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000
28Fh T2HLT PSYNC CKPOL CKSYNC — MODE 000- 0000 000- 0000
292h T4TMR Holding Register for the 8-bit TMR4 Register 0000 0000 0000 0000
295h T4HLT PSYNC CKPOL CKSYNC — MODE<3:0> 000- 0000 000- 0000
298h T6TMR Holding Register for the 8-bit TMR6 Register 0000 0000 0000 0000
29Bh T6HLT PSYNC CKPOL CKSYNC — MODE<3:0> 000- 0000 000- 0000
29Eh — Unimplemented — —
29Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 41
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 6
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 42
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 7
38Fh — Unimplemented — —
393h — Unimplemented — —
394h — Unimplemented — —
395h — Unimplemented — —
396h — Unimplemented — —
397h — Unimplemented — —
398h — Unimplemented — —
399h — Unimplemented — —
39Ah — Unimplemented — —
39Bh — Unimplemented — —
39Ch — Unimplemented — —
39Dh — Unimplemented — —
39Eh — Unimplemented — —
39Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 43
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 8
410h SCANCON0 EN SCANGO BUSY INVALID INTM — MODE<1:0> 0000 0-00 0000 0-00
412h — Unimplemented — —
413h — Unimplemented — —
414h — Unimplemented — —
415h — Unimplemented — —
41Eh CRCCON0 EN CRCGO BUSY ACCM — — SHIFTM FULL 0000 --00 0000 --00
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 44
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 9
498h SMT1CON0 EN — STP WPOL SPOL CPOL SMT1PS<1:0> 0-00 0000 0-00 0000
49Eh — Unimplemented — —
49Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 45
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 10
518h SMT2CON0 EN — STP WPOL SPOL CPOL SMT2PS<1:0> 0-00 0000 0-00 0000
51Eh — Unimplemented — —
51Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 46
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 11
592h NCO1CON N1EN — N1OUT N1POL — — — N1PFM 0-00 ---0 0-00 ---0
594h — Unimplemented — —
595h — Unimplemented — —
596h — Unimplemented — —
597h — Unimplemented — —
598h — Unimplemented — —
599h — Unimplemented — —
59Ah — Unimplemented — —
59Bh — Unimplemented — —
59Ch — Unimplemented — —
59Dh — Unimplemented — —
59Eh — Unimplemented — —
59Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 47
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Banks 12
611h CWG1CON1 — — IN — POLD POLC POLB POLA --x- 0000 --u- 0000
612h CWG1AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 0001 01-- 0001 01--
613h CWG1AS1 — AS6E AS5E AS4E AS3E AS2E AS1E AS0E -000 0000 -000 0000
614h CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000
615h — Unimplemented — —
61Bh CWG2CON1 — — IN — POLD POLC POLB POLA --x- 0000 --u- 0000
61Ch CWG2AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 0001 01-- 0001 01--
61Dh CWG2AS1 — AS6E AS5E AS4E AS3E AS2E AS1E AS0E -000 0000 -000 0000
61Eh CWG2STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000
61Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 48
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 13
691h CWG3CON1 — — IN — POLD POLC POLB POLA --x- 0000 --u- 0000
692h CWG3AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 0001 01-- 0001 01--
693h CWG3AS1 — AS6E AS5E AS4E AS3E AS2E AS1E AS0E -000 0000 -000 0000
694h CWG3STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000
695h — Unimplemented — —
696h — Unimplemented — —
697h — Unimplemented — —
698h — Unimplemented — —
699h — Unimplemented — —
69Ah — Unimplemented — —
69Bh — Unimplemented — —
69Ch — Unimplemented — —
69Dh — Unimplemented — —
69Eh — Unimplemented — —
69Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 49
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 14
70Dh PIR1 OSFIF CSWIF — — — — ADTIF ADIF 00-- --00 00-- --00
70Fh PIR3 — — RCIF TXIF BCL2IF SSP2IF BCL1IF SSP1IF --00 0000 --00 0000
710h PIR4 — — TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF --00 0000 --00 0000
711h PIR5 CLC4IF CLC3IF CLC2IF CLC1IF — TMR5GIF TMR3GIF TMR1GIF 0000 -000 0000 -000
712h PIR6 — — — CCP5IF CCP4IF CCP3IF CCP2IF CCP1IF ---0 0000 ---0 0000
713h PIR7 SCANIF CRCIF NVMIF NCO1IF — CWG3IF CWG2IF CWG1IF 0000 -000 0000 -000
714h PIR8 — — SMT2PWAIF SMT2PRAIF SMT2IF SMT1PWAIF SMT1PRAIF SMT1IF --00 0000 --00 0000
715h — Unimplemented — —
717h PIE1 OSFIE CSWIE — — — — ADTIE ADIE 00-- --00 00-- --00
719h PIE3 — — RCIE TXIE BCL2IE SSP2IE BCL1IE SSP1IE --00 0000 --00 0000
71Ah PIE4 — — TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE --00 0000 --00 0000
71Bh PIE5 CLC4IE CLC3IE CLC2IE CLC1IE — TMR5GIE TMR3GIE TMR1GIE 0000 -000 0000 -000
71Ch PIE6 — — — CCP5IE CCP4IE CCP3IE CCP2IE CCP1IE ---0 0000 ---0 0000
71Dh PIE7 SCANIE CRCIE NVMIE NCO1IE — CWG3IE CWG2IE CWG1IE 0000 -000 0000 -000
71Eh PIE8 — — SMT2PWAIE SMT2PRAIE SMT2IE SMT1PWAIE SMT1PRAIE SMT1IE --00 0000 --00 0000
71Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 50
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Banks 15
78Ch — Unimplemented — —
78Dh — Unimplemented — —
78Eh — Unimplemented — —
78Fh — Unimplemented — —
790h — Unimplemented — —
791h — Unimplemented — —
792h — Unimplemented — —
793h — Unimplemented — —
794h — Unimplemented — —
795h — Unimplemented — —
796h PMD0 SYSCMD FVRMD — CRCMD SCANMD NVMMD CLKRMD IOCMD 00-0 0000 00-0 0000
797h PMD1 NCOMD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD 0000 0000 0000 0000
798h PMD2 — DACMD ADCMD — — CMP2MD CMP1MD ZCDMD -00- -000 -00- -000
799h PMD3 — PWM7MD PWM6MD CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD -000 0000 -000 0000
79Ah PMD4 — UART1MD MSSP2MD MSSP1MD — CWG3MD CWG2MD CWG1MD -000 -000 -000 -000
79Bh PMD5 SMT2MD SMT1MD — CLC4MD CLC3MD CLC2MD CLC1MD DSMMD 00-0 0000 00-0 0000
79Ch — Unimplemented — —
79Dh — Unimplemented — —
79Eh — Unimplemented — —
79Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 51
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Banks 16
813h PCON0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 0011 11qq qqqq qquu
815h — Unimplemented — —
816h — Unimplemented — —
817h — Unimplemented — —
818h — Unimplemented — —
819h — Unimplemented — —
81Eh NVMCON1 — NVMREGS LWLO FREE WRERR WREN WR RD -000 x000 -000 q000
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 52
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Banks 17
88Ch CPUDOZE IDLEN DOZEN ROI DOE — DOZE2 DOZE1 DOZE0 0000 -000 0000 -000
88Fh OSCCON3 CSWHOLD SOSCPWR — ORDY NOSCR — — — 00-0 0--- 00-0 0---
890h OSCSTAT EXTOR HFOR MFOR LFOR SOR ADOR — PLLR q0-0 qq-0 q0-0 qq-0
891h OSCEN EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN — — 00-0 00-- 00-0 00--
894h — Unimplemented — —
897h MDCON0 MDEN — MDOUT MDOPOL — — — MDBIT 0-00 ---0 0-00 ---0
898h MDCON1 — — MDCHPOL MDCHSYNC — — MDCLPOL MDCLSYNC --00 --00 --00 --00
89Ch — Unimplemented — —
89Dh — Unimplemented — —
89Eh — Unimplemented — —
89Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 53
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 18
90Ch FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
90Dh — Unimplemented — —
90Eh DAC1CON0 DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS 0-0- 00-- 0-0- 00--
910h — Unimplemented — —
911h — Unimplemented — —
912h — Unimplemented — —
913h — Unimplemented — —
914h — Unimplemented — —
915h — Unimplemented — —
916h — Unimplemented — —
917h — Unimplemented — —
918h — Unimplemented — —
919h — Unimplemented — —
91Ah — Unimplemented — —
91Bh — Unimplemented — —
91Ch — Unimplemented — —
91Dh — Unimplemented — —
91Eh — Unimplemented — —
91Fh ZCDCON EN — OUT POL — — INTP INTN 0-x0 --00 0-x0 --00
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 54
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 19
98Ch — Unimplemented — —
98Dh — Unimplemented — —
98Eh — Unimplemented — —
990h CM1CON0 ON OUT — POL — — HYS SYNC 0x-0 -100 0x-0 -100
994h CM2CON0 ON OUT — POL — — HYS SYNC 0x-0 -100 0x-0 -100
998h — Unimplemented — —
999h — Unimplemented — —
99Ah — Unimplemented — —
99Bh — Unimplemented — —
99Ch — Unimplemented — —
99Dh — Unimplemented — —
99Eh — Unimplemented — —
99Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
DS40001826C-page 55
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 20-27
x0Ch/ — Unimplemented — —
x8Ch
—
x1Fh/
x9Fh
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
2: Unimplemented, read as ‘1’.
DS40001826C-page 56
TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 28
E0Ch — Unimplemented — —
E0Dh — Unimplemented — —
E0Eh — Unimplemented — —
E0Fh CLCDATA — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT ---- 0000 ---- 0000
E10h CLC1CON LC1EN — LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 0-x0 0000 0-x0 0000
E11h CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu
E16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu
E17h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu
E18h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu
E19h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu
E1Ah CLC2CON LC2EN — LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 0-x0 0000 0-x0 0000
E1Bh CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- uuuu
E20h CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu
DS40001826C-page 57
E21h CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu
E22h CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
2: Unimplemented, read as ‘1’.
TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 28 (Continued)
E23h CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu
E24h CLC3CON LC3EN — LC3OUT LC3INTP LC3INTN LC3MODE<2:0> 0-x0 0000 0-x0 0000
E25h CLC3POL LC3POL — — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL 0--- xxxx 0--- uuuu
E2Ah CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu
E2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu
E2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu
E2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu
E2Eh CLC4CON LC4EN — LC4OUT LC4INTP LC4INTN LC4MODE<2:0> 0-x0 0000 0-x0 0000
E2Fh CLC4POL LC4POL — — — LC4G4POL LC4G3POL LC4G2POL LC4G1POL 0--- xxxx 0--- uuuu
E34h CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N xxxx xxxx uuuu uuuu
E35h CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N xxxx xxxx uuuu uuuu
E36h CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N xxxx xxxx uuuu uuuu
E37h CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx uuuu uuuu
E38h to — Unimplemented — —
E6Fh
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
DS40001826C-page 58
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 29
E8Ch — Unimplemented — —
E8Dh — Unimplemented — —
E8Eh — Unimplemented — —
E98h — Unimplemented — —
E99h — Unimplemented — —
E9Ah — Unimplemented — —
E9Bh — Unimplemented — —
E9Fh — Unimplemented — —
EA0h — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
2: Unimplemented, read as ‘1’.
TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 29 (Continued)
EA2h CCP2PPS — — — CCP2PPS<4:0> ---1 0001 ---u uuuu
EA6h — Unimplemented — —
EA7h — Unimplemented — —
EA8h — Unimplemented — —
EADh — Unimplemented — —
EAEh — Unimplemented — —
EAFh — Unimplemented — —
EB0h — Unimplemented — —
EB4h — Unimplemented — —
EB5h — Unimplemented — —
EB6h — Unimplemented — —
EB7h — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
2: Unimplemented, read as ‘1’.
TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 29 (Continued)
EBAh MDSRCPPS — — — MDSRCPPS<4:0> ---0 0101 ---u uuuu
EBFh — Unimplemented — —
EC0h — Unimplemented — —
EC1h — Unimplemented — —
EC2h — Unimplemented — —
EC4h — Unimplemented — —
ECDh to — Unimplemented — —
EEFh
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
2: Unimplemented, read as ‘1’.
DS40001826C-page 61
TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 30
F0Ch — Unimplemented — —
F0Dh — Unimplemented — —
F0Eh — Unimplemented — —
F0Fh — Unimplemented — —
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
2: Unimplemented, read as ‘1’.
TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 30 (Continued)
F24h RC4PPS — — RC4PPS<5:0> --00 0000 --uu uuuu
F28h to — Unimplemented — —
F37h
F38h ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111
F39h WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 0000 0000 0000 0000
F3Ah ODCONA ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 0000 0000 0000
F3Bh SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 1111 1111 1111 1111
F3Ch INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 1111 1111 1111 1111
F3Dh IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 0000 0000 0000 0000
F3Eh IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 0000 0000 0000 0000
F3Fh IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 0000 0000 0000 0000
F42h — Unimplemented — —
F43h ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111
F44h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 0000 0000 0000 0000
F45h ODCONB ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 0000 0000 0000
F46h SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
2: Unimplemented, read as ‘1’.
DS40001826C-page 63
TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 30 (Continued)
F47h INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 1111 1111 1111 1111
F48h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000
F49h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000
F4Ah IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000
F4Dh — Unimplemented — —
F4Eh ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 1111 1111 1111 1111
F4Fh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 0000 0000 0000 0000
F50h ODCONC ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0000 0000 0000 0000
F51h SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 1111 1111 1111 1111
F52h INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111
F53h IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0000 0000 0000
F54h IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000
F55h IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000
F58h to
— Unimplemented — —
F64h
F65h WPUE — — — — WPUE3 — — — ---- 0--- ---- 0---
F66h to
— Unimplemented — —
F67h
F68h INLVLE — — — — INLVLE3 — — — ---- 1--- ---- 1---
F6Eh to
— Unimplemented — —
F6Fh
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
2: Unimplemented, read as ‘1’.
TABLE 3-11: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 31
F8Ch
— — Unimplemented — —
FE3h
FE4h STATUS_SHAD — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu
FE5h WREG_SHAD WREG_SHAD xxxx xxxx uuuu uuuu
FE6h BSR_SHAD — — — BSR_SHAD ---x xxxx ---u uuuu
FE7h PCLATH_SHAD — PCLATH_SHAD -xxx xxxx -uuu uuuu
FE8h FSR0L_SHAD FSR0L_SHAD xxxx xxxx uuuu uuuu
FE9h FSR0H_SHAD FSR0H_SHAD xxxx xxxx uuuu uuuu
FEAh FSR1L_SHAD FSR1L_SHAD xxxx xxxx uuuu uuuu
FEBh FSR1H_SHAD FSR1H_SHAD xxxx xxxx uuuu uuuu
FECh — Unimplemented — —
FEDh STKPTR — — — STKPTR<4;0> ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Note 1: Register present on PIC16F18854 devices only.
2: Unimplemented, read as ‘1’.
DS40001826C-page 65
PIC16(L)F18854
3.3 PCL and PCLATH 3.3.2 COMPUTED GOTO
The Program Counter (PC) is 15 bits wide. The low byte A computed GOTO is accomplished by adding an offset to
comes from the PCL register, which is a readable and the program counter (ADDWF PCL). When performing a
writable register. The high byte (PC<14:8>) is not directly table read using a computed GOTO method, care should
readable or writable and comes from PCLATH. On any be exercised if the table location crosses a PCL memory
Reset, the PC is cleared. Figure 3-3 shows the five boundary (each 256-byte block). Refer to Application
situations for the loading of the PC. Note AN556, “Implementing a Table Read” (DS00556).
Rev. 10-000043A
7/30/2013
Rev. 10-000043B
7/30/2013
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00
Rev. 10-000043C
7/30/2013
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure on
the left. A series of RETURN instructions will
0x0A
repeatedly place the return addresses into
0x09 the Program Counter and pop the stack.
0x08
0x07
TOSH:TOSL 0x06 Return Address STKPTR = 0x06
Rev. 10-000044A
7/30/2013
0x0000 0x0000
Traditional
Data Memory
0x0FFF 0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
Reserved
0x7FFF
FSR
0x8000 0x0000
Address
Range
Program
Flash Memory
0xFFFF 0x7FFF
Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.
Rev. 10-000056A
7/31/2013
From Opcode
4 BSR 0 6 0 7 FSRxH 0 7 FSRxL 0
0 0 0 0
0x7F
Bank 0 Bank 1 Bank 2 Bank 31
Program
Flash
Memory
(low 8
bits)
0xFFFF 0x7FFF
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is n = Value when blank or after Bulk Erase
set
bit 7 bit 0
Legend:
‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase
Legend:
R = Readable bit P = Programmable bit x = Bit is unknown U = Unimplemented bit, read
as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set W = Writable bit n = Value when blank or after
Bulk Erase
WDTWS at POR
Software Keyed
WDTCWS Window control of access
Window delay
Value opening WDTWS? required?
Percent of time
Percent of time
111 111 n/a 100 Yes No
110 111 n/a 100
101 101 25 75
100 100 37.5 62.5
011 011 50 50 No Yes
010 010 62.5 37.5
001 001 75 25
000 000 87.5 12.5
WDTPS at POR
Software control
WDTCPS Typical time out
Value Divider Ratio of WDTPS?
(FIN = 31 kHz)
11110 11110
... ... 1:32 25 1 ms No
10011 10011
10010 10010 1:8388608 223 256 s
22
10001 10001 1:4194304 2 128 s
10000 10000 1:2097152 221 64 s
20
01111 01111 1:1048576 2 32 s
01110 01110 1:524299 219 16 s
01101 01101 1:262144 218 8s
01100 01100 1:131072 217 4s
16
01011 01011 1:65536 2 2s
01010 01010 1:32768 215 1s
14
01001 01001 1:16384 2 512 ms No
01000 01000 1:8192 213 256 ms
00111 00111 1:4096 212 128 ms
00110 00110 1:2048 211 64 ms
00101 00101 1:1024 210 32 ms
00100 00100 1:512 29 16 ms
8
00011 00011 1:256 2 8 ms
00010 00010 1:128 27 4 ms
00001 00001 1:64 26 2 ms
00000 00000 1:32 25 1 ms
Legend:
R = Readable bit P = Programmable bit x = Bit is U = Unimplemented bit, read as ‘1’
unknown
‘0’ = Bit is cleared ‘1’ = Bit is set W = Writable bit n = Value when blank or after Bulk Erase
Legend:
R = Readable bit P = Programmable bit x = Bit is unknown U = Unimplemented bit, read
as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set W = Writable bit n = Value when blank or after
Bulk Erase
4.5 User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4.7 “NVMREG Data EEPROM Memory,
User ID, Device ID and Configuration Word
Access” for more information on accessing these
memory locations. For more information on checksum
calculation, see the “PIC16(L)F188XX Memory
Programming Specification” (DS40001753).
R R R R R R R R
DEV<7:0>
bit 7 bit 0
Legend:
R = Readable bit
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit
‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown
Stack Underflow
Stack Overflow
WDT
Time-out WDT Device
Window Reset
Violation
Power-on
Reset
VDD BOR Active(1)
R
Brown-out Power-up
Reset Timer
LFINTOSC PWRTE
LPBOR
Reset
VDD
VBOR
Internal
Reset TPWRT(1)
VDD
VBOR
VDD
VBOR
Internal
Reset TPWRT(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
CLKIN
FOSC
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
PIC16(L)F18854
Rev. 10-000208J
12/13/2016
CLKIN
External
Oscillator
(EXTOSC)
CLKOUT
CDIV<4:0>
4x PLL Mode
COSC<2:0>
SOSCIN/SOSCI
HFFRQ<2:0>
1 – 32 MHz
MFINTOSC FSCM
Oscillator
To Peripherals
To Peripherals
500 kHz
To Peripherals
DS40001826C-page 92
31.25 kHz
To Peripherals
To Peripherals
PIC16(L)F18854
6.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up
External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully
clock source to function. Examples are: oscillator static, stopping the external clock input will have the
modules (ECH, ECM, ECL mode), quartz crystal effect of halting the device while leaving all data intact.
resonators or ceramic resonators (LP, XT and HS Upon restarting the external clock, the device will
modes). resume operation as if no time had elapsed.
Internal clock sources are contained within the
oscillator module. The internal oscillator block has two FIGURE 6-2: EXTERNAL CLOCK (EC)
internal oscillators and a dedicated Phase Lock Loop MODE OPERATION
(PLL) that are used to generate internal system clock
sources. The High-Frequency Internal Oscillator OSC1/CLKIN
Clock from
(HFINTOSC) can produce a range from 1 to 32 MHz. Ext. System
The Low-Frequency Internal Oscillator (LFINTOSC) PIC® MCU
generates a 31 kHz frequency. The external oscillator
block can also be used with the PLL. See OSC2/CLKOUT
FOSC/4 or I/O(1)
Section 6.2.1.4 “4x PLL” for more details.
The system clock can be selected between external or
Note 1: Output depends upon CLKOUTEN bit of the
internal clock sources via the NOSC bits in the Configuration Words.
OSCCON1 register. See Section 6.3 “Clock
Switching” for additional information.
6.2.1.2 LP, XT, HS Modes
6.2.1 EXTERNAL CLOCK SOURCES
The LP, XT and HS modes support the use of quartz
An external clock source can be used as the device crystal resonators or ceramic resonators connected to
system clock by performing one of the following OSC1 and OSC2 (Figure 6-3). The three modes select
actions: a low, medium or high gain setting of the internal
• Program the RSTOSC<2:0> bits in the inverter-amplifier to support various resonator types
Configuration Words to select an external clock and speed.
source that will be used as the default system LP Oscillator mode selects the lowest gain setting of the
clock upon a device Reset internal inverter-amplifier. LP mode current consumption
• Write the NOSC<2:0> and NDIV<4:0> bits in the is the least of the three modes. This mode is designed to
OSCCON1 register to switch the system clock drive only 32.768 kHz tuning-fork type crystals (watch
source crystals).
See Section 6.3 “Clock Switching”for more XT Oscillator mode selects the intermediate gain
information. setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
6.2.1.1 EC Mode This mode is best suited to drive resonators with a
The External Clock (EC) mode allows an externally medium drive level specification.
generated logic level signal to be the system clock HS Oscillator mode selects the highest gain setting of the
source. When operating in this mode, an external clock internal inverter-amplifier. HS mode current consumption
source is connected to the OSC1 input. is the highest of the three modes. This mode is best
OSC2/CLKOUT is available for general purpose I/O or suited for resonators that require a high drive setting.
CLKOUT. Figure 6-2 shows the pin connections for EC Figure 6-3 and Figure 6-4 show typical circuits for
mode. quartz crystal and ceramic resonators, respectively.
EC mode has three power modes to select from through
Configuration Words:
• ECH – High power, 4-32 MHz
• ECM – Medium power, 0.1-4 MHz
• ECL – Low power, 0-0.1 MHz
OSC1/CLKIN OSC1/CLKIN
C1 To Internal C1 To Internal
Logic Logic
Quartz
RF(2) Sleep RP(3)
Crystal RF(2) Sleep
OSC2/CLKOUT
C2 RS(1) OSC2/CLKOUT
C2 Ceramic RS(1)
Resonator
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M. 2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator
according to type, package and operation.
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application. 6.2.1.3 Oscillator Start-up Timer (OST)
2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS
the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts
expected for the application. 1024 oscillations from OSC1. This occurs following a
3: For oscillator design assistance, reference Power-on Reset (POR), or a wake-up from Sleep. The
the following Microchip Application Notes: OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
• AN826, “Crystal Oscillator Basics and is providing a stable system clock to the oscillator
Crystal Selection for rfPIC® and PIC® module.
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
PIC® MCU
SOSCI
C1 To Internal
Logic
32.768 kHz
Quartz
Crystal
C2 SOSCO
OSC #1 OSC #2
ORDY
NOTE 2
NOSCR
NOTE 1
CSWIF
USER
CSWHOLD CLEAR
Note 1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.
2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.
OSC #1 OSC #2
ORDY
NOSCR
NOTE 1
CSWIF
USER
CSWHOLD CLEAR
Note 1: CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.
OSC #1
ORDY NOTE 2
NOSCR
NOTE 1
CSWIF
CSWHOLD
Note 1: CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared.
2: ORDY = 0 if OSCCON1 does not match OSCCON2; a new switch will begin.
LFINTOSC
÷ 64 R Q
Oscillator
31 kHz 488 Hz
(~32 s) (~2 ms)
Sample Clock
System Oscillator
Clock Failure
Output
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared f = determined by fuse setting
Note 1: The default value (f/f) is set equal to the RSTOSC Configuration bits.
2: If NOSC is written with a reserved value (Table 6-1), the operation is ignored and neither NOSC nor NDIV
is written.
3: When CSWEN = 0, this register is read-only and cannot be changed from the POR value.
4: When NOSC = 110 (HFINTOSC 4 MHz), the NDIV bits will default to ‘0010’ upon Reset; for all other
NOSC settings the NDIV bits will default to ‘0000’ upon Reset.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The POR value is the value present when user code execution begins.
2: The reset value (n/n) is the same as the NOSC/NDIV bits.
TABLE 6-1: NOSC/COSC BIT SETTINGS TABLE 6-2: NDIV/CDIV BIT SETTINGS
NOSC<2:0>/ NDIV<3:0>/
Clock Source Clock divider
COSC<2:0> CDIV<3:0>
111 EXTOSC(1) 1111-1010 Reserved
110 HFINTOSC(2) 1001 512
101 LFINTOSC 1000 256
100 SOSC 0111 128
011 Reserved (it operates like 0110 64
NOSC = 110) 0101 32
010 EXTOSC with 4x PLL(1) 0100 16
001 HFINTOSC with 2x PLL(1) 0011 8
000 Reserved (it operates like 0010 4
NOSC = 110)
0001 2
Note 1: EXTOSC configured by the FEXTOSC bits of
Configuration Word 1 (Register 4-1). 0000 1
2: HFINTOSC settings are configured with the
HFFRQ bits of the OSCFRQ register
(Register 6-6).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
TMR0IF Wake-up
TMR0IE (If in Sleep mode)
INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF
(TMR1IE) PIE1<0> Interrupt
IOCIE to CPU
PEIE
PIRn<7>
GIE
PIEn<7>
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF (5) Interrupt Latency (2)
GIE
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Note 1: The External Interrupt GPIO pin is selected by INTPPS (Register 13-1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers
PIE1-PIE8.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS= Hardware Set
Note 1: The External Interrupt GPIO pin is selected by INTPPS (Register 13-1).
2: The IOCIF bits are the logical OR of all the IOCAF-IOCEF flags. Therefore, to clear the IOCIF flag,
application firmware should clear all of the lower level IOCAF-IOCEF register bits.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware clearable
Note 1: The RCIF flag is a read-only bit. To clear the RCIF flag, the firmware must read from RCREG enough
times to remove all bytes from the receive buffer.
2: The TXIF flag is a read-only bit, indicating if there is room in the transmit buffer. To clear the TXIF flag, the
firmware must write enough data to TXREG to completely fill all available bytes in the buffer. The TXIF flag
does not indicate transmit completion (use TRMT for this purpose instead).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set
1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
/ŶƐƚƌƵĐƚŝŽŶ
WĞƌŝŽĚ 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4 4
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
CPU Clock
Interrupt
Here
(ROI = 1)
Note 1: Multi-cycle instructions are executed to completion before fetching 0004h.
2: If the pre-fetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed.
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)
8.2.3 LOW-POWER SLEEP MODE 8.2.3.1 Sleep Current vs. Wake-up Time
The PIC16F18854 device contains an internal Low In the default operating mode, the LDO and reference
Dropout (LDO) voltage regulator, which allows the circuitry remain in the normal configuration while in
device I/O pins to operate at voltages up to 5.5V while Sleep. The device is able to exit Sleep mode quickly
the internal device logic operates at a lower voltage. since all circuits remain active. In Low-Power Sleep
The LDO and its associated reference circuitry must mode, when waking-up from Sleep, an extra delay time
remain active when the device is in Sleep mode. is required for these circuits to return to the normal
The PIC16F18854 allows the user to optimize the configuration and stabilize.
operating current in Sleep, depending on the The Low-Power Sleep mode is beneficial for
application requirements. applications that stay in Sleep mode for long periods of
time. The Normal mode is beneficial for applications
Low-Power Sleep mode can be selected by setting the
that need to wake from Sleep quickly and frequently.
VREGPM bit of the VREGCON register. Depending on
the configuration of these bits, the LDO and reference
circuitry are placed in a low-power state when the
device is in Sleep.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.
2: Entering ICD overrides DOZEN, returning the CPU to full execution speed; this bit is not affected.
WWDT
Armed
WDT
Window
Violation
Window Closed
Window
Comparator
CLRWDT Sizes
WDTWS
RESET
Reserved 111
Reserved 110
Reserved 101
R
Reserved 100 18-bit Prescale
Reserved 011 Counter
E
Reserved 010
MFINTOSC/16 001
LFINTOSC 000
WDTCS
WDTPS
R
5-bit Overflow
WDT Time-out
WDT Counter Latch
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
WDTE<1:0> = 10
Sleep
WDT protection is unchanged by Sleep. See Table 9-1 9.5.1 CLRWDT CONSIDERATIONS
for more details. (WINDOWED MODE)
TABLE 9-1: WDT OPERATING MODES When in Windowed mode, the WDT must be armed
before a CLRWDT instruction will clear the timer. This is
Device WDT performed by reading the WDTCON0 register. Execut-
WDTE<1:0> SEN
Mode Mode ing a CLRWDT instruction without performing such an
arming action will trigger a window violation.
11 X X Active
See Table 9-2 for more information.
Awake Active
10 X
Sleep Disabled 9.6 Operation During Sleep
1 X Active When the device enters Sleep, the WDT is cleared. If
01 the WDT is enabled during Sleep, the WDT resumes
0 X Disabled
counting. When the device exits Sleep, the WDT is
00 X X Disabled cleared again.
The WDT remains clear until the OST, if enabled, com-
9.3 Time-Out Period pletes. See Section 6.0 “Oscillator Module (with Fail-
Safe Clock Monitor)” for more information on the OST.
The WDTPS bits of the WDTCON0 register set the
time-out period from 1 ms to 256 seconds (nominal). When a WDT time-out occurs while the device is in
After a Reset, the default time-out period is two Sleep, no Reset is generated. Instead, the device
seconds. wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. The RWDT bit in the PCON register can also be
used. See Section 3.0 “Memory Organization” for
more information.
Rev. 10-000163A
8/15/2016
CLRWDT Instruction
(or other WDT Reset)
Window Period
Time-out Event
Window Delay
(window violation can occur)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Note 1: If WDTCCS <2:0> in CONFIG3 = 111, the Reset value of WDTCS<2:0> is 000.
2: The Reset value of WINDOW<2:0> is determined by the value of WDTCWS<2:0> in the CONFIG3 register.
3: If WDTCCS<2:0> in CONFIG3 ≠ 111, these bits are read-only.
4: If WDTCWS<2:0> in CONFIG3 ≠ 111, these bits are read-only.
REGISTER 9-3: WDTPSL: WDT PRESCALE SELECT LOW BYTE REGISTER (READ-ONLY)
R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
PSCNT<7:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR
registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation.
REGISTER 9-4: WDTPSH: WDT PRESCALE SELECT HIGH BYTE REGISTER (READ-ONLY)
R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
PSCNT<15:8>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR
registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR
registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation.
Start
Read Operation
Select Memory:
PFM, EEPROM, Config Words, User
ID (NVMREGS)
Select
Word Address
(NVMADRH:NVMADRL)
End
Read Operation
Note 1: Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order shown.
2: Opcodes shown are illustrative; any instruction that has the indicated effect may be used.
BANKSEL NVMADRL
MOVF ADDRL,W
MOVWF NVMADRL ; Load lower 8 bits of erase address boundary
MOVF ADDRH,W
MOVWF NVMADRH ; Load upper 6 bits of erase address boundary
BCF NVMCON1,NVMREGS ; Choose PFM memory area
BSF NVMCON1,FREE ; Specify an erase operation
BSF NVMCON1,WREN ; Enable writes
BCF INTCON,GIE ; Disable interrupts during unlock sequence
; -------------------------------REQUIRED UNLOCK SEQUENCE:------------------------------
NVMREGS FSR
Memory ICSP™ Memory NVMADR Allowed FSR
bit Programming
Function Address Type <15:0> Operations Address
(NVMCON1) Address
Reset Vector 0000h 0 8000h 8000h
User Memory 0001h 0 8001h 8001h
0003h 8003h Read 8003h
PFM Read-Only
INT Vector 0004h 0 8004h Write 8004h
User Memory 0005h 0 8005h 8005h
07FFh 87FFh 87FFh
User ID 8000h PFM 1 8000h Read
8003h 8003h Write
Reserved 8004h — — 8004h —
Rev ID 8005h 1 8005h Read
Device ID 8006h 1 8006h Write
CONFIG1 8007h 1 8007h No Access
PFM
CONFIG2 8008h 1 8008h
CONFIG3 8009h 1 8009h Read-Only
CONFIG4 800Ah 1 800Ah
CONFIG5 800Bh 1 800Bh
User Memory F000h EEPROM 1 F000h Read 7000h Read-Only
F0FFh F0FFh Write 70FFh
PIC16(L)F18854
Rev. 10-000004E
7 6 0 7 4 3 0 7 5 0 7 0 8/14/2015
14
Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31
00h 01h 1Eh 1Fh
NVMADRL<3:0>
14 14 14 14
800h 8000h - 8003h 8004h 8005h 8006h 8007h – 800Bh 800Ch - 801Fh
MASK/ DEVICE ID Configuration
USER ID 0 - 3 reserved reserved
NVMREGS = 1 REV ID Words
Configuration Memory
PIC16(L)F18854
FIGURE 10-5: PROGRAM FLASH MEMORY (PFM) WRITE FLOWCHART
Rev. 10-000049C
8/24/2015
Start
Write Operation
Determine number of
words to be written into Load the value to write
PFM. The number of TABLAT
words cannot exceed the
number of words per row
(word_cnt)
Disable Interrupts
Select Write Operation (GIE = 0)
(FREE = 0)
CPU stalls while Write
operation completes
(2 ms typical)
Unlock Sequence
Load Write Latches Only (See note 1)
Enable Write/Erase
Operation (WREN = 1) No delay when writing to Re-enable Interrupts
PFM Latches (GIE = 1)
Disable Write/Erase
Operation (WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Write Operation
Increment Address
TBLPTR++
BANKSEL NVMADRH
MOVF ADDRH,W
MOVWF NVMADRH ; Load initial address
MOVF ADDRL,W
MOVWF NVMADRL
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L
MOVLW HIGH DATA_ADDR
MOVWF FSR0H
BCF NVMCON1,NVMREGS ; Set Program Flash Memory as write location
BSF NVMCON1,WREN ; Enable writes
BSF NVMCON1,LWLO ; Load only write latches
LOOP
MOVIW FSR0++
MOVWF NVMDATL ; Load first data byte
MOVIW FSR0++
MOVWF NVMDATH ; Load second data byte
MOVF NVMADRL,W
XORLW 0x1F ; Check if lower bits of address are 00000
ANDLW 0x1F ; and if on last of 32 addresses
BTFSC STATUS,Z ; Last of 32 words?
GOTO START_WRITE ; If so, go write latches into memory
CALL UNLOCK_SEQ ; If not, go load latch
INCF NVMADRL,F ; Increment address
GOTO LOOP
START_WRITE
BCF NVMCON1,LWLO ; Latch writes complete, now write memory
CALL UNLOCK_SEQ ; Perform required unlock sequence
BCF NVMCON1,WREN ; Disable writes
UNLOCK_SEQ
MOVLW 55h
BCF INTCON,GIE ; Disable interrupts
MOVWF NVMCON2 ; Begin unlock sequence
MOVLW AAh
MOVWF NVMCON2
BSF NVMCON1,WR
BSF INTCON,GIE ; Unlock sequence complete, re-enable interrupts
return
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(See Note 2)
Write Operation
Use RAM image
(See Note 3)
End
Modify Operation
Read Operation
(See Note 1)
PMDAT = No
RAM image ?
Yes
Fail
Verify Operation
No
Last word ?
Yes
End
Verify Operation
TABLE 10-3: EEPROM, USER ID, DEV/REV ID AND CONFIGURATION WORD ACCESS
(NVMREGS = 1)
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8005h-8006h Device ID/Revision ID Yes No
8007h-800Bh Configuration Words 1-5 Yes No
F000h-F0FFh EEPROM Yes Yes
BANKSEL NVMADRH
MOVF ADDRH,W
MOVWF NVMADRH ; Load initial address
MOVF ADDRL,W
MOVWF NVMADRL
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L
MOVLW HIGH DATA_ADDR
MOVWF FSR0H
BCF NVMCON1,NVMREGS ; Set PFM as write location
BSF NVMCON1,WREN ; Enable writes
BSF NVMCON1,LWLO ; Load only write latches
LOOP
MOVIW FSR0++
MOVWF NVMDATL ; Load first data byte
MOVIW FSR0++
MOVWF NVMDATH ; Load second data byte
MOVF NVMADRL,W
XORLW 0x1F ; Check if lower bits of address are 00000
ANDLW 0x1F ; and if on last of 32 addresses
BTFSC STATUS,Z ; Last of 32 words?
GOTO START_WRITE ; If so, go write latches into memory
CALL UNLOCK_SEQ ; If not, go load latch
INCF NVMADRL,F ; Increment address
GOTO LOOP
START_WRITE
BCF NVMCON1,LWLO ; Latch writes complete, now write memory
CALL UNLOCK_SEQ ; Perform required unlock sequence
BCF NVMCON1,WREN ; Disable writes
UNLOCK_SEQ
MOVLW 55h
BCF INTCON,GIE ; Disable interrupts
MOVWF NVMCON2 ; Begin unlock sequence
MOVLW AAh
MOVWF NVMCON2
BSF NVMCON1,WR
BSF INTCON,GIE ; Unlock sequence complete, re-enable interrupts
return
Start
Verify Operation
Read Operation
(Figure10-1
Figure x.x)
NVMDAT = No
RAM image
?
Yes Fail
Verify Operation
No Last
Word ?
Yes
End
Verify Operation
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 NVMDAT<7:0>: Read/write value for Least Significant bits of program memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 NVMADR<7:0>: Specifies the Least Significant bits for program memory address
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Bit is undefined while WR = 1 (during the EEPROM write operation it may be ‘0’ or ‘1’).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Note 1: Bit is undefined while WR = 1 (during the EEPROM write operation it may be ‘0’ or ‘1’).
2: Bit must be cleared by software; hardware will not clear this bit.
3: Bit may be written to ‘1’ by software in order to implement test sequences.
4: This bit can only be set by following the unlock sequence of Section 10.4.2 “NVM Unlock Sequence”.
5: Operations are self-timed, and the WR bit is cleared by hardware when complete.
6: Once a write operation is initiated, setting this bit to zero will have no effect.
7: Reading from EEPROM loads only NVMDATL<7:0> (Register 10-1).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Rev. 10-000207A
Linear Feedback Shift Register for CRC-16-ANSI 5/27/2014
x16 + x15 + x2 + 1
Data in
Augmentation Mode ON
Data in
Augmentation Mode OFF
Operation of the WDT is not affected by scanner The ICD interaction with each operating mode is
activity. Hence, it is possible that long scans, summarized in Table 11-3.
particularly in Burst mode, may exceed the WDT time-
out period and result in an undesired device Reset.
This should be considered when performing memory
scans with an application that also utilizes WDT.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Note 1: Setting EN = 0 (SCANCON0 register) does not affect any other register content.
2: This bit is cleared when LADR > HADR (and a data cycle is not occurring).
3: If INTM = 1, this bit is overridden (to zero, but not cleared) during an interrupt response.
4: BUSY = 1 when the NVM is being accessed, or when the CRC sends a ready signal.
5: See Table 11-1 for more detailed information.
6: An invalid address happens when the entire range of the PFM is scanned and completed, i.e., device
memory is 0x4000 and SCANHADR = 0x3FFF, after the last scan SCANLADR increments to 0x4000, the
address is invalid.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
HADR<15:8>(1,2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
PORTB
PORTC
PORTD
PORTA
PORTE
Device FIGURE 12-1: GENERIC I/O PORT
OPERATION
PIC16(L)F18854 ● ● ● ●
Each port has ten standard registers for its operation.
These registers are: Read LATx
TRISx
• PORTx registers (reads the levels on the pins of
the device) D Q
• LATx registers (output latch) Write LATx
Write PORTx
• TRISx registers (data direction) CK VDD
• ANSELx registers (analog select)
Data Register
• WPUx registers (weak pull-up)
• INLVLx (input level control) Data Bus
BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
BANKSEL LATA ;Data Latch
CLRF LATA ;
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW B'00111000' ;Set RA<5:3> as inputs
MOVWF TRISA ;and set RA<2:0> as
;outputs
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ANSA<7:0>: Analog Select between Analog or Digital Function on pins RA<7:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The weak pull-up device is automatically disabled if the pin is configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
BANKSEL LATA ;Data Latch
CLRF LATA ;
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW B'00111000' ;Set RA<5:3> as inputs
MOVWF TRISA ;and set RA<2:0> as
;outputs
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ANSB<7:0>: Analog Select between Analog or Digital Function on pins RB<7:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The weak pull-up device is automatically disabled if the pin is configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ANSC<7:0>: Analog Select between Analog or Digital Function on Pins RC<7:0>, respectively(1)
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The weak pull-up device is automatically disabled if the pin is configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The weak pull-up device is automatically disabled if the pin is configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
abcPPS RA0
RA0
Peripheral abc
RxyPPS
Rxy
Peripheral xyz
RE2(1) R E2PPS(1)
xyzPPS RE2(1)
Note 1: RD<7:0> and RE<2:0> are only implemented on the 40/44-pin devices.
RE3 is PPS input capable only (when MLCR is disabled).
ADGRDG 0x25
ADGRDA 0x24
CWG3D 0x23
CWG3C 0x22
CWG3B 0x21
CWG3A 0x20
CWG2D 0x1F
CWG2C 0x1E
CWG2B 0x1D
CWG2A 0x1C
DSM 0x1B
CLKR 0x1A
NCO 0x19
TMR0 0x18
SDO2/SDA2 0x17
SCK2/SCL2 0x16
SD01/SDA1 0x15
SCK1/SCL1 0x14
C2OUT 0x13
C1OUT 0x12
DT 0x11
TX/CK 0x10
PWM7OUT 0x0F
PWM6OUT 0x0E
CCP5 0x0D
CCP4 0x0C
CCP3 0x0B
CCP2 0x0A
CCP1 0x09
CWG1D 0x08
CWG1C 0x07
CWG1B 0x06
CWG1A 0x05
CLC4OUT 0x04
CLC3OUT 0x03
CLC2OUT 0x02
CLC1OUT 0x01
Note: When RxyPPS = 0x00, port pin Rxy output value is controlled by the respective LATxy bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral
Note 1: The “xxx” in the register name “xxxPPS” represents the input signal function name, such as “INT”,
“T0CKI”, “RX”, etc. This register summary shown here is only a prototype of the array of actual registers,
as each input function has its own dedicated SFR (ex: INTPPS, T0CKIPPS, RXPPS, etc.).
2: Each specific input signal may only be mapped to a subset of these I/O pins, as shown in Table 13-2.
Attempting to map an input signal to a non-supported I/O pin will result in undefined behavior. For
example, the “INT” signal map be mapped to any PORTA or PORTB pin. Therefore, the INTPPS register
may be written with values from 0x00-0x0F (corresponding to RA0-RB7). Attempting to write 0x10 or
higher to the INTPPS register is not supported and will result in undefined behavior.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Note 1: When enabling NVM, a delay of up to 1 µs may be required before accessing data.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
15.1 Enabling the Module In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
To allow individual pins to generate an interrupt, the changed bits should be performed. The following
IOCIE bit of the PIE0 register must be set. If the IOCIE sequence is an example of what should be performed.
bit is disabled, the edge detection on the pin will still
occur, but an interrupt will not be generated. EXAMPLE 15-1: CLEARING INTERRUPT
FLAGS
15.2 Individual Pin Configuration (PORTA EXAMPLE)
For each pin, a rising edge detector and a falling edge MOVLW 0xff
detector are present. To enable a pin to detect a rising XORWF IOCAF, W
edge, the associated bit of the IOCxP register is set. To ANDWF IOCAF, F
enable a pin to detect a falling edge, the associated bit
of the IOCxN register is set.
15.5 Operation in Sleep
A pin can be configured to detect rising and falling
edges simultaneously by setting the associated bits in The interrupt-on-change interrupt sequence will wake
both of the IOCxP and IOCxN registers. the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the affected
IOCxF register will be updated prior to the first instruction
executed out of Sleep.
IOCANx D Q
R Q4Q1
edge
detect
RAx
to data bus
data bus = S
IOCAFx
IOCAPx D Q
0 or 1
D Q
R
write IOCAFx
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
FOSC
Q1 Q1 Q1
Q2 Q2 Q2
Q3 Q3 Q3
Q4 Q4 Q4
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
2
ADFVR<1:0>
1x
FVR_buffer1
2x
4x (To ADC Module)
2
CDAFVR<1:0>
1x FVR_buffer2
2x (To Comparators
4x and DAC)
FVREN
+
_ FVRRDY
Note 1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
18.1 Comparator Overview Note: The black areas of the output of the
comparator represents the uncertainty
A single comparator is shown in Figure 18-1 along with due to input offsets and response time.
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparators available are shown in Table 18-1.
Rev. 10-000027K
11/20/2015
3 (1)
CxNCH<2:0> CxON
Interrupt CxINTP
Rising
Edge set bit
CxIN0- 000 CxIF
Interrupt CxINTN
CxIN1- 001
Falling
CxIN2- 010 CxON(1) Edge
CxOUT_sync to
peripherals
CxSYNC
CxIN0+ 000
TRIS bit
CxIN1+ 001 0
CxPCH<2:0> CxON(1)
2
Note 1: When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.
CPIN ILEAKAGE(1)
VA VT 0.6V
5 pF
Vss
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 185
ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 192
CMxCON0 ON OUT — POL — — HYS SYNC 240
CMxCON1 — — — — — — INTP INTN 241
CMOUT — — — — — — MC2OUT MC1OUT 243
CWG1AS1 — AS6E AS5E AS4E AS3E AS2E AS1E AS0E 271
CWG2AS1 AS6E AS5E AS4E AS3E AS2E AS1E AS0E 271
CWG3AS1 AS6E AS5E AS4E AS3E AS2E AS1E AS0E 271
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 230
DAC1CON0 DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> — DAC1NSS 349
DAC1CON1 — — — DAC1R<4:0> 349
INTCON GIE PEIE — 115
PIE2 — ZCDIE — — — — C2IE C1IE 118
PIR2 — ZCDIF — — — — C2IF C1IF 127
RxyPPS ― ― RxyPPS<5:0> 211
CLCINxPPS — — — CLCIN0PPS<4:0> 210
MDSRCPPS ― ― ― MDSRCPPS<4:0> 210
T1GPPS ― ― ― T1GPPS<4:0> 210
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 184
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 191
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the Comparator module.
functionality.
(1)
TMRx = PWMxDC
Rev. 10-000022B
9/24/2014
PWMx_out
To Peripherals
10-bit Latch
(Not visible to user)
Comparator R Q
0
PPS PWMx
1
S Q
TMR2 Module
R PWMxPOL RxyPPS TRIS Control
TMR2 (1)
Comparator
T2_match
PR2
Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.
When TMR2 is equal to PR2, the following three events log 4 PR2 + 1
Resolution = ------------------------------------------ bits
occur on the next increment cycle: log 2
• TMR2 is cleared
• The PWMx pin is set (Exception: If the PWM duty
cycle = 0%, the pin will not be set.) Note: If the pulse width value is greater than the
• The PWM pulse width is latched from PWMxDC. period the assigned PWM pin(s) will
remain unchanged.
Note: If the pulse width value is greater than the
period the assigned PWM pin(s) will 19.1.6 OPERATION IN SLEEP MODE
remain unchanged. In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
19.1.4 PWM DUTY CYCLE PWMx pin is driving a value, it will continue to drive that
The PWM duty cycle is specified by writing a 10-bit value. When the device wakes up, TMR2 will continue
value to the PWMxDC register. The PWMxDCH from its previous state.
contains the eight MSbs and the PWMxDCL<7:6> bits
contain the two LSbs.
19.1.9 SETUP FOR PWM OPERATION • Route the signal to the desired pin by
configuring the RxyPPS register.
The following steps should be taken when configuring
the module for using the PWMx outputs: • Enable the PWMx module by setting the
PWMxEN bit of the PWMxCON register.
1. Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s). In order to send a complete duty cycle and period on
the first PWM output, the above steps must be followed
2. Configure the PWM output polarity by
in the order given. If it is not critical to start with a com-
configuring the PWMxPOL bit of the PWMxCON
plete PWM signal, then the PWM module can be
register.
enabled during Step 2 by setting the PWMxEN bit of
3. Load the PR2 register with the PWM period value, the PWMxCON register.
as determined by Equation 19-1.
4. Load the PWMxDCH register and bits <7:6> of
the PWMxDCL register with the PWM duty cycle
value, as determined by Equation 19-2.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the PIR1
register.
• Select the Timer2 prescale value by configuring
the T2CKPS<1:0> bits of the T2CON
register.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6. Wait until the TMR2IF is set.
7. When the TMR2IF flag bit is set:
• Clear the associated TRIS bit(s) to enable the
output driver.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
PIC16(L)F18854
Rev. 10-000166B
8/29/2014
CWG_data
D Q
CWGxISM<3:0>
E Q
R
Falling Deadband Block
clock CWG_dataB
signal_out
signal_in CWG_dataD
EN
SHUTDOWN
HFINTOSC 1
FOSC 0
CWGxCLK<0>
DS40001826C-page 252
PIC16(L)F18854
20.1.2 PUSH-PULL MODE
In Push-Pull mode, two output signals are generated,
alternating copies of the input as illustrated in
Figure 20-2. This alternation creates the push-pull
effect required for driving some transformer-based
power supply designs.
The push-pull sequencer is reset whenever EN = 0 or
if an auto-shutdown event occurs. The sequencer is
clocked by the first input pulse, and the first output
appears on CWGxA.
The unused outputs CWGxC and CWGxD drive copies
of CWGxA and CWGxB, respectively, but with polarity
controlled by the POLC and POLD bits of the
CWGxCON1 register, respectively.
PIC16(L)F18854
Rev. 10-000167B
8/29/2014
CWG_data
See
CWGxISM
Register D Q
CWG_dataA
Q CWG_dataC
R
CWG_dataB
D Q
CWG_dataD
CWGxISM<3:0>
E Q
R
EN
SHUTDOWN
DS40001826C-page 254
FIGURE 20-3: SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE MODES)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Rev. 10-000165B
8/29/2014
D Q CWG_dataB
D Q
Q CWG_dataC
CWGxISM<3:0>
E
R
Q CWG_dataD
clock
signal_out
signal_in
Forward Deadband Block
EN CWG_data
SHUTDOWN
HFINTOSC 1
FOSC 0
CWGxCLK<0>
DS40001826C-page 255
PIC16(L)F18854
20.1.4 STEERING MODES
In Steering modes, the data input can be steered to any
or all of the four CWG output pins. In Synchronous
Steering mode, changes to steering selection registers
take effect on the next rising input.
In Non-Synchronous mode, steering takes effect on the
next instruction cycle. Additional details are provided in
Section 20.9 “CWG Steering Mode”.
See
CWGxISM CWG_dataA
Register
CWG_dataB
CWG_data
CWG_dataC
CWG_dataD
D Q
CWGxISM <3:0>
E Q
R
EN
SHUTDOWN
Rev. 10-000171B
9/24/2014
LSAC<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataA High Z 01 PPS CWGxA
1 0
POLA 00
OVRA 0
STRA(1)
LSBD<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataB High Z 01 PPS CWGxB
1 0
POLB 00
OVRB 0
STRB(1)
LSAC<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataC High Z 01 PPS CWGxC
1 0
POLC 00
OVRC 0
STRC(1)
LSBD<1:0>
‘1’ 11 RxyPPS
TRIS Control
‘0’ 10
1
CWG_dataD High Z 01 PPS CWGxD
1 0
POLD 00
OVRD 0
STRD(1)
CWG_shutdown
Note 1: STRx is held to 1 in all modes other than Output Steering Mode.
PIC16(L)F18854
cwg_clock
Input Source
CWGxA
CWGxB
FIGURE 20-7: DEAD-BAND OPERATION, CWGXDBR = 0X03, CWGXDBF = 0X04, SOURCE SHORTER THAN DEAD BAND
cwg_clock
Input Source
CWGxA
CWGxB
Therefore:
1
TDEADBAND_UNCERTAINTY = -----------------------------
Fcwg_clock
1
= ------------------
16MHz
= 62.5ns
MODE0
CWGxA
CWGxB
CWGxC
CWGxD
Note 1:WGPOL{ABCD} = 0
2: The direction bit MODE<0> (Register 20-1) can be written any time during the PWM cycle, and takes effect at the
next rising CWGx_data.
3: When changing directions, CWGxA and CWGxC switch at rising CWGx_data; modulated CWGxB and CWGxD are
held inactive for the dead band duration shown; dead band affects only the first pulse after the direction change.
CWGx_clock
CWGxA
CWGxC
Rising Event Dead Band Rising Event D
Falling Event Dead Band Falling Event Dead Band
CWGxB
CWGxD
CWGx_data
Note: CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out
Rising Event
CWGx_data
(Rising and Falling Source)
STR<D:A>
follows CWGx_data
CWGx_data
(Rising and Falling Source)
STR<D:A>
follows CWGx_data
PIC16(L)F18854
Write ‘1’ to Rev. 10-000172B
1/21/2015
SHUTDOWN bit
PPS
INAS
CWGINPPS
C1OUT_sync
C1AS
C2OUT_sync
C2AS
TMR2_postscaled SHUTDOWN S
S Q
TMR2AS
D Q CWG_shutdown
TMR4_postscaled
REN FREEZE
R
TMR4AS Write ‘0’ to
SHUTDOWN bit
TMR6_postscaled CWG_data CK
TMR6AS
DS40001826C-page 264
PIC16(L)F18854
20.12 Configuring the CWG 20.12.2 AUTO-SHUTDOWN RESTART
The following steps illustrate how to properly configure After an auto-shutdown event has occurred, there are
the CWG. two ways to resume operation:
PIC16(L)F18854
Shutdown Event Ceases REN Cleared by Software
CWG Input
Source
Shutdown Source
SHUTDOWN
FIGURE 20-14: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01, LSBD = 01)
CWG Input
Source
Shutdown Source
SHUTDOWN
CWGxC
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Note 1: This bit can only be set after EN = 1 and cannot be set in the same instruction that EN is set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Note 1: This bit may be written while EN = 0 (CWGxCON0 register) to place the outputs into the shutdown config-
uration.
2: The outputs will remain in auto-shutdown state until the next rising edge of the input signal after this bit is
cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Note 1: The bits in this register apply only when MODE<2:0> = 00x.
2: This bit is effectively double-buffered when MODE<2:0> = 001.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
CWG1CLKCON — — — — — — — CS 273
CWG1ISM — — — — IS<3:0> 273
CWG1DBR — — DBR<5:0> 269
CWG1DBF — — DBF<5:0> 269
CWG1CON0 EN LD — — — MODE<2:0> 272
CWG1CON1 — — IN — POLD POLC POLB POLA 268
CWG1AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 270
CWG1AS1 — AS6E AS5E AS4E AS3E AS2E AS1E AS0E 271
CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 272
CWG2CLKCON — — — — — — — CS 273
CWG2ISM — — — — IS<3:0> 273
CWG2DBR — — DBR<5:0> 269
CWG2DBF — — DBF<5:0> 269
CWG2CON0 EN LD — — — MODE<2:0> 272
CWG2CON1 — — IN — POLD POLC POLB POLA 268
CWG2AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 270
CWG2AS1 — AS6E AS5E AS4E AS3E AS2E AS1E AS0E 271
CWG2STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 272
CWG3CLKCON — — — — — — — CS 273
CWG3ISM — — — — IS<3:0> 273
CWG3DBR — — DBR<5:0> 269
CWG3DBF — — DBF<5:0> 269
CWG3CON0 EN LD — — — MODE<2:0> 272
CWG3CON1 — — IN — POLD POLC POLB POLA 268
CWG3AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> — — 270
CWG3AS1 — AS6E AS5E AS4E AS3E AS2E AS1E AS0E 271
CWG3STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 272
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by CWG.
VCPINV
optional
VDD RPULLUP
- ZCDxIN RSERIES
External
Zcpinv + RPULLDOWN voltage
source
optional
ZCDx_output
D Q OUT bit
POL
Q1
Interrupt
det
INTP Set
ZCDIF
INTN flag
Interrupt
det
asin ------------------
Vcpinv
2 2
R = Z – XC V PEAK
T OFFSET = ----------------------------------
–4 2 Freq
V C = X C 3 10
When External Voltage Source is relative to VDD:
= Tan -------
–1 X C
R
asin --------------------------------
V DD – Vcpinv
T = ---------
2f V PEAK
T OFFSET = -------------------------------------------------
2 Freq
EXAMPLE 21-1: R-C CALCULATIONS
This offset time can be compensated for by adding a
VRMS = 120
pull-up or pull-down biasing resistor to the ZCD pin. A
VPEAK = VRMS *= 169.7
pull-up resistor is used when the external voltage
f = 60 Hz
source is varying relative to VSS. A pull-down resistor is
C = 0.1 µF used when the voltage is varying relative to VDD. The
V PEAK 169.7 resistor adds a bias to the ZCD pin so that the target
Z = -------------------
–4
- = 565.7k
- = -------------------
–4 external voltage source must go to zero to pull the pin
3 10 3 10 voltage to the VCPINV switching voltage. The pull-up or
pull-down value can be determined with the equations
1 1
- = 26.53k
X C = ------------- = -------------------------------------------------
–7
shown in Equation 21-4.
2fC 2 60 1 10
EQUATION 21-4: ZCD PULL-UP/DOWN
2 2
R = Z X C = 565.1k computed
V MAXPEAK + V MINPEAK
R SERIES = ---------------------------------------------------------
–4
7 10
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits
OUT
D Q
&LCxOUT
Q1
LCx_in[0]
LCx_in[1] LCx_out
to Peripherals
LCx_in[2]
Input Data Selection Gates(1)
. lcxg1
EN
CLCxPPS
. lcxg2
lcxg3
Logic
Function
(2)
lcxq
PPS CLCx
. lcxg4
POL TRIS
Data Selection
LCx_in[0] 00000
Data GATE 1
lcxd1T LCxD1G1T
lcxd1N LCxD1G1N
LCx_in[46] 11111
LCxD2G1T
LCxD1S<5:0>
LCxD2G1N lcxg1
LCx_in[0] 00000
LCxD3G1T
LCxG1POL
lcxd2T
LCxD3G1N
lcxd2N
LCxD4G1T
LCx_in[46] 11111
LCxD2S<5:0> LCxD4G1N
LCx_in[0] 00000
Data GATE 2
lcxg2
lcxd3T
(Same as Data GATE 1)
lcxd3N
Data GATE 3
LCx_in[46] 11111
lcxg3
LCxD3S<5:0>
(Same as Data GATE 1)
lcxd4N
LCx_in[46] 11111
LCxD4S<5:0>
AND-OR OR-XOR
lcxg1 lcxg1
lcxg2 lcxg2
lcxq lcxq
lcxg3 lcxg3
lcxg4 lcxg4
lcxg1 lcxg1
S Q lcxq
lcxg2
lcxg2
lcxq
lcxg3
lcxg3
R
lcxg4 lcxg4
lcxg1 R
lcxg1 R
lcxg3 lcxg3
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N 292
CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N 293
CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N 294
CLCDATA ― ― ― ― MLC4OUT MLC3OUT MLC2OUT MLC1OUT 295
CLCIN0PPS ― ― ― CLCIN0PPS<4:0> 210
CLCIN1PPS ― ― ― CLCIN1PPS<4:0> 210
CLCIN2PPS ― ― ― CLCIN2PPS<4:0> 210
CLCIN3PPS ― ― ― CLCIN3PPS<4:0> 210
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.
10
complete 10-bit Result
Write to bit
GO/DONE
GO/DONE Q1 16
start
Q4
ADRESH ADRESL
Q2 Enable
Trigger Select
TRIGSEL<3:0> ADON
. . . VSS
Trigger Sources
AUTO CONVERSION
TRIGGER
ADC
ADCCS<5:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Clock Source
FOSC/2 000000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
(2) (2) (2) (2)
FOSC/4 000001 125 ns 200 ns 250 ns 500 ns 1.0 s 4.0 s
FOSC/6 000010 187.5 ns(2) 300 ns(2) 375 ns(2) 750 ns(2) 1.5 s 6.0 s
FOSC/8 000011 250 s(2) 400 ns(2) 500 s(2) 1.0 s 2.0 s 8.0 s(3)
... ... ... ... ... ... ... ...
FOSC/16 000111 500 ns(2) 800 ns(2) 1.0 s 2.0 s 4.0 s 16.0 s(2)
... ... ... ... ... ... ... ...
(3) (2)
FOSC/128 111111 4.0 s 6.4 s 8.0 s 16.0 s 32.0 s 128.0 s(2)
(1) (1) (1) (1) (1)
FRC ADCS(ADCON0 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s(1)
<4>)=1
Legend: Shaded cells are outside of recommended range.
Note 1: See TAD parameter for FRC source typical TAD value.
2: These values violate the required TAD time.
3: Outside the recommended TAD time.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the
device in Sleep mode.
ADRESH ADRESL
(ADFRM0 = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C + Temperature - 25°C 0.05µs/°C
V AP P LI ED 1 – -------------------------- = V CHOLD
1
;[1] VCHOLD charged to within 1/2 lsb
n+1
2 –1
–TC
----------
RC
V AP P LI ED 1 – e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
– Tc
---------
V AP P LI ED 1 – e = V A PP LIE D 1 – -------------------------- ;combining [1] and [2]
RC 1
n+1
2 –1
T C = – C HOLD R IC + R SS + R S ln(1/2047)
= – 10pF 1k + 7k + 10k ln(0.0004885)
= 1.37 µs
Therefore:
T A CQ = 2µs + 892ns + 50°C- 25°C 0.05 µs/°C
= 4.62µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
VA CPIN I LEAKAGE(1)
VT 0.6V CHOLD = 10 pF
5 pF
Ref-
6V
5V RSS
Legend: CHOLD = Sample/Hold Capacitance VDD 4V
3V
CPIN = Input Capacitance 2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 10 11
RIC = Interconnect Resistance
Sampling Switch
RSS = Resistance of Sampling Switch (k)
SS = Sampling Switch
VT = Threshold Voltage
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB
REF- Zero-Scale
Transition Full-Scale
Transition REF+
VDD
ADPPOL = 1
ANx Pads
ADPPOL = 0
VGND
ADCAP<2:0>
Additional
Sample and
Hold Cap
VSS
First Sample Second Sample
Time
Voltage
External Capacitive Sensor
Guard Ring Output
VSS
First Sample Second Sample
Time
ADCALC<2:0>
ADTMOD<2:0>
ADRES
ADFILT
Set
Error Threshold
Interrupt
Average/ Calculation ADERR Logic
1 Flag
Filter ADPREV
0
ADSTPT
ADUTHR ADLTHR
ADPSIS
The operation of the ADC computational features is • Low-Pass Filter (LPF): With each trigger, the ADC
controlled by the ADMD <2:0> bits in the ADCON2 conversion result is sent through a filter. When ADRPT
register. samples have occurred, a threshold test is performed.
The module can be operated in one of five modes: Every trigger after that the ADC conversion result is
sent through the filter and another threshold test is
• Basic: This is a legacy mode. In this mode, ADC performed.
conversion occurs on single (ADDSEN=0) or double
(ADDSEN=1) samples. ADIF is set after each The five modes are summarized in Table 23-3 below.
conversion completes.
• Accumulate: With each trigger, the ADC conversion
result is added to accumulator and ADCNT increments.
ADIF is set after each conversion. ADTIF is set accord-
ing to the Calculation mode.
• Average: With each trigger, the ADC conversion
result is added to the accumulator. When the ADRPT
number of samples have been accumulated, a
threshold test is performed. Upon the next trigger, the
counter is reset to ‘1’ and the accumulator is replaced
with the first ADC conversion cleared. For the
subsequent threshold tests, additional ADRPT
samples are required to be accumulated.
• Burst Average: At the trigger, the accumulator and
counter are cleared. The ADC conversion results are
then collected repetitively until ADRPT samples are
accumulated and finally the threshold is tested.
PIC16(L)F18854
TABLE 23-3: COMPUTATION MODES
Clear Conditions Value after Trigger completion Threshold Operations Value at ADTIF interrupt
Mode ADMD ADACC and ADCNT ADACC ADCNT Retrigger Threshold Interrupt ADAOV ADFLTR ADCNT
Test
Basic 0 ADACLR = 1 Unchanged Unchanged No Every If thresh- N/A N/A count
Sample old=true
Accumulate 1 ADACLR = 1 S + ADACC If (ADCNT=FF): ADCNT, No Every If thresh- ADACC Overflow ADACC/2ADCRS count
or otherwise: ADCNT+1 Sample old=true
(S2-S1) + ADACC
Average 2 ADACLR = 1 or S + ADACC If (ADCNT>=ADRPT):1, No If If thresh- ADACC Overflow ADACC/2ADCRS count
ADCNT>=ADRPT at ADGO or otherwise: ADCNT+1 ADCNT>= old=true
or retrigger (S2-S1) + ADACC ADRPT
Burst 3 ADACLR = 1 or ADGO set or Each repetition: same as Reset and count up until Repeat while If If thresh- ADACC Overflow ADACC/2ADCRS ADRPT
Average retrigger Average ADCNT=ADRPT ADCNT<ADRPT ADCNT>= old=true
End with sum of all ADRPT
samples
Lowpass 4 ADACLR = 1 S+ADACC-ADACC/ If (ADCNT=FF): ADCNT, No If If thresh- ADACC Overflow Filtered Value count
Filter 2ADCRS otherwise: ADCNT+1 ADCNT>= old=true
or ADRPT
(S2-S1)+ADACC-ADACC/
2ADCRS
Note 1: S, S1, and S2 are abbreviations for ADRES, ADRES(n), and ADRES(n+1), respectively. When ADDSEN = 0: S = ADRES. When ADDSEN = 1:
S1 = ADPREV, and S2 = ADRES.
2: All results of divisions using the ADCRS bits are truncated, not rounded.
DS40001826C-page 314
PIC16(L)F18854
23.5.1 DIGITAL FILTER/AVERAGE The ADAOV (accumulator overflow) bit in the ADSTAT
register, ADACC, and ADCNT registers will be cleared
The digital filter/average module consists of an accu-
any time the ADACLR bit in the ADCON2 register is
mulator with data feedback options, and control logic to
set.
determine when threshold tests need to be applied.
The accumulator is a 16-bit wide signed register
(15 bits + 1 sign bit), which can be accessed through
Note: When ADC is operating from FRC, 5 FRC
the ADACCH:ADACCL register pair.
clock cycles are required to execute the
Upon each trigger event (the ADGO bit set or external ADACC clearing operation.
event trigger), the ADC conversion result is added to
the accumulator. If the value exceeds The ADCRS <2:0> bits in the ADCON2 register control
‘1111111111111111’, then the overflow bit ADAOV in the data shift on the accumulator result, which
the ADSTAT register is set. effectively divides the value in the accumulator
(ADACCH:ADACCL) register pair. For the Accumulate
The number of samples to be accumulated is mode of the digital filter, the shift provides a simple
determined by the ADRPT (A/D Repeat Setting) scaling operation. For the Average/Burst Average
register. Each time a sample is added to the mode, the shift bits are used to determine number of
accumulator, the ADCNT register is incremented. In samples for averaging. For the Lowpass Filter mode,
Average and Burst Average modes the ADCNT and the shift is an integral part of the filter, and determines
ADACC registers are cleared automatically when a the cut-off frequency of the filter. Table 23-4 shows the
trigger causes the ADCNT value to exceed the ADRPT -3 dB cut-off frequency in ωT (radians) and the highest
value to ‘1’ and replace the ADACC contents with the signal attenuation obtained by this filter at nyquist
conversion result. frequency (ωT = π).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Otherwise
The bit is ignored
bit 6 ADIPEN: A/D Inverted Precharge Enable bit
If ADDSEN = 1:
1 = The precharge and guard signals in the second conversion cycle are the opposite polarity of the
first cycle
0 = Both Conversion cycles use the precharge and guards specified by ADPPOL and ADGPOL
Otherwise:
The bit is ignored
bit 5 ADGPOL: Guard Ring Polarity Selection bit
1 = ADC guard ring outputs start as digital high during precharge stage
0 = ADC guard ring outputs start as digital low during precharge stage
bit 4-1 Unimplemented: Read as ‘0’
bit 0 ADDSEN: Double-Sample Enable bit
1 = See Table 23-5.
0 = One conversion is performed for each trigger
TABLE 23-5: EXAMPLE OF REGISTER VALUES FOR ACCUMULATE AND AVERAGE MODES
Trigger ADPREV
ADCONT Sample ADPSIS
ADRES ADACC
n
0 1 0 1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Note 1: When ADPSIS = 0, the value of (ADRES-ADPREV) is the value of (S2-S1) from Table 23-3.
2: When ADPSIS = 0
3: When ADPSIS = 1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: See Section 25.0 “5-Bit Digital-to-Analog Converter (DAC1) Module” for more information.
2: See Section 16.0 “Fixed Voltage Reference (FVR)” for more information.
3: See Section 17.0 “Temperature Indicator Module” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
Note 1: When FOSC is selected as the ADC clock (ADCS bit of ADCON0 = 0), both ADPRE and ADACQ are
calculated using undivided FOSC, regardless of the value of the ADCLK register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADFLTR<15:8>: ADC Filter Output Most Significant bits and Sign bit
In Accumulate, Average, and Burst Average mode, this is equal to ADACC right shifted by the ADCRS
bits of ADCON2. In LPF mode, this is the output of the Lowpass Filter.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 ADRES<1:0>: ADC Result Register bits. Least Significant two bits of 10-bit conversion result.
bit 5-0 Reserved: Do not use.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADRES<7:0>: ADC Result Register bits. Least Significant eight bits of 10-bit conversion result.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: If ADPSIS = 0, ADPREVH and ADPREVL are formatted the same way as ADRES is, depending on the
ADFRM bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADACC<15:8>: ADC Accumulator MSB. Most Significant seven bits of accumulator value and sign bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADACC<7:0>: ADC Accumulator LSB. Least Significant eight bits of accumulator value.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADSTPT<15:8>: ADC Threshold Setpoint MSB. Most Significant Byte of ADC threshold setpoint,
depending on ADCALC, may be used to determine ADERR, see Register 21-1 for more details.
\
REGISTER 23-25: ADSTPTL: ADC THRESHOLD SETPOINT REGISTER LOW
R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x
ADSTPT<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADSTPT<7:0>: ADC Threshold Setpoint LSB. Least Significant Byte of ADC threshold setpoint,
depending on ADCALC, may be used to determine ADERR, see Register 21-1 for more details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADERR<15:8>: ADC Calculation Error MSB. Most Significant Byte of ADC Calculation Error.
Calculation is determined by ADCALC bits of ADCON3, see Register 21-1 for more details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADERR<7:0>: ADC Calculation Error LSB. Least Significant Byte of ADC Calculation Error. Calcula-
tion is determined by ADCALC bits of ADCON3, see Register 21-1 for more details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADLTH<15:8>: ADC Lower Threshold MSB. ADLTH and ADUTH are compared with ADERR to set
the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be
triggered by the results of this comparison.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADLTH<7:0>: ADC Lower Threshold LSB. ADLTH and ADUTH are compared with ADERR to set the
ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be
triggered by the results of this comparison.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADUTH<15:8>: ADC Upper Threshold MSB. ADLTH and ADUTH are compared with ADERR to set
the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be
triggered by the results of this comparison.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 ADUTH<7:0>: ADC Upper Threshold LSB. ADLTH and ADUTH are compared with ADERR to set the
ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be
triggered by the results of this comparison.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
PIC16(L)F18854
NCOxINCU NCOxINCH NCOxINCL Rev. 10-000028C
2/2/2015
20
(1)
INCBUFU INCBUFH INCBUFL
20
20
reserved 111
reserved 110
NCO_overflow Adder
CLC4_out 101
20
CLC3_out 100 NCOx_clk
NCOxACCU NCOxACCH NCOxACCL
CLC2_out 011 20
CLC1_out 010
HFINTOSC 001 NCO_interrupt set bit
NCOxIF
FOSC 000 Fixed Duty
Cycle Mode
Circuitry
NxCKS<2:0> D Q D Q 0 TRIS bit
3
NCOxOUT
_ 1
Q
NxPFM NxPOL
NCOx_out
To Peripherals
EN S Q
_ D Q NxOUT
Ripple
R Q
Counter
Pulse Q1
DS40001826C-page 337
R Frequency
3 Mode Circuitry
NxPWS<2:0>
Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO module. The full increment value is loaded into the buffer registers on the
second rising edge of the NCOx_clk signal that occurs immediately after a write to NCOxINCL register. The buffers are not user-accessible and are shown here for reference.
PIC16(L)F18854
24.1 NCO OPERATION
The NCO operates by repeatedly adding a fixed value to
an accumulator. Additions occur at the input clock rate.
The accumulator will overflow with a carry periodically,
which is the raw NCO output (NCO_overflow). This
effectively reduces the input clock by the ratio of the
addition value to the maximum accumulator value. See
Equation 24-1.
The NCO output can be further modified by stretching
the pulse or toggling a flip-flop. The modified NCO
output is then distributed internally to other peripherals
and can be optionally output to a pin. The accumulator
overflow also generates an interrupt (NCO_overflow).
The NCO period changes in discrete steps to create an
average frequency. This output depends on the ability
of the receiving circuit (i.e., CWG or external resonant
converter circuitry) to average the NCO output to
reduce uncertainty.
PIC16(L)F18854
Rev. 10-000029A
11/7/2013
NCOx
Clock
Source
NCOx
Increment 4000h 4000h 4000h
Value
NCOx
Accumulator 00000h 04000h 08000h FC000h 00000h 04000h 08000h FC000h 00000h 04000h 08000h
Value
NCO_overflow
NCO_interrupt
NCOx Output
FDC Mode
NCOx Output
DS40001826C-page 340
PF Mode
NCOxPWS =
000
NCOx Output
PF Mode
NCOxPWS =
001
PIC16(L)F18854
24.8 NCO Control Registers
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The accumulator spans registers NCO1ACCU:NCO1ACCH: NCO1ACCL. The 24 bits are reserved but
not all are used.This register updates in real-time, asynchronously to the CPU; there is no provision to
guarantee atomic access to this 24-bit space using an 8-bit bus. Writing to this register while the module is
operating will produce undefined results.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 185
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 198
INTCON GIE PEIE ― ― ― ― ― INTEDG 115
PIR2 ― ZCDIF ― ― ― ― C2IF C1IF 127
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 197
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for NCO module.
V
SOURCE- = SS or V REF-
V
Rev. 10-000026G
12/15/2016
Reserved 11
VSOURCE+ DACR<4:0>
FVR Buffer 10 5
VREF+ 01 R
VDD 00
R
DACPSS
32-to-1 MUX
32 DACx_output
To Peripherals
Steps
DACEN
R
R DACxOUT1(1)
DACOE1
R
DACxOUT2(1)
DACNSS
Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s).
PIC® MCU
DAC
R
Module
+
Voltage DAC1OUT Buffered DAC Output
–
Reference
Output
Impedance
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
See
MDCARH CARH
Register
MDCHPOL D
1111 SYNC
Q
MDSRCS<4:0> 1
0
00000
RxyPPS
MDCHSYNC
See
MOD
MDSRC
PPS
Register
MDOPOL
11111
MDCLS<3:0>
D
SYNC
0000 Q
1
0
See
MDCARL CARL
Register MDCLSYNC
MDCLPOL
1111
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
MDCHSYNC = 1
MDCLSYNC = 1
MDCHSYNC = 0
MDCLSYNC = 0
MDCHSYNC = 0
MDCLSYNC = 1
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 0
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit, the bit value may not be valid for higher speed modulator or carrier signals.
2: MDBIT must be selected as the modulation source in the MDSRC register for this operation.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
Rev. 10-000017E
6/15/2016
Reserved 111
LC1_out 110
SOSC 101 T0CKPS<3:0> TMR0
LFINTOSC 100 body T0OUTPS<3:0> TMR0IF
Prescaler 1
HFINTOSC 011 IN OUT Postscaler TMR0_overflow
SYNC 0
FOSC/4 010
PPS 001 FOSC/4 T016BIT TMR0
T0ASYNC D Q PPS
000
T0CKIPPS CK Q RxyPPS
T0CS<2:0>
8-bit TMR0 Body Diagram (T016BIT = 0) 16-bit TMR0 Body Diagram (T016BIT = 1)
Read TMR0L
COMPARATOR OUT
Write TMR0L
8
8 TMR0H
TMR0 High
Byte
Latch 8
Enable
TMR0H
8
Internal Data Bus
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
TMR0L Holding Register for the Least Significant Byte of the 16-bit TMR0 Register 364*
TMR0H Holding Register for the Most Significant Byte of the 16-bit TMR0 Register 364*
T0CON0 T0EN ― T0OUT T016BIT T0OUTPS<3:0> 367
T0CON1 T0CS<2:0> T0ASYNC T0CKPS<3:0> 368
T0CKIPPS ― ― ― — T0CKIPPS<3:0> 210
TMR0PPS ― ― ― TMR0PPS<4:0> 210
ADACT ― ― ― ADACT<4:0> 320
CLCxSELy ― ― ― LCxDyS<4:0> 290
T1GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 380
INTCON GIE PEIE ― ― ― ― ― INTEDG 115
PIR0 ― ― TMR0IF IOCIF ― ― ― INTF 125
PIE0 ― ― TMR0IE IOCIE ― ― ― INTE 116
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page with Register information.
4
TxGPPS
TxGSPM
PPS 00000
1
0 Single Pulse D Q TxGVAL
NOTE (5) 0
11111
1 Acq. Control
Q1
D Q
TxGPOL TxGGO/DONE
CK Q
TMRxON Interrupt
set bit
R
TxGTM det TMRxGIF
TMRxGE
set flag bit
TMRxIF
TMRxON
EN
(2) To Comparators (6)
TMRx
Tx_overflow Synchronized Clock Input
TMRxH TMRxL Q D 0
1
TxCLK
TxSYNC
TMRxCLK<3:0>
4
TxCKIPPS
(1)
PPS 0000
Prescaler
Synchronize(3)
1,2,4,8
(4)
Note det
1111
2
Fosc/2
TxCKPS<1:0> Internal Sleep
Clock Input
Note 1: ST Buffer is high speed type when using TxCKIPPS.
2: TMRx register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: See Register 28-3 for Clock source selections.
5: See Register 28-4 for GATE source selections.
6: Synchronized comparator output should not be used in conjunction with synchronized input clock.
When used with an internal clock source, the module is When using an external clock source, the timer can be
a timer and increments on every instruction cycle. configured to run synchronously or asynchronously, as
When used with an external clock source, the module described in Section 28.6 “Timer Operation in
can be used as either a timer or counter and incre- Asynchronous Counter Mode”.
ments on every selected edge of the external source. When used as a timer with a clock oscillator, an
The timer is enabled by configuring the TMR1ON and external 32.768 kHz crystal can be used connected to
GE bits in the T1CON and T1GCON registers, respec- the SOSCI/SOSCO pins.
tively. Table 28-1 displays the Timer1 enable selec- Note: In Counter mode, a falling edge must be
tions. registered by the counter prior to the first
incrementing rising edge after any one or
TABLE 28-1: TIMER1 ENABLE more of the following conditions:
SELECTIONS • The timer is first enabled after POR
Timer1 • Firmware writes to TMR1H or TMR1L
TMR1ON TMR1GE • The timer is disabled
Operation
• The timer is re-enabled (e.g.,
1 1 Count Enabled
TMR1ON-->1) when the T1CKI sig-
1 0 Always On nal is currently logic low.
0 1 Off
0 0 Off 28.3 Timer Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
28.2 Clock Source Selection divisions of the clock input. The CKPS bits of the
The T1CLK register is used to select the clock source for T1CON register control the prescale counter. The
the timer. Register 28-3 shows the possible clock prescale counter is not directly readable or writable;
sources that may be selected to make the timer however, the prescaler counter is cleared upon a write to
increment. TMR1H or TMR1L.
TxCKI = 1
when the timer is
enabled
TxCKI = 0
when the timer is
enabled
TMRxGE
TxGPOL
selected
gate input
TxCKI
TxGVAL
TMRxGE
TxGPOL
TxGTM
selected
gate input
TxCKI
TxGVAL
TMRxGE
TxGPOL
TxGSPM
Cleared by hardware on
TxGGO/ Set by software falling edge of TxGVAL
DONE
Counting enabled on
rising edge of selected source
selected gate
source
TxCKI
TxGVAL
TMRxGE
TxGPOL
TxGSPM
TxGTM
Cleared by hardware on
TxGGO/ Set by software falling edge of TxGVAL
DONE Counting enabled on
rising edge of selected source
selected gate
source
TxCKI
TxGVAL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
INPPS
TxIN PPS MODE<4:0> MODE<3>
enable MODE<4:3>=01
Clear ON
MODE<4:1>=1011 D Q
CPOL
TMRx_clk Prescaler 0
R
T[7MR
Set flag bit
3 Sync 1 TMRxIF
4
ON Sync
(2 Clocks)
1
7[PR OUTPS<3:0>
0
CSYNC
Rev. 10-000205A
4/7/2016
CKPS 0b010
PRx 1
OUTPS 0b0001
TMRx_clk
TMRx 0 1 0 1 0 1 0
TMRx_postscaled
Note 1: Setting the interrupt flag is synchronized with the instruction clock.
Synchronization may take as many as 2 instruction cycles
2: Cleared by software.
29.5 Operation Examples the TMRx count equals the PRx period count the timer
resets on the next clock and continues counting from 0.
Unless otherwise specified, the following notes apply to Operation with the ON bit software controlled is illus-
the following timing diagrams: trated in Figure 29-4. With PRx = 5, the counter
- Both the prescaler and postscaler are set to advances until TMRx = 5, and goes to zero with the
1:1 (both the CKPS and OUTPS bits in the next clock.
TxCON register are cleared).
- The diagrams illustrate any clock except
Fosc/4 and show clock-sync delays of at
least two full cycles for both ON and
Timer2_ers. When using Fosc/4, the
clock-sync delay is at least one instruction
period for Timer2_ers; ON applies in the next
instruction period.
- The PWM Duty Cycle and PWM output are
illustrated assuming that the timer is used for
the PWM function of the CCP module as
described in Section 30.0 “Capture/Com-
pare/PWM Modules”. The signals are not a
part of the Timer2 module.
MODE 0b00000
TMRx_clk
ON
PRx 5
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
MODE 0b00001
TMRx_clk
TMRx_ers
PRx 5
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
MODE 0b00100
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
MODE 0b00111
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
FIGURE 29-8: SOFTWARE START ONE-SHOT MODE TIMING DIAGRAM (MODE = 01000)
Rev. 10-000199B
4/7/2016
MODE 0b01000
TMRx_clk
PRx 5
ON
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions
executed by the CPU to set or clear the ON bit of TxCON. CPU
execution is asynchronous to the timer clock input.
MODE 0b01001
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 2
CCP_pset
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
PIC16(L)F18854
MODE period value. External signal edges will have no effect until after software sets
the ON bit. Figure 29-10 illustrates the rising edge hardware limit one-shot
In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first operation.
external signal edge after the ON bit is set and resets on all subsequent edges.
When this mode is used in conjunction with the CCP then the first starting edge
Only the first edge after the ON bit is set is needed to start the timer. The
trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM
counter will resume counting automatically two clocks after all subsequent drive will deactivate when the timer matches the CCPRx pulse-width value and
external Reset edges. Edge triggers are as follows: stay deactivated until the timer halts at the PRx period match unless an external
• Rising edge start and Reset (MODE<4:0> = 01100) signal edge resets the timer before the match occurs.
• Falling edge start and Reset (MODE<4:0> = 01101)
FIGURE 29-10: EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01100)
Rev. 10-000201B
4/7/2016
MODE 0b01100
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
DS40001826C-page 395
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
29.5.8 LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT When the timer count matches the PRx period count, the timer is reset and the
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
ONE-SHOT MODES ON bit is cleared. When the ON bit is cleared by either a PRx match or by soft-
ware control a new external signal edge is required after the ON bit is set to start
In Level -Triggered One-Shot mode the timer count is reset on the external the counter.
signal level and starts counting on the rising/falling edge of the transition from
When Level-Triggered Reset One-Shot mode is used in conjunction with the
Reset level to the active level while the ON bit is set. Reset levels are selected
CCP PWM operation the PWM drive goes active with the external signal edge
as follows: that starts the timer. The PWM drive goes inactive when the timer count equals
• Low Reset level (MODE<4:0> = 01110) the CCPRx pulse width count. The PWM drive does not go active when the
• High Reset level (MODE<4:0> = 01111) timer count clears at the PRx period count match.
FIGURE 29-11: LOW LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01110)
Rev. 10-000202B
4/7/2016
MODE 0b01110
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
DS40001826C-page 396
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
29.5.9 EDGE-TRIGGERED MONOSTABLE MODES When an Edge-Triggered Monostable mode is used in conjunction with the
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
CCP PWM operation the PWM drive goes active with the external Reset signal
The Edge-Triggered Monostable modes start the timer on an edge from the
edge that starts the timer, but will not go active when the timer matches the PRx
external Reset signal input, after the ON bit is set, and stop incrementing the
value. While the timer is incrementing, additional edges on the external Reset
timer when the timer matches the PRx period value. The following edges will
signal will not affect the CCP PWM.
start the timer:
• Rising edge (MODE<4:0> = 10001)
• Falling edge (MODE<4:0> = 10010)
• Rising or Falling edge (MODE<4:0> = 10011)
FIGURE 29-12: RISING EDGE-TRIGGERED MONOSTABLE MODE TIMING DIAGRAM (MODE = 10001)
Rev. 10-000203A
4/7/2016
MODE 0b10001
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
DS40001826C-page 397
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
29.5.10 LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT • High Reset level (MODE<4:0> = 10111)
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
MODES When the timer count matches the PRx period count, the timer is reset and the
The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset ON bit is cleared. When the ON bit is cleared by either a PRx match or by soft-
on an external Reset level and start counting when both the ON bit is set and ware control the timer will stay in Reset until both the ON bit is set and the exter-
the external signal is not at the Reset level. If one of either the external signal nal signal is not at the Reset level.
is not in Reset or the ON bit is set then the other signal being set/made active When Level-Triggered Hardware Limit One-Shot modes are used in conjunc-
will start the timer. Reset levels are selected as follows: tion with the CCP PWM operation the PWM drive goes active with either the
• Low Reset level (MODE<4:0> = 10110) external signal edge or the setting of the ON bit, whichever of the two starts the
timer.
FIGURE 29-13: LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 10110)
Rev. 10-000204A
4/7/2016
MODE 0b10110
TMR2_clk
PRx 5
ON
TMR2_ers
TMRx 0 1 2 3 4 5 0 1 2 3 0 1 2 3 4 5 0
TMR2_postscaled
PWM Duty
‘D3
Cycle
PWM Output
DS40001826C-page 398
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
PIC16(L)F18854
29.6 Timer2 Operation During Sleep
When PSYNC = 1, Timer2 cannot be operated while
the processor is in Sleep mode. The contents of the
TMR2 and T2PR registers will remain unchanged while
processor is in Sleep mode.
When PSYNC = 0, Timer2 will operate in Sleep as long
as the clock source selected is also still running.
Selecting the LFINTOSC, MFINTOSC, or HFINTOSC
oscillator as the timer clock source will keep the
selected oscillator running during Sleep.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
Note 1: In certain modes, the ON bit will be auto-cleared by hardware. See Section 29.5 “Operation Examples”.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: Setting this bit ensures that reading TMRx will return a valid value.
2: When this bit is ‘1’, Timer2 cannot operate in Sleep mode.
3: CKPOL should not be changed while ON = 1.
4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
5: When this bit is set then the timer operation will be delayed by two TMRx input clocks after the ON bit is set.
6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value
of TMRx).
7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Rev. 10-000158F
9/1/2015
RxyPPS
CCPx
CTS<2:0>
TRIS Control
LC4_out 111
LC3_out 110 CCPRxH CCPRxL
LC2_out 101 16
set CCPxIF
LC1_out 100 Prescaler and
IOC_interrupt 011 1,4,16 Edge Detect
16
C2OUT_sync 010
C1OUT_sync 001 MODE <3:0> TMR1H TMR1L
CCPx PPS 000
CCPxPPS
TMR1H TMR1L
TRIS
Output Enable
Auto-conversion Trigger
TMR2 = CCPRxH:CCPRxL
TMR2 = 0
CCPRxH CCPRxL
CCPx_out
To Peripherals
set CCPIF
10-bit Latch(2)
(Not accessible by user)
S RxyPPS
TMR2 Module TRIS Control
R
TMR2 (1)
ERS logic
Comparator CCPx_pset
PR2
that has many new modes, which allow for greater 12/9/201 3
Note: The Timer postscaler (see Section 29.4 The 8-bit timer TMR2 register is concatenated with
“Timer2 Interrupt”) is not used in the either the 2-bit internal system clock (FOSC), or two bits
determination of the PWM frequency. of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
30.3.6 PWM DUTY CYCLE When the 10-bit time base matches the
The PWM duty cycle is specified by writing a 10-bit CCPRxH:CCPRxL register pair, then the CCPx pin is
value to the CCPRxH:CCPRxL register pair. The cleared (see Figure 30-4).
alignment of the 10-bit value is determined by the
CCPRxFMT bit of the CCPxCON register (see 30.3.7 PWM RESOLUTION
Figure 30-5). The CCPRxH:CCPRxL register pair can The resolution determines the number of available duty
be written to at any time; however the duty cycle value cycles for a given period. For example, a 10-bit resolution
is not latched into the 10-bit buffer until after a match will result in 1024 discrete duty cycles, whereas an 8-bit
between PR2 and TMR2. resolution will result in 256 discrete duty cycles.
Equation 30-2 is used to calculate the PWM pulse The maximum PWM resolution is ten bits when PR2 is
width. 255. The resolution is a function of the PR2 register
Equation 30-3 is used to calculate the PWM duty cycle value as shown by Equation 30-4.
ratio.
EQUATION 30-4: PWM RESOLUTION
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: All modes will set the CCPxIF bit, and will trigger an ADC conversion if CCPx is selected as the ADC
trigger source.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
Data Bus
Read Write
SSPxBUF Reg
SSPDATPPS
SDI
PPS SSPSR Reg
SDO bit 0 Shift
Clock
PPS
RxyPPS
Edge
SSPSSPPS Select
SSPCLKPPS(2) SSPM<3:0>
SCK PPS
4
( T2_match
2
)
Edge Prescaler TOSC
PPS Select 4, 16, 64
Internal
data bus [SSPM<3:0>]
SSPDATPPS(1) Read Write
SDA
SDA in
PPS SSPxBUF Baud Rate
Generator
(SSPxADD)
Shift
RxyPPS(1) Clock
PPS
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output
Internal
Data Bus
Read Write
SSPxMSK Reg
SSPDATPPS(1)
SDA Match Detect Addr Match
PPS
SSPxADD Reg
PPS
Start and Set, Reset
RxyPPS(1) Stop bit Detect S, P bits
(SSPxSTAT Reg)
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
General I/O
General I/O SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
Slave Select
General I/O SS
Processor 1 (optional) Processor 2
Write to
SSPxBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPxSR
and bit count are reset
SSPxBUF to
SSPxSR
SDI bit 0
bit 7 bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDI
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDI
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid.
transition of SDA from a high to a low state while SCL A master can issue a Restart if it wishes to hold the
line is high. A Start condition is always generated by bus after terminating the current transfer. A Restart
the master and signifies the transition of the bus from has the same effect on the slave that a Start would,
an Idle to an Active state. Figure 31-12 shows wave resetting all slave logic and preparing it to clock in an
forms for Start and Stop conditions. address. The master may want to address the same or
A bus collision can occur on a Start condition if the another slave. Figure 31-13 shows the wave form for a
module samples the SDA line low before asserting it Restart condition.
low. This does not conform to the I2C Specification that In 10-bit Addressing Slave mode a Restart is required
states no bus collision can occur on a Start. for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, match-
31.4.6 STOP CONDITION ing both high and low address bytes, the master can
A Stop condition is a transition of the SDA line from issue a Restart and the high address byte with the
low-to-high state while the SCL line is high. R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
Note: At least one SCL low time must appear
After a full match with R/W clear in 10-bit mode, a prior
before a Stop is valid, therefore, if the SDA
match flag is set and maintained until a Stop condition, a
line goes low then high again while the SCL
high address with R/W clear, or high address match fails.
line stays high, only the Start condition is
detected. 31.4.8 START/STOP CONDITION INTERRUPT
MASKING
SDA
SCL
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition
Sr
Change of Change of
Data Allowed Data Allowed
Restart
Condition
When the SEN bit of the SSPxCON2 register is set, 1. S bit of SSPxSTAT is set; SSPxIF is set if
SCL will be held low (clock stretch) following each interrupt on Start detect is enabled.
received byte. The clock must be released by setting 2. Matching address with R/W bit clear is clocked
the CKP bit of the SSPxCON1 register, except in. SSPxIF is set and CKP cleared after the
sometimes in 10-bit mode. See Section 31.5.6.2 eighth falling edge of SCL.
“10-bit Addressing Mode” for more detail. 3. Slave clears the SSPxIF.
4. Slave can look at the ACKTIM bit of the
31.5.2.1 7-bit Addressing Reception
SSPxCON3 register to determine if the SSPxIF
This section describes a standard sequence of events was after or before the ACK.
for the MSSP module configured as an I2C slave in 5. Slave reads the address value from SSPxBUF,
7-bit Addressing mode. Figure 31-14 and Figure 31-15 clearing the BF flag.
is used as a visual reference for this description. 6. Slave sets ACK value clocked out to the master
This is a step by step process of what typically must by setting ACKDT.
be done to accomplish I2C communication. 7. Slave releases the clock by setting CKP.
1. Start bit detected. 8. SSPxIF is set after an ACK, not after a NACK.
2. S bit of SSPxSTAT is set; SSPxIF is set if 9. If SEN = 1 the slave hardware will stretch the
interrupt on Start detect is enabled. clock after the ACK.
3. Matching address with R/W bit clear is received. 10. Slave clears SSPxIF.
4. The slave pulls SDA low sending an ACK to the Note: SSPxIF is still set after the ninth falling edge
master, and sets SSPxIF bit. of SCL even if there is no clock stretching
5. Software clears the SSPxIF bit. and BF has been cleared. Only if NACK is
6. Software reads received address from sent to master is SSPxIF not set
SSPxBUF clearing the BF flag. 11. SSPxIF set and CKP cleared after eighth falling
7. If SEN = 1; Slave software sets CKP bit to edge of SCL for a received data byte.
release the SCL line.
12. Slave looks at ACKTIM bit of SSPxCON3 to
8. The master clocks out a data byte. determine the source of the interrupt.
9. Slave drives SDA low sending an ACK to the 13. Slave reads the received data from SSPxBUF
master, and sets SSPxIF bit. clearing BF.
10. Software clears SSPxIF. 14. Steps 7-14 are the same for each received data
11. Software reads the received byte from byte.
SSPxBUF clearing BF. 15. Communication is ended by either the slave
12. Steps 8-12 are repeated for all received bytes sending an ACK = 1, or the master sending a
from the master. Stop condition. If a Stop is sent and Interrupt on
13. Master sends Stop condition, setting P bit of Stop Detect is disabled, the slave will only know
SSPxSTAT, and the bus goes idle. by polling the P bit of the SSPxSTAT register.
FIGURE 31-14:
PIC16(L)F18854
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
Bus Master sends
Stop condition
From Slave to Master
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPxIF
SSPxIF set on 9th
Cleared by software Cleared by software falling edge of
SCL
BF
First byte
SSPxBUF is read of data is
available
in SSPxBUF
SSPOV
FIGURE 31-15:
PIC16(L)F18854
Bus Master sends
Stop condition
SSPxIF
BF
First byte
of data is
SSPxBUF is read available
in SSPxBUF
SSPOV
FIGURE 31-16:
PIC16(L)F18854
Master Releases SDA Master sends
to slave for ACK sequence Stop condition
SSPxIF
If AHEN = 1: SSPxIF is set on
SSPxIF is set 9th falling edge of Cleared by software No interrupt
SCL, after ACK after not ACK
BF from Slave
Address is
read from Data is read from SSPxBUF
ACKDT SSPxBUF
Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK
When AHEN = 1:
When DHEN = 1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCL is released
and SCL is stretched hardware on 8th falling
edge of SCL
ACKTIM
S
DS40001826C-page 436
P
2016-2018 Microchip Technology Inc.
FIGURE 31-17:
PIC16(L)F18854
Master sends
Stop condition
Master releases
R/W = 0 SDA to slave for ACK sequence
Receiving Address Receive Data Receive Data ACK
SDA
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SSPxIF
Cleared by software No interrupt after
if not ACK
from Slave
BF
Received
address is loaded into Received data is SSPxBUF can be
SSPxBUF available on SSPxBUF read any time before
next byte is loaded
ACKDT
ACKTIM
S
DS40001826C-page 437
P
PIC16(L)F18854
31.5.3 SLAVE TRANSMISSION 31.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set A master device can transmit a read request to a
and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list
SSPxSTAT register is set. The received address is below outlines what software for a slave will need to
loaded into the SSPxBUF register, and an ACK pulse is do to accomplish a standard transmission.
sent by the slave on the ninth bit. Figure 31-18 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and
and the SCL pin is held low (see Section 31.5.6 SCL.
“Clock Stretching” for more detail). By stretching the 2. S bit of SSPxSTAT is set; SSPxIF is set if
clock, the master will be unable to assert another clock interrupt on Start detect is enabled.
pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by
data. the Slave setting SSPxIF bit.
The transmit data must be loaded into the SSPxBUF 4. Slave hardware generates an ACK and sets
register which also loads the SSPxSR register. Then SSPxIF.
the SCL pin should be released by setting the CKP bit 5. SSPxIF bit is cleared by user.
of the SSPxCON1 register. The eight data bits are
6. Software reads the received address from
shifted out on the falling edge of the SCL input. This
SSPxBUF, clearing BF.
ensures that the SDA signal is valid during the SCL
high time. 7. R/W is set so CKP was automatically cleared
after the ACK.
The ACK pulse from the master-receiver is latched on
8. The slave software loads the transmit data into
the rising edge of the ninth SCL input pulse. This ACK
SSPxBUF.
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data 9. CKP bit is set releasing SCL, allowing the
transfer is complete. In this case, when the not ACK is master to clock the data out of the slave.
latched by the slave, the slave goes idle and waits for 10. SSPxIF is set after the ACK response from the
another occurrence of the Start bit. If the SDA line was master is loaded into the ACKSTAT register.
low (ACK), the next transmit data must be loaded into 11. SSPxIF bit is cleared.
the SSPxBUF register. Again, the SCL pin must be 12. The slave software checks the ACKSTAT bit to
released by setting bit CKP. see if the master wants to clock out more data.
An MSSP interrupt is generated for each data transfer Note 1: If the master ACKs the clock will be
byte. The SSPxIF bit must be cleared by software and stretched.
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of 2: ACKSTAT is the only bit updated on the
the ninth clock pulse. rising edge of SCL (9th) rather than the
falling.
31.5.3.1 Slave Mode Bus Collision 13. Steps 9-13 are repeated for each transmitted
A slave receives a read request and begins shifting byte.
data out on the SDA line. If a bus collision is detected 14. If the master sends a not ACK; the clock is not
and the SBCDE bit of the SSPxCON3 register is set, held, but SSPxIF is still set.
the BCL1IF bit of the PIR3 register is set. Once a bus 15. The master sends a Restart condition or a Stop.
collision is detected, the slave goes idle and waits to be
16. The slave is no longer addressed.
addressed again. User software can use the BCL1IF bit
to handle a slave bus collision.
FIGURE 31-18:
PIC16(L)F18854
Master sends
Stop condition
SSPxIF
Cleared by software
BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCL
CKP
When R/W is set CKP is not
SCL is always held for not
held low after 9th SCL Set by software ACK
falling edge
ACKSTAT
Indicates an address
has been received
DS40001826C-page 439
P
PIC16(L)F18854
31.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt
generation after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
Figure 31-19 displays a standard waveform of a 7-bit
address slave transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the eighth falling edge of the SCL line
the CKP bit is cleared and SSPxIF interrupt is
generated.
4. Slave software clears SSPxIF.
5. Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPxBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
13. Slave sets the CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the ninth SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last
byte to ensure that the slave releases the
SCL line to receive a Stop.
FIGURE 31-19:
PIC16(L)F18854
Master sends
Master releases SDA Stop condition
to slave for ACK sequence
Receiving Address R/W = 1 Automatic Transmitting Data Automatic Transmitting Data ACK
SDA
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SSPxIF
Cleared by software
BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCL
ACKDT
Slave clears
ACKDT to ACK
address
ACKSTAT
Master’s ACK
response is copied
to SSPxSTAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCL
address. cleared after ACK
ACKTIM
ACKTIM is set on 8th falling ACKTIM is cleared
edge of SCL on 9th rising edge of SCL
DS40001826C-page 441
R/W
D/A
PIC16(L)F18854
31.5.4 SLAVE MODE 10-BIT ADDRESS 31.5.5 10-BIT ADDRESSING WITH ADDRESS OR
RECEPTION DATA HOLD
This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSP module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSPxADD register
Figure 31-20 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCL line is held low are the
same. Figure 31-21 can be used as a reference of a
This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set.
slave software to accomplish I2C communication.
Figure 31-22 shows a standard waveform for a slave
1. Bus starts Idle. transmitter in 10-bit Addressing mode.
2. Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
4. Slave sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. Slave loads low address into SSPxADD,
releasing SCL.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
FIGURE 31-20:
PIC16(L)F18854
Master sends
Stop condition
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SCL is held low
while CKP = 0
SSPxIF
Set by hardware Cleared by software
on 9th falling edge
BF
If address matches Receive address is Data is read
SSPxADD it is loaded into read from SSPxBUF from SSPxBUF
SSPxBUF
UA
When UA = 1; Software updates SSPxADD
SCL is held low and releases SCL
CKP
DS40001826C-page 443
FIGURE 31-21:
PIC16(L)F18854
Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5
SSPxIF
Set by hardware Cleared by software Cleared by software
on 9th falling edge
BF
UA
FIGURE 31-22:
PIC16(L)F18854
Master sends
Master sends Stop condition
Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
Sr
SSPxIF
BF
Indicates an address
has been received
PIC16(L)F18854
31.5.6 CLOCK STRETCHING 31.5.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set the
holds the SCL line low, effectively pausing communi- clock is always stretched. This is the only time the SCL
cation. The slave may stretch the clock to allow more is stretched without CKP being cleared. SCL is
time to handle data or prepare a response for the released immediately after a write to SSPxADD.
master device. A master device is not concerned with
Note: Previous versions of the module did not
stretching as anytime it is active on the bus and not
stretch the clock if the second address byte
transferring data it is stretching. Any stretching done
did not match.
by a slave is invisible to the master software and
handled by the hardware that generates SCL. 31.5.6.3 Byte NACKing
The CKP bit of the SSPxCON1 register is used to
control stretching in software. Any time the CKP bit is When AHEN bit of SSPxCON3 is set; CKP is cleared
cleared, the module will wait for the SCL line to go low by hardware after the eighth falling edge of SCL for a
and then hold it. Setting CKP will release SCL and received matching address byte. When DHEN bit of
allow more communication. SSPxCON3 is set; CKP is cleared after the eighth fall-
ing edge of SCL for received data.
31.5.6.1 Normal Clock Stretching Stretching after the eighth falling edge of SCL allows
Following an ACK if the R/W bit of SSPxSTAT is set, a the slave to look at the received address or data and
read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data.
allows the slave time to update SSPxBUF with data to 31.5.7 CLOCK SYNCHRONIZATION AND THE
transfer to the master. If the SEN bit of SSPxCON2 is CKP BIT
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait
is set by software and communication resumes. for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
Note 1: The BF bit has no effect on if the clock will
until the SCL output is already sampled low. There-
be stretched or not. This is different than
fore, the CKP bit will not assert the SCL line until an
previous versions of the module that
external I2C master device has already asserted the
would not stretch the clock, clear CKP, if
SCL line. The SCL output will remain low until the CKP
SSPxBUF was read before the ninth
bit is set and all other devices on the I2C bus have
falling edge of SCL.
released SCL. This ensures that a write to the CKP bit
2: Previous versions of the module did not will not violate the minimum high time requirement for
stretch the clock for a transmission if SCL (see Figure 31-23).
SSPxBUF was loaded before the ninth
falling edge of SCL. It is now always
cleared for read requests.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX ‚ – 1
SCL
Master device
CKP asserts clock
Master device
releases clock
WR
SSPxCON1
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
SSPxBUF is read
GCEN (SSPxCON2<7>)
’1’
Master mode is enabled by setting and clearing the The master device generates all of the serial clock
appropriate SSPM bits in the SSPxCON1 register and pulses and the Start and Stop conditions. A transfer is
by setting the SSPEN bit. In Master mode, the SDA and ended with a Stop condition or with a Repeated Start
SCK pins must be configured as inputs. The MSSP condition. Since the Repeated Start condition is also
peripheral hardware will override the output driver TRIS the beginning of the next serial transfer, the I2C bus will
controls when necessary to drive the pins low. not be released.
Master mode of operation is supported by interrupt In Master Transmitter mode, serial data is output
generation on the detection of the Start and Stop through SDA, while SCL outputs the serial clock. The
conditions. The Stop (P) and Start (S) bits are cleared first byte transmitted contains the slave address of the
from a Reset or when the MSSP module is disabled. receiving device (7 bits) and the Read/Write (R/W) bit.
Control of the I 2C bus may be taken when the P bit is In this case, the R/W bit will be logic ‘0’. Serial data is
set, or the bus is Idle. transmitted eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
In Firmware Controlled Master mode, user code
Stop conditions are output to indicate the beginning
conducts all I 2C bus operations based on Start and
and the end of a serial transfer.
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted
other communication is done by the user software contains the slave address of the transmitting device
directly manipulating the SDA and SCL lines. (7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
The following events will cause the SSP Interrupt Flag address followed by a ‘1’ to indicate the receive bit.
bit, SSPxIF, to be set (SSP interrupt, if enabled): Serial data is received via SDA, while SCL outputs the
• Start condition detected serial clock. Serial data is received eight bits at a time.
• Stop condition detected After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
• Data transfer byte transmitted/received
beginning and end of transmission.
• Acknowledge transmitted/received
A Baud Rate Generator is used to set the clock
• Repeated Start generated
frequency output on SCL. See Section 31.7 “Baud
Note 1: The MSSP module, when configured in Rate Generator” for more detail.
I2C Master mode, does not allow queuing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPxBUF did not occur
2: Master mode suspends Start/Stop
detection when sending the Start/Stop
condition by means of the SEN/PEN
control bits. The SSPxIF bit is set at the
end of the Start/Stop generation when
hardware clears the control bit.
SDA DX DX ‚ – 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
TBRG
SCL
S
TBRG
FIGURE 31-28:
PIC16(L)F18854
Write SSPxCON2<0> SEN = 1 ACKSTAT in
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
BF (SSPxSTAT<0>)
PEN
R/W
DS40001826C-page 453
PIC16(L)F18854
31.6.7 I2C MASTER MODE RECEPTION 31.6.7.4 Typical Receive Sequence:
Master mode reception (Figure 31-29) is enabled by 1. The user generates a Start condition by setting
programming the Receive Enable bit, RCEN bit of the the SEN bit of the SSPxCON2 register.
SSPxCON2 register. 2. SSPxIF is set by hardware on completion of the
Note: The MSSP module must be in an Idle Start.
state before the RCEN bit is set or the 3. SSPxIF is cleared by software.
RCEN bit will be disregarded. 4. User writes SSPxBUF with the slave address to
The Baud Rate Generator begins counting and on each transmit and the R/W bit set.
rollover, the state of the SCL pin changes 5. Address is shifted out the SDA pin until all eight
(high-to-low/low-to-high) and data is shifted into the bits are transmitted. Transmission begins as
SSPxSR. After the falling edge of the eighth clock, the soon as SSPxBUF is written to.
receive enable flag is automatically cleared, the 6. The MSSP module shifts in the ACK bit from the
contents of the SSPxSR are loaded into the SSPxBUF, slave device and writes its value into the
the BF flag bit is set, the SSPxIF flag bit is set and the ACKSTAT bit of the SSPxCON2 register.
Baud Rate Generator is suspended from counting, 7. The MSSP module generates an interrupt at the
holding SCL low. The MSSP is now in Idle state end of the ninth clock cycle by setting the
awaiting the next command. When the buffer is read by SSPxIF bit.
the CPU, the BF flag bit is automatically cleared. The 8. User sets the RCEN bit of the SSPxCON2
user can then send an Acknowledge bit at the end of register and the master clocks in a byte from the
reception by setting the Acknowledge Sequence slave.
Enable, ACKEN bit of the SSPxCON2 register.
9. After the eighth falling edge of SCL, SSPxIF and
31.6.7.1 BF Status Flag BF are set.
10. Master clears SSPxIF and reads the received
In receive operation, the BF bit is set when an address
byte from SSPxBUF, clears BF.
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read. 11. Master sets ACK value sent to slave in ACKDT
bit of the SSPxCON2 register and initiates the
31.6.7.2 SSPOV Status Flag ACK by setting the ACKEN bit.
In receive operation, the SSPOV bit is set when eight 12. Master’s ACK is clocked out to the slave and
bits are received into the SSPxSR and the BF flag bit is SSPxIF is set.
already set from a previous reception. 13. User clears SSPxIF.
14. Steps 8-13 are repeated for each received byte
31.6.7.3 WCOL Status Flag from the slave.
If the user writes the SSPxBUF when a receive is 15. Master sends a not ACK or Stop to end
already in progress (i.e., SSPxSR is still shifting in a communication.
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
FIGURE 31-29:
PIC16(L)F18854
Write to SSPxCON2<4>
to start Ackno1wledge sequence
SDA = ACKDT (SSPxCON2<5>) = 0
Write to SSPxCON2<0>(SEN = 1),
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPxCON2<3> (RCEN = 1)
PEN bit = 1
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPxIF at end
of receive Set SSPxIF interrupt
Set SSPxIF interrupt at end of Acknow-
Set SSPxIF interrupt ledge sequence
at end of receive at end of Acknowledge
SSPxIF sequence
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPxSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPxIF
responds to SSPxIF
BF
(SSPxSTAT<0>) Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF
SSPOV
ACKEN
DS40001826C-page 455
RCEN
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPxCON2<3> (RCEN = 1) automatically SDA = ACKDT = 0 automatically
PIC16(L)F18854
31.6.8 ACKNOWLEDGE SEQUENCE 31.6.9 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPxCON2 register. At the end of a
SSPxCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDA pin. If the user wishes to the master will assert the SDA line low. When the SDA
generate an Acknowledge, then the ACKDT bit should line is sampled low, the Baud Rate Generator is
be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate
before starting an Acknowledge sequence. The Baud Generator times out, the SCL pin will be brought high
Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count)
(TBRG) and the SCL pin is deasserted (pulled high). later, the SDA pin will be deasserted. When the SDA
When the SCL pin is sampled high (clock arbitration), pin is sampled high while SCL is high, the P bit of the
the Baud Rate Generator counts for TBRG. The SCL pin SSPxSTAT register is set. A TBRG later, the PEN bit is
is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure 31-31).
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into IDLE mode 31.6.9.1 WCOL Status Flag
(Figure 31-30). If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
31.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does
If the user writes the SSPxBUF when an Acknowledge not occur).
sequence is in progress, then WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 31-30: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, ACKEN automatically cleared
write to SSPxCON2
ACKEN = 1, ACKDT = 0
TBRG TBRG
SDA D0 ACK
SCL 8 9
SSPxIF
Cleared in
SSPxIF set at software
the end of receive Cleared in
software SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
SDA
BCL1IF
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCL1IF.
S bit and SSPxIF set because
BCL1IF SDA = 0, SCL = 1.
SSPxIF and BCL1IF are
cleared by software
SSPxIF
TBRG TBRG
SDA
FIGURE 31-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPxIF
Less than TBRG
TBRG
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCL1IF ’0’
SSPxIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPxIF by software
SDA
SCL
RSEN
BCL1IF
Cleared by software
S ’0’
SSPxIF ’0’
TBRG TBRG
SDA
SCL
S ’0’
SSPxIF
PEN
BCL1IF
P ’0’
SSPxIF ’0’
SDA
PEN
BCL1IF
P ’0’
SSPxIF ’0’
SSPM<3:0> SSPxADD<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS/HC = Hardware set/clear
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new
byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
REGISTER 31-6: SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
SSPADD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Master mode:
bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 SSPADD<2:1>: Two Most Significant bits of 10-bit Address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode – Least Significant Address Byte:
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Period Latch
Set SMTxPRAIF
SMT_window SMT
Clock SMTxPR
Sync
Circuit
Control Set SMTxIF
Logic Comparator
SMT_signal SMT
Clock
Sync
Circuit
24-bit
Reset SMTxCPR
Buffer
SMTxCLK<2:0>
See See
SMTxSIG SMT_signal SMTxWIN SMT_window
Register Register
SMTxSIG<3:0> SMTxWIN<3:0>
PIC16(L)F18854
Rev. 10-000 174A
12/19/201 3
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxPR 11
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9
SMTxIF
DS40001826C-page 473
PIC16(L)F18854
32.6.2 GATED TIMER MODE
Gated Timer mode uses the SMTSIGx input to control
whether or not the SMTxTMR will increment. Upon a
falling edge of the external signal, the SMTxCPW
register will update to the current value of the
SMTxTMR. Example waveforms for both repeated and
single acquisitions are provided in Figure 32-4 and
Figure 32-5.
PIC16(L)F18854
Rev. 10-000 176A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxPR 0xFFFFFF
SMTxTMR 0 1 2 3 4 5 6 7
SMTxCPW 5 7
SMTxPWAIF
DS40001826C-page 475
FIGURE 32-5: GATED TIMER MODE SINGLE ACQUISITION TIMING DIAGRAM
DS40001826C-page 476
PIC16(L)F18854
Rev. 10-000 175A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxPR 0xFFFFFF
SMTxTMR 0 1 2 3 4 5
SMTxCPW 5
SMTxPWAIF
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
32.6.3 PERIOD AND DUTY-CYCLE MODE
In Duty-Cycle mode, either the duty cycle or period
(depending on polarity) of the SMTx_signal can be
acquired relative to the SMT clock. The CPW register is
updated on a falling edge of the signal, and the CPR
register is updated on a rising edge of the signal, along
with the SMTxTMR resetting to 0x0001. In addition, the
SMTxGO bit is reset on a rising edge when the SMT is
in Single Acquisition mode. See Figure 32-6 and
Figure 32-7.
PIC16(L)F18854
Rev. 10-000 177A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5
SMTxCPW 5 2
SMTxCPR 11
SMTxPWAIF
SMTxPRAIF
2016-2018 Microchip Technology Inc.
FIGURE 32-7: PERIOD AND DUTY-CYCLE SINGLE ACQUISITION TIMING DIAGRAM
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Rev. 10-000 178A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11
SMTxCPW 5
SMTxCPR 11
SMTxPWAIF
SMTxPRAIF
DS40001826C-page 479
PIC16(L)F18854
32.6.4 HIGH AND LOW MEASURE MODE
This mode measures the high and low pulse time of the
SMTSIGx relative to the SMT clock. It begins
incrementing the SMTxTMR on a rising edge on the
SMTSIGx input, then updates the SMTxCPW register
with the value and resets the SMTxTMR on a falling
edge, starting to increment again. Upon observing
another rising edge, it updates the SMTxCPR register
with its current value and once again resets the
SMTxTMR value and begins incrementing again. See
Figure 32-8 and Figure 32-9.
PIC16(L)F18854
Rev. 10-000 180A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 1 2 3 4 5 6 1 2 1 2 3
SMTxCPW 5 2
SMTxCPR 6
SMTxPWAIF
SMTxPRAIF
DS40001826C-page 481
FIGURE 32-9: HIGH AND LOW MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Rev. 10-000 179A
12/19/201 3
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 1 2 3 4 5 6
SMTxCPW 5
SMTxCPR 6
SMTxPWAIF
SMTxPRAIF
DS40001826C-page 482
PIC16(L)F18854
32.6.5 WINDOWED MEASURE MODE
This mode measures the window duration of the
SMTWINx input of the SMT. It begins incrementing the
timer on a rising edge of the SMTWINx input and
updates the SMTxCPR register with the value of the
timer and resets the timer on a second rising edge. See
Figure 32-10 and Figure 32-11.
PIC16(L)F18854
Rev. 10-000 182A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 1 2 3 4
SMTxCPR 12 8
SMTxPRAIF
DS40001826C-page 484
FIGURE 32-11: WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Rev. 10-000 181A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12
SMTxCPR 12
SMTxPRAIF
DS40001826C-page 485
PIC16(L)F18854
32.6.6 GATED WINDOW MEASURE MODE
This mode measures the duty cycle of the SMTx_signal
input over a known input window. It does so by
incrementing the timer on each pulse of the clock signal
while the SMTx_signal input is high, updating the
SMTxCPR register and resetting the timer on every
rising edge of the SMTWINx input after the first. See
Figure 32-12 and Figure 32-13.
PIC16(L)F18854
Rev. 10-000 184A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 0 1 2 3 0
SMTxCPR 6 3
SMTxPRAIF
DS40001826C-page 487
FIGURE 32-13: GATED WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAMS
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Rev. 10-000 183A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6
SMTxCPR 6
SMTxPRAIF
DS40001826C-page 488
PIC16(L)F18854
32.6.7 TIME OF FLIGHT MEASURE MODE
This mode measures the time interval between a rising
edge on the SMTWINx input and a rising edge on the
SMTx_signal input, beginning to increment the timer
upon observing a rising edge on the SMTWINx input,
while updating the SMTxCPR register and resetting the
timer upon observing a rising edge on the SMTx_signal
input. In the event of two SMTWINx rising edges
without an SMTx_signal rising edge, it will update the
SMTxCPW register with the current value of the timer
and reset the timer value. See Figure 32-14 and
Figure 32-15.
PIC16(L)F18854
Rev. 10-000186A
4/22/2016
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2
SMTxCPW 13
SMTxCPR 4
SMTxPWAIF
SMTxPRAIF
DS40001826C-page 490
FIGURE 32-15: TIME OF FLIGHT MODE SINGLE ACQUISITION TIMING DIAGRAM
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Rev. 10-000185A
4/26/2016
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5
SMTxCPW
SMTxCPR 4
SMTxPWAIF
SMTxPRAIF
DS40001826C-page 491
PIC16(L)F18854
32.6.8 CAPTURE MODE
This mode captures the Timer value based on a rising
or falling edge on the SMTWINx input and triggers an
interrupt. This mimics the capture feature of a CCP
module. The timer begins incrementing upon the
SMTxGO bit being set, and updates the value of the
SMTxCPR register on each rising edge of SMTWINx,
and updates the value of the CPW register on each
falling edge of the SMTWINx. The timer is not reset by
any hardware conditions in this mode and must be
reset by software, if desired. See Figure 32-16 and
Figure 32-17.
PIC16(L)F18854
Rev. 10-000 188A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SMTxCPW 3 19 32
SMTxCPR 2 18 31
SMTxPWAIF
SMTxPRAIF
DS40001826C-page 493
FIGURE 32-17: CAPTURE MODE SINGLE ACQUISITION TIMING DIAGRAM
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Rev. 10-000 187A
12/19/201 3
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR 0 1 2 3
SMTxCPW 3
SMTxCPR 2
SMTxPWAIF
SMTxPRAIF
DS40001826C-page 494
PIC16(L)F18854
32.6.9 COUNTER MODE
This mode increments the timer on each pulse of the
SMTx_signal input. This mode is asynchronous to the
SMT clock and uses the SMTx_signal as a time source.
The SMTxCPW register will be updated with the
current SMTxTMR value on the falling edge of the
SMTxWIN input. See Figure 32-18.
PIC16(L)F18854
Rev. 10-000189A
4/12/2016
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SMTxCPW 12 25
DS40001826C-page 496
PIC16(L)F18854
32.6.10 GATED COUNTER MODE
This mode counts pulses on the SMTx_signal input,
gated by the SMTxWIN input. It begins incrementing
the timer upon seeing a rising edge of the SMTxWIN
input and updates the SMTxCPW register upon a fall-
ing edge on the SMTxWIN input. See Figure 32-19
and Figure 32-20.
PIC16(L)F18854
Rev. 10-000190A
12/18/2013
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13
SMTxCPW 8 13
SMTxPWAIF
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8
DS40001826C-page 498
SMTxCPW 8
SMTxPWAIF
PIC16(L)F18854
32.6.11 WINDOWED COUNTER MODE
This mode counts pulses on the SMTx_signal input,
within a window dictated by the SMTxWIN input. It
begins counting upon seeing a rising edge of the
SMTxWIN input, updates the SMTxCPW register on a
falling edge of the SMTxWIN input, and updates the
SMTxCPR register on each rising edge of the
SMTxWIN input beyond the first. See Figure 32-21 and
Figure 32-22.
PIC16(L)F18854
Rev. 10-000192A
12/18/2013
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
SMTxCPW 9 5
SMTxCPR 16
SMTxPWAIF
SMTxPRAIF
DS40001826C-page 500
FIGURE 32-22: WINDOWED COUNTER MODE SINGLE ACQUISITION TIMING DIAGRAM
2016-2018 Microchip Technology Inc.
PIC16(L)F18854
Rev. 10-000193A
12/18/2013
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SMTxCPW 9
SMTxCPR 16
SMTxPWAIF
DS40001826C-page 501
PIC16(L)F18854
32.7 Interrupts
The SMT can trigger an interrupt under three different
conditions:
• PW Acquisition Complete
• PR Acquisition Complete
• Counter Period Match
The interrupts are controlled by the PIR and PIE
registers of the device.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxTMR<7:0>: Significant bits of the SMT Counter – Low Byte
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxTMR<15:8>: Significant bits of the SMT Counter – High Byte
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxTMR<23:16>: Significant bits of the SMT Counter – Upper Byte
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxCPR<7:0>: Significant bits of the SMT Period Latch – Low Byte
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxCPR<15:8>: Significant bits of the SMT Period Latch – High Byte
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxCPR<23:16>: Significant bits of the SMT Period Latch – Upper Byte
REGISTER 32-13: SMTxCPWL: SMT CAPTURED PULSE WIDTH REGISTER – LOW BYTE
R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x
SMTxCPW<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxCPW<7:0>: Significant bits of the SMT PW Latch – Low Byte
REGISTER 32-14: SMTxCPWH: SMT CAPTURED PULSE WIDTH REGISTER – HIGH BYTE
R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x
SMTxCPW<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxCPW<15:8>: Significant bits of the SMT PW Latch – High Byte
REGISTER 32-15: SMTxCPWU: SMT CAPTURED PULSE WIDTH REGISTER – UPPER BYTE
R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x
SMTxCPW<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxCPW<23:16>: Significant bits of the SMT PW Latch – Upper Byte
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxPR<7:0>: Significant bits of the SMT Timer Value for Period Match – Low Byte
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxPR<15:8>: Significant bits of the SMT Timer Value for Period Match – High Byte
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SMTxPR<23:16>: Significant bits of the SMT Timer Value for Period Match – Upper Byte
Data Bus
TXIE
SYNC
Interrupt
CSRC
TXxREG Register TXIF
8 RxyPPS(1)
CK pin TXEN
MSb LSb RX/DT pin
PPS 1 (8) 0 Pin Buffer
• • • and Control PPS
0 Transmit Shift Register (TSR)
CKPPS SYNC
TRMT TX_out
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D TX/CK pin
SYNC 1 X 0 0 0 0
SPxBRGH SPxBRGL PPS
BRGH X 1 1 0 0
1
BRG16 X 1 0 1 0
RxyPPS
SYNC
Note 1: In Synchronous mode the DT output and RX input PPS CSRC
selections should enable the same pin.
RXPPS(1)
RX/DT pin MSb RSR Register LSb
Pin Buffer Data
PPS and Control Recovery
Stop (8) 7 ••• 1 0 Start
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPxBRGH SPxBRGL BRGH FIFO
X 1 1 0 0 FERR RX9D RCxREG Register
BRG16 X 1 0 1 0
8
Data Bus
Note 1: In Synchronous mode the DT output and RX input PPS RCIF Interrupt
selections should enable the same pin. RCIE
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY
• CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
• SYNC = 0
to the EUSART receive FIFO and the RCIF interrupt
• SPEN = 1 flag bit of the PIR3 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCREG register.
Setting the CREN bit of the RC1STA register enables Note: If the receive FIFO is overrun, no additional
the receiver circuitry of the EUSART. Clearing the SYNC characters will be received until the overrun
bit of the TX1STA register configures the EUSART for condition is cleared. See Section 33.1.2.5
asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more
RC1STA register enables the EUSART. The information on overrun errors.
programmer must set the corresponding TRIS bit to
configure the RX/DT I/O pin as an input.
Note: If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
BRG Clock
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
33.3.4 BREAK CHARACTER SEQUENCE 33.3.4.1 Break and Sync Transmit Sequence
The EUSART module has the capability of sending the The following sequence will start a message frame
special Break character sequences that are required by header made up of a Break, followed by an auto-baud
the LIN bus standard. A Break character consists of a Sync byte. This sequence is typical of a LIN bus
Start bit, followed by 12 ‘0’ bits and a Stop bit. master.
To send a Break character, set the SENDB and TXEN 1. Configure the EUSART for the desired mode.
bits of the TX1STA register. The Break character trans- 2. Set the TXEN and SENDB bits to enable the
mission is then initiated by a write to the TXREG. The Break sequence.
value of data written to TXREG will be ignored and all 3. Load the TXREG with a dummy character to
‘0’s will be transmitted. initiate transmission (the value is ignored).
The SENDB bit is automatically reset by hardware after 4. Write ‘55h’ to TXREG to load the Sync character
the corresponding Stop bit is sent. This allows the user into the transmit FIFO buffer.
to preload the transmit FIFO with the next transmit byte 5. After the Break has been sent, the SENDB bit is
following the Break character (typically, the Sync reset by hardware and the Sync character is
character in the LIN specification). then transmitted.
The TRMT bit of the TX1STA register indicates when the When the TXREG becomes empty, as indicated by the
transmit operation is active or idle, just as it does during TXIF, the next data byte can be written to TXREG.
normal transmission. See Figure 33-9 for the timing of
the Break character sequence.
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
33.4.1.5 Synchronous Master Reception To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
Data is received at the RX/DT pin. The RX/DT pin
TX/CK clock pin and is shifted into the Receive Shift
output driver is automatically disabled when the
Register (RSR). When a complete character is
EUSART is configured for synchronous master receive
received into the RSR, the RCIF bit is set and the char-
operation.
acter is automatically transferred to the two character
In Synchronous mode, reception is enabled by setting receive FIFO. The Least Significant eight bits of the top
either the Single Receive Enable bit (SREN of the character in the receive FIFO are available in RCREG.
RC1STA register) or the Continuous Receive Enable The RCIF bit remains set as long as there are unread
bit (CREN of the RC1STA register). characters in the receive FIFO.
When SREN is set and CREN is clear, only as many Note: If the RX/DT function is on an analog pin,
clock cycles are generated as there are data bits in a the corresponding ANSEL bit must be
single character. The SREN bit is automatically cleared cleared for the receiver to function.
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: The EUSART module automatically changes the pin from tri-state to drive as needed. Configure the
associated TRIS bits for TX/CK and RX/DT to 1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 RC1REG<7:0>: Lower eight bits of the received data; read-only; see also RX9D (Register 33-2)
Note 1: RCREG (including the 9th bit) is double buffered, and data is available while new data is being received.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 TX1REG<7:0>: Lower eight bits of the received data; read-only; see also RX9D (Register 33-1)
Note 1: TXREG (including the 9th bit) is double buffered, and can be written when previous data has started
shifting.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-0 SP1BRG<7:0>: Lower eight bits of the Baud Rate Generator
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Note 1: SPBRGH value is ignored for all modes unless BAUD1CON<BRG16> is active.
2: Writing to SPBRGH resets the BRG counter.
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303
1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575
2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215
1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303
2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151
9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287
10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264
19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47
115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —
Rev. 10-000261A
9/10/2015
CLKRDIV<2:0>
CLKREN Counter Reset
128
111
CLKREN
D Q 000
CLKRCLK<3:0>
FREEZE ENABLED(1) EN
ICD FREEZE MODE(1)
P1 P2
FOSC
CLKREN
CLKR Output
CLKRDIV[2:0] = 001
Duty Cycle
CLKRDC[1:0] = 10
(50%)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
Pin 1 Indicator
Pin Description*
1 1 = VPP/MCLR
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
External
Programming VDD Device to be
Signals Programmed
VDD VDD
VPP MCLR/VPP
VSS VSS
Data ICSPDAT
Clock ICSPCLK
* * *
To Normal Connections
OPCODE only
13 0
OPCODE
CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW – Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW – Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP – No Operation 1 00 0000 0000 0000
RESET – Software device Reset 1 00 0000 0000 0001
SLEEP – Go into Standby or IDLE mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
register f C
ADDWFC ADD W and CARRY bit to f
Syntax: [ label ] ADDWFC f {,d}
Operands: 0 f 127
d [0,1]
Operation: (W) + (f) + (C) dest
Status Affected: C, DC, Z
Description: Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
LSRF Logical Right Shift
W = value in FSR register
Syntax: [ label ] LSRF f {,d} Z = 1
Operands: 0 f 127
d [0,1]
Operation: 0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0 register f C
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE k
Description: This instruction is used to move data
between W and one of the indirect Operands: None
registers (INDFn). Before/after this Operation: TOS PC,
move, the pointer (FSRn) is updated by 1 GIE
pre/post incrementing/decrementing it. Status Affected: None
Note: The INDFn registers are not Description: Return from Interrupt. Stack is POPed
physical registers. Any instruction that and Top-of-Stack (TOS) is loaded in
accesses an INDFn register actually the PC. Interrupts are enabled by
accesses the register at the address setting Global Interrupt Enable bit,
specified by the FSRn. GIE (INTCON<7>). This is a 2-cycle
instruction.
FSRn is limited to the range Words: 1
0000h-FFFFh.
Incrementing/decrementing it beyond Cycles: 2
these bounds will cause it to Example: RETFIE
wrap-around. After Interrupt
PC = TOS
The increment/decrement operation on GIE = 1
FSRn WILL NOT affect any Status bits.
C=0 Wf
C=1 Wf
DC = 0 W<3:0> f<3:0>
DC = 1 W<3:0> f<3:0>
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 37-6 to calculate device
specifications.
2: Power dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + VDD - VOH) x IOH} + VOI x IOL
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
5.5
VDD (V)
2.5
2.3
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table for each Oscillator mode’s supported frequencies.
3.6
2.5
1.8
0 4 10 16 32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table for each Oscillator mode’s supported frequencies.
PIC16F18854
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
Supply Voltage
D002 VDD 1.8 — 3.6 V FOSC 16 MHz
2.5 — 3.6 V FOSC 16 MHz
D002 VDD 2.3 — 5.5 V FOSC 16 MHz
2.5 — 5.5 V FOSC 16 MHz
RAM Data Retention(1)
D003 VDR 1.5 — — V Device in Sleep mode
D003 VDR 1.5 — — V Device in Sleep mode
Power-on Reset Release Voltage(2)
D004 VPOR — 1.6 — V BOR or LPBOR disabled(3)
D004 VPOR — 1.6 — V BOR or LPBOR disabled(3)
Power-on Reset Rearm Voltage(2)
D005 VPORR — 0.8 — V BOR or LPBOR disabled(3)
D005 VPORR — 1.2 — V BOR or LPBOR disabled(3)
VDD Rise Rate to ensure internal Power-on Reset signal(2)
D006 SVDD 0.05 — — V/ms BOR or LPBOR disabled(3)
D006 SVDD 0.05 — — V/ms BOR or LPBOR disabled(3)
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: See Figure 37-3, POR and POR REARM with Slow Rising VDD.
3: Please see Table 37-11 for BOR and LPBOR trip point information.
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
TVLOW(3) TPOR(2)
PIC16F18854
Param. Conditions
Symbol Device Characteristics Min. Typ.† Max. Units
No. VDD Note
D100 IDDXT4 XT = 4 MHz — 400 600 A 3.0V
D100 IDDXT4 XT = 4 MHz — 450 700 A 3.0V
D101 IDDHFO16 HFINTOSC = 16 MHz — 1.8 2.6 mA 3.0V
D101 IDDHFO16 HFINTOSC = 16 MHz — 1.9 2.7 mA 3.0V
D102 IDDHFOPLL HFINTOSC = 32 MHz — 2.6 3.6 mA 3.0V
D102 IDDHFOPLL HFINTOSC = 32 MHz — 2.7 3.7 mA 3.0V
D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.6 3.6 mA 3.0V
D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.7 3.7 mA 3.0V
D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.05 — mA 3.0V
D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.15 — mA 3.0V
D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.1 — mA 3.0V
D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.2 — mA 3.0V
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switch-
ing rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.
3: IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (Register 8-2).
4: PMD bits are all in the default state, no modules are disabled.
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
VIL Input Low Voltage
I/O PORT:
D300 with TTL buffer — — 0.8 V 4.5V VDD 5.5V
D301 — — 0.15 VDD V 1.8V VDD 4.5V
D302 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V VDD 5.5V
D303 with I2C levels — — 0.3 VDD V
D304 with SMBus levels — — 0.8 V 2.7V VDD 5.5V
D305 MCLR — — 0.2 VDD V
VIH Input High Voltage
I/O PORT:
D320 with TTL buffer 2.0 — — V 4.5V VDD 5.5V
D321 0.25 VDD + — — V 1.8V VDD 4.5V
0.8
D322 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V VDD 5.5V
D323 with I2C levels 0.7 VDD — — V
D324 with SMBus levels 2.1 — — V 2.7V VDD 5.5V
D325 MCLR 0.7 VDD — — V
IIL Input Leakage Current(1)
D340 I/O Ports — ±5 ± 125 nA VSS VPIN VDD,
Pin at high-impedance, 85°C
D341 — ±5 ± 1000 nA VSS VPIN VDD,
Pin at high-impedance, 125°C
D342 MCLR(2) — ± 50 ± 200 nA VSS VPIN VDD,
Pin at high-impedance, 85°C
IPUR Weak Pull-up Current
D350 25 120 200 A VDD = 3.0V, VPIN = VSS
VOL Output Low Voltage
D360 I/O ports — — 0.6 V IOL = 10.0mA, VDD = 3.0V
VOH Output High Voltage
D370 I/O ports VDD - 0.7 — — V IOH = 6.0 mA, VDD = 3.0V
D380 CIO All I/O pins — 5 50 pF
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Param.
Sym. Characteristic Typ. Units Conditions
No.
TH01 JA Thermal Resistance Junction to Ambient 60 C/W 28-pin SPDIP package
80 C/W 28-pin SOIC package
90 C/W 28-pin SSOP package
27.5 C/W 28-pin UQFN 4x4 mm package
27.5 C/W 28-pin QFN 6x6mm package
TH02 JC Thermal Resistance Junction to Case 31.4 C/W 28-pin SPDIP package
24 C/W 28-pin SOIC package
24 C/W 28-pin SSOP package
24 C/W 28-pin UQFN 4x4mm package
24 C/W 28-pin QFN 6x6mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature
Rev. 10-000133A
8/1/2013
Load Condition
Pin
CL
VSS
Q4 Q1 Q2 Q3 Q4
CLKIN
OS1 OS2 OS2
OS20
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
ECL Oscillator
OS1 FECL Clock Frequency — — 500 kHz
OS2 TECL_DC Clock Duty Cycle 40 — 60 %
ECM Oscillator
OS3 FECM Clock Frequency — — 8 MHz
OS4 TECM_DC Clock Duty Cycle 40 — 60 %
ECH Oscillator
OS5 FECH Clock Frequency — — 32 MHz
OS6 TECH_DC Clock Duty Cycle 40 — 60 %
LP Oscillator
OS7 FLP Clock Frequency — — 100 kHz Note 4
XT Oscillator
OS8 FXT Clock Frequency — — 4 MHz Note 4
HS Oscillator
OS9 FHS Clock Frequency — — 20 MHz Note 4
System Oscillator
OS20 FOSC System Clock Frequency — — 32 MHz (Note 2, Note 3)
OS21 FCY Instruction Frequency — FOSC/4 — MHz
OS22 TCY Instruction Period 125 1/FCY — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in Section 6.0 “Oscil-
lator Module (with Fail-Safe Clock Monitor)”.
3: The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 37.2 “Standard
Operating Conditions”.
4: LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking
the device with the external square wave, one of the EC mode selections must be used.
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
OS50 FHFOSC Precision Calibrated HFINTOSC — 4 — MHz (Note 2)
Frequency 8
12
16
32
OS51 FHFOSCLP Low-Power Optimized HFINTOSC — 1 — MHz
Frequency — 2 — MHz
OS52 FMFOSC Internal Calibrated MFINTOSC — 500 — kHz
Frequency
OS53* FLFOSC Internal LFINTOSC Frequency — 31 — kHz (Note 3)
OS54* THFOSCST HFINTOSC — 11 20 s VREGPM = 0(4)
Wake-up from Sleep Start-up — 50 — s VREGPM = 1(4)
Time
OS56 TLFOSCST LFINTOSC — 0.2 — ms
Wake-up from Sleep Start-up Time
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 37-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Tempera-
ture, Figure 38-78 HFINTOSC Typical Frequency Error, PIC16LF18854 Only and Figure 38-79 HFINTOSC
Typical Frequency Error, PIC16F18854 Only.
3: See Figure 38-7 LFINTOSC Frequency, PIC16LF18854 Only and Figure 38-8: LFINTOSC Frequency,
PIC16F18854 only.
4: On LF devices, the VREGPM bit is unimplemented. On LF devices, the VREGPM=0 parameter applies
when either the FVR or BOR are active in Sleep and the VREGPM=1 parameter applies when neither are
active in Sleep.
125
± 5%
85
± 3%
Temperature (°C)
60
± 2%
0
± 5%
-40
1.8 2.0 2.3 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VDD
MCLR
RST01
Internal
POR
RST04
PWRT
Time-out RST05
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
RST03
RST02
RST02
I/O pins
VDD
VBOR and VHYST
VBOR
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms
delay if PWRTE = 0.
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
Param.
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
AD20 TAD ADC Clock Period 1 — 9 s Using FOSC as the ADC clock
source ADOCS = 0
AD21 1 2 6 s Using FRC as the ADC clock
source ADOCS = 1
AD22 TCNV Conversion Time — 11+3TCY — TAD Set of GO/DONE bit to Clear of
GO/DONE bit
AD23 TACQ Acquisition Time — 2 — s
AD24 THCD Sample and Hold Capacitor — — — s FOSC-based clock source
Disconnect Time FRC-based clock source
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Rev. 10-000321A
12/16/2016
AD24 AD22
Q4
AD20
ADC_clk
ADC Data 9 8 7 6 3 2 1 0
ADIF 1 TCY
GO DONE
Sampling Stopped
Sample AD23
Rev. 10-000328A
3/20/2017
AD24 AD22
Q4
AD21
ADC_clk
ADC Data 9 8 7 6 3 2 1 0
ADIF 1 TCY
GO DONE
Sampling Stopped
Sample AD23
Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage — — ±30 mV VICM = VDD/2
CM02 VICM Input Common Mode Range GND — VDD V
CM03 CMRR Common Mode Input Rejection Ratio — 50 — dB
CM04 VHYST Comparator Hysteresis 15 25 35 mV
CM05 TRESP(1) Response Time, Rising Edge — 300 600 ns
Response Time, Falling Edge — 220 500 ns
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD.
2: A mode change includes changing any of the control register values, including module enable.
Param.
Sym. Characteristics Min. Typ. Max. Units Comments
No.
Param.
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
FVR01 VFVR1 1x Gain (1.024V) -4 — +4 % VDD 2.5V, -40°C to 85°C
FVR02 VFVR2 2x Gain (2.048V) -4 — +4 % VDD 2.5V, -40°C to 85°C
FVR03 VFVR4 4x Gain (4.096V) -5 — +5 % VDD 4.75V, -40°C to 85°C
FVR04 TFVRST FVR Start-up Time — 25 — us
Param.
Sym. Characteristics Min Typ† Max Units Comments
No.
ZC01 VPINZC Voltage on Zero Cross Pin — 0.75 — V
ZC02 IZCD_MAX Maximum source or sink current — — 600 A
ZC03 TRESPH Response Time, Rising Edge — 1 — s
TRESPL Response Time, Falling Edge — 1 — s
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
CC01 CC02
CC03
CK
US121 US121
DT
US120 US122
Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US120 TCKH2DTV SYNC XMIT (Master and Slave) — 80 ns 3.0V VDD 5.5V
Clock high to data-out valid — 100 ns 1.8V VDD 5.5V
US121 TCKRF Clock out rise time and fall time — 45 ns 3.0V VDD 5.5V
(Master mode) — 50 ns 1.8V VDD 5.5V
US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V VDD 5.5V
— 50 ns 1.8V VDD 5.5V
CK
US125
DT
US126
Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-setup before CK (DT hold time) 10 — ns
US126 TCKL2DTL Data-hold after CK (DT hold time) 15 — ns
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP75, SP76
SP74
SP73
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SP78
SP75, SP76
SP74
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP74
SP73
SP82
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SCK
(CKP = 1)
SP80
SP77
SP75, SP76
SDI
MSb In bit 6 - - - -1 LSb In
SP74
Param.
Symbol Characteristic Min. Typ† Max. Units Conditions
No.
SCL
SP91 SP93
SP90 SP92
SDA
Start Stop
Condition Condition
Param.
Symbol Characteristic Min. Typ Max. Units Conditions
No.
SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Start
Setup time 400 kHz mode 600 — — condition
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first clock
Hold time 400 kHz mode 600 — — pulse is generated
SCL
SP90
SP106
SP107
SP91 SP92
SDA
In
SP110
SP109
SP109
SDA
Out
Param.
Symbol Characteristic Min. Max. Units Conditions
No.
SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY —
SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns
time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10-400 pF
SP103* TF SDA and SCL fall time 100 kHz mode — 250 ns
400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1)
clock 400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free
400 kHz mode 1.3 — s before a new transmission
can start
SP111 CB Bus capacitive loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement
TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of
the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL
line is released.
6 3.0
4 2.0
VOH (V)
VOL (V)
3 1.5
25°C
Typical
yp
125°C 125°C -40°C
2 1.0
1 0.5
0 0.0
-45 -40 -35 -30 -25 -20 -15 -10 -5 0 0 5 10 15 20 25 30 35 40 45 50 55 60
FIGURE 38-1: VOH vs. IOH Over FIGURE 38-4: VOL vs. IOL Over
Temperature, VDD = 5.0V, PIC16F18854 Only. Temperature, VDD = 3.0V.
5 2.0
Graph represents 3ı Limits
1.8
Graph represents 3ı Limits
4 1.6
1.4
-40°C
3 1.2
125°C
VOH (V)
VOL (V)
1.0
Typical
0.8
2
25°C
0.6
125°C -40°C
0.4
1
0.2
02
0.0
0 -8 -7.5 -7 -6.5 -6 -5.5 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0
0 10 20 30 40 50 60 70 80 90 100 110
IOL (mA) IOH (mA)
FIGURE 38-2: VOL vs. IOL Over FIGURE 38-5: VOH vs. IOH Over
Temperature, VDD = 5.0V, PIC16F18854 Only. Temperature, VDD = 1.8V, PIC16LF18854 Only.
3.5 1.8
2.0 1
VOH (V)
-40°C
0.8
15
1.5
Typical 125°C 0.6
1.0
0.4
0.5 0.2
02
0.0 0
-30 -25 -20 -15 -10 -5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
FIGURE 38-3: VOH vs. IOH Over FIGURE 38-6: VOL vs. IOL Over
Temperature, VDD = 3.0V. Temperature, VDD = 1.8V, PIC16LF18854 Only.
36,000
4.2
35,000
34,000 4.1
33,000
Frequency (Hz)
ms)
Time (m
32,000 40
4.0
31,000
30,000 3.9
29,000
28,000 3.8
1.7 2.0 2.3 2.6 2.9 3.2 3.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Typical 25°C
25 C +3 Sigma (-40°C
(-40 C to 125
125°C)
C) -3 Sigma (-40°C
(-40 C to 125°C)
125 C) Typical 25°C +3ı (-40°C to +125°C) -3ı (-40°C to +125°C)
36,000
35,000
34,000
33,000
Frequency (Hz)
32,000
31,000
30,000
29,000
28,000
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)
4.2
4.1
ms)
Time (m
40
4.0
3.9
3.8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 38-9: WDT Time-Out Period, FIGURE 38-12: Brown-Out Reset Hysteresis,
PIC16F18854 Only. Low Trip Point (BORV = 00).
2.10
2.05
2.00
1.95
Voltage (V)
1.90
1.85
1.80
1.75
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
50.0
45.0
40.0
35.0
30.0
Voltage (mV)
25.0
20.0
15.0
10.0
5.0
0.0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
+3 Sigma Typical
75.0
73.0
71.0
69.0
Time (ms)
67.0
65.0
63.0
61.0
59.0
57.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
1.7
+3 Sigma
1.675
1.65 Typical
Voltage (V)
1.625
-3 Sigma
1.6
1.575
1.55
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
FIGURE 38-20: LPBOR Reset Hysteresis, FIGURE 38-23: POR Release Voltage.
PIC16LF18854 Only.
1.6
1.8 Typical
Max: Typical + 3ı
1.4 +3 Sigma
1.7 Typical: 25°C
74.0 Min: Typical - 3ı
1.2
1.6
72.0 1
(V) (V)
Voltage
1.5
0.8 Typical
70.0
Voltage
0.6
1.4
Time (ms)
68.0
0.4 -3 Sigma
1.3
66.0 0.2
1.2
0
64.0
-40 -20 0 20 40 60 80 100 120
1.1
Temperature (°C)
62.0
1
60.0 -40 -20 0 20 40 60 80 100 120
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Temperature (°C)
VDD (V)
1.6
1.8 Typical 120
Max: Typical + 3ı
1.4
1.7 Typical: 25°C 110
Min: Typical - 3ı
1.2
1.6 +3 Sigma
100
1.5
1 90
(V) (V)
1.4
Voltage
0.8 80
Time (us)
1.3
Voltage
0.6 Typical 70
1.2
0.4 60
1.1
0.2 50
1 -3 Sigma
40
0
0.9 -40 -20 0 20 40 60 80 100 120 30
0.8 Temperature (°C)
20
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.7
-40 -20 0 20 40 60 80 100 120 VDD (V)
Temperature (°C)
( C) Typical 25°C +3ı (-40°C to +125°C)
FIGURE 38-25: POR Rearm Voltage, FIGURE 38-28: Wake From Sleep,
VREGPM1 = 1, PIC16F18854 Only. VREGPM = 1, HFINTOSC = 4 MHz,
PIC16F18854 Only.
1.8
28
+3 Sigma
1.6
27
1.4 26
Voltage (V)
Typical 25
Time (us)
1.2
24
1
23
-3 Sigma
0.8 22
21
0.6
-40 -20 0 20 40 60 80 100 120 20
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Temperature (°C)
VDD (V)
FIGURE 38-26: POR Rearm Voltage, Typical 25°C +3ı (-40°C to +125°C)
Normal Power Mode, PIC16LF18854 Only. FIGURE 38-29: Wake From Sleep,
VREGPM = 0, HFINTOSC = 16 MHz,
18
PIC16F18854 Only.
17
120
16 110
Time (us)
100
15
90
Time (us)
14
80
13 70
60
12
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
50
VDD (V)
Typical 25°C +3ı (-40°C to +125°C)
40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FIGURE 38-27: Wake From Sleep, VDD (V)
700 1.0
650
600 0.5
550
DNL (LSb)
Time (us)
500 0.0
450
400
-0.5
350
300
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 -1.0
0 128 256 384 512 640 768 896 1024
VDD (V)
Output Code
Typical 25°C + 3ı (-40°C to +125°C)
FIGURE 38-31: Wake From Sleep, FIGURE 38-34: ADC, DNL, VDD = 3.0V,
VREGPM = 1, LFINTOSC, PIC16F18854 Only. TAD = 4 S, 25°C.
700
1.0
650
600
0.5
550
INL (LSb)
Time (us)
500
0.0
450
400
-0.5
350
300
1.7 2.2 2.7 3.2 3.7 -1.0
0 128 256 384 512 640 768 896 1024
VDD (V)
Output Code
Typical 25°C + 3ı (-40°C to +125°C)
FIGURE 38-32: Wake From Sleep, FIGURE 38-35: ADC, INL, VDD = 3.0V,
LFINTOSC, PIC16LF18854 Only. TAD = 1 S, 25°C.
1.0 1.0
0.5 0.5
INL (LSb)
DNL (LSb)
0.0 0.0
-0.5 -0.5
-1.0 -1.0
0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024
FIGURE 38-33: ADC, DNL, VDD = 3.0V, FIGURE 38-36: ADC, INL, VDD = 3.0V,
TAD = 1 S, 25°C. TAD = 4 S, 25°C.
1.5 1.5
1 1
Max
Max 0.5
0.5
INL (LSb)
DNL (LSb)
0 0
-0.5 -0.5
Min
Min
-1 -1
-1.5 -1.5
5.00E-07 1.00E-06 2.00E-06 4.00E-06 8.00E-06 1.8 2.3 3.0
TAD (S) VREF
FIGURE 38-37: ADC 10-bit Mode, FIGURE 38-40: ADC 10-bit Mode,
Single-Ended DNL, VDD = 3.0V, VREF = 3.0V. Single-Ended INL, VDD = 3.0V, TAD = 1 S.
900
800
1.5
700
1 600
300
0
200
ADC VREF+ set to VDD
-0.5 100 ADC VREF- set to Gnd
Min
0
-1 2.9 3.4 3.9 4.4 4.9 5.4
VDD (V)
1,000
1.5 900
1 800
ADC Output Codes
Max 700
0.5
DNL (LSb)
600
0
500
Min
-1 300
2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4
VDD (V)
-1.5 Typical +3 Sigma -3 Sigma
1.8 2.3 3.0
VREF FIGURE 38-42: Temp. Indicator Initial Offset,
FIGURE 38-39: ADC 10-bit Mode, Low Range, Temp. = 20°C, PIC16F18854 Only.
Single-Ended DNL, VDD = 3.0V, TAD = 1 S.
900 250
200
800
150
700
100
600 50
0
500
-50
400
-100 ADC VREF+ set to VDD
ADC VREF+ set to VDD
ADC VREF- set to Gnd
ADC VREF- set to Gnd
300 -150
2.2 2.5 2.8 3.1 3.4 3.7 -40 -20 0 20 40 60 80 100 120
VDD (V) Temperature (°C)
FIGURE 38-43: Temp. Indicator Initial Offset, FIGURE 38-46: Temp. Indicator Slope
Low Range, Temp. = 20°C, PIC16LF18854 Only. Normalized to 20°C, High Range, VDD = 3.0V.
150
125 120
100 100
75 80
ADC Output Codes
50 60
0
20
-25
0
-50 ADC VREF+ set to VDD
ADC VREF- set to Gnd -20
-75 ADC VREF+ set to VDD
-40 -20 0 20 40 60 80 100 120 -40 ADC VREF- set to Gnd
Normalized to 20°C, High Range, VDD = 5.5V, FIGURE 38-47: Temp. Indicator Slope
PIC16F18854 Only. Normalized to 20°C, Low Range, VDD = 3.6V.
230
150
180
100
130
ADC Output Codes
80
50
ADC Output Codes
30
0
-20
FIGURE 38-45: Temp. Indicator Slope FIGURE 38-48: Temp. Indicator Slope
Normalized to 20°C, High Range, VDD = 3.6V. Normalized to 20°C, Low Range, VDD = 3.0V.
200
30
25
150
20
100 15
10
50 5
0
0
-5
-10
-50 MIN
ADC VREF+ set to VDD -15
ADC VREF- set to Gnd
-100 -20
-40 -20 0 20 40 60 80 100 120 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Temperature (°C)
Typical +3 Sigma -3 Sigma Common Mode Voltage (V)
43 50
-40°C
41
39 45
Hysteresis (mV)
25°C
37
Hysteresis (mV)
85°C 40
35 25°C
125° 125°
33 35
31
85°
29 30
27 -40°C
25
25
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
20
Common Mode Voltage (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
NP Mode (CxSP = 1), VDD = 3.0V, Typical FIGURE 38-53: Comparator Hysteresis,
Measured Values. NP Mode (CxSP = 1), VDD = 5.5V, Typical
Measured Values, PIC16F18854 Only.
30
25
30
20
25
15
Offset Voltage (mV)
20
10
MAX 15
Hysteresis (mV)
5 MAX
10
0
5
-5
0
MIN
-10
-5
-15
-10
MIN
-20
-15
0.0 0.5 1.0 1.5 2.0 2.5 3.0
-20
Common Mode Voltage (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
NP Mode (CxSP = 1), VDD = 3.0V, Typical FIGURE 38-54: Comparator Offset, NP Mode
Measured Values at 25°C. (CxSP = 1), VDD = 5.0V, Typical Measured Values
at 25°C, PIC16F18854 Only.
0.025
40
0.02
30
0.015
Offset Voltage (mV)
20 0.01
DNL (LSb)
MAX 0.005
-40°C
10
25°C
0
85°C
0
-0.005 125°C
-0.01
-10
MIN
-0.015
-20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0.02
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
Common Mode Voltage (V) Output Code
FIGURE 38-55: Comparator Offset, NP Mode FIGURE 38-58: Typical DAC DNL Error,
(CxSP = 1), VDD = 5.5V, Typical Measured Values VDD = 3.0V, VREF = External 3V.
from -40°C to 125°C, PIC16F18854 Only.
140 0.00
Max: Typical + 3ı (-40°C to +125°C)
120 Typical; statistical mean @ 25°C -0.05
Min: Typical - 3ı (-40°C to +125°C)
-0.10
100
125°C -0.15
Time (nS)
80
INL (LSb)
-0.20
25°C -40°C
60 25°C
-0.25
85°C
40 -0.30 125°C
-40°C
-0.35
20
-0.40
0
1.7 2.0 2.3 2.6 2.9 3.2 3.5
-0.45
0 14 28 42 56 70 84 98 112126140154168182196210224238252
VDD (V)
Output Code
FIGURE 38-56: Comparator Response Time FIGURE 38-59: Typical DAC INL Error,
Over Voltage, NP Mode (CxSP = 1), Typical VDD = 3.0V, VREF = External 3V.
Measured Values, PIC16LF18854 Only.
0.020
90
0.015
Max: Typical + 3ı (-40°C to +125°C)
80 Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
0.010
70
125°C
60
DNL (LSb)
0.005
-40°C
Time (nS)
50 25°C
25°C 0.000
85°C
40
125°C
30 -0.005
20
-0.010
-40°C
10
-0.015
0 0 14 28 42 56 70 84 98 112126140154168182196210224238252
2.2 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 Output Code
VDD (V)
FIGURE 38-60: Typical DAC DNL Error,
FIGURE 38-57: Comparator Response Time VDD = 5.0V, VREF = External 5V, PIC16F18854
Over Voltage, NP Mode (CxSP = 1), Typical Only.
Measured Values, PIC16F18854 Only.
0.00 4.0
-0.05 3.5
-0.10 3.0
-0.15 2.5
Time (us)
INL (LSb)
-0.20 2.0
-40°C
25°C
-0.25 1.5
85°C
-0.30 125°C 1.0
-0.35 0.5
-0.40 0.0
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
-0.45 VDD (V)
0 14 28 42 56 70 84 98 112126140154168182196210224238252
Output Code Typical 25°C +3ı (-40°C to +125°C) -3ı (-40°C to +125°C)
FIGURE 38-61: Typical DAC INL Error, FIGURE 38-64: ADC RC Oscillator Period,
VDD = 5.0V, VREF = External 5V, PIC16F18854 PIC16F18854 Only.
Only.
24
70
22
Max.
60
20
50
DNL (LSb)
18 Time (us)
Typical 40
16
30
14
FIGURE 38-62: DAC INL Error, FIGURE 38-65: Bandgap Ready Time,
VDD = 3.0V, PIC16LF18854 Only. PIC16LF18854 Only.
5.0
5.0
4.5
4.5
4.0
4.0
3.5
3.5
3.0
Time (us)
3.0
Time (us)
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0.0
0.0
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
VDD (V)
VDD (V)
Typical 25°C
25 C +3ı (-40
(-40°C
C to +125
+125°C)
C) -3ı (-40
(-40°C
C to +125
+125°C)
C)
Typical 25°C +3 Sigma 125°C
FIGURE 38-63: ADC RC Oscillator Period, FIGURE 38-66: BOR Response Time,
PIC16LF18854 Only. PIC16LF18854 Only.
7 700
6 600
5 500
Time (us)
Time (ns)
4 400
3 300
200
2
100
1
0
0 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)
VDD (V)
Typical 25°C +3 Sigma 125°C Typical 25°C +3 Sigma 125°C
FIGURE 38-67: BOR Response Time, FIGURE 38-70: Comparator Response Time,
PIC16F18854 Only. Rising Edge, PIC16LF18854 Only.
300 900
800
250
700
200 600
Time (ns)
Time (ns)
500
150
400
100 300
200
50
100
0 0
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
FIGURE 38-68: Comparator Response Time, FIGURE 38-71: Comparator Response Time,
Falling Edge, PIC16LF18854 Only. Rising Edge, PIC16F18854 Only.
250
70
200 60
50
150
Time (ns)
40
Time (us)
100 30
20
50
10 Note:
The FVR Stabiliztion Period applies when coming out of
RESET or exiting sleep mode.
0 0
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
FIGURE 38-69: Comparator Response Time, FIGURE 38-72: FVR Stabilization Period,
Falling Edge, PIC16F18854 Only. PIC16LF18854 Only.
1.1% 1.0%
1.0%
0.8%
0.9%
0.8%
0.6%
0.7%
Error (%)
Error (%)
0.6% 0.4%
0.5%
0.4% 0.2%
0.3%
0.0%
0.2%
0.1%
-0.2%
0.0% 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
VDD (V)
VDD (V)
Typical -40°C Typical 25°C Typical 85°C Typical 125°C Typical -40°C Typical 25°C Typical 85°C Typical 125°C
FIGURE 38-73: Typical FVR Voltage 1x, FIGURE 38-76: FVR Voltage Error 2x,
PIC16LF18854 Only. PIC16F18854 Only.
1.2%
1.0%
1.0% 0.8%
0.6%
0.8%
Error (%)
Error (%)
0.4%
0.6%
0.2%
0.4%
0.0%
0.2%
-0.2%
0.0% -0.4%
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6
VDD (V) VDD (V)
Typical -40°C Typical 25°C Typical 85°C Typical 125°C
Typical -40°C
40°C Typical 25°C Typical 85°C Typical 125°C
FIGURE 38-74: FVR Voltage Error 1x, FIGURE 38-77: FVR Voltage Error 4x,
PIC16F18854 Only. PIC16F18854 Only.
1.0%
3.0%
0.8%
2.0%
0.6% 1.0%
0.0%
Error (%)
0.4%
Error (%)
-1.0%
0.2%
-2.0%
0.0%
-3.0%
-0.2%
-4.0%
-0.4% -5.0%
2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V) VDD (V)
Typical -40°C Typical 25°C Typical 85°C Typical 125°C Typical 25°C +3ı (-40°C to +125°C) -3ı (-40°C to +125°C)
FIGURE 38-75: FVR Voltage Error 2x, FIGURE 38-78: HFINTOSC Typical
PIC16LF18854 Only. Frequency Error, PIC16LF18854 Only.
2.0%
2
1.0%
Voltage (V)
1.5
0.0%
Error (%)
-1.0% 1
-2.0%
0.5
-3.0%
0
-4.0% 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
VDD (V)
VDD (V)
FIGURE 38-79: HFINTOSC Typical FIGURE 38-82: Schmitt Trigger Low Values.
Frequency Error, PIC16F18854 Only.
3.0% 1.8
2.5% 1.6
2.0% 1.4
ltage (V)
1.5% 1.2
Voltage (
1.0% 1
Error (%)
0.8
0.5%
0.6
0.0%
0.4
-0.5%
0.2
-1.0%
0
-1.5% 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-2.0% VDD (V)
-50 0 50 100 150
Typical 25°C +3ı (-40°C to +125°C) -3ı (-40°C to +125°C)
Temperature (°C)
3.5 40
35
3
30
Time (ns)
2.5
Voltage (V)
25
2
20
1.5 15
1 10
5
0.5
0
0 1.5 2.5 3.5 4.5 5.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
VDD (V)
60 4.00%
Max: Typical + 3ı (-40°C to +125°C)
50 3.00% Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
2.00%
40
Time (ns)
1 00%
1.00%
30
Error (%)
Max
0.00%
Min
20
-1.00% Average
10
-2.00%
0
-3.00%
1.5 2.5 3.5 4.5 5.5
VDD (V)
-4.00%
-32 -24 -16 -8 0 8 16 24 32
Min Center Max
Typical 25°C +3 Sigma (-40°C to 125°C) OSCTUNE Setting
FIGURE 38-85: Fall Time, Slew Rate Control FIGURE 38-88: OSCTUNE Center
Enabled. Frequency, PIC16LF18854 Only.
30
35.0
25 30.0
15 20.0
10 15.0
Pu
10.0
5
5.0
0
1.5 2.5 3.5 4.5 5.5
VDD (V) 0.0
2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
VDD (V)
Typical 25°C +3 Sigma (-40°C to 125°C)
Typical 25°C + 3ı (-40°C to +125°C) - 3ı (-40°C to +125°C)
FIGURE 38-86: Rise Time, Slew Rate FIGURE 38-89: Weak Pull-up Current,
Control Disabled. PIC16F18854 Only.
20
18
25.0
16
14
12 20.0
Time (ns)
Curre (uA)
10
Pull-Up Current
8 15.0
6
4 10.0
2
0 5.0
1.5 2.5 3.5 4.5 5.5
VDD (V)
0.0
Typical 25°C +3 Sigma (-40°C to 125°C) 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 38-87: Fall Time, Slew Rate Control
Typical 25°C + 3ı (-40°C to +125°C) - 3ı (-40°C to +125°C)
Disabled.
FIGURE 38-90: Weak Pull-up Current,
PIC16LF18854 Only.
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
PIC16F18854
/SP e3
1525017
XXXXXXXXXXXXXXXXXXXX PIC16LF18854
XXXXXXXXXXXXXXXXXXXX /SO e3
XXXXXXXXXXXXXXXXXXXX
YYWWNNN 1525017
PIC16F18854
/SS e3
1525017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
PIN 1 PIN 1
XXXXXXXX LF18854
XXXXXXXX /ML e3
YYWWNNN 1525017
525017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
NOTE 1
E1
1 2 3
A A2
L c
A1 b1
b e eB
V'" X7Y;
*" [*'" X X\ ]
X#*/ &" X ^
' B7
' ' _ _
$$J J"" 9
B"' ' _ _
#$ ' #$ `$' ; 9 99
$$J`$' ; ^
\! [' 9 9j
' ' [ 9
[$ J"" ^
V [$`$' /
[ 5 [$`$' / ^
\! 5 6 B _ _ 9
"#
!"#$%&'# *! +/#'*#"'/ '$5' ' ' $
6&'7 ' "'
9 *" "$;$ '#$* $&" ' #" " $&" ' #" "" '%$? "$
*" $' ;@
B7G B"*" '%'!#" 55' #'' "
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
1 2
b
NOTE 1
e
c
A A2
φ
A1
L1 L
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
+ ,4 " 5 7 9;9 +,"!
< $ *'' = 5$
"# H ' * "'# ' J$ 5"+ ""' J &' '$'
'' GKK555* *K J
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Revision A (01/2016)
Initial release of the document.
Revision B (06/2017)
Removed Preliminary Status - Added Char Graphs;
Updated Cover Page. Figures 6-1, 23-2, 27-1, 28-1,
29-2, 29-3, 29-8, 29-9, 29-10, 29-11, 29-12, 29-13,
32-14, 32-15, 32-18, and 37-10; Registers 4-1, 4-3,
6-3, 8-2, 9-2, 12-2, 12-4, 12-6, 12-12, 12-14, 12-16,
20-9, 23-1, 23-3, 23-4, 27-2, 28-1, 28-3, 29-1, 31-4,
31-5, 31-6, 31-7, 34-1, and 34-2; Sections 9.1, 10.4.3,
21.5, 23.1.1, 23.1.4, 23.4.4, 23.5.2, 23.5.3, 29.1, 29.2,
31.6, 32.1.1, 32.6.9, 34.2, and 34.4; Tables 10-2, 20-2,
23-1, 23-2, 31-3, 36-4, 37-3, 37-5, 37-11 and 37-13.
Added Figure 37-11. Added Section 6.2.2.4
MFINTOSC, 21.5.1 Correction by AC Coupling. Added
Section 28.4: Timer1 16-Bit Read/Write Mode.
Updated Instruction Sets MOVWF and NOP.
Removed Figure 37-11.
Revision C (01/2018)
Updated Registers 4-2 and 23-8; Sections 12.3 and
29.1; and Tables 1-2, 22-2, 29-3, 37-2, 37-3 and 37-12.
Removed Section 12.8.5 (duplicate). Corrected various
typos.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
== ISO/TS 16949 ==