Analog Electronics 2023

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SECOND SEMESTER CA EXAMINATION

Department: School of Engineering Course Title: Analogue Electronics II Course code:

Course Status: Networks and Security Duration: 2hrs Level: 100 Total Marks: 70

Lecturer: Dr. MBIEDA N. Frank Gaetan

INSTRUCTIONS:

Students are to answer all questions. Good English and orderly presentation of work is highly

Exercise 1: Bipolar Junction Transistor Amplifier (20 Marks)

Consider the NPN Silicium transistor amplifier below;

I. Static Analysis Regime


1) Determine the equivalent Circuit of the above figure corresponding to Static regime. (1
marks)
2) Determine the elements RB et VBB of the generator of the Thevenin equivalent for the
transistor at the point of polarization; (2 marks)
3) Taking  = 120 and VBE =0.7V, calculate the values of polarization, IB0, IC0 and VCE0. (5
marks)
4) Draw the DC bias line and DC load line, and determine the point of operation of the
transistor. (3 marks)

II. Dynamic Analysis Regime


1. Draw the equivalent circuit of the figure above in Dynamic regime (that is, small signal
regime). (1 mark)
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2. Calculate the value of the capacitor CE using the rule ( ). (1 mark)

3. Calculate the parameter r such that: , with IC0 in mA. (1 mark)


4. Giving that and that  = 0, compute the dynamic Equations of the transistor.
(1 mark)
5. Deduce the equivalent model of the dynamic equivalent circuit or small signal circuit. (1
mark)
6. What should be the value of Ru for the charge to receive maximum power? (1 mark)

7. iu been the current in Ru, calculate the amplification and (3 marks)

Exercise 2: Field Effect Transistor (10 Marks)

1) In the amplifier of the figure below, VDD = 20 V; R1 = 1 MΩ; R2 = 15.7 MΩ; RD = 3kΩ,
and RS = 2kΩ. For the JFET characteristics, give the Thevenin equivalent circuit of the
corresponding circuit below. (3 marks)
a) Find the equation of the transfer bias line (2 marks)
b) Find the equation of the dc load line (3 marks)
c) Find IDQ, (2 marks)

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