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    Time Allowed: Three Hours 13 June, 2016, 9am-12 Noon: Instructions To Candidates

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    This document contains instructions for a 3-hour closed book examination on computer technology consisting of 6 questions worth a total of 100 marks and accounting for 20% of the course assessment. Section A deals with digital electronics circuit design and contains questions about De Morgan's theorems, Karnaugh maps, multiplexers and the differences between combinational and sequential logic circuits. Section B covers physical electronics, including questions about n-type semiconductors, PN junction diodes, bipolar junction transistors, JFET characteristics and digital logic families.

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    Time Allowed: Three Hours 13 June, 2016, 9am-12 Noon: Instructions To Candidates

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    This document contains instructions for a 3-hour closed book examination on computer technology consisting of 6 questions worth a total of 100 marks and accounting for 20% of the course assessment. Section A deals with digital electronics circuit design and contains questions about De Morgan's theorems, Karnaugh maps, multiplexers and the differences between combinational and sequential logic circuits. Section B covers physical electronics, including questions about n-type semiconductors, PN junction diodes, bipolar junction transistors, JFET characteristics and digital logic families.

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    This document contains instructions for a 3-hour closed book examination on computer technology consisting of 6 questions worth a total of 100 marks and accounting for 20% of the course assessment. Section A deals with digital electronics circuit design and contains questions about De Morgan's theorems, Karnaugh maps, multiplexers and the differences between combinational and sequential logic circuits. Section B covers physical electronics, including questions about n-type semiconductors, PN junction diodes, bipolar junction transistors, JFET characteristics and digital logic families.

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    5 views6 pages

    Time Allowed: Three Hours 13 June, 2016, 9am-12 Noon: Instructions To Candidates

    Uploaded by

    Har
    This document contains instructions for a 3-hour closed book examination on computer technology consisting of 6 questions worth a total of 100 marks and accounting for 20% of the course assessment. Section A deals with digital electronics circuit design and contains questions about De Morgan's theorems, Karnaugh maps, multiplexers and the differences between combinational and sequential logic circuits. Section B covers physical electronics, including questions about n-type semiconductors, PN junction diodes, bipolar junction transistors, JFET characteristics and digital logic families.

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    of 6

    NATIONAL INSTITUTE OF BUSINESS MANAGEMENT

    Diploma in Computer System Design-15.3 /Software Engineering-15.2 /Computer Networks – 15.1

    Computer Technology- DCSD 104

    Time allowed: Three hours 13th June, 2016, 9am-12 noon


    INSTRUCTIONS TO CANDIDATES

     This paper contains 6 questions on 5 pages (2-6).


     The total marks obtainable for this examination is 100.
     Mark of each question is indicated.
     This examination accounts 20% for the course assessments.
     This is a closed book examination.
     Calculators are allowed.
     Answer ALL questions.

    ADDITIONAL MATERIALS

     None

    Page 1 of 6
    Section A: Digital Electronics Circuit Design

    1.
    a. Apply De Morgan’s Theorems to the following expressions and simplify:

    i. Z = A.B.  A.( A.B  A.B)

    ii. Z = ( A.B  B.C).( A.B  A.B.C  ABC)

    b. Z = F (A, B, C, D)
    Z = 1 for the minterms (3, 6, 8, 12, 13, 14)
    Z = don’t care for the minterms (2, 7, 9)
    Z = 0 for the remaining minterms

    Simplify Z using:
    i. K-map Method
    ii. Tabular Method

    c. Explain the difference between a combinational logic circuit and a sequential logic
    circuit.

    (14 Marks)

    2.
    a. A conference room has three doors and a switch by each door to control a single light in
    the room. Let X, Y, and Z denote the state of the three switches. The following conditions
    will determine if the light is switched ON or OFF.
     The light will be OFF if all switches are turned to OFF.
     If any one of the switches is turned to ON, the light will be ON.
     If two switches are turned to ON, the light will be OFF.
     If all three switches are turned to ON, the light will be ON.

    i. Determine the truth table for the system


    ii. Get the simplified:
    a) SOP
    b) POS expressions

    iii. Implement the circuit using:


    a) NAND gates only
    b) A suitable Multiplexer(s)

    b. Explain the operation of a Demultiplexer taking a 1:4 Demux as an example.


    (20 Marks)

    Page 2 of 6
    3.

    a. Draw the output waveform Q and of a positive edge triggered SR flip flop. Assume
    that the initial value of the flip flop is 0.

    Figure 1

    b. Obtain the complete truth table of a Toggle flip-flop and derive its excitation
    table.

    c. Design a 3-bit counter to count the bit sequence 0,2,5,7. Use positive-edge triggered T
    flip-flops and logic gates to implement the circuit.

    d. Three edge-triggered JK flip-flops in a synchronous circuit have the following input


    conditions.

    JA = QB KA = 1

    JB = 1 KB = QA

    JC = QB KC = 1

    Assume that the initial state is QA = 0 QB = 0 QC = 0. Find the count sequence.

    (16 Marks)

    Page 3 of 6
    Section B: Physical Electronics

    4.

    a. Explain how the n-type semi-conductors are formed (designed) using a proper structural diagram.
    b. Explain how the P-N junction (Diode) behaves in the forward biased mode.
    c. Draw a schematic diagram of half wave rectifier and explain its operation using appropriate
    waveforms.
    d. Figure 1 depicts a circuit containing a Silicon diode. The external voltage source is 10V. The
    resistor (R) is 2k ohms. Calculate followings.

    Figure 2

    i. Operating Mode of the Diode


    ii. Potential Difference across the diode
    iii. Potential Difference across the Resistor
    iv. Current passing through the diode
    (20 Marks)

    Page 4 of 6
    5.

    a. What are the two types of Bipolar Junction Transistors? Draw their circuit symbols.
    b. Consider the following circuit and obtain the operating mode of the transistor. Hence
    calculate IB, IC and VCE. Assume that the transistor is made out of Silicon.

    Material VCE(sat) VBE(sat) VBE(act) VBE(cut


    in)
    Si 0.2V 0.8V 0.7V 0.5V
    Ge 0.1V 0.3V 0.2V 0.1V

    β RB RC Vcc VBB
    100 200kΩ 2kΩ 10V 5V
    RC

    RB

    VCC

    VBB

    (15 Marks)

    Figure 3
    6.
    a. Consider the circuit in figure 4 and the characteristic curve of the JFET in figure5 .If VDD =
    12V, VGG = 1.2V, RG = 2kΩ, RD = 2kΩ.
    RD

    VDD
    RG
    VGG

    Figure 4

    Page 5 of 6
    Figure 5

    i. What is the type of the given JFET?


    ii.Indicate the three regions of the characteristic curve.
    iii.
    Calculate Gate-Source voltage.
    iv.Obtain an equation for the load line of the circuit and plot it over the given
    characteristic curve.
    v. Hence identify the operating mode of the JFET and find the coordinate of the
    operating point.

    b) There are many digital logic families.


    a. Explain two important characteristics of Digital Logic Families briefly.

    b. Consider the following digital logic circuit. Then identify its logic family and
    show that it is a NOR gate by using suitable truth table.

    (15 Marks)
    Figure 6

    Page 6 of 6

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