S-35770

COUNTER IC

www.ablic.com
COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
© ABLIC Inc., 2019 Rev.1.0_00

The counter IC allows for counting externally input clocks.

The counter of the S-35770 is a 24-bit binary-up counter. The counter data can be read via a 2-wire serial interface.

 Features
• External clock signal count function: Countable from 0 to 16,777,215, with output pin for counter loop flag
• Low current consumption: 0.01 μA typ. (VDD = 3.0 V, Ta = +25°C, out of communication (CLKIN pin = 0 V))
• Wide range of operation voltage: 1.5 V to 5.5 V
• 2-wire (I2C-bus) CPU interface
• Operation temperature range: Ta = −40°C to +85°C
• Lead-free (Sn 100%), halogen-free

 Applications
• Various measurement equipment
• Infrastructure-related meter
• Amusement equipment
• Life counter

 Package
• TMSOP-8

1
COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
S-35770 Rev.1.0_00

 Block Diagram

Counter
CLKIN (24-bit) LOOP

Count register
N.C.
(24-bit)

Free register
(24-bit)

SDA

Serial interface VDD

SCL Power-on
detection
circuit

VSS
RST Internal reset signal

Figure 1

2
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
Rev.1.0_00 S-35770

 Product Name Structure

1. Product name

S-35770 E 01 I - K8T2 U

Environmental code
U: Lead-free (Sn 100%), halogen-free

Package abbreviation and IC packing specification*1

K8T2: TMSOP-8, Tape

Operation temperature
I: Ta = −40°C to +85°C

Fixed value

Fixed value
Product name

*1. Refer to the tape drawing.

2. Package
Table 1 Package Drawing Codes

Package Name Dimension Tape Reel

TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD

3. Product name list

Table 2
_______
Product Name RST Pin LOOP Pin Output Form LOOP Pin Output*1
S-35770E01I-K8T2U Without pull-up resistor CMOS output "L"
*1. The output status at power-on.

3
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
S-35770 Rev.1.0_00

 Pin Configuration
1. TMSOP-8
Table 3 List of Pins
Top view
Pin No. Symbol Description I/O Configuration
1 8 _______
Input pin for CMOS input
2 7 1 RST Input
3 6 reset signal (without pull-up resistor)
4 5 2 NC*1 No connection − −
Input pin for
Figure 2 3 CLKIN Input CMOS input
external clock
4 VSS GND pin − −
Output pin for
5 LOOP Output CMOS output
counter loop flag
I/O pin for serial Nch open-drain output,
6 SDA Bi-directional
data CMOS input
Input pin for
7 SCL Input CMOS input
serial clock
Pin for positive
8 VDD − −
power supply

*1. The NC pin is electrically open.

Therefore, leave it open or connect it to VDD pin or VSS pin.

4
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
Rev.1.0_00 S-35770

 Pin Functions
1. SDA (I/O for serial data) pin
This is a data input / output pin for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with a clock
pulse from the SCL pin. This pin has CMOS input and Nch open-drain output. Generally in use, the SDA pin is pulled
up to VDD potential via a resistor, and is used with wired-OR connection of other device of Nch open-drain output or
open collector output.

2. SCL (Input for serial clock) pin

This is a clock input pin for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with this clock
_______
3. RST (Input for reset signal) pin
_______
This
_______
pin inputs the reset signal. The counter is reset when inputting "L" to the RST pin. When inputting "H" to the
RST pin, the _______
count-up action of the counter is started.
Besides, the RST pin has no pull-up resistor.

4. CLKIN (Input for external clock) pin

This pin inputs an external clock. The counter is incremented by 1 when the CLKIN pin input changes from "L" to "H".

5. LOOP (Output for counter loop flag) pin

Each time the counter loops back to 0 after reaching 16,777,215, the LOOP pin performs a toggle operation.
Regarding the operation of the LOOP pin, refer to " LOOP Pin".
Besides, the LOOP pin output form is CMOS output.

6. VDD (Positive power supply) pin

Connect this pin with a positive power supply. Regarding the values of voltage to be applied, refer to
" Recommended Operation Condition".

7. VSS pin
Connect this pin to GND.

5
COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
S-35770 Rev.1.0_00

 Equivalent Circuits of Pins

SDA
CLKIN, SCL

Figure 3 CLKIN Pin and SCL Pin Figure 4 SDA Pin

_______
RST LOOP

_______
Figure 5 RST Pin Figure 6 LOOP Pin

6
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
Rev.1.0_00 S-35770

 Absolute Maximum Ratings

Table 4

Item Symbol Applied Pin Absolute Maximum Rating Unit

Power supply voltage VDD − _______
VSS − 0.3 to VSS + 6.5 V
Input voltage VIN CLKIN, SDA, SCL, RST VSS − 0.3 to VSS + 6.5 V
SDA VSS − 0.3 to VSS + 6.5 V
Output voltage VOUT
LOOP VSS − 0.3 to VDD + 0.3 ≤ VSS + 6.5 V
Operation ambient temperature*1 Topr − −40 to +85 °C
Storage temperature Tstg − −55 to +150 °C
*1. Conditions with no condensation or frost. Condensation or frost causes short-circuiting between pins, resulting in a
malfunction.

Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.

 Recommended Operation Condition

Table 5
(VSS = 0 V)
Item Symbol Condition Min. Typ. Max. Unit
Operation power supply voltage VDD Ta = −40°C to +85C 1.5 − 5.5 V

7
COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
S-35770 Rev.1.0_00

 DC Electrical Characteristics
Table 6
(Ta = −40°C to +85°C, VSS = 0 V)
Item Symbol Applied Pin Condition Min. Typ. Max. Unit
VDD = 3.0 V,
Current Out of communication
IDD1 − − 0.01 0.1 μA
consumption 1 (CLKIN pin = 0 V),
LOOP pin = no load
VDD = 3.0 V,
Current fSCL = 1 MHz,
IDD2 − − 170 300 μA
consumption 2 During communication,
LOOP pin = no load
High level input CLKIN, SDA, SCL,
IIZH _______
VIN = VDD −0.5 − 0.5 μA
leakage current RST
Low level input CLKIN, SDA, SCL,
IIZL _______
VIN = VSS −0.5 − 0.5 μA
leakage current RST
High level output
IOZH SDA VOUT = VDD −0.5 − 0.5 μA
leakage current
Low level output
IOZL SDA VOUT = VSS −0.5 − 0.5 μA
leakage current
High level input CLKIN, SDA, SCL,
VIH _______
− 0.7 × VDD − VSS + 5.5 V
voltage RST
Low level input CLKIN, SDA, SCL,
VIL _______
− VSS − 0.3 − 0.3 × VDD V
voltage RST
Low level output
VOL SDA IOL = 2.0 mA − − 0.4 V
voltage

8
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
Rev.1.0_00 S-35770

 AC Electrical Characteristics
Table 7 Measurement Conditions Input pulse voltage Output reference voltage
VIH = 0.8 × VDD, 0.8 × VDD
Input pulse voltage
VIL = 0.2 × VDD 0.7 × VDD
Input pulse rise / fall time 20 ns
VOH = 0.7 × VDD,
Output reference voltage 0.3 × VDD
VOL = 0.3 × VDD
Output load 100 pF 0.2 × VDD

Figure 7 Input / Output Waveform during AC Measurement

Table 8 AC Electrical Characteristics

(Ta = −40°C to +85°C)
VDD = 1.5 V to 2.5 V VDD = 2.5 V to 5.5 V
Item Symbol Unit
Min. Max. Min. Max.
SCL clock frequency fSCL 0 400 0 1000 kHz
SCL clock "L" time tLOW 1.3 − 0.4 − μs
SCL clock "H" time tHIGH 0.6 − 0.3 − μs
SDA output delay time*1 tAA − 0.9 − 0.5 μs
Start condition set-up time tSU.STA 0.6 − 0.25 − μs
Start condition hold time tHD.STA 0.6 − 0.25 − μs
Data input set-up time tSU.DAT 100 − 80 − ns
Data input hold time tHD.DAT 0 − 0 − ns
Stop condition set-up time tSU.STO 0.6 − 0.25 − μs
SCL, SDA rise time tR − 0.3 − 0.3 μs
SCL, SDA fall time tF − 0.3 − 0.3 μs
Bus release time tBUF 1.3 − 0.5 − μs
Noise suppression time tl − 50 − 50 ns
CLKIN clock frequency fCLKIN 0 400 0 1000 kHz
CLKIN clock "L" time tCLKIN_L 1.3 − 0.4 − μs
CLKIN clock "H" time tCLKIN_H 0.6 − 0.3 − μs
CLKIN rise time tCLKIN_R − 0.3 − 0.3 μs
CLKIN fall time tCLKIN_F − 0.3 − 0.3 μs
*1. Since the output form of the SDA pin is Nch open-drain output, the SDA output delay time is determined by the values of
the load resistance and load capacitance outside the IC. Figure 9 shows the relationship between the output load
values.

9
COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
S-35770 Rev.1.0_00

tF tHIGH tLOW tR

SCL

tHD.DAT tSU.DAT tSU.STO

tSU.STA tHD.STA

SDA
(S-35770 input)

tBUF
tAA

SDA
(S-35770 output)

Figure 8 Bus Timing

15

13
Maximum pull-up resistance [kΩ]

11

7 fSCL = 400 kHz

3
fSCL = 1.0 MHz
1
10 100 1000
Load capacitance [pF]

Figure 9 Output Load

tCLKIN_H tCLKIN_L tCLKIN_F tCLKIN_R

CLKIN

Figure 10 CLKIN Pin Clock Timing

10
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
Rev.1.0_00 S-35770

 External Clock Signal Count Function

The S-35770 detects the change of the CLKIN pin from "L" to "H", and then starts the count-up action of the counter. The
counter is a 24-bit binary counter which can count from 0 to 16,777,215 (FFFFFF h). After reaching 16,777,215, the
S-35770 detects the change of the CLKIN pin from "L" to "H", the counter loops back to 0. _______
The counter value can be confirmed by reading the count register. To initialize the counter, input "L" to the RST pin or
input the reset command to the free register. Regarding the count register and the reset command, refer to
" Configuration of registers".

RST

CLKIN

Counter 0 1 2 3 0 1 2 3 0 1 2 3 16,777,214 16,777,215 0 1

The counter does The counter is reset

not start the at RST pin = "L". The counter is reset by The counter loops back to 0.
the reset command.
count-up action at
RST pin = "L". The counter starts the count-up action
at the rising edge of CLKIN pin.

Figure 11 Counter Operation

During communication, the S-35770 does not detect the change of the CLKIN pin from "L" to "H" and maintains the
counter data. The duration of the communication is defined as the time period from the start condition to the stop
condition. The count-up action of the counter is executed 1 time if the CLKIN pin is "L" when the start condition is
recognized and if the CLKIN pin is "H" when the stop condition is recognized.

RST
STA STO STA STO STA STO STA STO STA STO
SDA

CLKIN

Counter 0 1 2 3 4 5 6

The counter does not The counter does not start the count-up action during The counter does not The counter does not start
start the count-up action communication. start the count-up action the count-up action.
during communication. The counter starts the count-up action 1 time when during communication.
communication ends.

Figure 12 Counter Operation during Communication

11
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
S-35770 Rev.1.0_00

 LOOP Pin
The S-35770 detects the change of the CLKIN pin from "L" to "H", and then starts the count-up action of the counter.
The counter loops back to 0 after reaching
_______
16,777,215. At this time, the LOOP pin changes from "L" to "H". To change
the LOOP pin to "L", input "L" to the RST pin or input the reset command to the free register.
Furthermore, if the counter loops back to 0 again after reaching 16,777,215 under the condition the LOOP pin maintains
"H", the LOOP pin changes from "H" to "L". In other word, each time the counter loops back to 0 after reaching
16,777,215, the LOOP pin performs a toggle operation.

RST

CLKIN

Counter 0 1 2 3 16,777,214 16,777,215 0 1 2 16,777,215 0 1 2 16,777,215 0 1 2 0

LOOP

Figure 13 LOOP Pin Operation

12
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
Rev.1.0_00 S-35770

 Configuration of Registers

1. Count register
The count register is a 3-byte register that stores the counter value as binary code.
The count register is read-only.
Perform the read operation of the count register in 3-byte unit from CNT23 to CNT0.

Example: 3 (0000_0000_0000_0000_0000_0011)
45 (0000_0000_0000_1010_1000_1100)
19,800 (0000_0000_0100_1101_0101_1000)

CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16

B7 B0

CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8

B7 B0

CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0

B7 B0
Figure 14

2. Free register
The free register is a 3-byte register that can be freely read and written by the user. The lower 3 bits, RST2 to RST0 are
used as a register to input the counter reset command. The counter is reset by writing RST2 = "0", RST1 = "1", and
RST0 = "0". The data of F20 to F0 are not reset when inputting the reset command; however, the data when the reset
command is input are set.
When only the data of F20 to F0 are rewritten without resetting the counter, write the data except for the above
mentioned ones, such as RST2 = "1", RST1 = "1" and RST0 = "1" to the free register.
Perform the write and read operation of the free register in 3-byte unit.

F20 F19 F18 F17 F16 F15 F14 F13

B7 B0

F12 F11 F10 F9 F8 F7 F6 F5

B7 B0

F4 F3 F2 F1 F0 RST2 RST1 RST0

B7 B0
Figure 15

13
COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
S-35770 Rev.1.0_00

 Serial Interface
The S-35770 transmits and receives various commands via I2C-bus serial interface to read / write data.

1. Start condition

When SDA changes from "H" to "L" with SCL at "H", the S-35770 recognizes start condition and the access operation is
started.

2. Stop condition

When SDA changes from "L" to "H" with SCL at "H", the S-35770 recognizes stop condition and the access operation is
completed. The S-35770 enters standby mode, consequently.

tSU.STA tHD.STA tSU.STO

SCL

SDA

Start condition Stop condition

Figure 16 Start / Stop Condition

3. Data transmission and acknowledge

The data transmission is performed at every one byte after the start condition detection. Pay attention to the
specification of tSU.DAT and tHD.DAT when changing SDA, and perform the operation when SCL is "L". If SDA changes
when SCL is "H", the start / stop condition is recognized even during the data transmission, and the access operation
will be interrupted.
Whenever a one-byte data is received during data transimmion, the receiving device returns an acknowledge. For
example, as shown in Figure 17, assume that the S-35770 is a receiving device, and the master device is a
transmitting device. If the clock pulse at the 8th bit falls, the master device releases SDA. Consequently, the S-35770,
as an acknowledge, sets SDA to "L" during the 9th bit pulse. The access operation is not performed properly when the
S-35770 does not output an acknowledge.

SCL
(S-35770 input) 1 8 9

tSU.DAT tHD.DAT
SDA
Release SDA
(Master device output)
High-Z

SDA Acknowledge
(S-35770 output) output
(Active "L")
Start Condition High-Z

tAA

Figure 17 Acknowledge Output Timing

14
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
Rev.1.0_00 S-35770

4. Data transmission format

After the start condition transmission, the 1st byte is a slave address and a command (read / write bit) that shows the
transmission direction at the 2nd byte or subsequent bytes.
The slave address of the S-35770 is specified to "0110010". The data can be written to the free register when read /
write bit is "0", and the data of count register or the free regiister can be read when read / write bit is "1".
When the data can be written to the free register, input the data from the master device in order of B7 to B0. The
acknowledge ("L") is output from the S-35770 whenever a one-byte data is input.
When the data of the count register or the free register can be read, the data from the S-35770 is output in order of B7
to B0 in byte unit. Input the acknowledge ("L") from the master device whenever a one-byte data is input. However, do
not input the acknowledge for the last byte (NO_ACK). By this, the end of the data read is informed.
After the master device receives / transmits the acknowledge for the last byte data, input the stop condition to the
S-35770 to finish the access operation.
When the master device inputs start condition instead of stop condition, the S-35770 becomes restart condition, and
can transmit / receive the data if the master device inputs the slave address continuously.

1 9 18 27 36 45

SCL
Data write
SDA ST Slave address 0 A Data A Data A Data A Data A SP
format
B7 B1 R/W B7 B0 B7 B0 B7 B0 B7 B0

Data read SDA ST Slave address 1 A Data A Data A Data A SP

format
B7 B1 R/W B7 B0 B7 B0 B7 B0

Restart format SDA ST

Slave address 0 A Data A Data A Data A Data A
B7 B1 R/W B7 B0 B7 B0 B7 B0 B7 B0

ST Slave address 1 A Data A Data A Data A SP

B7 B1 R/W B7 B0 B7 B0 B7 B0

: Master device input data ST : Start condition SP : Stop condition

: S-35770 output data A A A : Acknowledge

Figure 18 Data Transmission Format of Serial Interface

In the time period from the start condition to the stop condition, the S-35770 does not detect the change of the CLKIN pin
from "L" to "H" and maintains the counter data. Therefore, the output data of the count register does not change even if
an external clock is input during a read operation of the count register.
Regarding the counter operation during communication, refer to " External Clock Signal Count Function".

15
COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
S-35770 Rev.1.0_00

5. Read operation of count register

Transmit the start condition and slave address from the master device. The slave address of the S-35770 is specified
to "0110010". The data of the count register can be read when the read / write bit is "1".
The 2nd byte to the 4th byte are used as the count register. Each byte from B7 is transmitted.
When the read operation of the count register is finished, transmit "1" (NO_ACK) to the acknowledge after B0 is output
from the master device, and then transmit the stop condition.
The count register is a 3-byte register. "1" is read if the read operation is performed continuously after reading 3 bytes
of the count register. Regarding the count register, refer to " Configuration of Registers".

Disable time period of count-up action

1 9 18 27 36

SCL

SDA
CNT23

CNT21
CNT20

CNT18

CNT16

CNT15

CNT13
CNT12

CNT10
CNT22

CNT19

CNT17

CNT14

NO_ACK
CNT11

STOP
CNT5
CNT4

CNT1
CNT6
CNT7

CNT2
CNT3

CNT0
CNT9
CNT8
START

ACK
ACK
ACK

0 1 1 0 0 1 0 1

B7 B1 R/W B7 B0 B7 B0 B7 B0

Slave address Count register (3-byte)

(0110010)

: Master device input data Input NO_ACK after the 3rd byte data is transmitted.

: S-35770 output data

Figure 19 Read Timing of Count Register

16
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
Rev.1.0_00 S-35770

6. Write operation of free register

Transmit the start condition and slave address from the master device. The slave address of the S-35770 is specified
to "0110010". Next, transmit "0" to the read / write bit.
Transmit the 2nd byte data. Set B7 to "1" since it is an address pointer. Set B6 to B1 to "0" or "1" since they are dummy
data. Be sure to set B0 to "1" since it is a test bit.
B7 in the 3rd byte to B3 in the 5th byte are used as the free register.
B2 to B0 (RST2 to RST0) in the 5th byte are used as a register to input the counter reset command. The counter is
reset when transmitting RST2 = "0", RST1 = "1" and RST0 = "0". When not resetting the counter, transmit the data
except for the above mentioned ones, such as RST2 = "1", RST1 = "1" and RST0 = "1".
Transmit the stop condition from the master device to finish the access operation.
Regarding the free register, refer to " Configuration of Registers".
Write operation of the free register is performed each byte, so transmit the data in 3-byte unit. Note that the S-35770
may not operate as desired if the data is not transmitted in 3-byte unit.
Disable time period of count-up action
1 9 18 27 36 45

SCL

F[20:13] F[12:5] F[4:0], RST[2:0]

Write timing Write timing Write timing

STOP
START

RST2
RST1
RST0
SDA
ACK

ACK

ACK

ACK
ACK

F20
F19
F18
F17
F16
F15
F14
F13

F12

F10
F11

0 1 1 0 0 1 0 0 1 1

F6
F5

F4
F3
F2
F9
F8
F7

F1
F0
B7 B1 R/W B7 B0 B7 B0 B7 B0 B7 B0

Slave address Dummy data*1 Free register (3-byte)

(0110010)
Make sure to set B0 to "1" since it is a test bit.
Set B7 as an address pointer.

: Master device input data

: S-35770 output data

*1. Set B6 to B1 to "0" or "1" since they are dummy data.

Figure 20 Write Timing of Free Register

17
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
S-35770 Rev.1.0_00

7. Read operation of free register

Perform the read operation of the free register with the restart format. Regarding the restart format, refer to
"4. Data transmission format".

Transmit the start condition and the slave address from the master device. The slave address of the S-35770 is
specified to "0110010". Next, transmit "0" to the read / write bit.
B7 in the 2nd byte is an address pointer. Set B7 to "0" when reading the free register. Next, transmit the dummy data to
B6 to B1. Make sure to set B0 to "1" since it is a test bit. This processing is called "dummy write".
Then transmit the start condition, the slave address and the read / write bit. If the read / write bit is set to "1", the
S-35770 becomes the mode to read the free register.
Consequently, the data of the free register is output from the S-35770. Each byte from B7 is transmitted.
When the read operation of the free register is finished, transmit "1" (NO_ACK) to the acknowledge after B0 output
from the master device, and then transmit the stop condition.
The free register is a 3-byte register. "1" is read if the read operation is performed continuously after reading 3 bytes of
the free register.
Regarding the free register, refer to " Configuration of Registers".

Moreover, the internal address pointer is reset if recognizing the stop condition. Therefore, do not transmit the stop
condition after dummy write operation. The counter data is read when reading the free register after transmission of
the stop condition.
Disable time period of count-up action

1 9 18 1 9 18 27 36

SCL
START

START

STOP
NO_ACK
RST2
RST1
RST0
ACK

ACK

ACK

ACK

ACK
F20
F19
F18
F17
F16
F15
F14
F13

F12
F11
F10

SDA 01100100 0 1 01100101

F9
F8
F7
F6
F5

F4
F3
F2
F1
F0
B7 B1 R/W B7 B0 B7 B1R/W B7 B0 B7 B0 B7 B0
*1
Slave address Dummy data Slave address Free register (3-byte)
(0110010) (0110010)
Input NO_ACK after
Make sure to set B0 to "1" since it is a test bit. the 3rd byte transmission.
Set B7 as an address pointer.

Dummy write

: Master device input data

: S-35770 output data

*1. Set B6 to B1 to "0" or "1" since they are dummy data.

Figure 21 Read Timing of Free Register

18
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
Rev.1.0_00 S-35770

 Release of SDA
_______
The RST pin of the S-35770 does not perform the reset operation of the communication interface. Therefore, the stop
condition is input to reset the internal interface circuit usually.
However, the S-35770 does not accept the stop condition from the master device when in the status that SDA outputs
"L" (at the time of acknowledge outputting or reading). Consequently, it is necessary to finish the acknowledge output or
the read operation. Figure 22 shows the SDA release method.
First, input the start condition from the master device (since SDA of the S-35770 outputs "L", the S-35770 can not detect
the start condition). Next, input the clocks for 1-byte data access (9 clocks) from SCL. During the time, release SDA of
the master device. By this, the SDA input / output before communication interrupt is completed, and SDA of the S-35770
becomes release status. Continuously, if the stop condition is input, the internal circuit resets and the communication
returns to normal status.
It is strongly recommended that the SDA release method is performed at the time of system initialization after the power
supply voltage of the master device rises.

Start condition Clocks for 1-byte data access Stop condition

SCL 1 2 8 9

SDA
(Master device output)

SDA "L" "L" or High-Z High-Z

(S-35770 output)

"L"
SDA "L" or High-Z

Figure 22 SDA Release Method

 Power-on Detection Circuit

In order for the power-on detection circuit to operate normally, raise the power supply voltage of the IC from 0.2 V or lower
so that it reaches 1.5 V of the operation power supply voltage minimum value within 10 ms, as shown in Figure 23.

Within 10 ms

1.5 V
(Operation power
supply voltage min.)

0.2 V or lower
*1
0V

*1. 0 V means that there is no potential difference between the VDD pin and the VSS pin of the S-35770.

Figure 23 How to Raise the Power Supply Voltage

19
COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
S-35770 Rev.1.0_00

 Example of Application Circuit

V CC

10 kΩ
1 kΩ
1 kΩ
S-1xxx S-35770
VIN VOUT VDD SCL VCC
VR SDA
VSS RST CPU
VSS LOOP
CLKIN VSS

External clock

Figure 24

Caution 1. Start communication under stable condition after turning on the system power supply.
2. The above connection diagrams do not guarantee operation. Set the constants after performing
sufficient evaluation using the actual application.

20
 COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
Rev.1.0_00 S-35770

 Precautions

• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.

21
COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE
S-35770 Rev.1.0_00

 Characteristics (Typical Data)

1. Current consumption 1 vs. Power supply voltage characteristics 2. Current consumption 2 vs. SCL frequency characteristics
Ta = +25°C Ta = +25°C
1.0 600
0.8 500 VDD = 5.0 V
400
IDD1 [μA]

IDD2 [μA]
0.6
300
0.4 VDD = 3.0 V
200
0.2 100
0 0
0 2 4 6 0 500 1000 1500
VDD [V] SCL frequency [kHz]

3. Current consumption 1 vs. Temperature characteristics 4. Current consumption 1 vs. CLKIN frequency characteristics

1.0 90
80
0.8 70 VDD = 5.0 V
60
IDD1 [μA]

IDD1 [μA]

0.6 50
VDD = 3.0 V
0.4 40
30 VDD = 3.0 V
VDD = 5.0 V
0.2 20
10
0 0
−40 −25 0 25 50 75 85 0 500 1000 1500
Ta [°C] CLKIN frequency [kHz]

5. Low level output current vs. Output voltage characteristics 6. High level output current vs. VDD − VOUT characteristics
LOOP pin, SDA pin,
Ta = +25°C LOOP pin, Ta = +25°C
70 0
60 VDD = 3.0 V
−5
50 VDD = 5.0 V
IOH [mA]
IOL [mA]

40 −10
30 −15 VDD = 5.0 V
20
VDD = 3.0 V −20
10
0 −25
0 2 4 6 0 2 4 6
VOUT [V] VDD − VOUT [V]

22
 2.90±0.2

8 5

1 4
0.13±0.1

0.2±0.1
0.65±0.1

No. FM008-A-P-SD-1.2

TITLE TMSOP8-A-PKG Dimensions

No. FM008-A-P-SD-1.2
ANGLE
UNIT mm

ABLIC Inc.
 2.00±0.05
1.00±0.1
4.00±0.1 4.00±0.1 +0.1
1.5 -0

1.05±0.05 0.30±0.05

3.25±0.05

4 1

5 8

Feed direction

No. FM008-A-C-SD-2.0

TITLE TMSOP8-A-Carrier Tape

No. FM008-A-C-SD-2.0
ANGLE
UNIT mm

ABLIC Inc.
 16.5max.

13.0±0.3

Enlarged drawing in the central part

13±0.2

(60°) (60°)

No. FM008-A-R-SD-1.0

TITLE TMSOP8-A-Reel
No. FM008-A-R-SD-1.0
ANGLE QTY. 4,000
UNIT mm

ABLIC Inc.
 Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.

2.4-2019.07

www.ablic.com