PCA9539

PCA9539; PCA9539R
16-bit I2C-bus and SMBus low power I/O port with interrupt
and reset
Rev. 05 — 28 July 2008 Product data sheet
1. General description
The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General
Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for
I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors
family of I2C-bus I/O expanders. I/O expanders provide a simple solution when additional
I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
The PCA9539; PCA9539R consists of two 8-bit configuration (input or output selection),
input, output and polarity inversion (active HIGH or active LOW operation) registers. The
system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration bits. The data for each input or output is kept in the corresponding Input or
Output register. The polarity of the read register can be inverted with the Polarity inversion
register. All registers can be read by the system master.
The PCA9539; PCA9539R is identical to the PCA9555 except for the removal of the
internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are
held LOW, replacement of A2 with RESET and a different address range.
The PCA9539; PCA9539R open-drain interrupt output is activated when any input state
differs from its corresponding input port register state and is used to indicate to the system
master that an input state has changed.
The power-on reset sets the registers to their default values and initializes the device state
machine. In the PCA9539, the RESET pin causes the same reset/default I/O input
configuration to occur without de-powering the device, holding the registers and I2C-bus
state machine in their default state until the RESET input is once again HIGH. This input
requires a pull-up to VDD. In the PCA9539R however, only the device state machine is
initialized by the RESET pin and the internal general-purpose registers remain
unchanged. Using the PCA9539R RESET pin will only reset the I2C-bus interface should
it be stuck LOW to regain access to the I2C-bus. This allows the I/O pins to retain their last
configured state so that they can keep any lines in their previously defined state and not
cause system errors while the I2C-bus is being restored.
Two hardware pins (A0, A1) vary the fixed I2C-bus address and allow up to four devices to
share the same I2C-bus/SMBus.
2. Features
n 16-bit I2C-bus GPIO with interrupt and reset
n Operating power supply voltage range of 2.3 V to 5.5 V
n 5 V tolerant I/Os
n Polarity inversion register
NXP Semiconductors PCA9539; PCA9539R
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
n Active LOW interrupt output

n Active LOW reset input
n Low standby current
n Noise filter on SCL/SDA inputs
n No glitch on power-up
n Internal power-on reset
n 16 I/O pins which default to 16 inputs
n 0 Hz to 400 kHz clock frequency
n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Offered in three different packages: SO24, TSSOP24, and HVQFN24
3. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
PCA9539D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
PCA9539PW TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
PCA9539RPW
PCA9539BS HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; SOT616-1
PCA9539RBS 24 terminals; body 4 × 4 × 0.85 mm
3.1 Ordering options

Table 2. Ordering options
Type number Topside mark Temperature range
PCA9539D PCA9539D −40 °C to +85 °C
PCA9539PW PCA9539PW −40 °C to +85 °C
PCA9539RPW PA9539RPW −40 °C to +85 °C
PCA9539BS 9539 −40 °C to +85 °C
PCA9539RBS 539R −40 °C to +85 °C
PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 05 — 28 July 2008 2 of 31

4. Block diagram
PCA9539
IO1_0
PCA9539R
IO1_1
8-bit IO1_2
A0
INPUT/ IO1_3
A1 OUTPUT
IO1_4
PORTS
write pulse IO1_5
IO1_6
read pulse
IO1_7
I2C-BUS/SMBus
CONTROL
SCL IO0_0
INPUT
FILTER IO0_1
SDA
8-bit IO0_2
INPUT/ IO0_3
OUTPUT
IO0_4
PORTS
write pulse IO0_5
IO0_6
read pulse
VDD POWER-ON IO0_7
RESET RESET VDD
VSS
LP INT
FILTER
002aad722
Remark: All I/Os are set to inputs at reset.

Fig 1. Block diagram of PCA9539; PCA9539R

5. Pinning information
5.1 Pinning
INT 1 24 VDD INT 1 24 VDD

A1 2 23 SDA A1 2 23 SDA
RESET 3 22 SCL RESET 3 22 SCL
IO0_0 4 21 A0 IO0_0 4 21 A0
IO0_1 5 20 IO1_7 IO0_1 5 20 IO1_7
IO0_2 6 19 IO1_6 IO0_2 6 PCA9539PW 19 IO1_6
PCA9539D
IO0_3 7 18 IO1_5 IO0_3 7 PCA9539RPW 18 IO1_5
IO0_4 8 17 IO1_4 IO0_4 8 17 IO1_4
IO0_5 9 16 IO1_3 IO0_5 9 16 IO1_3
IO0_6 10 15 IO1_2 IO0_6 10 15 IO1_2
IO0_7 11 14 IO1_1 IO0_7 11 14 IO1_1
VSS 12 13 IO1_0 VSS 12 13 IO1_0
002aad719 002aad720
Fig 2. Pin configuration for SO24 Fig 3. Pin configuration for TSSOP24
PCA9539BS
PCA9539RBS
24 RESET
20 SDA
19 SCL
21 VDD
22 INT
terminal 1
23 A1
index area
IO0_0 1 18 A0
IO0_1 2 17 IO1_7
IO0_2 3 16 IO1_6
IO0_3 4 15 IO1_5
IO0_4 5 14 IO1_4
IO0_5 6 13 IO1_3
IO1_0 10
IO1_1 11
IO1_2 12
7
8
9
IO0_6
IO0_7
VSS
002aad721
Transparent top view
Fig 4. Pin configuration for HVQFN24

5.2 Pin description

Table 3. Pin description
Symbol Pin Description
SO24, TSSOP24 HVQFN24
INT 1 22 interrupt output (open-drain)
A1 2 23 address input 1
RESET 3 24 active LOW reset input. Driving this pin LOW
causes:
• PCA9539 to reset its state machine and
registers
• PCA9539R to reset its state machine, but
has no effect on its registers
IO0_0 4 1 port 0 input/output 0
VSS 12 9[1] supply ground
A0 21 18 address input 0
SCL 22 19 serial clock line input
SDA 23 20 serial data line open-drain input/output
VDD 24 21 supply voltage
[1] HVQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.

6. Functional description
Refer to Figure 1 “Block diagram of PCA9539; PCA9539R”.
6.1 Device address
slave address
1 1 1 0 1 A1 A0 R/W
fixed programmable
002aad724
Fig 5. PCA9539; PCA9539R device address
6.2 Registers
6.2.1 Command byte

The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
Table 4. Command byte

Command Register
0 Input port 0
1 Input port 1
2 Output port 0
3 Output port 1
4 Polarity inversion port 0
5 Polarity inversion port 1
6 Configuration port 0
7 Configuration port 1

6.2.2 Registers 0 and 1: Input port registers

This register is an input-only port. It reflects the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by Register 3. Writes to
this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
Table 5. Input port 0 register

Bit 7 6 5 4 3 2 1 0
Symbol I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0
Default X X X X X X X X
Table 6. Input port 1 register

Bit 7 6 5 4 3 2 1 0
Symbol I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0
Default X X X X X X X X
6.2.3 Registers 2 and 3: Output port registers

This register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined
as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling
the output selection, not the actual pin value.
Table 7. Output port 0 register

Bit 7 6 5 4 3 2 1 0
Symbol O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0
Default 1 1 1 1 1 1 1 1
Table 8. Output port 1 register

Bit 7 6 5 4 3 2 1 0
Symbol O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0
Default 1 1 1 1 1 1 1 1
6.2.4 Registers 4 and 5: Polarity inversion registers

This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this
register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 9. Polarity inversion port 0 register

Bit 7 6 5 4 3 2 1 0
Symbol N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
Default 0 0 0 0 0 0 0 0
Table 10. Polarity inversion port 1 register

Bit 7 6 5 4 3 2 1 0
Symbol N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
Default 0 0 0 0 0 0 0 0

6.2.5 Registers 6 and 7: Configuration registers

This register configures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. At reset, the device's ports are inputs.
Table 11. Configuration port 0 register

Bit 7 6 5 4 3 2 1 0
Symbol C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0
Default 1 1 1 1 1 1 1 1
Table 12. Configuration port 1 register

Bit 7 6 5 4 3 2 1 0
Symbol C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
Default 1 1 1 1 1 1 1 1
6.3 Power-on reset

When power is applied to VDD, an internal power-on reset holds the PCA9539; PCA9539R
in a reset condition until VDD has reached VPOR. At that point, the reset condition is
released and the PCA9539; PCA9539R registers and SMBus state machine will initialize
to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.4 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). In
the PCA9539 the registers and SMBus/I2C-bus state machine will be held in their default
state until the RESET input is once again HIGH. This input typically requires a pull-up to
VDD. In the PCA9539R, only the device state machine is initialized. The internal
general-purpose registers remain unchanged. Using the PCA9539R hardware reset pin
will only reset the I2C-bus interface should it be stuck LOW to regain access to the
I2C-bus. This allows the I/O pins to retain their last configured state so that they can keep
any lines in their previously defined state and not cause system errors while the I2C-bus is
being restored.
6.5 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of
the Output port register. Care should be exercised if an external voltage is applied to an
I/O configured as an output because of the low-impedance path that exists between the
pin and either VDD or VSS.

data from output port

shift register register data
configuration
register
VDD
data from Q1
D Q
shift register
FF
write
D Q
configuration CK Q
pulse FF
I/O pin
write pulse CK Q2
input port VSS

output port
register register
D Q
input port
FF register data
read pulse CK
to INT
polarity inversion
register
data from
D Q polarity
shift register inversion
FF register data
write polarity
CK
pulse
002aad723
At power-on reset, all registers return to default values.

Fig 6. Simplified schematic of I/Os
6.6 Bus transactions
6.6.1 Writing to the port registers

Data is transmitted to the PCA9539; PCA9539R by sending the device address and
setting the least significant bit to a logic 0 (see Figure 5 “PCA9539; PCA9539R device
address”). The command byte is sent after the address and determines which register will
receive the data following the command byte.
The eight registers within the PCA9539; PCA9539R are configured to operate as four
register pairs. The four pairs are Input ports, Output ports, Polarity inversion ports, and
Configuration ports. After sending data to one register, the next data byte will be sent to
the other register in the pair (see Figure 7 and Figure 8). For example, if the first byte is
sent to Output port 1 (register 3), then the next byte will be stored in Output port 0
(register 2). There is no limitation on the number of data bytes sent in one write
transmission. In this way, each 8-bit register may be updated independently of the other
registers.

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Product data sheet
PCA9539_PCA9539R_5
NXP Semiconductors
SCL 1 2 3 4 5 6 7 8 9
slave address command byte data to port 0 data to port 1
SDA S 1 1 1 0 1 A1 A0 0 A 0 0 0 0 0 0 1 0 A 0.7 DATA 0 0.0 A 1.7 DATA 1 1.0 A P
START condition R/W acknowledge acknowledge acknowledge STOP

from slave from slave from slave condition
write to port
tv(Q)
data out
from port 0
tv(Q)
Rev. 05 — 28 July 2008
data out
from port 1 DATA VALID
002aad725
Fig 7. Write to output port registers
PCA9539; PCA9539R
SCL 1 2 3 4 5 6 7 8 9
data to register data to register
slave address command byte
MSB LSB MSB LSB
SDA S 1 1 1 0 1 A1 A0 0 A 0 0 0 0 0 1 1 0 A DATA 0 A DATA 1 A P
© NXP B.V. 2008. All rights reserved.
START condition R/W acknowledge acknowledge acknowledge STOP

from slave from slave from slave condition
002aad726
10 of 31
Fig 8. Write to configuration registers

6.6.2 Reading the port registers

In order to read data from the PCA9539; PCA9539R, the bus master must first send the
PCA9539; PCA9539R address with the least significant bit set to a logic 0 (see Figure 5
“PCA9539; PCA9539R device address”). The command byte is sent after the address and
determines which register will be accessed. After a restart, the device address is sent
again, but this time the least significant bit is set to a logic 1. Data from the register
defined by the command byte will then be sent by the PCA9539; PCA9539R (see
Figure 9, Figure 10 and Figure 11). Data is clocked into the register on the falling edge of
the acknowledge clock pulse. After the first byte is read, additional bytes may be read but
the data will now reflect the information in the other register in the pair. For example, if you
read Input port 1, then the next byte read would be Input port 0. There is no limitation on
the number of data bytes received in one read transmission but the final byte received, the
bus master must not acknowledge the data.
slave address
SDA S 1 1 1 0 1 A1 A0 0 A COMMAND BYTE A (cont.)
START condition R/W acknowledge

acknowledge from slave
from slave
data from lower or data from upper or
upper byte of register lower byte of register
slave address
MSB LSB MSB LSB
(cont.) S 1 1 1 0 1 A1 A0 1 A DATA (first byte) A DATA (last byte) NA P
(repeated) R/W acknowledge no acknowledge STOP

START condition acknowledge from master from master condition
from slave at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter 002aad727
Remark: Transfer can be stopped at any time by a STOP condition.

Fig 9. Read from register

Product data sheet
PCA9539_PCA9539R_5
NXP Semiconductors
data into port 0
data into port 1
INT
tv(INT_N) trst(INT_N)
Rev. 05 — 28 July 2008
SCL 1 2 3 4 5 6 7 8 9
R/W STOP condition

slave address I0.x I1.x I0.x I1.x
SDA S 1 1 1 0 1 A1 A0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P
START condition acknowledge acknowledge acknowledge acknowledge non acknowledge

from slave from master from master from master from master
PCA9539; PCA9539R
read from port 0
read from port 1

002aad728
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
12 of 31
It is assumed that the command byte has previously been set to ‘00’ (read input port register).
Fig 10. Read input port register, scenario 1
Product data sheet
PCA9539_PCA9539R_5
NXP Semiconductors
data into port 0 DATA 00 DATA 01 DATA 02 DATA 03
th(D) tsu(D)
data into port 1 DATA 10 DATA 11 DATA 12

th(D) tsu(D)
INT
Rev. 05 — 28 July 2008
SCL 1 2 3 4 5 6 7 8 9
R/W STOP condition

slave address I0.x I1.x I0.x I1.x
SDA S 1 1 1 0 1 A1 A0 1 A DATA 00 A DATA 10 A DATA 03 A DATA 12 1 P
START condition acknowledge acknowledge acknowledge acknowledge non acknowledge

from slave from master from master from master from master
PCA9539; PCA9539R
read from port 0
read from port 1

002aad729
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
13 of 31
It is assumed that the command byte has previously been set to ‘00’ (read input port register).
Fig 11. Read input port register, scenario 2
6.6.3 Interrupt output

The open-drain interrupt output is activated when one of the port pins change state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input port register is read (see Figure 10). A pin configured as an
output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt
caused by Port 0 will not be cleared by a read of Port 1 or the other way around.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input port register.
7. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 12).
SDA
SCL
data line change

stable; of data
data valid allowed mba607
Fig 12. Bit transfer
7.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 13).
SDA SDA
SCL SCL
S P
START condition STOP condition

mba608
Fig 13. Definition of START and STOP conditions

7.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 14).
SDA
SCL
MASTER SLAVE MASTER

SLAVE MASTER I2C-BUS
TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/
MULTIPLEXER
RECEIVER RECEIVER RECEIVER
SLAVE
002aaa966
Fig 14. System configuration
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master 1 2 8 9

S
clock pulse for
START acknowledgement
condition 002aaa987
Fig 15. Acknowledgement on the I2C-bus

8. Application design-in information
VDD
(5 V) SUB-SYSTEM 1
10 kΩ 10 kΩ 10 kΩ 10 kΩ 2 kΩ 100 kΩ
(e.g., temp sensor)
VDD (×3)
VDD
MASTER INT
CONTROLLER PCA9539
SCL SCL IO0_0
SUB-SYSTEM 2
SDA SDA IO0_1 (e.g., counter)
INT INT
IO0_2 RESET
RESET RESET
IO0_3
A
VSS
IO0_4 controlled
enable
switch
IO0_5 (e.g., CBT device)
B
IO0_6
IO0_7
SUB-SYSTEM 3
IO1_0 (e.g., alarm system)
IO1_1 10 DIGIT
IO1_2 NUMERIC ALARM
IO1_3 KEYPAD
IO1_4
VDD
IO1_5
A1 IO1_6
A0 IO1_7
VSS
002aad730
Device address configured as 1110 100X for this example.

IO0_0, IO0_2, IO0_3 configured as outputs.
IO0_1, IO0_4, IO0_5 configured as inputs.
IO0_6, IO0_7 and (IO1_0 to IO1_7) configured as inputs.
Fig 16. Typical application

8.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 16. Since the LED acts as a diode, when the LED is off the I/O
VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower
than VDD.
Designs needing to minimize current consumption, such as battery power applications,

should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 17 shows a high value resistor in parallel with the LED. Figure 18 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at
or above VDD and prevents additional supply current consumption when the LED is off.
3.3 V 5V
VDD
VDD LED 100 kΩ VDD LED
LEDn LEDn
002aac189 002aac190
Fig 17. High value resistor in parallel with Fig 18. Device supplied by a lower voltage
the LED
9. Limiting values
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage −0.5 +6.0 V
VI/O voltage on an input/output pin VSS − 0.5 6 V
IO output current on an I/O pin - ±50 mA
II input current - ±20 mA
IDD supply current - 160 mA
ISS ground supply current - 200 mA
Ptot total power dissipation - 200 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature operating −40 +85 °C
Tj(max) maximum junction temperature - 125 °C

10. Static characteristics

Table 14. Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 2.3 - 5.5 V
IDD supply current Operating mode; VDD = 5.5 V; - 135 200 µA
no load; fSCL = 100 kHz; I/O = inputs
Istb standby current Standby mode; VDD = 5.5 V; no load; - 0.25 1 µA
VI = VSS; fSCL = 0 kHz; I/O = inputs
Standby mode; VDD = 5.5 V; no load; - 0.25 1 µA
VI = VDD; fSCL = 0 kHz; I/O = inputs
VPOR power-on reset voltage[1] no load; VI = VDD or VSS - 1.5 1.65 V
Input SCL; input/output SDA
VIL LOW-level input voltage −0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
IOL LOW-level output current VOL = 0.4 V 3 - - mA
IL leakage current VI = VDD = VSS −1 - +1 µA
Ci input capacitance VI = VSS - 6 10 pF
I/Os
IOL LOW-level output current VDD = 2.3 V to 5.5 V; VOL = 0.5 V [2] 8 9 - mA
VDD = 2.3 V to 5.5 V; VOL = 0.7 V [2] 10 11 - mA
VOH HIGH-level output voltage IOH = −8 mA; VDD = 2.3 V [3] 1.8 - - V
IOH = −10 mA; VDD = 2.3 V [3] 1.7 - - V
IOH = −8 mA; VDD = 3.0 V [3] 2.6 - - V
IOH = −10 mA; VDD = 3.0 V [3] 2.5 - - V
IOH = −8 mA; VDD = 4.75 V [3] 4.1 - - V
IOH = −10 mA; VDD = 4.75 V [3] 4.0 - - V
ILIH HIGH-level input leakage current VDD = 5.5 V; VI = VDD - - 1 µA
ILIL LOW-level input leakage current VDD = 5.5 V; VI = VSS - - −1 µA
Ci input capacitance - 3.7 5 pF
Co output capacitance - 3.7 5 pF
Interrupt INT
IOL LOW-level output current VOL = 0.4 V 3 - - mA
Select inputs A0, A1 and RESET
ILI input leakage current −1 - +1 µA
[1] VDD must be lowered to 0.2 V for at least 5 µs in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a
maximum current of 100 mA for a device total of 200 mA.

[3] The total current sourced by all I/Os must be limited to 160 mA (80 mA for IO0_0 through IO0_7 and 80 mA for IO1_0 through IO1_7).
11. Dynamic characteristics

Table 15. Dynamic characteristics
Symbol Parameter Conditions Standard-mode Fast-mode I2C-bus Unit
I2C-bus
Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and 4.7 - 1.3 - µs
START condition
tHD;STA hold time (repeated) START condition 4.0 - 0.6 - µs
tSU;STA set-up time for a repeated START 4.7 - 0.6 - µs
condition
tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs
tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 µs
tHD;DAT data hold time 0 - 0 - ns
tVD;DAT data valid time [2] 300 - 50 - ns
tSU;DAT data set-up time 250 - 100 - ns
tLOW LOW period of the SCL clock 4.7 - 1.3 - µs
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs
tf fall time of both SDA and SCL signals [3] - 300 20 + 0.1Cb 300 ns
tr rise time of both SDA and SCL signals [3] - 1000 20 + 0.1Cb 300 ns
tSP pulse width of spikes that must be - 50 - 50 ns
suppressed by the input filter
Port timing
tv(Q) data output valid time [4] - 200 - 200 ns
tsu(D) data input set-up time 150 - 150 - ns
th(D) data input hold time 1 - 1 - µs
Interrupt timing
tv(INT_N) valid time on pin INT - 4 - 4 µs
trst(INT_N) reset time on pin INT - 4 - 4 µs
RESET timing
tw(rst) reset pulse width 4 - 4 - ns
trec(rst) reset recovery time 0 - 0 - ns
trst reset time [5][6] 400 - 400 - ns
[1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3] Cb = total capacitance of one bus line in pF.
[4] tv(Q) measured from 0.7VDD on SCL to 50 % I/O output.
[5] Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
[6] Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA bus.

SDA
tBUF tr tf tHD;STA tSP

tLOW
SCL
tHD;STA tSU;STA tSU;STO

P S tHD;DAT tHIGH tSU;DAT Sr P
002aaa986
Fig 19. Definition of timing on the I2C-bus
START ACK or read cycle
SCL
SDA
30 %
trst
RESET 50 % 50 % 50 %
trec(rst) tw(rst)
trst
after reset,
IOn 50 %
I/Os reconfigured
as inputs
002aad732
Fig 20. Definition of RESET timing in PCA9539
START ACK or read cycle
SCL
SDA
30 %
trst
RESET 50 % 50 % 50 %
trec(rst) tw(rst)
trst
after reset, I/Os unchanged;

IOn 50 %
device state machine reset
002aad733
Fig 21. Definition of RESET timing in PCA9539R

70 %
SCL 2 1 0 A P
30 %
SDA
tsu(D) th(Q)
input 50 %
INT
002aad734
Fig 22. Expanded view of read input port register
70 %
SCL 2 1 0 A P
SDA
tv(Q)
output 50 %
002aad735
Fig 23. Expanded view of write to output port register
START bit 7 STOP

bit 6 bit 1 bit 0 acknowledge
protocol condition MSB condition
(A6) (D1) (D0) (A)
(S) (A7) (P)
tSU;STA tLOW tHIGH

1 / fSCL
SCL
tBUF tf
tr
SDA
tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO
002aab285
Rise and fall times refer to VIL and VIH.

Fig 24. I2C-bus timing diagram

12. Test information
VDD
open
GND
VDD RL
500 Ω
VI VO
PULSE
DUT
GENERATOR
RT CL
50 pF
002aab284
RL = load resistor.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance of Zo of the pulse generators.
Fig 25. Test circuitry for switching times
RL S1 2VDD
from output under test open
500 Ω GND
CL RL
50 pF 500 Ω
002aac226
Fig 26. Load circuit
Table 16. Test data

Test Load Switch
CL RL
tv(Q) 50 pF 500 Ω 2 × VDD

13. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D E A
X
y HE v M A
24 13
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 12 detail X
e w M
bp
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z
(1)
θ
max.
2.65 0.3 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9
mm 0.25 1.27 1.4 0.25 0.25 0.1 o
0.1 2.25 0.36 0.23 15.2 7.4 10.00 0.4 1.0 0.4 8
o
0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0
inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.60 0.29 0.394 0.016 0.039 0.016
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
99-12-27
SOT137-1 075E05 MS-013
03-02-19
Fig 27. Package outline SOT137-1 (SO24)


TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
D E A
X
y HE v M A
24 13
Q
A2 (A 3) A
A1
pin 1 index
θ
Lp
L
1 12
detail X
w M
e bp
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.
mm
0.15 0.95 0.30 0.2 7.9 4.5 6.6 0.75 0.4 0.5 8o
1.1 0.25 0.65 1 0.2 0.13 0.1
0.05 0.80 0.19 0.1 7.7 4.3 6.2 0.50 0.3 0.2 0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

ISSUE DATE
99-12-27
SOT355-1 MO-153
03-02-19
Fig 28. Package outline SOT355-1 (TSSOP24)


HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm SOT616-1
D B A
terminal 1
index area
A
A1
E c
detail X
e1 C
1/2 e
y1 C y
e b v M C A B
7 12 w M C
L
13
6
e
Eh e2
1/2 e
1
18
terminal 1
index area 24 19
Dh X
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
A(1)
UNIT A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1
max.
mm 0.05 0.30 4.1 2.25 4.1 2.25 0.5

1 0.2 0.5 2.5 2.5 0.1 0.05 0.05 0.1
0.00 0.18 3.9 1.95 3.9 1.95 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

ISSUE DATE
01-08-08
SOT616-1 --- MO-220 ---
02-10-22
Fig 29. Package outline SOT616-1 (HVQFN24)


14. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe you must take normal precautions appropriate to handling
integrated circuits.
15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
15.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
15.4 Reflow soldering

Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 30) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 17 and 18
Table 17. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 ≥ 350
< 2.5 235 220
≥ 2.5 220 220
Table 18. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 30.

maximum peak temperature

temperature = MSL limit, damage level
minimum peak temperature

= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level

Fig 30. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.
16. Abbreviations
Table 19. Abbreviations
Acronym Description
ACPI Advanced Configuration and Power Interface
CBT Cross-Bar Technology
CDM Charged-Device Model
CMOS Complementary Metal-Oxide Semiconductor
ESD ElectroStatic Discharge
FET Field-Effect Transistor
FF Flip-Flop
GPIO General Purpose Input/Output
HBM Human Body Model
I2C-bus Inter-Integrated Circuit bus
I/O Input/Output
LED Light Emitting Diode
MM Machine Model
SMBus System Management Bus

17. Revision history

Table 20. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA9539_PCA9539R_5 20080728 Product data sheet - PCA9539_PCA9539R_4
Modifications: • Section 1 “General description”:
– split (old) 4th paragraph to 2 (new) 4th and (new) 5th paragraphs
– (new) 5th paragraph re-written
• Table 2 “Ordering options”:
– changed Topside mark for Type number PCA9539RPW from “PCA9539RPW” to
“PA9539RPW”
– changed Topside mark for Type number PCA9539RBS from “9539R” to “539R”
PCA9539_PCA9539R_4 20080519 Product data sheet - PCA9539_3
PCA9539_3 20060921 Product data sheet - PCA9539_2
PCA9539_2 20040930 Product data sheet - PCA9539_1
(9397 750 14048)
PCA9539_1 20040827 Product data sheet - -
(9397 750 12898)

18. Legal information
18.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
Draft — The document is a draft version only. The content is still under
therefore such inclusion and/or use is at the customer’s own risk.
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any Applications — Applications that are described herein for any of these
representations or warranties as to the accuracy or completeness of products are for illustrative purposes only. NXP Semiconductors makes no
information included herein and shall have no liability for the consequences of representation or warranty that such applications will be suitable for the
use of such information. specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet Limiting values — Stress above one or more limiting values (as defined in
with the same product type number(s) and title. A short data sheet is intended the Absolute Maximum Ratings System of IEC 60134) may cause permanent
for quick reference only and should not be relied upon to contain detailed and damage to the device. Limiting values are stress ratings only and operation of
full information. For detailed and full information see the relevant full data the device at these or any other conditions above those given in the
sheet, which is available on request via the local NXP Semiconductors sales Characteristics sections of this document is not implied. Exposure to limiting
office. In case of any inconsistency or conflict with the short data sheet, the values for extended periods may affect device reliability.
full data sheet shall prevail. Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
18.3 Disclaimers intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
General — Information in this document is believed to be accurate and any inconsistency or conflict between information in this document and such
reliable. However, NXP Semiconductors does not give any representations or terms and conditions, the latter will prevail.
warranties, expressed or implied, as to the accuracy or completeness of such
No offer to sell or license — Nothing in this document may be interpreted
information and shall have no liability for the consequences of use of such
or construed as an offer to sell products that is open for acceptance or the
information.
grant, conveyance or implication of any license under any copyrights, patents
Right to make changes — NXP Semiconductors reserves the right to make or other industrial or intellectual property rights.
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior 18.4 Trademarks
to the publication hereof.
Notice: All referenced brands, product names, service names and trademarks
Suitability for use — NXP Semiconductors products are not designed,
are the property of their respective owners.
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or I2C-bus — logo is a trademark of NXP B.V.
malfunction of an NXP Semiconductors product can reasonably be expected
19. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

20. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 18 Legal information . . . . . . . . . . . . . . . . . . . . . . 30
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
19 Contact information . . . . . . . . . . . . . . . . . . . . 30
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Functional description . . . . . . . . . . . . . . . . . . . 6
6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2.1 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2.2 Registers 0 and 1: Input port registers . . . . . . . 7
6.2.3 Registers 2 and 3: Output port registers. . . . . . 7
6.2.4 Registers 4 and 5: Polarity inversion
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2.5 Registers 6 and 7: Configuration registers . . . . 8
6.3 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.4 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.5 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.6 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9
6.6.1 Writing to the port registers . . . . . . . . . . . . . . . 9
6.6.2 Reading the port registers . . . . . . . . . . . . . . . 11
6.6.3 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 14
7 Characteristics of the I2C-bus. . . . . . . . . . . . . 14
7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.1.1 START and STOP conditions . . . . . . . . . . . . . 14
7.2 System configuration . . . . . . . . . . . . . . . . . . . 15
7.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15
8 Application design-in information . . . . . . . . . 16
8.1 Minimizing IDD when the I/Os are used to
control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 18
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 19
12 Test information . . . . . . . . . . . . . . . . . . . . . . . . 22
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23
14 Handling information. . . . . . . . . . . . . . . . . . . . 26
15 Soldering of SMD packages . . . . . . . . . . . . . . 26
15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 26
15.2 Wave and reflow soldering . . . . . . . . . . . . . . . 26
15.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26
15.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 27
16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28
17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 28 July 2008
Document identifier: PCA9539_PCA9539R_5

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PCA9539; PCA9539R

n Active LOW interrupt output

3.1 Ordering options

PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 05 — 28 July 2008 2 of 31

Remark: All I/Os are set to inputs at reset.

PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 05 — 28 July 2008 3 of 31

INT 1 24 VDD INT 1 24 VDD

Transparent top view

Fig 4. Pin configuration for HVQFN24

PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 05 — 28 July 2008 4 of 31

5.2 Pin description

PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 05 — 28 July 2008 5 of 31

6.1 Device address

Fig 5. PCA9539; PCA9539R device address

6.2.1 Command byte

Table 4. Command byte

PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 05 — 28 July 2008 6 of 31

6.2.2 Registers 0 and 1: Input port registers

Table 5. Input port 0 register

Table 6. Input port 1 register

6.2.3 Registers 2 and 3: Output port registers

Table 7. Output port 0 register

Table 8. Output port 1 register

6.2.4 Registers 4 and 5: Polarity inversion registers

Table 9. Polarity inversion port 0 register

Table 10. Polarity inversion port 1 register

PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 05 — 28 July 2008 7 of 31

6.2.5 Registers 6 and 7: Configuration registers

Table 11. Configuration port 0 register

Table 12. Configuration port 1 register

6.3 Power-on reset

6.4 RESET input

6.5 I/O port

PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 05 — 28 July 2008 8 of 31

data from output port

input port VSS

At power-on reset, all registers return to default values.

6.6 Bus transactions

6.6.1 Writing to the port registers

PCA9539_PCA9539R_5 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 05 — 28 July 2008 9 of 31

slave address command byte data to port 0 data to port 1

SDA S 1 1 1 0 1 A1 A0 0 A 0 0 0 0 0 0 1 0 A 0.7 DATA 0 0.0 A 1.7 DATA 1 1.0 A P

START condition R/W acknowledge acknowledge acknowledge STOP

Fig 7. Write to output port registers

START condition R/W acknowledge acknowledge acknowledge STOP

Fig 8. Write to configuration registers

6.6.2 Reading the port registers

SDA S 1 1 1 0 1 A1 A0 0 A COMMAND BYTE A (cont.)

START condition R/W acknowledge

(repeated) R/W acknowledge no acknowledge STOP

Remark: Transfer can be stopped at any time by a STOP condition.