Design a logic diagram and write a Verilog program to implement 4-bit ripple carry adder.
1. Design a logic diagram for a full adder.
a. Create a new project named Adder.
b. Add a new block diagram file (schematic file) named full_adder.bdf into the project. 2. Create a symbol for the block diagram full_adder. - Make sure that the diagram full_adder is currently open. Select File\Create/Update\Create Symbols File for Current File. 3. Design a block diagram of 4-bit ripple carry adder named ripple_carry_adder_4.bdf using full_adder circuit created in the previous step. - Insert full_adder symbol: - Design the 4-bit ripple carry adder block diagram
- Compile the design
4. Simulate the 4-bit ripple carry adder using waveform editor tool Test the adder with some input values. 5. Write a program in Verilog to implement 4-bit ripple carry adder:
hs
hc tc Simulate the 4-bit ripple carry adder using waveform editor tool Test the adder with some input values. Assignment 2 (20 Points) Design a logic diagram and write a Verilog program to implement 4-bit adder-subtractor.
Assignment 3 (Problem 3.3) (20 Points)
Design a Gray code–to–BCD code converter that gives output code 1111 for all invalid input combinations. Assume that the Gray code sequence for decimal numbers 0 through 9 is 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, and 1101. All other input combinations should be considered to be invalid.
A traffic light control at a simple intersection uses a binary counter to produce the following sequence of combinations on lines A, B, C, and D: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111. After 1111, the sequence repeats, beginning again with 0000, forever. Each combination is present for 5 seconds before the next one appears. These lines drive combinational logic with outputs to lamps RNS (red—north/south), YNS (yellow—north/south), GNS (green— north/south), REW (red—east/west), YEW (yellow—east/west), and GEW (green—east/west). The lamp controlled by each output is ON for a 1 applied and OFF for a 0 applied. For a given direction, assume that green is on for 30 seconds, yellow for 5 seconds, and red for 45 seconds. (The red intervals overlap for 5 seconds.) Divide the 80 seconds available for the cycle through the 16 combinations into 16 intervals and determine which lamps should be lit in each interval based on expected driver behavior. Assume that, for interval 0001, a change has just occurred and that RNS = 1, GEW = 1, and all other outputs are 0 (this means that the lamp EW begins GREEN for 30 seconds, the lamp NS is RED). Design the logic to produce the six outputs using AND, OR gates and inverters.
a. Truth table (modified version – yellow-highlighted text)
