CHP 2
CHP 2
CHP 2
Analog-to-Digital Converters
2-1
Architecture and Function of the
MSP430 14-Bit ADC
Lutz Bierl
2–3
IMPORTANT NOTICE
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2–4
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
1.1 Characteristics of the 14-Bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
2 ADC Function and Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2.1 Function of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
2.1.1 ADC Timing Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
2.1.2 Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2.1.3 Absolute and Relative Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
2.2 Using the ADC in 14-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
2.2.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
2.2.2 Software Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
2.3 Using the ADC in 12-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
2.3.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
2.3.2 Software Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
3 The A/D Controller Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
3.1 ADC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
3.1.1 ACTL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
3.1.2 A/D Data Register ADAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
3.1.3 Input Register AIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
3.1.4 Input Enable Register AEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
3.2 Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
3.2.1 Normal Use of the Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
3.2.2 Current Source Used for Level Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
3.3 SVcc Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
3.3.1 SVcc Terminal Used as an Output for the ADC Reference Voltage . . . . . . . . . . . . . . . . . . . . 2–31
3.3.2 SVcc Terminal Used as an Input for the ADC Reference Voltage . . . . . . . . . . . . . . . . . . . . . 2–32
3.3.3 Connection of Current Consuming Loads to SVcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33
3.4 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34
3.4.1 Interrupt Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34
3.4.2 Interrupt Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34
3.5 ADC Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37
4 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37
5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38
6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38
Appendix A Definitions Used With the Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39
List of Figures
1 Hardware of the 14-Bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
2 Possible Connections to the Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
3 Sources of the Conversion Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
4 ADC Spikes Due to Violated Timing Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
5 Simplified Input Circuitry for Signal Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
6 Relative Measurements With the MSP430C32x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
7 Absolute Measurements Using External Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
8 Complete 14-Bit ADC Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
9 Timing for the 14-bit Analog-to-Digital Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
10 The Four 12-Bit ADC Ranges A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
11 Single 12-Bit ADC Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
12 Timing for the 12-Bit A/D Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
13 ACTL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
14 Conversion Start (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
15 Voltage Reference Bit (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
16 ADC Input Selection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
17 Current Source Output Select Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
18 Range Select Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
19 Power Down Bit (Pd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
20 Clock Frequency Selection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
21 Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
22 The Data Register ADAT, 12-Bit A/D Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
23 Data Register ADAT, 14-Bit A/D Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
24 Input Register AIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
25 Input Enable Register AEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
26 The Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
27 Measurement Circuitry for the Error of the Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
28 Error of the Current Source at the Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
29 Error of the Current Source at the Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
30 Application of the Current Source With the Full ADC Range at Input A0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
31 Current Measurement With Level Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
32 SVcc Terminal Used as an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32
33 SVcc Terminal Used as an Input for a Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33
34 Connection of Current Consuming Loads to SVcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34
35 Error Characteristic Device 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37
36 Error Characteristic Device 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37
37 Error Characteristic Device 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38
38 Error Characteristic Device 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38
2–6 SLAA045
Tables
List of Tables
1 ADC Input Selection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
2 Current Source Output Select Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
3 Range Select Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
4 Clock Frequency Selection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
Lutz Bierl
ABSTRACT
This application report describes the architecture and function of the 14-bit
analog-to-digital converter (ADC) of the MSP430 family. The principles of the ADC are
explained and software examples are given. The report also explains the function of all
hardware registers in the ADC. The References section at the end of the report lists
related application reports in the MSP430 14-bit ADC series.
1 Introduction
The analog-to-digital converter (ADC) of the MSP430 family can work in two
modes: the 12-bit mode or the 14-bit mode. Hardware registers allow easy
adaptation to different ADC tasks. The following paragraphs describe the modes
and hardware registers.
2–9
Introduction
AVcc
SVcc Switch ACTL.1 (Vref)
Offset
SVcc ACTL.12(Pd) Canc. Pd
AVcc/2
Generator
_
Rex
C 2C 4C 8C 16C +
128 Range
Rext _ D MUX
Isource 0.75 SVcc
+
VH
128
PD C Resistor
Capacitor
Array
AVcc/2 ACTL.6,7 128
B Decoder VL
Generator ACTL.8
1:4 Delay
(CSoff)
128
A
AGND 7 2 5
ACTL.9, 10(Range)
(AVss)
ACTL.11(Auto) Successive Approximation
A0 Register
ACTL.0(SOC)
A1 ADCLK/12
A2 8:1 EOC
Input
A3
A4 /12
A5 Input
A6 MUX ACTL.2.4 (Ax)
A7 /1, /2 ACTL 14
ACTL.5 (None)
/3, /4 ACTL 13
MCLK
SAR.13 SAR.0 ACTL.14 ACTL.0
A7 A0 AEN.0–7
8
Input Buffer AIN Input Buffer Enable AEN Output Buffer ADAT Control Register ACTL
2–10 SLAA045
ADC Function and Modes
SVcc SVcc
Ics
Rv Rex Ics A3
Rext A6
A4
Vin A2
R1 MSP430C32x
A1 Rsens3
A5
A0 Ics Dr1
R2 Rsens2 Rsens1 A7
Ics Dr2
AVss AVss
DVss DVcc
0V +5 V/3 V
The calculation formulas for all connection methods shown in Figure 2 are
explained in the application report, Application Basics for the MSP430 14-Bit
ADC (SLAA046). [3]
14-Bit Conversion
2–12 SLAA045
ADC Function and Modes
If higher MCLK frequencies are used, then a delay needs to be inserted between
the definition and the start of the measurement. See the source of the MEASR
subroutine in section 2.2.2. The number n of additional delay cycles (MCLK
cycles) needed is:
n ≥ (6 µs × MCLK) –15
• If the input voltage changes very fast, then the range sample and the
conversion sample may be captured in different ranges. See section 2.2.1 if
this cannot be tolerated. For applications like an electricity meter, this doesn’t
matter: the error occurs as often for the increasing voltage as for the
decreasing voltage so the resulting error is zero.
• After the start of a conversion, no modification of the ACTL register is allowed
until the conversion is complete. Otherwise the ADC result will be invalid.
The previously described timing errors lead to spikes in the ADC characteristic:
the ADC seems to get caught at certain steps of the ADC. This is not an ADC
error; the reasons are violations of the ADC timing restrictions. See Figure 4. The
x-axis shows the range A from step 0 to step 4096, the y-axis shows the ADC error
(steps).
Range A
1556
1945
2334
2723
3501
3890
389
778
1167
3112
-2
-4
-6
Series 1
-8
-10
-12
-14
42 pF
Vin MSP430C32x
Csample
AVss
0V
( Ri 2 k) 42 pF 12
ln 2 14 ADCLK
Solved for Ri with ADCLK = 1 MHz this results in:
Ri 27.4 k
This means, for the full resolution of the ADC, the internal resistance of the input
signal must be lower than 27.4 kΩ.
If a resolution of n bits is sufficient, then the internal resistance of the ADC input
source can be higher:
2–14 SLAA045
ADC Function and Modes
Ri t 12 * 2 k
lnǒ2 nǓ 42 pF ADCLK
For example, to get a resolution of 13 bits with ADCLK = 1 MHz, the maximum
Ri of the input signal is:
Ri t 12 * 2 k + 31.7 k * 2 k + 29.7 k
lnǒ2 13Ǔ 42 pF 10 6
SVcc
Ics
Rv Rex Ics A3
Rext
A4
MSP430C32x
A1 Rsens3
A5
Rsens2 A0
Rsens1
Ics
AVss AVss
DVss DVcc
0V +5 V/3 V
<80 µA
Ri
SVcc
Rext
A2
VREF R1
A1
V2 V1
MSP430C32x
R2
AVss
DVss DVcc
0V +5 V/3 V
ADC Value
Overflow
03FFFh
03000h
01000h
ADC Input
00000h
Voltage
Underflow 0 0.25 SVcc 0.5 SVcc 0.75 SVcc SVcc
ADC Saturation
2–16 SLAA045
ADC Function and Modes
2.2.1 Timing
The two ADCLK bits (ACTL.13 and ACTL.14) in the ACTL control register are
used to select the ADCLK frequency best suited for the ADC. The MCLK clock
signal can be divided by a factor 1, 2, 3, or 4 to get the best suited ADCLK.
Using the autorange mode (RNGAUTO/ACTL.11 = 1) executes a 14-bit
conversion. The selected analog input signal at input Ax is sampled twice. The
range decision is made after the first sampling of the input signal; the 12-bit
conversion is made after the second sampling. Both samplings are 12 ADCLK
cycles in length. Altogether the 14-bit conversion takes 132 ADCLK cycles. See
Figure 9 for timing details.
12/ADCLK
New
Conversion
ADCLK/12
Power-up Time
Pd
CONV. START
Range Sample Conversion Sample
SAMPLING
END OF CONV.
0C00h A B C D
0800h
0400h
00000h Input
Underflow 0 0.25 SVcc 0.5 SVcc 0.75 SVcc SVcc Voltage VAx
2–18 SLAA045
ADC Function and Modes
NOTE: The ADC results 0000h and 0FFFh mean underflow and
overflow: the voltage at the measured analog input is below or
above the limits of the programmed range.
All of the formulas given for the 12-bit mode assume a faultless
conversion result N:
0 < N < 0FFFh
If underflow or overflow are not checked, erroneous calculation
results occur.
Figure 11 shows how any of the four ADC ranges appears to the software:
ADC Value
0FFFh
n = 0, 1, 2, 3 Range Constant
0800h
N+
VAx * ( n 0.25
VREF
VREF )
2 14 ³ VAx + VREF ǒ2N ) n
14
0.25 Ǔ
Where:
N = 12-bit result of the ADC conversion
VAx = Input voltage at the selected analog input Ax [V]
VREF = Voltage at pin SVcc (external reference or internal AVcc) [V]
n = Range constant (n = 0, 1,2, 3 for ranges A, B, C, D)
To get the 14-bit equivalent N14 of a 12-bit ADC result N12, the following formula
may be used:
N 14 + N 12 ) n 1000h
To check if the result of a 12-bit A/D conversion is correct, the following software
sequence can be used:
MOV #xxx,&ACTL ; Define measurement
CALL #MEASR ; Measure ADC input
TST &ADAT ; Check if underflow (000h)
JZ UFL ; Underflow: go to error handling
CMP #0FFFh,&ADAT ; Check if overflow (0FFFh)
JEQ OFL ; Overflow: go to error handling
... ; Result is correct: use ADAT
2.3.1 Timing
The two ADCLK bits (ACTL.13 and ACTL.14) in the ACTL control register are
used to select the ADCLK frequency best suited for the ADC. The MCLK clock
signal can be divided by a factor 1, 2, 3, or 4 to get the best suited ADCLK.
Disabling the autorange mode (RNGAUTO/ACTL.11 = 0) executes a 12-bit
conversion; the range defined by the ACTL.10 and ACTL.9 bits is used. The
selected analog input signal at input Ax is sampled once; after the sampling, the
12-bit conversion is executed. The 12-bit conversion takes 96 ADCLK cycles.
See Figure 12 for timing details.
12/ADCLK New Conversion
ADCLK/12
Power-Up Time
PD
CONV. START
SAMPLING
END OF CONV.
2–20 SLAA045
The A/D Controller Hardware
2–22 SLAA045
The A/D Controller Hardware
ÎÎÎÎ
ÎÎÎÎ
0 ADCLK PD Range Select Current Source AD Input Select VREF SOC
EXAMPLE: connect the current source to pin A3, and start measurement at pin
A4. All other ADC conditions stay unchanged. This example refers to the
hardware configuration for Rsens3 shown in Figure 2.
BIC #01FCh+PD,&ACTL ; Reset SOC and input sel. Bits
... ;6 µs delay
BIS #CSA3+A4+SOC,&ACTL ; Start conversion for A4
0 ADCLK PD
ÎÎÎÎ
Range Select Current Source AD Input Select VREF SOC
EXAMPLE: prepare the ACTL register for measurement of analog input A3 using
the internal reference, and with the current source connected to A3 and fixed to
range B.
MOV #RNGB+CSA3+A3+VREF,&ACTL
3.1.1.6 Power Down Bit (Pd)
The power-down bit (see Figure 19) reduces the power consumption of the ADC
to the lowest possible value. It switches off the comparator, the SVcc switch, and
the current source.
EXAMPLE: For MCLK = 2.5 MHz, the highest possible ADCLK frequency
(1.25 MHz) is set.
MOV #ADCLK2+RNGAUTO+A3+VREF,&ACTL
3.1.1.8 Bit 15
Bit 15 (see Figure 21) should always be set to zero to maintain software
ÎÎÎÎ
compatibility with future versions of the ADC.
ÎÎÎÎ
0 ADCLK PD Range Select Current Source AD Input Select VREF SOC
2–24 SLAA045
The A/D Controller Hardware
15 11 0
ADAT
0 0 0 0 MSB LSB
ACTL.11=0
0118h
r0 r0 r0 r0 r r r r r r r r r r r r
2–26 SLAA045
The A/D Controller Hardware
Where:
Rex = Resistor between pins SVcc and Rex (defines current Ics) [Ω]
Rsens= Resistor to be measured (connected between Ax and AGND) [Ω]
VREF = Voltage at SVcc. External (VREF = 0) or internal (VREF = 1) [V]
AVcc
SVcc Switch ACTL.1 (VREF = 1)
SVcc ACTL.12 (Pd = 0)
T1 _ 128
Rext D
Ics + 0.75SVcc
128
VREF Pd C To
ACTL. Resistor
128
6,7(0,0) B Decoder
1:4 ACTL. 8 (0)
128
Ics A
When using the current source, it is not possible to use the full range of the ADC:
only the range defined with Load Compliance in the Electrical Description is valid
(0.5 × SVcc, which means only the ranges A and B). Figures 28 and 29 show the
typical error characteristics of the current source at its limit. Figure 28 shows the
error characteristic for Vcc = 4.5 V and a relatively high Rex (1 kΩ). It shows that
up to a ratio of 0.745 for VA0/SVcc (which means range A, B, and nearly all of
range C) the current source works correctly. Then ∆Ics (the difference between
the programmed Ics and the real Ics) increases linearly with
DV + Rex
DI
SVcc
I∆IcsI
Rex ICS
0.25xVREF/Rex Rext
Rsens=Infinite
A1
Rsens=7xRex ICS
A0
Rsens=Rex Rsens
∆V/∆I=Rex
0...Infinite MSP430C32x
Rsens=0 Rsens=2xRex ∆I Va0
∆V AVss AVcc
DVss DVcc
0
0 0.25 0.5 0.75 1.0 VA0/AVcc
A B C D Range 0 V +4.5 V/ 2.5 V
Figure 27. Measurement Circuitry for the Error of the Current Source
2–28 SLAA045
The A/D Controller Hardware
85C
2.00E–05
25C
–40C
1.50E–05
∆ Ics
1.00E–05
5.00E–06
0.00E+00
0.74 0.741 0.742 0.743 0.744 0.745 0.746 0.747 0.748 0.749 0.75
Ratio VA0 /AVcc
Figure 29 gives the characteristic at the other extreme: Vcc = 2.5 V and
Rex = 150 Ω. The slope beyond the operation limit of the current source (here at
VA0/AVcc = 0.7125) is also:
DV Rex
DI
2.00E–04
1.50E–04
∆Ics
1.00E–04
5.00E–05
0.00E+00
0.7 0.7025 0.705 0.7075 0.71 0.7125 0.715 0.7175 0.72 0.7225 0.725 0.7275 0.73
Ratio VA0/AVcc
The characteristic shown in Figure 29 indicates that the current source works up
to 71% of the applied AVcc under worst case conditions; this includes ADC
ranges A, B and 84% of range C. If Rex is chosen as 1 kΩ and SVcc is 4.5 V, then
the current source works up to a ratio of 0.745, which means it covers nearly 98%
of range C.
If the current source is used with an external amplifier (operational amplifier) that
amplifies the output signal coming from the current source, then the full range of
the ADC can be used with a different ADC input. Figure 30 shows such a circuit.
The signal at analog input A0 can use the full range of the A/D converter; the
signal at A1 is restricted to the working area of Ics that is shown in Figures 28 and
29.
The equations for the circuitry are explained in Application Basics for the MSP430
14-Bit ADC Application Report (SLAA046).[3]
Rex
Rext
SVcc
A1
Ics R1 R3
MSP430C32x
Vm
_
A0
+ Vp
v =R1/(R3R4) Rsens
R4
AVss
DVss AVcc
0V +3 V (+5 V)
Figure 30. Application of the Current Source With the Full ADC Range at Input A0
2–30 SLAA045
The A/D Controller Hardware
To To
Charger Load
SVcc
AVcc
AVss AVcc/2
Rex
AVss Accumulators
Rext R1
Voltage
CT Rsh A1
Current
A2 A0
Ics Rc Ics
Iac
MSP430C32x Va0 R2 Shunt
Vct VA2 Vsh
Rld
AVss AVss 0V
AC Measurement DC Measurement
VA2 = Vct + Ics x Rsh VA0 = Vsh + Ics x Rc
3.3.1 SVcc Terminal Used as an Output for the ADC Reference Voltage
Typically, the SVcc terminal is used to supply the reference and voltage to the
ADC circuitry. It can be activated while measurements are being taken and
deactivated for low power periods. Figure 32 shows an example of this. All of the
sensors connected to the MSP430 are powered by the SVcc terminal.
The SVcc terminal outputs the AVcc voltage if the following conditions are true:
VSVcc VREF .and. @ Pd .and. VAVcc
VREF
Isvcc
SVcc Ics
Rv Rex Ics A3
Rext A6
A4 Rsens3
Vin A2
R1
A1
A5 Ics
Rsens2 Rsens1 A0
R2 A7
MSP430C32x Vrd Vrd
Ics
Dr2 Dr1
AVss AVss
AVcc
DVss DVcc
0V +5 V/3 V
Where:
Vrd = Voltage of the reference diode [V]
Nin = 14-bit result for Vin
Nrd = 14-bit result for the voltage Vrd of the reference diode
3.3.2 SVcc Terminal Used as an Input for the ADC Reference Voltage
For absolute voltage measurements an external reference voltage, VREF, is
necessary (see Figure 33). The sensor measurements for Rsens1 to Rsens3 are
made the same way as with the internal reference voltage. The only difference
is the VREF bit of the ACTL register: it is set to zero to allow an external reference
voltage to be used. The formula for Vin is:
Vin VREF N R1 R2
2 14 R2
2–32 SLAA045
The A/D Controller Hardware
Ics MSP430C32x
0V AVss AVss
AVcc
DVss DVcc
0V +5 V/3 V
+5 V/3 V
AVcc DVcc
SVcc
Rv Rex MSP430C32x
Rext
TP.0
Analog
Circuit A0
A1
A2
Rsens2 Rsens1 A3
AVss DVss
Dr
0V
2–34 SLAA045
The A/D Controller Hardware
EXAMPLE: analog input A0 (without current source) and A1 (with the current
source enabled) are measured alternately. The measured 14-bit results are
stored in address MEAS0 for input A0 and MEAS1 for input A1. The time interval
between the two measurements is defined by the 8-bit timer: each timer interrupt
starts a new conversion for the previously prepared analog input. Other timers
may also be used for the generation of the time interval.
; Analog input A0 A1
; Current Source OFF ON
; Result to MEAS0 MEAS1
; Range selection AUTO AUTO
; Reference SVcc SVcc
;
; Initialization part for the ADC:
;
MOV #RNGAUTO+CSOFF+A0+VREF,&ACTL
BIS.B #ADIE,&IE2 ; Enable ADC interrupt
MOV.B #0FFh–3,&AEN ; Only A0 and A1 analog inputs
... ; Initialize other modules
;
; ADC interrupt handler: A0 and A1 are measured alternately.
; The next measurement is prepared but not started.
; The interrupt flag ADIFG is reset automatically
;
ADC_INT BIT #A1,&ACTL ; A1 result in ADAT?
JNZ ADI ; Yes
MOV &ADAT,MEAS0 ; A0 value is actual
MOV #RNGAUTO+CSON+A1+VREF,&ACTL ; A1 next meas.
RETI
ADI MOV &ADAT,MEAS1 ; A1 value is actual
MOV #RNGAUTO+CSOFF+A0+VREF,&ACTL ; A0 next meas.
RETI
;
; 8-bit timer interrupt handler: the ADC conversion is started
; for the previously prepared ADC input
;
T8BINT BIS #SOC,&ACTL ; Start conversion for the ADC
... ; Execute other timer tasks
RETI
;
.SECT ”INT_VEC0”,0FFEAh ; Interrupt vectors
.WORD ADC_INT ; ADC interrupt vector
.SECT ”INT_VEC1”,0FFF8h
.WORD T8BINT ; 8-bit timer interrupt vector
The software for the 12-bit conversion is similar to that for the 14-bit conversion,
the only difference being the replacement of the RNGAUTO bit during the
initialization of the ACTL control register. Instead, the desired range (RNGA,
RNGB, RNGC, or RNGD) is included in the initialization part of each
measurement.
EXAMPLE: for best results the CPU is switched off during the ADC
measurement. The measurement subroutine starts the conversion and switches
off the CPU afterwards. The interrupt routine called by the conversion completion
resets the CPUoff bit (SR.4) of the stored status register SR and allows the CPU
to continue with the measured ADC result. The 12-bit result is moved to R5.
CPUoff .equ 010h ; SR: CPU off bit
GIE .equ 008h ; SR: General Intrpt enable
RNGB .equ 0200h ; ACTL: Select Range B
;
...
BIC.B #ADIFG,&IFG2 ; Reset ADC flag
BIS.B #ADIE,&IE2 ; ADC Intrpt Enable
EINT ; Enable GIE interrupt
MOV #RNGB+CSOFF+A1+VREF,&ACTL ; Define ADC
CALL #MEASURE ; Measure with ADC
MOV &ADAT,R5 ; Result to R5
... ; Process result in R5
;
; Subroutine: CPU is switched off to get minimum noise
;
MEASURE BIS #SOC,&ACTL ; Start ADC conversion
BIS #CPUoff,SR ; Switch CPU off, MCLK active
NOP ; Wait for completion of ADC
RET ;
;
; Interrupt Handler for the Analog-to-Digital Converter
; The CPUoff bit of the saved SR is cleared to allow the
; software to continue after the RETI
;
ADC_INT BIC #CPUoff,0(SP) ; Allow SW run (CPUoff = 0)
RETI
;
; Interrupt Vectors
;
.sect ”INT_VEC1”,0FFEAh
.WORD ADC_INT ; ADC Vector
2–36 SLAA045
ADC Characteristics
4 ADC Characteristics
The next four figures show typical measured ADC characteristics: the absolute
error (ADC steps) is dependent on the input value (ADC steps from 5 to 16380).
Error characteristics like these are used with Additive Improvement of the
MSP430 14-Bit ADC Characteristic (SLAA047)[4], Linear Improvement of the
MSP430 14-Bit ADC Characteristic (SLAA048)[5], and Nonlinear Improvement
of the MSP430 14-Bit ADC Characteristic (SLAA050)[6] to illustrate the
improvements possible by methods using different hardware and software.
10005
15005
5005
5
5
ADC Error [Steps]
0
–5
–10
–15
ADC Steps
15005
5005
5
15
ADC Error [Steps]
10
5
0
–5
–10
–15
ADC Steps
10005
15005
5005
5
10
ADC Error [Steps]
0
–5
–10
ADC Steps
10005
15005
5005
5
10
ADC Error [Steps]
5
0
–5
–10
–15
ADC Steps
5 Summary
This application report complements Application Basics for the MSP430 14-Bit
ADC (SLAA046)[3] that contains applications of the 14-bit ADC. Additive
Improvement of the MSP430 14-Bit ADC Characteristic (SLAA047)[4] explains
different methods to minimize the ADC error, and the limitations of the ADC.
All five of the application reports in the MSP430 14-bit ADC series include system
applications (hardware and proven software) using all parts and modes of the
ADC.
6 References
1. MSP430 Family Architecture Guide and Module Library, 1996, Literature
#SLAUE10B
2. Data Sheet, MSP430x32x Mixed Signal Microcontroller, 1998, Literature
#SLAS164
3. Application Basics for the MSP430 14-Bit ADC application report, 1999,
Literature #SLAA046
4. Additive Improvement of the MSP430 14-Bit ADC Characteristic application
report, 1999, Literature #SLAA047
5. Linear Improvement of the MSP430 14-Bit ADC Characteristic application
report, 1999, Literature #SLAA048
6. Nonlinear Improvement of the MSP430 14-Bit ADC Characteristic
Application Report, 1999, Literature #SLAA050
7. MSP430 Metering Application Report, 1998, Literature #SLAAE10C
2–38 SLAA045
Definitions Used With the Application Examples
Lutz Bierl
2–41
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their
products or to discontinue any product or service without notice, and advise customers to
obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current and complete. All products are sold subject to the terms
and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent
right, copyright, mask work right, or other intellectual property right of TI covering or relating
to any combination, machine, or process in which such semiconductor products or services
might be or are used. TI’s publication of information regarding any third party’s products or
services does not constitute TI’s approval, warranty or endorsement thereof.
2–42
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
2.1 Connection of Analog Signals and Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46
2.1.1 Current Supply for Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46
2.1.2 Voltage Supply for Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48
2.1.3 Four-Wire Sensors Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–49
2.1.4 Connection of Bridge Assemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50
2.1.5 Reference Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–52
2.2 14-Bit Analog-to-Digital Conversion With Signed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–54
2.2.1 Virtual Ground IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–54
2.2.2 Split Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–55
2.2.3 Use of the Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–56
2.2.4 Resistor Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–59
2.3 12-Bit Analog-to-Digital Conversion With Signed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–60
2.3.1 Virtual Ground Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–60
2.3.2 Use of the Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–62
2.3.3 Resistor Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–62
2.4 Reference Resistor Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–63
2.4.1 Reference Resistor Method Without Amplification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–63
2.4.2 Reference Resistor Method With Amplification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–65
3 Hum and Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
3.1 Connection of Long Sensor Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–67
3.2 Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–68
3.3 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–69
4 Enhancement of the Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
4.1 16-Bit Mode With the Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–70
4.2 Enhanced Resolution Without Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–72
4.3 Calculated Resolution of the 16-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–75
4.3.1 16-Bit Mode With the Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–75
4.3.2 16-Bit Mode Without the Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–75
5 Hints and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76
5.1 Replacement of the First Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–76
5.2 Grounding and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–76
5.3 Supply Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–76
5.3.1 Influence of the Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–76
5.3.2 Battery Driven Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–77
5.3.3 Mains Driven Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–78
5.3.4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–78
5.4 Use of the Floating Point Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–78
6 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79
7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79
Appendix A Definitions Used With the Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81
List of Figures
1 MSP430 14-Bit ADC Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45
2 Possible Connections to the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46
3 Current Supply for the Sensor Rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47
4 Voltage Supply for the Sensor Rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48
5 Four-Wire Circuit With Current Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–49
6 Connection of Bridge Assemblies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50
7 Connecting Reference Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–53
8 Virtual Ground IC for Signed Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–54
9 Split Power Supply for Signed Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–56
10 Current Source Used for Level Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–57
11 Signed Signals Shifted With the Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–57
12 Signed Current Measurement With Level Shifting (Current Source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–58
13 Resistor Divider for High Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–59
14 Virtual Ground Circuitry for Level Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–61
15 Current Source Used for Level Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–62
16 Referencing With Precision Resistors – No Amplification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–64
17 Referencing with Precision Resistors – With Amplification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–66
18 Sensor Connection via Long Cables With Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–67
19 Analog-to-Digital Converter Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–68
20 Routing That is Sensitive to External EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–69
21 Routing for Minimum EMI Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–69
22 Dividing of an ADC-Step Into Four Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–70
23 Hardware for a 16-Bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–71
24 ADC-Resolution Expanded to 15 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–72
25 ADC-Resolution Expanded to 16 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–73
26 Influence of the Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–77
List of Tables
1 Resistor Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–61
2 Measurement Results of the 16-Bit Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–70
3 Calculation Results for Different 16-Bit Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–75
2–44 SLAA046
Application Basics for the MSP430 14-Bit ADC
Lutz Bierl
ABSTRACT
This application report gives a detailed overview of several applications for the 14-bit
analog-to-digital converter (ADC) of the MSP430 family. Proven software examples and
basic circuitry are shown and explained. The 12-bit mode is also considered, when
possible. The References section at the end of the report lists related application reports
in the MSP430 14-bit ADC series.
1 Introduction
The application report Architecture and Function of the MSP430 14-Bit ADC[1]
explained the architecture and function of the MSP430 14-bit analog-to-digital
converter (ADC). The hardware (registers, current source, used reference,
interrupt handling, clock generation) was explained in detail and typical ADC
characteristics were shown.
Figure 1 shows the block diagram of the MSP430 14-bit ADC.
AVcc
SVcc Switch ACTL.1 (Vref)
Offset
SVcc ACTL.12(Pd) Canc. Pd
AVcc/2
Generator
_
Rex
C 2C 4C 8C 16C +
128 Range
Rext _ D MUX
Isource 0.75 SVcc
+
VH
128
PD C Resistor
Capacitor
Array
AVcc/2 ACTL.6,7 128
B Decoder VL
Generator ACTL.8
1:4 Delay
(CSoff)
128
A
AGND 7 2 5
ACTL.9, 10(Range)
(AVss)
ACTL.11(Auto) Successive Approximation
A0 Register
ACTL.0(SOC)
A1 ADCLK/12
A2 8:1 EOC
Input
A3
A4 /12
A5 Input
A6 MUX ACTL.2.4 (Ax)
A7 /1, /2 ACTL 14
ACTL.5 (None)
/3, /4 ACTL 13
MCLK
SAR.13 SAR.0 ACTL.14 ACTL.0
A7 A0 AEN.0–7
8
Input Buffer AIN Input Buffer Enable AEN Output Buffer ADAT Control Register ACTL
2–45
Applications
2 Applications
This application report shows several methods for connecting resistive sensors,
bridge assemblies, and analog signals to the ADC. Solutions are given for the
12-bit and 14-bit conversions, with and without using the integrated current
source. The equations shown result in voltages and resistances. To calculate the
sensor values (pressure, current, temperature, light intensity a.s.o) normally with
non-linear equations, refer to the following sections of Chapter 5:
• Table Processing (Section 5.2)
• Temperature Calculations for Sensors (Section 5.5.6)
– Table Processing for Sensor Calculations
– Algorithms for Sensor Calculations
– Coefficient Calculations for the Equations
• The Floating Point Package (Section 5.6)
2.1 Connection of Analog Signals and Sensors
Figure 2 shows possible methods for connecting analog signals to the ADC. The
methods shown are valid for the 12-bit and 14-bit conversion modes:
1. Current supply for resistive sensors Rsens1 at analog input A0
2. Voltage supply for resistive sensors Rsens2 at analog input A1
3. Direct connection of input signals Vin at analog input A7
4. Four-wire circuitry with current supply Rsens3 at output A3 and inputs
A4 and A5
5. Reference diode with voltage supply Dr1 at analog input A6
6. Reference diode with current supply Dr2 at analog input A2
The resistance of the wiring, Rwire, in the following equations may be neglected
if it is low compared to the sensor resistance.
SVcc SVcc
ICS
Rv Rex ICS A3 Rvd
Rext A6
A4
Vin A7
R1 MSP430C32x Rsens3
A1
A5
ICS
R2 A0 A2
Rsens2 Rsens1
0V 5 V/3 V
2–46 SLAA046
Applications
Ics ( Rx ) 2 Rwire )
N + VA0 × 2 14 + × 2 14
VREF VREF
0.25 × VREF × ( Rx ) 2 Rwire )
N+ Rex × 2 14 + Rx ) 2 Rwire × 2 12
Vref Rex
This leads to:
ǒ
N + VA0 * n × 0.25 × VREF × 2 14 + Rx ) 2 × Rwire * n × 2 12
VREF Rex
Ǔ
This leads to:
VREF SVcc
Rex
Ics
Rext
Rwire
ICS
A0 MSP430
Rx VA0
Rwire
AVss AVcc
DVss DVcc
0V 5V
If the resistance of the wires may be neglected (Rx >> Rwire) then the above
formulas simplify to (14-bit conversion):
N + Rx × 2 12 Rx + Rex × N12
Rex 2
N+ ǒRex
Rx * n Ǔ × 2 12
Rx + Rex × ǒ2N ) n Ǔ
12
N+ ǒVVREF
A1
* n × 0.25 Ǔ × 2 14
+ ǒRv )RxRx))2 ×2 Rwire
Rwire
* n × 0.25 Ǔ × 2 14
Rx + Rv × 1 * 2 × Rwire
2 14 *1
N)n × 2 12
VREF SVcc
Rv
Rwire
A1 MSP430
Rx VA1
Rwire
AVss AVcc
DVss DVcc
0V 5V
N+ Rx × 2 14 ³ Rx + Rv × 14N
Rv ) Rx 2 *N
2–48 SLAA046
Applications
N+ ǒRv Rx
) Rx
* n × 0.25 Ǔ × 2 14
³ Rx + Rv ×
2 14
1
*1
N)n × 2 12
VREF SVcc
Rex
Rext
Rwire Ics
A2
A1
I=0 MSP430
Rx I=0
A0
VA1
Rwire VA0
R2
AVss
DVss DVcc
0V 5V
DN + 0.25 × VREF × Rx × 2 + Rx × 2 12
14
Rex VREF Rex
Rx + Rex × D12
N
2
NOTE:
The two formulas above are valid for 14-bit and 12-bit conversions. If
the 12-bit ADC results are measured in different ADC ranges, then the
12-bit results need a correction (the missing two MSBs—13th and 14th
bits—of the ADC results must be added):
Range A: 0 Range B: 1000h Range C: 2000h Range D: not possible
Resistor R2 is necessary, because the ADC cannot measure down to AVss (0 V)
due to saturation effects. R2 may be quite small; it is only necessary to get above
the saturation voltage—normally less than 30 ADC steps.
The software to measure ∆N is shown next. The hardware of Figure 5 is used:
; Measure upper leg of Rx at input A1 and store ADC value.
; The Current Source is connected to A2
;
MOV #RNGAUTO+CSA2+A1+VREF,&ACTL ; Define ADC
CALL #MEASR ; Upper leg voltage of Rx (A1)
MOV &ADAT,R5 ; Store A1 value in R5
;
; Measure lower leg of Rx at input A0. Current Src to A2
;
MOV #RNGAUTO+CSA2+A0+VREF,&ACTL ; Define ADC
CALL #MEASR ; Lower leg voltage of Rx (A0)
;
; The difference delta N of the 2 measurements is proportional
; to the value Rx: Rx = Rext x deltaN x 2∧–12
;
SUB &ADAT,R5 ; R5 contains delta N
... ; Calculate Rx
2.1.4 Connection of Bridge Assemblies
Bridge assembly sensors are best known for pressure measurement. The
voltage difference (Vp – Vm) between the two bridge legs changes with the
pressure to be measured. For clarity, the temperature measurement circuitry that
is normally necessary is not included.
Bridge Assembly 1
VREF SVcc Bridge Assembly 2
Rb R1 Rb
Rb Rext Rb
R2
A1 + Vm
Vm Vp A3
A2 – Vp
Reference
Rb A4 Rb
Rb Rb
MSP430C32x
AVss Avss
DVss DVss
0V 3 V (5 V)
2–50 SLAA046
Applications
Combining the two equations above delivers the interesting two equations:
DN + v × DRb × 2 14 + R1 × DRb × 2 14
Rb R2 Rb
For the bridge output value ∆Rb/Rb, the following equation is used: the value
∆Rb/Rb is necessary for the final calculation of the measured item, e.g., pressure
p = f(∆Rb/Rb):
DRb + DN + R2 × N A3 * N A4
Rb v × 2 14 R1 2 14
If the reference input (analog input A4 in Figure 6) is not implemented, then the
difference of two measurements at the amplifier output (analog input A3 in
Figure 6) is used. The voltage difference ∆V between two measurements is:
DRb1 * DRb 0
DV + V
A31 * V A30 + v ) 0.5 × Vref ×
( )
Rb
The same voltage difference ∆V described with the ADC equation is:
The two equations above deliver the equation for ∆N, e.g., the ADC value
representing the difference of two weights:
Rb R2
ǒ
DN + NA31 * NA30 + ( v ) 0.5 ) × DRb1 * DRb0 × 2 14 + R1 ) 0.5 ×
Rb
Ǔ
( DRb1 * DRb0 )
× 2 14
And for the difference of the two bridge output values that represent for example
a weight difference. The value ∆Rb/Rb is used for the final calculation of the
measured item, e.g., the weight G = f(∆Rb/Rb):
DRb + DRb1 * DRb0 + NA31*NA30 + NA31 * NA30
Rb Rb ( v ) 0.5 ) × 2 14 ǒ
R1 ) 0.5 × 2 14
R2
Ǔ
Where: ∆N Difference of the two ADC results (here NA31–NA30)
NA30 ADC result of the 1st measurement, e.g., the zero point
of the bridge
NA31 ADC result of the 2nd measurement, e.g., a weight
measurement
∆V Voltage difference of two analog measurements
(VA31–VA30) [V]
VA30 Voltage at the analog input A3, e.g., for the zero point
of bridge [V]
VA31 Voltage at the analog input A3, e.g., a weight
measurement [V]
v Amplification of the operational amplifier: v=R1/R2
∆Rb0 Resistor deviation (Rb0–Rb) of the 1st measurement [Ω]
∆Rb1 Resistor deviation (Rb1–Rb) of the 2nd measurement [Ω]
∆Rb Resistor difference (Rb1–Rb0)
Rb Nominal value of a single bridge resistance [Ω]
2–52 SLAA046
Applications
VSVcc
SVcc
Vin A2
R1
A1
R2 A0
VDr1 VDr2 ICS
Dr1 Dr2
AVss
DVss DVcc
0V 5V/3V
The unknown voltage Vsvcc is fixed by the measurement of the reference voltage
VDr:
14
VDr N14
Dr
× Vsvcc Vsvcc 2 × V
Dr
2 NDr
The calculation above uses the mean value of the measured values of the voltage
Vsvcc (linear correction).
0V
AVss
DVss DVcc
NOTE: The V1 range is –1.5 V to 1.5 V for Vref = 3.0 V
0V 5V
2–54 SLAA046
Applications
V1 VREF × D14
N
2
2.5 V
SVcc
–2.5 V to 2.5 V
A1
V1 V1
VREF
0V A0 MSP430
0.5xVREF
–2.5 V
AVss
DVss DVcc
–2.5 V 2.5 V
V1 + VREF × D14
N
2
2–56 SLAA046
Applications
VREF SVcc
ICS
Rex
Rext
Rh
A1
ICS MSP430
V1 VA1
–1.25 V to 1.25 V @ 5 V V1
AVSS
DVSS DVCC
0V 5V/3V
NOTE: The V1 range is –0.75 V...+0.75 V for Vref = 3 V
V1 ADC Value
VREF 03FFFh
0 00000h
Time
0
Rh Vzv × Rex
0.25 × VREF
Where: Vzv Voltage of the signal midpoint (signal zero voltage) [V]
VREF Voltage at the SVcc terminal (external or AVcc) [V]
Rex Resistor between SVcc and Rext terminal (defines Ics) [Ω]
Rh Shift resistor [Ω]
The voltage VA1 at the analog input A1 is:
Voltage
CT Rsh A1
Current
A2 A0
Rc Ics
Iac Ics
MSP430C32x VA0 R2 Shunt
Vct VA2 Vsh
Rld
AVss AVss OV
0V
AC Measurement DC Measurement
Figure 12. Signed Current Measurement With Level Shifting (Current Source)
AC Measurement: A current transformer CT is shown. Its output voltage is
shifted into the ADC range by the current Ics of the current source and the resistor
Rsh. The tolerable range for Ics is:
ICSmin ¦ ICS ¦ Idcmax
Icsmin is defined by the ADC specification, and Idcmax is given by the current
transformer specification. Current transformers normally are sensitive to dc bias
currents. Rcu is the resistance of the transformer’s secondary winding (normally
Rld >> Rcu).
VA2 + Vct ) ( Rsh ) Rcu ) × ICS
2–58 SLAA046
Applications
0V 5 V or 3 V
For high input voltages V1 the resistors R1 and R2 are normally equal—it is not
possible or necessary to correct the small error of the input signal—so the
equation simplifies to:
NOTE: The formulas given in this section are valid only if both
measurements for differences (∆N) are measured in the same
ADC range. If they are measured in different ADC ranges, then the
12–bit results need a correction (the missing two MSBs of the
ADC result must be added). The correction numbers are:
Range A: 0
Range B: 1000h
Range C: 2000h
Range D: 3000h
2–60 SLAA046
Applications
Resistors R1 and R2 can have relatively high resistances. Only the offset current
of the op amp limits these resistor values.
VREF
SVcc
R1
A1
V1 –0.6 V to 0.6 V @ 5V V1
_
A0
+
R2 Vvg
MSP430
AVss
0V
DVss DVcc
NOTE: The range for V1 is –0.37 V to 0.37 V if VREF is 3 V
0V 5V/3V
V1 VREF × D14
N
2
Where: V1 Voltage to be measured inside of one ADC range [V]
∆N Difference of two ADC results (here NA1–NA0)
VREF Voltage at the SVcc terminal measured against AVss terminal [V]
Vvg Voltage at the A0 input (center of the used ADC range) [V]
EXAMPLE: The center voltage of the C range (at analog input A0) is measured
and stored in location VIRTGR (register or RAM). The value of VIRTGR is
subtracted from the ADC value measured at analog input A1; this gives the
signed, offset corrected value for the input signal at the A1 input. The
measurement subroutine MEASR of section 4.1 is used.
; Measure center voltage of range C at analog input A0 and
; store value for reference. MCLK = 3.3MHz: divide MCLK by 3
;
MOV #ADCLK3+RNGC+CSOFF+A0+VREF,&ACTL
CALL #MEASR ; Measure A0 (center voltage)
V1 VA1 VA1
VREF SVcc
2000h
Range B Ics
Rex
1000h
Range A Rext
0 Rh
A1
ICS MSP430
V1 VA1
–1.6 V to 0.6 V @ 5 V V1
AVSS
DVSS DVcc
NOTE: The range for V1 is –0.37 V to 0.37 V if VREF is 3 V
0V 5 V or 3 V
The unknown voltage V1 measured to its zero point in the center of range n is:
V1 + VAx * Rh × ICS
2–62 SLAA046
Applications
For input voltages V1 that are much higher than VREF, the following equation is
valid (Rh >> R2):
R1||R2 R2
VA1 + V1 × ) VREF × + N14
A1
× VREF
R1||R2 ) Rh R1 ) R2 2
2
ǒ
V1 + VREF × 0.125 × N11
A1
*1 × 1) Ǔ ǒ Rh
0.125 × 0.875 × R
Ǔ
To get the full accuracy of the ADC, the condition R1||R2 < 27 kΩ must be fulfilled.
This means R < 247 kΩ.
The nominal formulas given in the previous section need to be modified if the
tolerances of the ADC, the current source, the external components, and the
sensor are considered. The ADC value Nx for a given resistor Rx is now:
Nx + Rx × 2 12 × Slope ) Offset
Rex
The slope and the offset are used for the correction of the measured result Nx.
For the calculation of the slope and offset measurements with different resistors,
Rx are necessary. With the hardware shown in figure 16 this calibration process
can be omitted.
Rex SVCC
Ics
Rext
A0
A1
MSP430
A2
Rref1 Rx Rref2
AVSS
DVSS DVCC
0V 3V/5V
2–64 SLAA046
Applications
Rex Rref2
2
VREF
SVCC
R2 R1 Rex
TP.1
TP.2
AVss
0V
DVss DVcc
0V 5V/3V
DNx * DNref 2
Rx + × ǒ Rref 2 * Rref 1 Ǔ ) Rref 2
DNref 2 * DNref 1
Where: ∆Nx Difference of the two ADC results for Rx (NA1–NA0)
∆Nref1 Difference of the two ADC results for Rref1 (NA1–NA0)
∆Nref2 Difference of the two ADC results for Rref2 (NA1–NA0)
Vm Voltage generated by the resistor divider R2 and R3
The differences named above are the differences between the ADC conversion
results measured at the analog inputs A1 and A0 for each resistor:
∆N = NA1 – NA0.
2–66 SLAA046
Hum and Noise Considerations
SVCC SVCC
RV RV
Shield Shield C C
No Shield, Twisted Pair
AVSS AVSS
DVSS DVCC
0V 5V
Figure 18. Sensor Connection via Long Cables With Voltage Supply
With the circuitry of figure 18, the minimum time tdelay between the switch-on of
the voltage SVcc and the actual measurement—to get the full 14-bit
accuracy—is:
tdelay § ln 2 14 × tmax + 9.704 × tmax [ 10 × tmax
The value of τmax is:
tmax + ( Rp ) Rsensmax||Rv ) × C
If the current source is used, then:
Rv + R : t max + ( Rp ) Rsensmax ) × C
3.2 Grounding
Correct grounding is very important for ADCs with high resolution. There are
some basic rules that need to be observed1. See Figure 19 also.
1. Use a separate analog and digital ground plane wherever possible: thin
traces from the battery to terminals DVss and AVss should be avoided.
2. The AVss terminal should serve as a star point for all analog ground
connections e.g. sensors, analog input signals. The DVss terminal should
serve as a star point for all digital ground connections e.g. switches, keys,
power transistors, output lines, digital input signals.
3. The battery and storage capacitor Cb should be connected close together
(the capacitor Cb is needed for batteries with a relatively high internal
resistance). From this capacitor two different paths go to the analog and the
digital supply terminals. Two small capacitors are connected across the
digital (Cd) and the analog (Ca) supply terminals. See Figure 19.
4. Rules 1 to 3 above are also true for the Vcc paths (DVCC and AVCC).
5. The AVss and DVss terminals must be connected together externally; they
are not connected internally. The same is true for the AVcc and DVcc
terminals. These connections should be made with the configuration shown
in Figure 19.
6. The coil L should be used in very difficult cases.
7. The connections of the capacitor Cb are the star point of the complete system.
This is due to the low impedance of this capacitor.
SVCC
Rv Rex
Rext
MSP430C32x
A1
RSENS2 RSENS1 A0
Ca L Cd
To Other Digital Parts
AGND
0V 3V
Cb
To Metallization of Case
Battery
2–68 SLAA046
Hum and Noise Considerations
3.3 Routing
Correct routing for a PC board is very important for minimum noise. Figure 20
shows a simplified routing that is not optimal; the gray areas receive EMI from
external sources. For a minimum influence coming from external sources these
areas must be as small as possible.
Sensor RV
SVCC
Long Rp
RSENS Cable A1
MSP43032x
Shield C
AVSS
DVSS DVCC
PC Board 0
V
Battery
Figure 21 shows an optimized routing; the areas that may fetch noise have a
minimum size.
Sensor RV
SVCC
Long Rp
RSENS Cable A1
MSP43032x
Shield C
PC Board AVSS
DVSS DVCC
0
V
Battery
ADC Value
XXXX + 1
XXXX
XXXX – 1
00000h ADC Input Voltage
0 V0 V1 V2 V3
Table 2 shows the different results of these four measurements for the four
possible input voltages V0 to V3 inside of one ADC-step; the table refers to the
hardware shown in Figure 23.
Table 2. Measurement Results of the 16-Bit Method
MEASUREMENT 1 MEASUREMENT 2 MEASUREMENT 3 MEASUREMENT 4
INPUT MEAN VALUE
TP.1: Hi-Z TP.1: Hi-Z TP.1: Hi OUT TP.1: Hi OUT
VOLTAGE (BINARY)
TP.0: Hi-Z TP.0: Hi OUT TP.0: Hi-Z TP.0: Hi OUT
V0 XXXX XXXX XXXX XXXX XXXX.00
V1 XXXX XXXX XXXX XXXX+1 xxxx.01
V2 XXXX XXXX XXXX+1 XXXX+1 XXXX.10
V3 XXXX XXXX+1 XXXX+1 XXXX+1 XXXX.11
2–70 SLAA046
Enhancement of the Resolution
TP.0
TP.1
Simplified Circuity of a TP–Output SVcc
Vcc R16 R15 Rex
TP.x MSP430C32x
Hi–Z Rext
RDSon
Rn VSS A1
Rext
Rx
AVSS
DVSS DVCC
0V 5V
R1 V = R1/(R2+Rb/ 2)
MSP430C32c
R2 Rb
+ Vm
A0
– Vp ≈ VREF/2
Reference
A1
Rn Icorr Rb=350Ω
TP.0
AvSS
DVCC DVSS
3 V (5 V) 0V
DVA0 + VREF
2 15
+
2 ×
Rb
Rn ) Rb
× VCC * VREF × v
2
ǒ Ǔ
This gives an approximate value for Rn (VCC = VREF):
Rn [ Rb × 2 13 × R1
R2
Where: ∆VA0 Change of the input voltage at input A0 due to Rn [V]
Rb Resistance of a half bridge leg (here 350 Ω) [Ω]
Rn Resistance of the resistor for 15 bits resolution [Ω]
v Amplification of the operational amplifier: v = R1/R2
VREF Supply voltage at the SVcc terminal (int. or ext.) [V]
DVCC Supply voltage at DVcc terminal (output voltage of TP.0)[V]
R1,R2 Resistors defining the amplification of the op amp
2–72 SLAA046
Enhancement of the Resolution
Without any change to the hardware above, the resolution of the ADC can be
increased to 15.5 bits (this method is only possible with sensor assemblies like
those shown in Figure 24, that deliver output voltages near 0.5 x Vref):
• TP.0 is off (Hi-Z): normal measurement
• TP.0 is switched to Vcc: the current into the right bridge leg increases the
voltage at A1 by 0.5 steps of the ADC
• TP.0 is switched to Vss: the current out of the right bridge leg decreases the
voltage at A1 by 0.5 steps of the ADC
Three differential ADC measurements (NA0 – NA1)—one with TP.0 switched to
Hi-Z, one with TP.0 switched to Vss, and one switched to VCC—are summed-up
and provide (nearly) 15.5-bit resolution. The calculations following these six
measurements must be changed for an input value of 3 × N.
R1
MSP430C32x
R2 Rb
+ Vm
A0 Vp≈Vref/2
–
Reference
A1
R15 Rb=350Ω
TP.0
R16 RS (1M)
TP.1
AvSS
RP (1kΩ)
DVCC DVSS
3V/5V 0V
Rp Rb
Rn 2 n × R1 × ×
R2 Rs 2
Where: n Bit number of resolution resistor (15 or 16)
Rn Resistance of resolution resistor (bit n) [Ω]
Rb Resistance of a half bridge leg (here 350 Ω) [Ω]
Rp Parallel resistor (chosen to be 1k: small compared to 1 M) [Ω]
Rs Serial resistor (chosen to be 1M: large compared to 350 Ω) [Ω]
With the circuitry of Figure 25 (v = 100) R15 now becomes 573 k and R16
becomes 1.15M.
The necessary four measurements are described in Table 2. Each measurement
consists of two ADC conversions that are subtracted afterwards (∆N = NA0 – NA1).
The four differences ∆N are summed and deliver a 16-bit result with nearly two
bits more resolution than the normal 14-bit result. The result in R5 is 4 × ∆N.
EXAMPLE: With the hardware shown in Figure 25, four differential
measurements for ∆N are made (∆N = NA0 – NA1). The four values for ∆N are
summed in R5. The software assumes ascending order for the two TP outputs
(TP.x and TP.x+1).
BIC.B #TP1+TP0,&TPE ; TP.0 and TP.1 to Hi–Z
BIS.B #TP1+TP0,&TPD ; Set TPD.0 and TPD.1 to Hi
MOV #RNGAUTO+A0+VREF,&ACTL ; Define ADC
CALL #MEASR ; Measure with R15 = R16 = Hi–Z
MOV &ADAT,R5 ; 14–bit value to result
MOV #RNGAUTO+A1+VREF,&ACTL ; Define ADC
CALL #MEASR ; Measure with R15 = R16 = Hi–Z
SUB &ADAT,R5 ; (NA0 – NA1) to result
;
ADD.B #TP0,&TPE ; Set R16 to Hi–Out, R15 = Hi–Z
MOV #RNGAUTO+A0+VREF,&ACTL ; Define ADC
CALL #MEASR ; Measure
ADD &ADAT,R5 ; Add 14–bit value to result
MOV #RNGAUTO+A1+VREF,&ACTL ; Define ADC
CALL #MEASR ; Measure
SUB &ADAT,R5 ; (NA0 – NA1) to result
;
ADD.B #TP0,&TPE ; Set R15 to Hi–Out,R16 to Hi–Z
MOV #RNGAUTO+A0+VREF,&ACTL ; Define ADC
CALL #MEASR ; Measure
ADD &ADAT,R5 ; Add 14–bit value to result
MOV #RNGAUTO+A1+VREF,&ACTL ; Define ADC
CALL #MEASR ; Measure
SUB &ADAT,R5 ; (NA0 – NA1) to result
;
ADD.B #TP0,&TPE ; Set R15 and R16 to Hi–Out
MOV #RNGAUTO+A0+VREF,&ACTL ; Define ADC
CALL #MEASR ; Measure
ADD &ADAT,R5 ; Add 14–bit value to result
MOV #RNGAUTO+A1+VREF,&ACTL ; Define ADC
CALL #MEASR ; Measure
SUB &ADAT,R5 ; (NA0 – NA1) to result
;
BIC.B #TP1+TP0,&TPE ; TP.n off
... ; 16–Bit result 4xN in R5
;
2–74 SLAA046
Enhancement of the Resolution
N1 Vref 0
N0 Vref 1
2–76 SLAA046
Hints and Recommendations
emax + N1 * N0 × 100 +
N0
ǒ Vref 0
Vref 1
* 1Ǔ × 100
AVCC
Vref1
Range
Sampling Sample Conversion Sample End of Conversion
Time
I
CC
+ ICCdigital ) ICCanalog + ǒ V5V
DVcc
×
f MCLK
1MHz
Ǔ ǒ
× 750 µA ) VAVcc × 200 µA
3V
Ǔ
Where: ICC Complete current consumption of MSP430 (nominal) [µA]
ICCdigital Current consumption of the digital parts [µA]
ICCanalog Current consumption of the ADC [µA]
VDVcc Voltage at the DVCC terminal [V]
VAVcc Voltage at the AVCC [V]
fMCLK Frequency of the system clock generator (MCLK) [Hz]
2–78 SLAA046
Additional Information
6 Additional Information
This application report is complemented by the Additive Improvement of the
MSP430 14-Bit ADC Characteristic application report[5] that explains several
methods to minimize the error of the 14-Bit ADC. For all methods (linear,
quadratic, cubic and others) the actual improvement for a measured ADC
characteristic is shown. The enhancement methods discussed are compared
completely with statistic results, advantages and disadvantages, necessary CPU
cycles, and storage needs.
7 References
1. Architecture and Function of the MSP430 14-Bit ADC Application Report,
1999, Literature #SLAA045
2. MSP430 Application Report, 1998, Literature #SLAAE10C
3. MSP430 Family Architecture Guide and Module Library, 1996, Literature
#SLAUE10B
4. MSP430C325, MSP430P323 Data Sheet, 1999, Literature #SLAS219
5. Additive Improvement of the MSP430 14-Bit ADC Characteristic Application
Report, 1999, Literature #SLAA047
6. Linear Improvement of the MSP430 14-Bit ADC Characteristic Application
Report, 1999, Literature #SLAA048
7. Nonlinear Improvement of the MSP430 14-Bit ADC Characteristic
Application Report, 1999, Literature #SLAA050
Lutz Bierl
2-83
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
2-84
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–87
2 The External Calibration Hardware for the ADC Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–89
2.1 Measurement Methods for the ADC Reference Samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–89
2.2 External Digital-to-Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–89
2.3 External Discrete, Precise Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–92
2.4 External Discrete Precision Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–93
2.5 Storage of the Correction Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–93
3 Different Improvement Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–94
3.1 The ADC Characteristic of Device 1 Without Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–95
3.2 Correction Methods Using Addition Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–96
3.2.1 Correction With the Mean Value of the Full ADC Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–96
3.2.2 Correction With the Mean Values of the Four Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–99
3.2.3 Correction With the Center Points of the Four Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–101
3.2.4 Correction With Multiple Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–103
3.2.5 Summary of the Additive Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–108
3.3 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–108
4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–109
Appendix A Definitions Used With the Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–111
List of Figures
1 The Hardware of the 14-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–88
2 Flowchart 1: Calibration With an External Digital-to-Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–90
3 External, Serially Controlled DAC for ADC Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–91
4 External, Parallel Controlled DAC for ADC Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–92
5 External, Precise Voltages for Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–92
6 External Precision Resistors for Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–93
7 The Noncorrected Characteristic of Device 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–96
8 Principle of the Error Correction by the Mean Value of the Full Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–97
9 Error Correction With the Mean Value of the Used Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–98
10 Principle of the Error Correction With the Mean Values of the Four Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 2–99
11 Error Correction With the Mean Values of the Four Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–100
12 Principle of the Error Correction With the Centers of the Four Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–101
13 Correction With the Centers of the Four Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–102
14 Principle of the Additive Correction With Multiple Sections (8 sections) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–103
15 Additive Correction With 8 Sections Over the Full ADC Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–104
16 Additive Correction With 16 Sections Over the Full ADC Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–104
17 Additive Correction With 32 Sections Over the Full ADC Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–105
18 Additive Correction With 64 Sections Over the Full ADC Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–106
19 Improvement of the ADC Results With Increasing Section Count p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–107
20 Overview of the Additive Correction Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–108
2–86 SLAA047
Additive Improvement of the MSP430 14-Bit ADC Characteristic
Lutz Bierl
ABSTRACT
This application report shows different simple methods to improve the accuracy of the
14-bit analog-to-digital converter of the MSP430 family. They all use only addition for the
correction of the analog-to-digital converter characteristic. Different correction methods
are explained—all without the need for multiplication—which makes them usable for real
time systems like electronic electricity meters. The methods used differ in RAM and ROM
allocation, reachable improvement, and complexity. The external hardware for the
measurement of the analog-to-digital converter characteristic is also described. For all
correction methods, proven, optimized software examples are given. The References
section at the end of the report lists related application reports in the MSP430 14-bit ADC
series.
1 Introduction
The application report Architecture and Function of the MSP430 14-Bit ADC[1]
gives a detailed overview to the architecture and function of the 14-bit
analog-to-digital converter (ADC) of the MSP430 family. The principle of the ADC
is explained and software examples are given. Also included are the explanation
of the function of all hardware registers contained in the ADC.
The application report Application Basics for the MSP430 14-Bit ADC[2] shows
several applications of the 14-bit ADC of the MSP430 family. Proven software
examples and basic circuitry are shown and explained.
Figure 1 shows the block diagram of the 14-bit analog-to-digital converter of the
MSP430 family.
2–87
Introduction
AVcc
SVcc Switch ACTL.1 (Vref)
Offset
SVcc ACTL.12(Pd) Canc. Pd
AVcc/2
Generator
_
Rex
C 2C 4C 8C 16C +
128 Range
Rext _ D MUX
Isource 0.75 SVcc
+
VH
128
PD C Resistor
Capacitor
Array
AVcc/2 ACTL.6,7 128
B Decoder VL
Generator ACTL.8
1:4 Delay
(CSoff)
128
A
AGND 7 2 5
ACTL.9, 10(Range)
(AVss)
ACTL.11(Auto) Successive Approximation
A0 Register
ACTL.0(SOC)
A1 ADCLK/12
A2 8:1 EOC
Input
A3
A4 /12
A5 Input
A6 MUX ACTL.2.4 (Ax)
A7 /1, /2 ACTL 14
ACTL.5 (None)
/3, /4 ACTL 13
MCLK
SAR.13 SAR.0 ACTL.14 ACTL.0
A7 A0 AEN.0–7
8
Input Buffer AIN Input Buffer Enable AEN Output Buffer ADAT Control Register ACTL
2–88 SLAA047
The External Calibration Hardware for the ADC
Power-Up
No
Calibration? Initialization A
Yes
No All
Values Measured?
Output to DAC
Yes
Measure ADC Value Calculate Coefficients
for all Ranges
Calculate Error;
ADC - DAC = Error Store Coefficients in
RAM or EEPROM
Initialization
A
2–90 SLAA047
The External Calibration Hardware for the ADC
Error kW kWh
Vdd +15 V
Ox Data
O19 CS 16-Bit
0V
DAC
O20 LDAC
DG 0V
Ax VOUT
EEPROM
SVcc Vref+
AVss Vref–
Port Vss –15 V
0V
CIN,TP0.5
MSP430C32x Calibration 0V
To System Connector
TXD
To Host Computer
RCV
Error kW kWh
Vdd +15 V
O03...O18 16 DB0...15
O19 NCS 0V
O20 NLDAC
DG 0V
Ax Vout
DAC
EEPROM
SVcc Vref+ AD7846
AVss Vref–
Port Vss –15 V
0V
CIN,TP0.5
MSP430C32x Calibration 0V
To System Connector
TXD
To Host Computer
RCV
Error kW kWh
Rel. Reference
Vcc
O03...O18
SVcc 1A 1B
Ax
2A 2B Vref
MUX
EEPROM 4 TPC4016
Ox 3A 3B
AVss
Calibration 4A 4B
Connector xC Vss
MSP430C32x
TXD
To Host Computer
RCV
2–92 SLAA047
The External Calibration Hardware for the ADC
This calibration method includes all onboard error sources such as Rext and the
ADC characteristic.
Error kW kWh
S01 – S21
SVcc Rex
Ics Calibration
MSP430C32x
Connector
Rext
Ics Reference 1 Reference 2
EEPROM
Ax
AVss
DVcc
To Host DVss
TXD
Computer Ox 2
RCV 6.2 V 6.2 V
0V
The format of the used 8-bit coefficients is given in Nonlinear Improvement of the
MSP430 14-Bit ADC Characteristic, SLAA050 [4]. If the accuracy that can be
reached with these 8-bit numbers is insufficient, then 16-bit numbers—with
doubled RAM space and calculation time—may be used. Also the MSP430
floating point package can be a solution in this case.
Ǹ
The standard deviation S is defined as:
ǒȍ Ǔ
2
i+k
ei
i+k
ȍ ei 2 * i+1
Ǹ
k
i+1 k
S+ + V
k*1 k*1
ǒȍ Ǔ
2
i+k
ei
i+k
ȍ ei 2 *
i+k i+k
i+1
k ȍ ei 2 * x ȍ ei
i+1 i+1 i+1
V+ +
k k
Where:
k = Number of included ADC errors ei
ei = ADC error at ADC step i, ranging from e1 to ek [Steps]
i = Index for ADC errors
2–94 SLAA047
Different Improvement Methods
The circle in Figure 7 indicates the irregularity located in range B. This irregularity
is the reason why more sophisticated methods sometimes have worse results
than simpler ones.
Device 1 Uncorrected
4
-2
ADC Error [Steps]
-4
-6
-8
-10
-12
-14
-16
ADC Steps [0 to 16383]
3.2.1 Correction With the Mean Value of the Full ADC Range
The ADC is measured at k equally spaced points. The errors of these k
measurements are calculated and the mean value of these errors is stored and
used for the correction of the ADC. The correction formula for each ADC sample
Ni to get the corrected value Nicorr is:
2–96 SLAA047
Different Improvement Methods
ik
ei
i1
Nicorr Ni
k
Where:
Nicorr = Corrected ADC sample [Steps}
Ni = Measured ADC sample (noncorrected) [Steps]
k = Number of included ADC errors ei
ei = ADC error i, ranging from e1 to ek [Steps]
The principle is shown in Figure 8, the full ADC range is corrected with its mean
value. As with all future principle figures in this report, the black straight line
indicates the correction value, the scribbled black line indicates the noncorrected
ADC characteristic, and the white line shows the corrected ADC characteristic.
The small circles indicate the measured ADC points (the 128 circles of Figure 8
are not shown).
Device 1
10
ADC Error [Steps]
5
0
-5
-10
-15
ADC Steps
Figure 8. Principle of the Error Correction by the Mean Value of the Full Range
For k = 128—which means 128 samples over the complete ADC range—the
statistical results are:
Full range Ranges A and B only
Mean Value: –0.44 Steps 0.15 Steps
Range: 17.10 Steps 10.80 Steps
Standard Deviation: 4.74 Steps 2.61 Steps
Variance: 22.51 Steps 6.80 Steps
Figure 9 shows the result in a graph. The corrected characteristic is displayed for
the full range and for the ranges A and B only:
8
6 A and B Only
4
ADC Error [Steps]
-2
-4 Full Range
-6
-8
-10
ADC Steps [0 to 16383]
Figure 9. Error Correction With the Mean Value of the Used Range
Advantages: Only one addition is necessary
Very fast due to no missing multiplication or shifts
No gaps; the monotonicity of the ADC characteristic remains
Only one byte of RAM is needed for the correction coefficient
Disadvantages: Range, standard deviation and variance are not improved
Many calibration measurements are necessary
NOTE: Within the software examples, the format of the integer number
is noted at the right margin. The meaning of the different notations is:
0.7 Zero integer bits, 7 fraction bits. Unsigned number
±4.3 Four integer bits, 3 fraction bits. Signed number
8.0 Eight integer bits, no fraction bits. Unsigned integer number
±7.0 Seven integer bits, no fraction bits. Signed integer number
2–98 SLAA047
Different Improvement Methods
EXAMPLE: The ADC is measured at nine points (rather than 128 to keep the
example under control) and the calculated mean value is used for the correction
of the full ADC range. The measured (k+1) errors (for device 1) are shown below.
The numbers used for the correction are slightly shaded.
ADC Step 50 2048 4096 6144 8192 10240 12288 14336 16330
Error [Steps] –6 –8 –13 –13 –10 –5 0 0 –3
ik
ei
i1 5 –0–0
6 8 13 13 10 3 58 6.5
Correction: k 9 9
Corrected ADC sample: Nicorr = Ni + 6.5 Valid for the Full ADC range
7 0
7 0
±6.1 6.5/2–1 = 13 = 0Dh 0 0 0 0 1 1 0 1
10
ADC Error [Steps]
5
0
-5
-10
-15
ADC Steps
Figure 10. Principle of the Error Correction With the Mean Values of the Four Ranges
For k = 8 (8 samples per range) the statistical results are:
Full range Ranges A and B only
Mean Value: –0.31 Steps 0.15 Steps
Range: 13.5 Steps 9.80 Steps
Standard Deviation: 2.49 Steps 2.10 Steps
Variance: 6.20 Steps 4.41 Steps
Figure 11 shows the graph for k = 8 (eight samples per range, 32 samples over
the full ADC range):
4
ADC Error [Steps]
-2
-4
-6
-8
ADC Steps [0 to 16383]
Figure 11. Error Correction With the Mean Values of the Four Ranges
Advantages: Only one addition is necessary for the correction
Fast due to no multiplication
Only four bytes are needed for the storage of the correction
values
Disadvantages: Range, standard deviation and variance are only slightly
improved
Monotonicity is not preserved: gaps appear at the range
borders.
The software part after each ADC measurement is as follows:
; Correction with the mean values of the four ranges. 16 cycles
; The four signed correction values are located in four RAM
; bytes starting at label TAB
;
MOV &ADAT,R5 ; ADC result Ni to R5 (0...3FFFh)
MOV R5,R6 ; Copy result for correction 14.0
SWPB R6 ; Range bits of result to low byte
RRA.B R6 ; Calc. byte address for corr. 5.0
RRA.B R6 ; Shift two range bits to LSBs 4.0
RRA.B R6 ; 3.0
RRA.B R6 ; Range bits now 0 to 3 2.0
MOV.B TAB(R6),R6 ; Correction from table TAB ±7.0
SXT R6 ; Signed byte to signed word ±15.0
ADD R6,R5 ; Corrected result Nicorr in R5 14.0
... ; Proceed with corrected Nicorr
14.0
;
; The four signed correction values are located in four RAM bytes
; starting at label TAB.
;
.bss TAB,4 ; Signed 8–bit numbers ±7.0
2–100 SLAA047
Different Improvement Methods
EXAMPLE: Range A of the ADC is measured at four points and the mean value
is used for the correction of this ADC range. The corrections for the other three
ranges (B, C and D) are calculated the same way. The measured errors for range
A are shown below (for device 1):
ADC Step 1024 2048 3072 4096
Error [Steps] –6 –8 –12 –13
ik
ei
i1
6 8 12 13 39 9.75
Correction: k 4 4
7 0
7 0
±5.2 9.75/2–2 = 39 = 27h 0 0 1 0 0 1 1 1
The principle is shown in Figure 12, the four A/D ranges are corrected individually
with the errors of their center points:
Device 1
10
ADC Error [Steps]
5
0
-5
-10
-15
ADC Steps
Figure 12. Principle of the Error Correction With the Centers of the Four Ranges
Device 1
8
4
ADC Error [Steps]
-2
-4
-6
-8
The software part after each ADC measurement is the same one as shown for
the correction with the mean values of the four ranges.
EXAMPLE: The center point of range C (10240 steps) of the ADC is measured
and the result is used for the correction of this ADC range. The other three ranges
are treated the same way. The measured errors of the centers of the four ADC
ranges are shown below (for device 1):
ADC Step 2048 6144 10240 14336
Error [Steps] –6 –13 –5 0
2–102 SLAA047
Different Improvement Methods
Correction: ec = – (–5) = 5
The principle is shown in Figure 14. The full ADC range is divided into eight
sections (p = 8). The nine measured ADC samples are indicated with circles.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Device 1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6
4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ADC [Steps]
-2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
-4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
-6
-8
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
-10
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
-12
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
-14
-16
ADC Steps
Figure 14. Principle of the Additive Correction With Multiple Sections (8 sections)
For p = 8 (section length is 2048 steps) the statistical results are:
Full range Ranges A and B only
Mean Value: –0.14 Steps 0.22 Steps
Range: 8.40 Steps 6.30 Steps
Standard Deviation: 1.47 Steps 1.37 Steps
Variance: 2.16 Steps 1.89 Steps
Figure 15 shows the resulting graph for an additive correction with 8 sections
(p = 8) over the full ADC range:
Device 1 Corrected with Eight Sections over the Full ADC Range
5
2
ADC Error [Steps]
-1
-2
-3
-4
-5
Figure 15. Additive Correction With 8 Sections Over the Full ADC Range
1
ADC Error [Steps]
-1
-2
-3
-4
-5
ADC Steps [0 to 16383]
Figure 16. Additive Correction With 16 Sections Over the Full ADC Range
2–104 SLAA047
Different Improvement Methods
1
ADC Error [Steps]
-1
-2
-3
-4
Figure 17. Additive Correction With 32 Sections Over the Full ADC Range
For p = 64 (section length is 256 steps) the statistical results are:
Mean Value: –0.08 Steps 0.02 Steps
Range: 4.60 Steps 3.10 Steps
Standard Deviation: 0.64 Steps 0.53 Steps
Variance: 0.41 Steps 0.28 Steps
Figure 18 shows the resulting graph for an additive correction with 64 sections
(p = 64) over the full ADC range. Note the scaling of Figure 18: only ±3 steps!
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
Figure 18. Additive Correction With 64 Sections Over the Full ADC Range
Advantages: Very good improvement with large section counts p
Fast due to no multiplication
The section count p is adaptable to specific applications.
Disadvantages: Relative large RAM storage is needed for a large section count p
Gaps appear at the section borders: they get smaller with
increasing p
The results for the additive correction with multiple sections are summarized
below for section counts p ranging from 8 to 64. For comparison purposes, the
results for p = 4 ( the center of ranges method is used) are given as well.
p=4 p=8 p = 16 p = 32 p = 64
Mean Value: +0.2 –0.14 –0.29 –0.14 –0.08 Steps
Range: 13.5 8.40 6.40 5.20 4.60 Steps
Standard Deviation: 2.56 1.47 1.04 0.77 0.64 Steps
Variance: 6.53 2.16 1.08 0.59 0.41 Steps
The improvement of the statistical results with increasing section count p can be
clearly seen. Figure 19 illustrates this.
2–106 SLAA047
Different Improvement Methods
ADC Error
10
8
4
Range
2
Variance
0
-2 Standard
-4 Deviation
p=8 p = 16 p = 32 p = 64 Mean
Section Count Value x10
Figure 19. Improvement of the ADC Results With Increasing Section Count p
The software part after each ADC measurement follows. The addressing of the
correction byte can be adapted easily also to 4, 8, 16, and 32 sections.
; Additive correction for 64 sections over the full ADC range.
; The 64 signed correction values are located in the RAM
; bytes starting at label TAB. 11 cycles
;
MOV &ADAT,R5 ; ADC result Ni to R5 (0...3FFFh)
MOV R5,R6 ; Copy Ni for correction 14.0
SWPB R6 ; MSBs of result to low byte 6.0
MOV.B R6,R6 ; 00h...3Fh to R6 (0..63) 6.0
MOV.B TAB(R6),R6 ; Corr. eim from table TAB ±4.0
SXT R6 ; Extend sign of correction ±4.0
ADD R6,R5 ; Nicorr = Ni + eim 14.0
... ; Proceed with corrected Nicorr
;
; The 64 RAM bytes starting at label TAB contain the corrections
; eim for the 64 sections: each one for 256 ADC points.
; The bytes are loaded during initialization Signed 8–bit numbers
;
.bss TAB,64 ; 0..255..511....16127..16383 ±4.0
EXAMPLE: The ADC is measured at nine points (8 sections) like shown in
Figure 14. The measured errors for device 1 are shown below. The correction
coefficient ekm of the 2nd section (2048 to 4095 ADC steps, upper half of range
A) is calculated.
ADC Step 50 2048 4096 6144 8192 10240 12288 14336 16330
Error [Steps] –6 –8 –13 –13 –10 –5 0 0 –3
ekm ek 1 ek 13 8 10.5
Correction: 2 2
Corrected ADC sample: Nicorr = Ni + 10.5 Valid for the 2nd section
7 0
Format: ±7.0 10.5/20 = 10.5 ≈ 0Bh 0 0 0 0 1 0 1 1
7 0
±6.1 10.5/2–1 = 21 = 15h 0 0 0 1 0 1 0 1
ADC Error
25
20
15
10
5
Variance
Range
-5
Standard
-10 Deviation
N.C. p=1 p=2 p=4 p=8 p = 16 p = 32 p = 64 Mean
Section Count Value
2–108 SLAA047
References
4 References
1. Architecture and Function of the MSP430 14-Bit ADC Application Report,
1999, Literature #SLAA045
2. Application Basics for the MSP430 14-Bit ADC Application Report, 1999,
Literature #SLAA046
3. Linear Improvement of the MSP430 14-Bit ADC Characteristic Application
Report, 1999, Literature #SLAA048
4. Nonlinear Improvement of the MSP430 14-Bit ADC Characteristic
Application Report, 1999, Literature #SLAA050
5. MSP430 Application Report, 1998, Literature #SLAAE10C
6. Data Sheet MSP430C325, MSP430P323, 1997, Literature #SLASE06
7. MSP430 Family Architecture Guide and Module Library, 1996, Literature
#SLAUE10B
;
; ADAT .equ 0118h ; ADC data register (12 or 14–bits)
; ACTL .equ 0114h ; ADC control register: control bits
2–113
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their
products or to discontinue any product or service without notice, and advise customers to
obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current and complete. All products are sold subject to the terms
and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent
right, copyright, mask work right, or other intellectual property right of TI covering or relating
to any combination, machine, or process in which such semiconductor products or services
might be or are used. TI’s publication of information regarding any third party’s products or
services does not constitute TI’s approval, warranty or endorsement thereof.
2–114
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–117
1.1 Correction With Linear Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–118
1.2 Coefficients Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–120
1.2.1 Linear Equations With Border Fit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–120
1.2.2 Linear Equations With Linear Regression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–130
2 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–138
3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–139
Appendix A Definitions Used With the Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–141
List of Figures
1 The Hardware of the 14-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–118
2 Principle of the Correction With Border Fit (single linear equation per range) . . . . . . . . . . . . . . . . . . . . . . . . . 2–121
3 Error Correction With Border Fit (single linear equation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–122
4 Principle of the Correction With Border Fit (two linear equations per range) . . . . . . . . . . . . . . . . . . . . . . . . . . 2–125
5 Error Correction With Border Fit (two linear equations per range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–126
6 Principle of the Correction With Border Fit (four linear equations per range) . . . . . . . . . . . . . . . . . . . . . . . . . . 2–127
7 Error Correction With Border Fit (four linear equations per range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–128
8 Principle of the Linear Regression Method (single linear equation per range) . . . . . . . . . . . . . . . . . . . . . . . . 2–131
9 Error Correction With Linear Regression (single linear equation per range) . . . . . . . . . . . . . . . . . . . . . . . . . . 2–132
10 Device 2 Showing the Typical Gaps at the Range Borders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–132
11 Principle of the Linear Regression Method (two linear equations per range) . . . . . . . . . . . . . . . . . . . . . . . . . 2–136
12 Error Correction With Linear Regression (two linear equations per range) . . . . . . . . . . . . . . . . . . . . . . . . . . 2–136
List of Tables
1 Worst Case Coefficients With 8-Bit Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–120
Lutz Bierl
ABSTRACT
This application report shows different linear methods to improve the accuracy of the
14-bit analog-to-digital converter (ADC) of the MSP430 family. Different correction
methods are explained: some with monotonicity and some using linear regression. The
methods used differ in RAM and ROM allocation, calculation speed, reachable
improvement, and complexity. For all correction methods, proven, optimized, software
examples are given with 8-bit and 16-bit arithmetic. The References section at the end
of the report lists related application reports in the MSP430 14-bit ADC series.
1 Introduction
The application report Architecture and Function of the MSP430 14-Bit ADC[1]
gives a detailed overview to the architecture and function of the 14-bit
analog-to-digital converter (ADC) of the MSP430 family. The principle of the ADC
is explained and software examples are given. Also included are the explanation
of the function of all hardware registers contained in the ADC.
The application report Application Basics for the MSP430 14-Bit ADC[2] shows
several applications of the 14-bit ADC of the MSP430 family. Proven software
examples and basic circuitry are shown and explained.
The application report Additive Improvement of the MSP430 14-Bit ADC
Characteristic[3] explains the external hardware that is needed for the
measurement of the characteristic of the MSP430’s analog-to-digital converter.
This report also demonstrates correction methods that use only addition. This
allows the application of these methods in real time systems, were execution time
can be critical.
Figure 1 shows the block diagram of the 14-bit analog-to-digital converter of the
MSP430 family.
2–117
Introduction
AVcc
SVcc Switch ACTL.1 (Vref)
Offset
SVcc ACTL.12(Pd) Canc. Pd
AVcc/2
Generator
_
Rex
C 2C 4C 8C 16C +
128 Range
Rext _ D MUX
Isource 0.75 SVcc
+
VH
128
PD C Resistor
Capacitor
Array
AVcc/2 ACTL.6,7 128
B Decoder VL
Generator ACTL.8
1:4 Delay
(CSoff)
128
A
AGND 7 2 5
ACTL.9, 10(Range)
(AVss)
ACTL.11(Auto) Successive Approximation
A0 Register
ACTL.0(SOC)
A1 ADCLK/12
A2 8:1 EOC
Input
A3
A4 /12
A5 Input
A6 MUX ACTL.2.4 (Ax)
A7 /1, /2 ACTL 14
ACTL.5 (None)
/3, /4 ACTL 13
MCLK
SAR.13 SAR.0 ACTL.14 ACTL.0
A7 A0 AEN.0–7
8
Input Buffer AIN Input Buffer Enable AEN Output Buffer ADAT Control Register ACTL
2–118 SLAA048
Introduction
Nicorr Ni ( Ni a1 a0 )
a1 e2 e1 a0 e1 N2 e2 N1
N2 N1 N2 N1
The advantages of the negated correction coefficients a1 and a0 are:
• Shorter and faster software: the INV (invert) and INC (increment) instructions
for the negation of the corrections are not necessary
• The ADAT register (ADC result register) is a read-only register and can be
used for additions directly. If the correction needs to be subtracted from the
ADAT register, then an intermediate step is necessary.
All principle figures of this report—as in Additive Improvement of the MSP430
14-Bit ADC Characteristic[3]—have the same structure:
• The black straight line indicates the negated correction value (this is to show
the precision of the correction).
• The scribbled black line indicates the noncorrected ADC characteristic.
• The white line shows the corrected ADC characteristic.
• The small circles indicate the measured ADC points (not all measured
samples are shown).
An example using the 16-bit arithmetic is given in section 1.2.2.1, Linear
Regression: Single Equation per Range.
All other given equations in the following sections assume the use of the 8-bit
arithmetic as described in Nonlinear Improvement of the MSP430 14-Bit ADC
Characterisitc,SLAA050[4]. Therefore the correction formulas are adapted to the
limited, but fast 8-bit arithmetic. This reduced arithmetic makes relative
addresses for the ADC steps necessary: the full ADC range is divided into
sections and the ADC value is adapted to 128 subdivisions for the full section. The
equations for the 8-bit arithmetic are given and explained with each method.
2–120 SLAA048
Introduction
Nicorr + Ni ) ƪǒ4096
Ni –n Ǔ 128 a1 ) a0ƫ
a1 + * eu * el a0 + * el
128
Where:
Nicorr = Corrected ADC sample [Steps}
Ni = Measured ADC sample (noncorrected) [Steps]
n = Range number (0...3 for ranges A...D)
a1 = Slope of the correction
a0 = Offset of the correction [Steps]
eu = Error of the ADC at the upper border of the range [Steps]
el = Error of the ADC at the lower border of the range [Steps]
ǒ Ni
The term 4096 * n Ǔ 128 of the equation above is the adaptation of a
complete section—here a full range—to 128 subdivisions. The calculation of the
term is made by simple shifts and logical AND instructions and not a division and
a multiplication. See the initialization part of the software example.
The principle of the correction with a linear equation for each range (border fit)
is shown in Figure 2. Border fit means, that the borders of the four ranges A to
D fit together without gaps from one range to the other one: the border value is
used for both ranges.
The improvement methods and their results for this report are demonstrated with
the characteristic of device 1 and device 2 due to their worst characteristic
compared to the other three devices shown in Architecture and Function of the
MSP430 14-Bit ADC.
Device 1
5
ADC Error [Steps]
-5
-10
-15
ADC Steps
Figure 2. Principle of the Correction With Border Fit (single linear equation per range)
1
ADC Error [Steps]
-1
-2
-3
-4
ADC Steps [0 to 16383]
2–122 SLAA048
Introduction
;
MACU8 BIT.B #1,IROP1 ; Test actual bit (LSB)
JZ L$01 ; If 0: do nothing
ADD IROP2L,IRACL ; If 1: add multiplier to result
L$01 RLA IROP2L ; Double multiplier IROP2
RRC.B IROP1 ; Next bit of IROP1 to LSB
JNZ MACU8 ; If IROP1 = 0: finished
RET
EXAMPLE: The ADC is measured at the five borders of the ADC ranges. The
measured errors—device 1 is used—are shown below. The correction
coefficients for the range C are calculated. The correction coefficients for the
other three ranges may be calculated the same way, using the appropriate border
errors.
ADC Step 50 4096 8192 12288 16330
Error [Steps] –6 –13 –10 0 –3
a0 + –el + * (–10) + ) 10
Correction:
ǒ4096
Ni * n Ǔ 128 a1 ) a0 + ǒ4096
Ni * 2 Ǔ 128 (* 0.078125) ) 10.0
The correction for the ADC step 11000—located in range C—is calculated:
ǒ 11000
4096
* 2Ǔ 128 (* 0.078125) ) 10.0 + ) 3.1
Corrected ADC sample: Nicorr + Ni ) 3.1 Valid for the ADC step 11000
7 0
Format: a1: ±0.9 –0.078125/2–9 = –40 = D8h 1 1 1 1 0 1 1 0 0 0
20 2 -9
7 0
a0: ±5.2 +10.0/2–2 = +40 = 28h 0 0 1 0 1 0 0 0
20 2 -2
The number of fractional bits for a1 is derived from the following consideration:
a1 is maximally ±0.15625 (see Table 1). This value must be possible with the
largest number that can be expressed with a signed 8-bit number (7Fh):
2–124 SLAA048
Introduction
Nicorr + Ni ) ƪǒ Ni p
2 14
* n1 Ǔ 128 a1 ) a0 ƫ
(eu–el)
a1 + * a0 + * e l
128
Where:
Nicorr = Corrected ADC sample [Steps}
Ni = Measured ADC sample (noncorrected) [Steps]
n1 = Value of the MSBs of Ni (0 to p–1)
p = Number of sections over the full ADC range (8 for Figure 4)
a1 = Slope of the correction
a0 = Offset of the correction [Steps]
eu = Error of the ADC at the upper border of the section [Steps]
el = Error of the ADC at the lower border of the section [Steps]
n1 ranges from 0 to (p–1) and has a length of log2 p bits. This means for n1:
• Two linear equations per range (Figure 4): value is 0...7, length is log2 8 = 3
bits;
• Four linear equations per range (Figure 6): value is 0...15, length is
log2 16 = 4 bits;
-5
-10
-15
ADC Steps
Figure 4. Principle of the Correction With Border Fit (two linear equations per range)
The statistical results for two linear equations per range are:
Full range Ranges A and B only
Mean Value: –0.29 Steps –0.02 Steps
Range: 6.49 Steps 5.3 Steps
Standard Deviation: 0.97 Steps 1.06 Steps
Variance: 0.94 Steps 1.12 Steps
Figure 5 shows the result in a graph.
Device 1 Corrected With Eight Linear Equations (Border Fit)
2
ADC Error [Steps]
-1
-2
-3
-4
Figure 5. Error Correction With Border Fit (two linear equations per range)
Advantages: Only few measurements are necessary (p+1). Nine for the
example above
No gaps; the monotonicity of the ADC characteristic is
preserved
Better correction than with a single linear equation per range
Low memory needs: 2 × p bytes (16 for the example)
Disadvantages: Multiplication is necessary
The software is the same as shown in section 1.2.2.2, Multiple Linear Equations
per Range.
EXAMPLE: The ADC is corrected with eight sections, each one with a length of
2048 steps (p = 8). The measured errors—(device 1 of Architecture and Function
of the MSP430 14-Bit ADC, SLAA045 is used)—are shown below. The correction
coefficients for the lower section of range C—ADC steps 8192 to 10240 (n1 =
4)—are calculated. The correction coefficients for the other seven sections are
calculated the same way.
ADC Step 50 2048 4096 6144 8192 10240 12288 14336 16330
n1 0 1 2 3 4 5 6 7 7
Error [Steps] –6 –8 –13 –13 –10 –5 0 0 –3
2–126 SLAA048
Introduction
* 5 * (* 10)
a1 + * eu * el + * + * 5 + * 0.0390625
128 128 128
a0 + * el + * (* 10) + ) 10
Correction:
ǒ Ni2 14
p
* n1 Ǔ 128 a1 ) a0 + ǒ Ni2 14
8*4 Ǔ 128 (* 0.03906) ) 10.0
The correction for the ADC step 9000—located in the lower section of range C—is
calculated (p = 8, n1 = 4):
ǒ 90002 14
8*4 Ǔ 128 (* 0.0390625) ) 10.0 + 50.5 (* 0.0390625) ) 10.0 + ) 8.027
Corrected ADC sample: Nicorr + Ni ) 8.03 Valid for the ADC step 9000 (range C)
7 0
Format: a1: ±0.10 –0.039625/2–10 = –40 = D8h 1 1 1 1 1 0 1 1 0 0 0
0
2 2 -10
7 0
a0: ±5.2 +10.0/2–2 = 40 = 28h 0 0 1 0 1 0 0 0
20 2 -2
4
2
0
ADC Error [Steps]
-2
-4
-6
-8
-10
-12
-14
-16
ADC Steps
Figure 6. Principle of the Correction With Border Fit (four linear equations per range)
The statistical results for four linear equations per range are:
Full range Ranges A and B only
Mean Value: –0.22 Steps 0.07 Steps
Range: 5.36 Steps 4.07 Steps
Standard Deviation: 0.83 Steps 0.65 Steps
Variance: 0.69 Steps 0.42 Steps
1
ADC Error [Steps]
-1
-2
-3
-4
ADC Steps [0 to 16383]
Figure 7. Error Correction With Border Fit (four linear equations per range)
Advantages: Only a few measurements are necessary (p+1). Seventeen for
the example above
No gaps; the monotonicity of the ADC characteristic is
preserved
Better correction than with one or two linear equations per
range
Low memory requirements if p is small: 2 × p bytes (32 for above
example)
Disadvantages: Multiplication is necessary
For 16 linear equations for the full ADC range, the software for each ADC
measurement is as follows:
; Error correction with four linear equations per range
; (16 for the full ADC range) 8–bit arithmetic. Cycles needed:
; Subdivision = 0: 49 cycles
; Subdivision > 3Fh: 101 cycles
;
MOV &ADAT,R5 ; ADC result Ni to R5 4.0
MOV R5,R6 ; Address info for correction
AND #03FFh,R5 ; Delete 4 MSBs (n1 bits) 10.0
RLA R5 ; Calculate subdivision 11.0
RLA R5 ; 12.0
RLA R5 ; Prepare 13.0
RLA R5 ; ((Ni x p/2^14)–n1)x 128 14.0
RLA R5 ; 7 bit ADC info to high byte 15.0
SWPB R5 ; ADC info to low byte 0...7Fh 7.0
MOV.B R5,IROP1 ; To MPY operand register 7.0
2–128 SLAA048
Introduction
EXAMPLE: The ADC is corrected with sixteen sections, each one with a length
of 1024 steps (p = 16). The measured errors (device 1 of Architeture and Function
of the MSP430 14-Bit ADC, SLAA045 is used.) are shown below. The correction
coefficients for the lowest section of range C—ADC steps 8192 to 9216 (n1 =
8)—are calculated. The correction coefficients for the other seven sections are
calculated the same way.
ADC Step 8192 9216 10240
n1 8 9 10
Error [Steps] –10 –7 –5
a0 + * el + * (* 10) + ) 10
Correction:
ǒ Ni2 14
p
* n1 Ǔ 128 a0 ) a1 + ǒ Ni2 16 * 8
14
Ǔ 128 (* 0.0234375) ) 10.0
The correction for the ADC step 9000—located in the lower section of range C—is
calculated (p = 16, n1 = 8):
ǒ 90002 14
16 * 8 Ǔ 128 (* 0.0234375) ) 10.0 + 101.0 (* 0.0234375) ) 10.0 + ) 7.63
Corrected ADC sample: Nicorr + Ni ) 7.63 Valid for the ADC step 9000 (range C)
7 0
20 2 -11
7 0
a0: ±5.2 +10.0/2–2 = 40 = 28h 0 0 1 0 1 0 0 0
20 2 -2
ǒȍ Ǔ
2
i +k
N
i+k
i+1
k
* ȍ N2
i+1
2–130 SLAA048
Introduction
Nicorr + Ni ) ƪǒ4096
Ni * n Ǔ 128 a1 ) a0 ƫ
Where:
n = Range number (0...3) for ADC ranges A...D)
a1 = Slope calculated by the host or MSP430
a0 = Offset calculated by the host or MSP430 [Steps]
k = Number of samples for each linear equation (range)
ǒNi
The term 4096 * n Ǔ 128 of the above equation is the adaptation of a
complete section—here a full range—to 128 subdivisions. The calculation is
made by simple shifts and logical AND instructions. See the initialization part of
the example below.
The principle of this method is shown in Figure 8, the eight measured samples
are drawn only in range A (k = 8):
Device 1
5
ADC Error [Steps]
-5
-10
-15
ADC Steps
Figure 8. Principle of the Linear Regression Method (single linear equation per range)
Full range Ranges A and B only
Mean Value: 0.03 Steps 0.12 Steps
Range: 5.09 Steps 4.85 Steps
Standard Deviation: 0.94 Steps 1.00 Steps
Variance: 0.88 Steps 1.00 Steps
The statistical results for 8 and 16 measurements per range are shown below:
as it can be seen, 16 samples per range improve the final result only marginally.
8 Samples per range 16 Samples per Range
Mean Value: 0.03 Steps 0.07 Steps
Range: 5.09 Steps 5.04 Steps
Standard Deviation: 0.94 Steps 0.92 Steps
Variance: 0.88 Steps 0.85 Steps
Figure 9 shows the result of this method: eight samples per range are measured
(k=8). Note the small range of only ±3 steps.
Device 1 Corrected With Four Linear Equations (Linear Regression, EIght Samples per Range)
3
2
ADC Error [Steps]
-1
-2
-3
ADC Steps [0 to 16383]
Figure 9. Error Correction With Linear Regression (single linear equation per range)
Advantages: Good adaptation to the ADC characteristic
Disadvantages: One multiplication is necessary
Small gaps at the borders of the four ranges
Calculation of the linear regression is necessary during the
calibration
Device 2
15
10
ADC Error [Steps]
-5
-10
ADC Steps [0 to 16383]
Figure 10. Device 21 Showing the Typical Gaps at the Range Borders
1 This is device 2 from Archecture and Function of the MSP430 14-Bit ADC Application Report #SLAA045.
2–132 SLAA048
Introduction
The correction software for the 8-bit arithmetic is identical to the one shown in
section Single Linear Equation per Range (Border Fit), section 1.2.1.1.
Here an additional solution with 16-bit integer arithmetic is given.
; Error correction with a single equation per range
; 16-bit arithmetic. Cycles needed:
; ADAT value = 0000h: 47 cycles
; ADAT value = 3FFFh: 178 cycles
;
MOV &ADAT,IROP1 ; ADC result Ni to MPY reg. 14.0
MOV IROP1,R6 ; Calculation of coeff. address 14.0
SWPB R6 ; MSBs to low byte 0...3Fh 6.0
RRA.B R6 ; 5.0
RRA.B R6 ; 4n (Range) in R6 0...0Fh 4.0
BIC #3,R6 ; 0...0Ch: address of slope a1 4.0
MOV TAB1(R6),IROP2L ; Slope a1 0.22
CALL #MPYS ; Ni x a1 ±4.22
RRA IRACM ; Only HI result is used ±4.5
RRA IRACM ; To format 4.3 of offset a0 ±4.4
RRA IRACM ; ±4.3
ADD TAB0(R6),IRACM ; Add Offset a0 ±5.3
RRA IRACM ; Nicorr = Ni x a1 + a0 ±5.2
RRA IRACM ; ±5.1
RRA IRACM ; Carry is used for rounding ±5.0
ADDC &ADAT,IRACM ; Nicorr in IRACM 14.0
... ; Proceed with corr. result Nicorr
;
; The 16 RAM bytes starting at label TAB1 contain the
; correction info a1 and a0 for all four ranges. The bytes
; are loaded during the calibration
;
.bss TAB1,2 ; Range A a1: lin. coefficient ±0.22
.bss TAB0,2 ; a0: constant coefficient ±5.3
.bss TABx,12 ; Ranges B, C, D: a1, a0.
; Run time optimized 16–bit Multiplication Subroutines
;
IROP1 .EQU R11 ; Unsigned ADC result (0...3FFFh)
IROP2L .EQU R12 ; Signed factor (8000h...7FFFh)
IROP2M .EQU R13 ; High word of signed factor (0)
IRACL .EQU R14 ; Result word low
IRACM .EQU R15 ; Result word high
;
; Signed multiply subroutine: IROP1 x IROP2L –> IRACM|IRACL
;
EXAMPLE: (8-bit arithmetic). The ADC is measured at five points of the ADC
range A (n = 0). The measured errors—device 1 is used—are shown below. The
correction coefficients for the range A are calculated with the linear regression
method. The correction coefficients for the other three ranges may be calculated
the same way. The used numbers are shaded.
ADC Step 50 1024 2048 3072 4096
Subdivision 1.56 32 64 96 128
Error [Steps] –6 –6 –8 –12 –13
The correction coefficients for the range A (n=0), are calculated with the formulas
shown in section 1.2.2.
a1 + ) 0.06326 Negated result of linear coefficient
a0 + ) 4.9312 Negated result of constant coefficient
Correction:
ƪǒ4096
Ni * 0 Ǔ 128 a1 ) a0 ƫ + ǒ 32
Ni 0.06326 ) 4.9312 Ǔ
The correction for the ADC step 2000—located in range A—is calculated:
Ni 0.06326 ) 4.93 + 2000 0.06326 ) 4.93 + ) 8.88
32 32
Corrected ADC sample: Nicorr + Ni ) 8.9
Format: Valid for the ADC step 2000
7 0
a1: ±0.9 +0.06326/2–9 = +32.4 ≈ 20h 0 0 0 0 1 0 0 0 0 0
20 2 -9
7 0
a0: ±5.2 +4.93/2–2 = +19.7 ≈ 14h 0 0 0 1 0 1 0 0
20 2 -2
2–134 SLAA048
Introduction
EXAMPLE: (16-bit arithmetic). The ADC is measured at five points of the ADC
range C. The measured errors—device 1 is used—are shown in the table below.
The correction coefficients for the range C are calculated with the linear
regression method. The correction coefficients for the other three ranges may be
calculated the same way. The used numbers are shaded.
ADC Step 8192 9216 10240 11254 12288
Error [Steps] –9.6 –8.6 –5.2 –1 +0.1
The correction coefficients for the range C are calculated with the formulas shown
in section 1.2.2. The full 14-bit ADC result is used for the calculations due to the
available 16 bits of resolution.
a1 + –0.0026381701 Negated result of linear coefficient
a0 + ) 31.8695 Negated result of constant coefficient
Correction: Ni a1 ) a0 + Ni (–0.00263817) ) 31.8695
The correction for the ADC step 12000—located in range C—is calculated:
Ni (–0.00263817) ) 31.8695 + 12000 (–0.00263817) ) 31.8695 + ) 0.204
Corrected ADC sample: Nicorr + Ni ) 0.2 Valid for the ADC step 12000
Format:
a1: ±0.22 –0.0026381701/2–22 = –11065.3 ≈ D4C7h
15 8 7 0
1 1 1 1 1 1 1 1 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1
20 2 -8 2 -22
Nicorr + Ni ) ƪǒ Ni p
2 14
* n1 Ǔ 128 a1 ) a0 ƫ
Where:
Nicorr = Corrected ADC sample [Steps]
Ni = Measured ADC sample (noncorrected) [Steps]
p = Number of sections for the full ADC range. p is a power of 2.
n1 = Value of the MSBS of Ni. n1 ranges from 0 to (p–1)
a1 = Slope of the correction
a0 = Offset of the correction
k = Number of samples for each linear equation (section)
-5
-10
-15
ADC Steps
Figure 11. Principle of the Linear Regression Method (two linear equations per range)
The statistical results for 16 points per range—eight samples for each one of the
eight linear equations (k = 8, p = 8)—are:
Full range Ranges A and B only
Mean Value: –0.03 Steps +0.09 Steps
Range: 4.84 Steps 4.80 Steps
Standard Deviation: 0.78 Steps 0.79 Steps
Variance: 0.61 Steps 0.63 Steps
The result is shown in Figure 12. Note the error range of this figure: only ±3 ADC
steps.
Device 1 Corrected With Eight Linear Equations (Linear Regression Used)
2.5
2
1.5
1
ADC Error [Steps]
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
ADC Steps [0 to 16383]
Figure 12. Error Correction With Linear Regression (two linear equations per range)
2–136 SLAA048
Introduction
EXAMPLE: The ADC ranges are split into two sections each. The measured
errors of five points located in the upper section of range B—device 1 is
used—are shown below (k = 4, p = 8). The correction coefficients for this section
are calculated with the linear regression method. The correction coefficients for
the other seven sections may be calculated the same way.
ADC Step 6144 6656 7168 7680 8192
Subdivision 0 32 64 96 128
Error [Steps] –14 –13.6 –12 –10.5 –9.6
The correction coefficients a1 and a0 for the upper section of range B (n1 = 3) are
calculated with the formulas shown in section 1.2.2. The subdivision of the ADC
step (0 to 127) is used (8-bit arithmetic).
a1 + ) 0.03719 Negated value
a0 + ) 14.32 Negated value
Correction:
ƪǒ Ni p
2 14
* n1 Ǔ 128 a0 ) a1 + ƫ ƪǒ Ni 8 * 3
2 14
Ǔ 128 (* 0.03719) ) 14.32 ƫ
The correction for the ADC step 7000—located in the upper section of range
B—is calculated:
ǒ 70002 14
8*3 Ǔ 128 (* 0.03719) ) 14.32 + ) 12.33
Corrected ADC sample: Nicorr + Ni ) 12.3 Valid for ADC step 7000 range B
Format: 7 0
20 2 -10
7 0
a0: ±5.2 +14.32/2–2 = 57.3 ≈ 39h 0 0 1 1 1 0 0 1
20 2 -2
2 Additional Information
The application report Nonlinear Improvement of the MSP430 14-Bit ADC
Characteristic[4] shows nonlinear methods such as quadratic and cubic
corrections for the improvement of the 14-bit analog-to-digital converter of the
MSP430. Also included are the integer multiplication subroutines for the fast
correction software and considerations to the obtainable accuracy with the 8-bit
software. Finally all explained correction methods presented are compared by
ROM and RAM needs, accuracy improvement, and required CPU cycles.
2–138 SLAA048
References
3 References
1. Architecture and Function of the MSP430 14-Bit ADC Application Report,
1999, Literature #SLAA045
2. Application Basics for the MSP430 14-Bit ADC Application Report, 1999,
Literature #SLAA046
3. Additive Improvement of the MSP430 14-Bit ADC Characteristic Application
Report, 1999, Literature #SLAA047
4. Nonlinear Improvement of the MSP430 14-Bit ADC Characteristic
Application Report, 1999, Literature #SLAA050
5. MSP430 Application Report, 1998, Literature #SLAAE10C
6. Data Sheet MSP430C325, MSP430P323, 1997, Literature #SLASE06B
7. MSP430 Family Architecture Guide and Module Library, 1996, Literature
#SLAUE10B
2–143
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their
products or to discontinue any product or service without notice, and advise customers to
obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current and complete. All products are sold subject to the terms
and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent
right, copyright, mask work right, or other intellectual property right of TI covering or relating
to any combination, machine, or process in which such semiconductor products or services
might be or are used. TI’s publication of information regarding any third party’s products or
services does not constitute TI’s approval, warranty or endorsement thereof.
2–144
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–147
1.1 Correction With Quadratic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–148
1.2 Coefficients Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–151
1.3 Correction With Cubic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–154
1.4 Coefficients Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–156
2 Considerations to the Integer Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–161
2.1 Multiplication Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–161
2.2 Maximum Magnitude of the 8-Bit Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–162
2.3 Number Formats of the 8-Bit Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–163
2.4 Calculation of the 8-Bit Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–164
2.5 Accuracy With the 8-Bit Integer Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–166
2.5.1 Accuracy for the Linear Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–166
2.5.2 Accuracy for the Cubic Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–168
3 Comparison of the Used Improvement Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–169
3.1 Comparison Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–169
3.2 Comparison Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–170
4 Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–172
5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–172
6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–173
List of Figures
1 The Hardware of the 14-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–148
2 Principle of the Error Correction With Four Quadratic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–150
3 Error Correction With Four Quadratic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–151
4 Principle of the Error Correction With Four Cubic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–155
5 Error Correction With Four Cubic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–156
6 Worst Case ADC Error With Different Improvement Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–163
7 Number Format With Integers for 8-Bit Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–164
8 Number Format With Fraction Part Only for 8-Bit Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–164
9 Comparison of Corrected ADC Characteristics. 8-Bit Results After Rounding . . . . . . . . . . . . . . . . . . . . . . . . 2–167
10 Comparison of Corrected ADC Characteristics. 8-Bit Results Before Rounding . . . . . . . . . . . . . . . . . . . . . . 2–167
11 Comparison of Corrected ADC Characteristics. 8-Bit Results Before Rounding . . . . . . . . . . . . . . . . . . . . . . 2–168
12 Comparison of the Non-Corrected ADC Characteristic and the Best Improvement . . . . . . . . . . . . . . . . . . . 2–171
List of Tables
1 Worst Case Coefficients for Quadratic Equations (8-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–151
2 8-Bit Coefficients for the Four Quadratic Equations of Device 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–152
3 Worst Case Cubic Coefficients (8-Bit Arithmetic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–156
4 Correction Coefficients for the Cubic Equations of Device 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–157
5 Worst Case Correction Coefficients (8-Bit Arithmetic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–163
6 Comparison Table for the Different Improvement Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–169
7 Comparison Table for the Different Improvement Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–170
8 Selection for the Improvement Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–172
2–146 SLAA050
Nonlinear Improvement of the MSP430 14-Bit ADC Characteristic
Lutz Bierl
ABSTRACT
This application report shows nonlinear methods—with quadratic and cubic equations
—to improve the accuracy of the 14-bit analog-to-digital converter (ADC) of the MSP430
family. The methods used differ in RAM and ROM requirements, calculation speed,
achievable improvement, and complexity. The influence of the restricted calculation
accuracy for 8-bit coefficients is compared to the accuracy of floating-point calculations.
Finally, a comparison of all improvement methods is given. The References section at the
end of the report lists related application reports in the MSP430 14-bit ADC series.
1 Introduction
The application report Architecture and Function of the MSP430 14-Bit ADC[1]
gives a detailed overview of the architecture and function of the 14-bit
analog-to-digital converter (ADC) of the MSP430 family. The principle of the ADC
is explained and software examples are given. Also included are the explanation
of the function of all hardware registers contained in the ADC.
The application report Application Basics for the MSP430 14-Bit ADC[2] shows
several applications of the 14-bit ADC of the MSP430 family. Proven software
examples and basic circuitry are shown and explained.
The application report Additive Improvement of the MSP430 14-Bit ADC
Characteristic[3] explains the external hardware that is needed for the
measurement of the characteristic of the MSP430’s analog-to-digital converter.
This report also demonstrates correction methods that use addition only: no
multiplication is needed. This allows the application of these methods in real-time
systems, where execution time can be critical.
The application report Linear Improvement of the MSP430 14-Bit ADC
Characteristic[4] shows linear improvements using linear equations with border
fit and correction by linear regression methods.
Figure 1 shows the block diagram of the 14-bit analog-to-digital converter of the
MSP430 family.
2–147
Introduction
AVcc
SVcc Switch ACTL.1 (Vref)
Offset
SVcc ACTL.12(Pd) Canc. Pd
AVcc/2
Generator
_
Rex
C 2C 4C 8C 16C +
128 Range
Rext _ D MUX
Isource 0.75 SVcc
+
VH
128
PD C Resistor
Capacitor
Array
AVcc/2 ACTL.6,7 128
B Decoder VL
Generator ACTL.8
1:4 Delay
(CSoff)
128
A
AGND 7 2 5
ACTL.9, 10(Range)
(AVss)
ACTL.11(Auto) Successive Approximation
A0 Register
ACTL.0(SOC)
A1 ADCLK/12
A2 8:1 EOC
Input
A3
A4 /12
A5 Input
A6 MUX ACTL.2.4 (Ax)
A7 /1, /2 ACTL 14
ACTL.5 (None)
/3, /4 ACTL 13
MCLK
SAR.13 SAR.0 ACTL.14 ACTL.0
A7 A0 AEN.0–7
8
Input Buffer AIN Input Buffer Enable AEN Output Buffer ADAT Control Register ACTL
2–148 SLAA050
Introduction
The formula used for each range with separate factors ax for 8-bit integer
calculations is:
Nicorr + Ni ) ǒǒǒ Ǔ
Ni * n × 256
4096
Ǔ
2
× a2 ) ǒ4096
Ni * n Ǔ × 256 × a1 ) a0 Ǔ
Where: Nicorr Corrected ADC sample [Steps]
Ni Measured ADC sample (non-corrected) [Steps]
N Subdivision representing the ADC sample (0...255)
n Range number (0...3 for ranges A...D)
a2 Quadratic coefficient of the correction [Steps–1]
a1 Linear coefficient of the correction
a0 Offset of the correction [Steps]
i Nominal ADC step of the ADC input (DAC output) [Steps]
The formula above uses the subdivisions (0 to 255) inside of an ADC range (0
to 4095 steps) instead of the full 14-bit position (0 to 16383 steps) of an ADC point.
This is to maintain the accuracy of the calculation with limited coefficient length
(here for 8-bit coefficients). The above formula is used with the 8-bit calculation.
Nicorr + Ni ) ǒ Ni 2 × a2 ) Ni × a1 ) a0 Ǔ
The software example given for the cubic correction in section 1.3—which is
written in floating point notation—may be adapted easily to quadratic correction:
the unused cubic part is simply left out and the address calculation for the
coefficients is modified to three coefficients (a2..a0) instead of the four (a3..a0).
Nicorr + Ni ) ǒǒǒ4096
Ni * n Ǔ × 256 × a2 ) a1Ǔ × ǒ Ni * n Ǔ × 256 × a0Ǔ
4096
The 16-bit formula and the FPP formula now require only two multiplications
instead of three.
Nicorr Ni (( Ni × a2 a1 )Ni a0 )
Figure 2 shows the principle of the correction with four quadratic equations: the
used correction parabolas are drawn together with the non-corrected ADC
characteristic. As with all principle figures in this report, the black straight line
indicates the correction value, the scribbled black line indicates the
non-corrected ADC characteristic and the white line shows the corrected ADC
characteristic. The small circles indicate the measured ADC points.
Device 1
5
ADC Error [Steps]
–5
–10
–15
ADC Steps
The statistical results for the quadratic correction are (single measurement for
each one of the nine ADC steps used for the calculation of the correction
coefficients):
Full range Ranges A and B only
Mean Value: –0.08 Steps 0.24 Steps
Range: 6.78 Steps 5.86 Steps
Standard Deviation: 1.05 Steps 1.10 Steps
Variance: 1.11 Steps 1.21 Steps
If each of the nine ADC steps used for the calculation of the correction coefficients
is measured in a slightly modified way, then the statistical results change also.
Now the mean value of seven measured ADC steps is taken for the calculation.
The seven ADC steps are:
Nn–12, Nn–8, Nn–4, Nn, Nn+4, Nn+8 and Nn+12, where Nn is the ADC step used
in the calculation formula. Now the statistical results are:
Full range Ranges A and B only
Mean Value: –0.07 Steps 0.11 Steps
Range: 6.47 Steps 6.02 Steps
Standard Deviation: 1.00 Steps 1.12 Steps
Variance: 1.00 Steps 1.24 Steps
Figure 3 shows the resulting errors of both methods in a graph (differences
cannot be seen):
2–150 SLAA050
Introduction
2
ADC Error [Steps]
–1
–2
–3
The integer calculation operates with signed 8-bit coefficients and ax ADC result
rounded to 8 bits. The floating point calculation uses the full ADC result (0 to
16383) and a 32-bit format for the calculations.
The three equations to calculate the correction coefficients a2, a1 and a0 out of
the three known errors e3, e2 and e1 at the ADC steps N3, N2 and N1 are:
e 2
e 1 × N 3
2
N2
2
e 3
e 2 × N 2
2
N1
2
a1
N 2 N × N N 3 N × N N
2 2 2 2
1 3 N2 2 2 1
e 2 e 1 a 1 × N 2 N 1
a2 2 2
a0 e1 a2 × N 1
2
a1 × N1
N2 N1
NOTE:
N3, N2, and N1 can be expressed in ADC steps (0...16383), range steps
(0...4095) or subdivisions of the range (0...255) for 8-bit calculations.
In the following, N represents subdivisions.
As shown with the linear improvements, using more than one quadratic parabola
per ADC range is also possible. It is only necessary to adapt the 256 subdivisions
to the sections of the ranges, to calculate the new coefficients a2 to a0, and to
modify the addressing of the coefficients.
The software part after each ADC measurement is as follows. The numbers at
the right border—below int.frct—indicate the maximum integer bits and the actual
number of fraction bits for the result (integer.fraction). The Horner scheme is used
for the calculation.
; Quadratic error correction with a single equation per range.
; 8–bit arithmetic. Cycles needed:
; Subdivision N = 0: 85 cycles
; Subdivision N > 7Fh: 206 cycles
;
; int.frct
MOV &ADAT,R5 ; ADC result Ni to R5 14.0
MOV R5,R6 ; Address info for correction 14.0
RRA R5 ; Calculate subdivision 0...FFh 13.0
RRA R5 ; Prepare N = (Ni/4096–n)x256 12.0
RRA R5 ; 8 bit ADC info to low byte 11.0
RRA R5 ; 10.0
ADC.B R5 ; Round subdivision 0...FFh 8.0
JNC L$1 ; If result overflows to 100h:
DEC.B R5 ; Limit subdivision to FFh 8.0
;
L$1 SWPB R6 ; Calculate coefficient address 6.0
RRA.B R6 ; 0...1Fh 5.0
RRA.B R6 ; 0...0Fh 4.0
RRA.B R6 ; 0...07h 3.0
BIC #1h,R6 ; 0...06h 3.0
2–152 SLAA050
Introduction
Correction:
(( N × a2 ) a1 ) × N ) a0) + (( N × (* 0.000183106) ) 0.0328125 ) × N ) 13.2)
The correction for the ADC step 7000—located in range B—is calculated:
ǒǒǒ 7000
4096
* 1Ǔ × 256 × (* 0.000183106) ) 0.0328125Ǔ × ǒ 7000 * 1Ǔ × 256 ) 13.2Ǔ + ) 13.3
4096
Corrected ADC sample: Nicorr + Ni ) 13.3. Valid for ADC step 7000
Format: a2: ±0.17 –0.000183106/2–17 = –24 = E8h
7 0
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0
20 2–17
7 0
a1: ±0.10 +0.0328125/2–10 = +33.6 ≈ 22h 0 0 0 0 0 1 0 0 0 1 0
20 2–10
7 0
20 2–2
Where: N + ǒ4096
Ni –n Ǔ × 256, the ADC result of a range adapted to the
subdivisions 0...255.
Where: Nicorr Corrected ADC sample [Steps]
Ni Measured ADC sample (non-corrected) [Steps]
N Subdivision representing the ADC sample (0...255)
n Range number (0...3 for ranges A...D)
a3 Cubic coefficient of the correction [Steps–2]
a2 Quadratic coefficient of the correction [Steps–1]
a1 Linear coefficient of the correction
a0 Offset of the correction [Steps]
i Nominal ADC step of the ADC input (DAC output) [Steps]
2–154 SLAA050
Introduction
The integer formula above uses the subdivision (0..255) inside of an ADC range
(0 to 4095) instead of the full 14-bit position (0 to 16383) of an ADC point. This
is to increase the accuracy of the calculation also with limited coefficient length,
e.g., for 8-bit coefficients.
If floating point calculation is used, the high resolution of the 24-bit mantissa
makes the range correction unnecessary. The equation simplifies to:
Nicorr Ni Ni 3 × a3 Ni 2 × a2 Ni × a1 a0
To save multiplications the Horner scheme is used again. This reduces the
number of multiplications from six to only three. The formula using the 8-bit
arithmetic now becomes (N represents the actual subdivision 0...255. See
above):
Nicorr Ni ((( N × a3 ) a2 ) × N a1 ) × N a0
The formula for 16-bit and floating point calculations now becomes:
Figure 4 shows the principle of the correction with four cubic equations: the
correction parabolas actually used are printed together with the corrected and
non-corrected ADC characteristic. The circles indicate the measured ADC
points.
Device 1
4
2
0
ADC Error [Steps]
–2
–4
–6
–8
–10
–12
–14
–16
ADC Steps
1
ADC Error [Steps]
–1
–2
–3
The integer calculation operates with signed 8-bit coefficients and an ADC result
rounded to 8 bits (256 subdivisions).
2–156 SLAA050
Introduction
The floating point calculation uses the full ADC result (0 to 16383) and a 32-bit
format for the calculations. To give an example, for device 1 the calculated sixteen
correction factors a3 to a0 are (12-bit ADC info is used):
Table 4. Correction Coefficients for the Cubic Equations of Device 1
COEFFICIENT RANGE A RANGE B RANGE C RANGE D
a3 – 1.18E–10 – 6.483598E–10 3.286326E–11 5.17398E–10
a2 1.02E–06 3.943417E–06 – 3.497543E–07 – 2.655711E–06
a1 – 4.37E–04 – 6.153471E–03 – 1.486924E–03 3.83333E–03
a0 6.00E+00 1.320000E+01 9.600000E+00 – 1.000000E–01
The algorithm to calculate the four correction coefficients a3 to a0 out of the four
measured errors e4, e3, e2 and e1 at the ADC steps N4, N3, N2 and N1 is very
complex. It is recommended to use a mathematical support software running on
a host computer for this task. A simple calculation software routine is available
from Texas Instruments on request.
For the cubic correction an example using the MSP430 Floating Point Package
FPP4 is given below. This software example can be adapted easily to linear and
quadratic correction:
• The parts not used are deleted (e.g., the parts handling the coefficients a3 and
a2 if a linear correction is needed)
• The calculation of the start address of the correction coefficients (address of
a3 in the example) out of the ADC result is modified slightly.
; Cubic error correction with a single equation per range.
; Floating point arithmetic. Cycles needed: 800 to 2400
;
DOUBLE .EQU 0 ; Use .FLOAT format (32 bit)
;
MOV #xxx,&ACTL ; Define ADC measurement
CALL #MEASR ; Measure. Result Ni to ADAT
CALL #FLT_SAV ; Save registers R5 to R12
SUB #4,SP ; Allocate stack for FP result
MOV #ADAT,RPARG ; Load address of ADC buffer
CALL #CNV_BIN16U ; Convert ADC result Ni to FP
SUB #4,SP ; New working space for calc.
;
MOV &ADAT,R15 ; Calc. address of coeff. a3
SWPB R15
AND #0030h,R15 ; Range x 16: rel. address a3
ADD #a3,R15 ; Start address of coeff. block
MOV R15,RPARG ; Points to actual a3
CALL #FLT_MUL ; a3 x Ni
ADD #a2–a3,R15 ; Address of a2
MOV R15,RPARG ; Points to actual a2
CALL #FLT_ADD ; a3 x Ni + a2
ADD #4,RPARG ; To Ni
CALL #FLT_MUL ; (a3 x Ni+a2)Ni
ADD #a2–a3,R15 ; Address of a1
MOV R15,RPARG ; Points to actual a1
CALL #FLT_ADD ; ((a3 x Ni)+a2)Ni + a1
ADD #4,RPARG ; To Ni
CALL #FLT_MUL ; (((a3 x Ni) + a2)Ni + a1)Ni
ADD #a2–a3,R15 ; To actual a0
MOV R15,RPARG
CALL #FLT_ADD ; (((a3 x Ni)+a2)Ni+a1)Ni+a0
ADD #4,RPARG ; To Ni
CALL #FLT_ADD ; Nicorr = Ni + correction
;
2–158 SLAA050
Introduction
a2 + –0.000512371
a1 + ) 0.0518045
a0 + –0.10
The correction for the ADC step 15000—located in range D—is calculated:
N+ ǒ 15000
4096
* 3Ǔ × 256 + 169.5 [ 170
20 2–24
20 2–15
7 0
20 2–9
7 0
a0: ±5.2 –0.1/2–2 = –0.4 ≈ 00h 0 0 0 0 0 0 0 0
20 2–2
2–160 SLAA050
Considerations to the Integer Calculations
1The idea for these subroutines initially came from Leslie Mable of TIL.
2–162 SLAA050
Considerations to the Integer Calculations
range border to +2.5 then back to +7.5 and back to 0 steps at the upper range
border.
Examples for Worst Case ADC Errors
25
Range A Range B Range C Range D
20
15
ADC Error [Steps]
10
–5
+ –20 Steps
–10 + –10
–15
–20
+–4.3
7 0
7 0
4.375 0 0 1 0 0 0 1 1
23 20 2–3
7 0
–4.375 1 1 0 1 1 1 0 1
23 20 2–3
Integer Bit 7 0
20 2–15
7 0
4x2–15 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
20 2–9 2–15
7 0
–4x2–15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
20 2–9 2–15
Figure 8. Number Format With Fraction Part Only for 8-Bit Calculations
N 4096
Ni
n × 128 ranging from 0 to 128 for linear correction
2–164 SLAA050
Considerations to the Integer Calculations
N+ ǒ4096
Ni * n Ǔ × 256 ranging from 0 to 256 for quadratic and cubic
correction
With two, three, or four subdivisions N—dependent on the used correction
method—the coefficients ax are calculated. See the appropriate sections.
1. To start, it is necessary to find the minimum valence—a power of 2—of bit 6
(MSB) of the 8-bit number that is sufficient for the worst case value of the
coefficient ax. The formula for this calculation is:
VMSB w log2|ax |–1
Where: VMSB Valence for the MSB (bit 6) of the 8-bit number
VLSB Valence for the LSB (bit 0) of the 8-bit number
ax Decimal correction coefficient (a3 to a0)
The above formula ensures that the worst case value of the coefficient ax fits into
an 8-bit twos complement number.
2. The valence VLSB of the LSB is for 8-bit arithmetic
VLSB + VMSB *6
With this valence VLSB the 8-bit coefficient ax8bit is calculated:
ax8bit + ax
V
2 LSB
3. The result ax8bit—which is also named ax in the following equations—is
converted into a signed hexadecimal number using the twos complement
format:
• A positive coefficient is simply converted.
• A negative coefficient is converted and negated afterwards (complemented
and incremented).
EXAMPLE: The worst case value for the cubic correction coefficient a3 is
±6.357828E–6 (see Table 5). To find the minimum valence of the MSB of the
number format the equation above is used:
VMSB w log2|ax | * 1 + log2 6.357828E * 6 * 1 + * 17.263 * 1 + * 18.263
7 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1
20 2–24
The bits 20 to 2–17 for the above example always have the same value: they
contain the extended sign: the same value as the sign bit in bit 7 of the 8–bit value
(2s complement arithmetic):
• Zero for a positive coefficient
• One for a negative coefficient
Information is contained only in the bits 7 to 0 (2–18 to 2–24 for the above example).
This is possible due to the known maximum value of these coefficients.
2–166 SLAA050
Considerations to the Integer Calculations
2
ADC Error [Steps]
–1
–2
–3
–4
–5
1
ADC Error [Steps]
–1
–2
–3
–4
–5
ADC Steps [0 to 16383]
Figure 10. Comparison of Corrected ADC Characteristics. 8-Bit Results Before Rounding
Nearly no difference now exists between the floating point and the 8-bit results.
2
ADC Error [Steps]
–2
–4
–6
–8
Figure 11. Comparison of Corrected ADC Characteristics. 8-Bit Results Before Rounding
The loss of accuracy is not critical (±1 LSB), but higher than with the linear
improvement method. The statistical values are nearly identical to the floating
point results.
2–168 SLAA050
Comparison of the Used Improvement Methods
Table 7 gives the memory (RAM, ROM, EEPROM) requirements and the
necessary number of CPU cycles for all improvement methods. The meaning of
the four columns is:
• RAM/EEPROM: The number of bytes in the RAM or an external EEPROM
that are needed for the continuous storage of the correction coefficients if 8-bit
arithmetic is used (full range). It indicates words, if 16-bit arithmetic is used
for the calculations. If the correction coefficients are stored in an external
memory (e.g., EEPROM), then only a part of this number (the coefficients
actually used) need RAM space. If the current source is used, then only one
half of the given number is needed (for the ranges A and B only).
• ROM: The number of ROM bytes needed for the correction algorithm. The
multiplication subroutine is not included in this number.
• Cycles: The number of CPU cycles needed for the calculation of the
correction.
• Calibration Samples: The number of ADC samples that are needed for the
used improvement method. The number of actual measurements for each
sample is not included in this number. See Measurement Methods for the
ADC Reference Samples in the application report Additive Improvement of
the MSP430 14-Bit ADC Characteristic[3] for examples.
Table 7. Comparison Table for the Different Improvement Methods
RAM
ROM CALIBRATION
CORRECTION METHOD EEPROM CYCLES
BYTES SAMPLES
BYTES
Additive Corrections:
Mean value of full range 2 10 7 16...64
Mean value of 4 ranges 4 24 16 16...64
Center of ranges 4 24 16 4
Multiple sections (8 sections) 8 22 13 9
(16 sections) 16 20 12 17
(32 sections) 32 18 11 33
(64 sections) 64 18 11 65
Linear Equations With Border Fit:
Single linear equation per range 8 60 51...100 5
Two linear equations per range 16 64 48...97 9
Four linear equations per range 32 56 49...101 17
Linear Equations With Linear Regression:
Single linear equation per range
8-Bit calculation 8 60 51...100 16...64
16-Bit calculation 16 44 47...178 16...64
Multiple linear equations per range (2) 16 54 48...97 32...128
Correction With Quadratic Equations 12 84 85...206 9
Correction With Cubic Equations:
8-Bit calculation 16 102 108...283 13
Floating point calculation 64 88 800...2400 13
2–170 SLAA050
Comparison of the Used Improvement Methods
4
2
0
ADC Error [Steps]
–2
–4
–6
–8
–10
–12
–14
–16
Figure 12. Comparison of the Non-Corrected ADC Characteristic and the Best Improvement
As can be seen, the non-corrected range (17 steps) reduces to a range of less
than 5 steps. The statistical results are (full range):
• Best correction: Additive correction of 64 sections for the full ADC range
• Second best correction: Linear regression with two equations per ADC
range
Non-Corrected Best 2nd Best
Device 1 Correction Corrected
Mean Value: –6.95 Steps –0.08 Steps –0.03 Steps
Range: 17 Steps 4.60 Steps 4.84 Steps
Standard Deviation: 4.74 Steps 0.64 Steps 0.78 Steps
Variance: 22.51 Steps 0.41 Steps 0.61 Steps
4 Selection Guide
To quickly find the best improvement method for the 14-bit ADC, Table 8 gives a
hint to which method is best for a given application. The selection criteria are:
• Accuracy: The range is used.
• RAM critical: The RAM needed for the coefficients is ≤ 8 bytes.
• Time critical: The calculation time takes ≤ 60 cycles on an average.
This table is taken from the results of device 1. But the table may be usable for
other MSP430 devices too. With a more regular ADC characteristic than
device 1, the more complex methods will show better results than the simpler
ones.
Table 8. Selection for the Improvement Methods
NEEDED RAM CRITICAL RAM AND TIME
RAM CRITICAL TIME CRITICAL
ACCURACY TIME CRITICAL NON-CRITICAL
High Not possible Single linear Multiple sections Two linear
(± 2.5 Steps) equation/range (64 sections) equations/range
(linear regression) (linear regression)
Medium Not possible Single linear Multiple sections (16 and All others not named
(± 3.5 Steps) equation/range (border fit) 32 sections)
Low Mean
(± 7 Steps) Value/Range
Center of Ranges
Multiple Sections
(8 Sections)
Very Low Mean value of
(± 10 Steps) full range
5 Summary
The five application reports in this series show many simple-to-realize
improvements for the accuracy of the 14-bit analog-to-digital converter of the
MSP430. From a non-corrected error range of 17 steps, it was possible to reduce
the range to less than ±2.5 steps. Even better, the standard deviation improved
from 4.74 steps to 0.65 steps. With a larger effort, the results can be even
better—for example if sophisticated statistical methods are applied. Solutions are
possible for real-time systems also, e.g., the additive method with its simple and
fast algorithm. It was also shown, that relatively simple correction methods can
deliver the best results.
2–172 SLAA050
References
6 References
1. Architecture and Function of the MSP430 14-Bit ADC Application Report,
1999, Literature #SLAA045
2. Application Basics for the MSP430 14-Bit ADC Application Report, 1999,
Literature #SLAA046
3. Additive Improvement of the MSP430 14-Bit ADC Characteristic Application
Report, 1999, Literature #SLAA047
4. Linear Improvement of the MSP430 14-Bit ADC Characteristic Application
Report, 1999, Literature #SLAA048
5. MSP430 Metering Application Report, 1997, Literature #SLAAE10B
6. Data Sheet MSP430C325, MSP430P323, 1998, Literature #SLASE06A
7. MSP430 Family Architecture Guide and Module Library, 1996, Literature
#SLAUE10B
8. MSP430 Application Report, 1998, Literature #SLAAE10C
Lutz Bierl
2–175
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their
products or to discontinue any product or service without notice, and advise customers to
obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current and complete. All products are sold subject to the terms
and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent
right, copyright, mask work right, or other intellectual property right of TI covering or relating
to any combination, machine, or process in which such semiconductor products or services
might be or are used. TI’s publication of information regarding any third party’s products or
services does not constitute TI’s approval, warranty or endorsement thereof.
2–176
Contents
1 The Universal Timer/Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–179
1.1 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–185
1.2 Connection of Long Sensor Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–192
1.3 Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–192
1.4 Voltage Measurement With the Universal Timer Port/Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–193
1.4.1 Measurement Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–193
1.4.2 Resolution of the Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–197
1.4.3 Measurement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–198
1.4.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–198
1.5 Temperature Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–203
1.6 Measurement of the Position of a Potentiometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–206
1.7 Measurement of Sensors With Low Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–207
1.8 Measurement of Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–208
2 External Analog-To-Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–209
2.1 External Analog-To-Digital Converter ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–209
2.2 R/2R Analog-To-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–210
List of Figures
1 Block Diagram of the Universal Timer/Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–180
2 Minimum Sensor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–180
3 Timing for the Universal Timer/Port Module ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–181
4 Schematic of Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–183
5 Noise Influence During Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–186
6 Hardware Schematic for Interrupt Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–186
7 Measurement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–187
8 Connection of Long Sensor Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–192
9 Grounding for the Universal Timer/Port ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–193
10 Voltage Measurement With the Universal Timer/Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–194
11 Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–195
12 Voltage Measurement of a Voltage Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–199
13 Circuit for the Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–201
14 Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–202
15 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–203
16 Measurement of a Potentiometer’s Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–206
17 Hardware Schematic for Low-Resistive Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–207
18 Solution With a Low-Resistive Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–208
19 Measurement of a Capacitor Cx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–208
20 Timing for the Capacity Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–209
21 Analog-to-Digital Conversion With External ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–210
22 R/2R Method for Analog-to-Digital Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–211
List of Tables
1 ADC Conversion With the Timer/Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–182
2–178
Using the MSP430 Universal Timer/Port Module as an
Analog-to-Digital Converter
Lutz Bierl
ABSTRACT
This application report gives a detailed overview of several applications for theMSP430
family Universal Timer/Port Module when used as an analog-to-digital converter (ADC).
Proven software examples and basic circuitry are shown and explained.
2–179
The Universal Timer/Port Module
ENB ENA
CIN
CMP
Enable
+ Set_EN1FG
– Control
CMPI Vcc/4 TPIN.5
CPON
TPSSEL0 EN1 Control Register
8bit Counter TPCTL
TPSSEL1 TPSSEL0
TP.0 CLK1 TPCNT1
RC1 r/w
TPD.0 CMP 0
TPE.0 ACLK 1
TPSSEL ENA EN1 RC1FG
TP.1 2 B16
TPD.1 MCLK Set_RC1FG 1 0 ENB RC2FG EN1FG
3
TPE.1
Data Register
TP.2 TPD
TPSSEL3 TPSSEL2
TPD.2
TPE.2 0
TP.3 TPIN.5 EN2
B16 TPD.5 TPD.0
TPD.3 ACLK 1 1 8bit Counter CPON
TPE.3 MCLK 2 CLK2 TPCNT2
TP.4 0 RC2 r/w
3 Data Enable Register
TPD.4 Set_RC2FG TPE
TPE.4
TP.5 TPIN.5
TPD.5 TPSSEL
TPE.5 TPE.0
3 2
TPE.5
32kHz
TP.0
TP.1 Vcc +5V
Rref
10k Rsens
MSP430
CIN,CMPI
Cm
Vss
0V
2–180
The Universal Timer/Port Module
tref
–
Cm × Rref tref
Vth = Vcc × e ≈ Rref = –
Vth
Cm × ln
Vcc
Vcm
Vcc
Vth
0
tc tref tc tsens
Time
Vth
Cm × ln
Rsens –tsens Vcc ≈ tsens
= × Rsens = Rref ×
Rref Vth – tref tref
Cm × ln
Vcc
With two known reference resistors (Rref1 and Rref2) it is possible to compute
the slope and offset and get the exact values of the unknown resistors. The result
of the solved equations gives:
tsens – tref2
Rsens = × (Rref2 – Rref1) + Rref2
tref2 – tref1
Where:
tsens Discharge time for sensor Rsens [s]
tref1 Discharge time for Rref1 [s]
tref2 Discharge time for Rref2 [s]
Rref1 Resistance of reference resistor Rref1 [Ω]
Rref2 Resistance of reference resistor Rref2 [Ω]
As shown only known or measurable values are needed for the computation of
Rsens from tsens. The slope and offset of the measurement disappear
completely.
To get a resolution of n bits, the capacitor Cm must have a minimum capacity:
–2n
Cm >
Vthmax
Rxmin × f × ln
Vcc
2n
tconv ≈
f
Where:
f Measurement frequency (ACLK or MCLK) [Hz]
Rxmin Lowest resistance of sensor or reference resistor [Ω]
Vthmax Maximum value for threshold voltage Vth [V]
tconv Conversion time for an analog-to-digital conversion [s]
Table 1 gives an overview of different resolutions, capacitors, and conversion
times. The sensor resistance is 1 kΩ, f = 1.048 MHz:
Table 1. ADC Conversion With the Timer/Port Module
Resolution Bits Capacitor Conversion Time Complete Conversion Time tcompl
Cm tconv
8 232 nF 256 µs 2.8 ms
10 1 µF 1 ms 12.0 ms
12 3.7 µF 4.1 ms 45.2 ms
14 15 µF 16.4 ms 182.8 ms
16 60 µF 65 ms 730 ms
2–182
The Universal Timer/Port Module
EXAMPLE: Use of the Universal Timer Port as an ADC without an interrupt. The
measured time values of the two sensors (Rsens1 and Rsens2) and the
reference resistors (Rref1 and Rref2) are stored in RAM starting at label MSTACK
(Rref1 location). If an error occurs, 0FFFFh is written to the RAM location.
MSP430
Enable Control TPIN.5 TPD.5 TPE.5 TPD.4 TPE.4 TPD.3 TPE.3 TPD.2 TPE.2 TPD.1 TPE.1 TPD.0 TPE.0
Rref1 Rref2
Rsens1 Rsens2
Cm
0V
2–184
The Universal Timer/Port Module
;
; EN1 = 0: End of Conversion: Store 2 x 8 bit result on MSTACK
; Address next sensor, if no one addressed: End reached
;
MOV.B &TPCNT1,MSTACK(R5) ; STORE RESULT ON STACK
MOV.B &TPCNT2,MSTACK+1(R5) ; HI BYTE
L$301 INCD R5 ; ADDRESS NEXT WORD
RRA.B @SP ; NEXT OUTPUT TPD.x
JNC MEASLOP ; IF C=1: FINISHED
INCD SP ; HOUSEKEEPING: TPDMAX
RET
;
; ERROR HANDLING: ONLY OVERFLOW POSSIBLE (BROKEN SENSOR ?)
; 0FFFFh IS WRITTEN FOR RESULT AND SUBROUTINE CONTINUED
;
MERR MOV #0FFFFh,MSTACK(R5) ; Overflow
JMP L$301
tdcw – tdcc
Ecnv = × 100
tdcc
Where:
tdcw Resulting measurement time caused by CPU noise [s]
tdcc Correct measurement time [s]
Vcm
Vcc
Vth
0
tc tdcw
Time
tdcc
Rref0
TP.0
Rmeas0
TP.1
Rmeas1
TP.2
Rref1 MSP430x3xx
TP.3
Rcharge
TP.4
CIN, CMPI
Cm
Vss Vcc
0V +3V
AGND
2–186
The Universal Timer/Port Module
The measured discharge times (a direct measure for the relative resistance) are
placed in successive RAM words starting at label ADCRESULT.
First these RAM words are set to zero (a value impossible as a measurement
result). If an error occurs, the zero value indicates an erroneous result.
The Basic Timer is programmed to 0.5 s interrupt timing. The measurement
sequence is shown in Figure 7. This sequence can be shortened to one reference
resistor and one sensor as well as enlarged up to four sensors and two reference
resistors. It is only necessary to add or delete charging and measurement states
and the accompanying software parts.
The modulation mode of the FLL is switched off during the measurement to have
the exactly same MCLK during all four measurements. Status 9 switches on the
modulation mode again.
The software shown can be used for the MSP430C31x and MSP430C32x. The
different interrupt enable bits and the different addresses of the interrupt vectors
are used correctly by the definition of the software switch Type. If this switch is
defined as 310, the MSP430C31x is used; otherwise, the MSP430C32x is used.
0.5s
CPUoff = 1
MOD = 1
Status 0 1 2 3 4 5 6 7 8 9/0
;
TPCTL .equ 04Bh ; Timer Port: Control Reg.
TPCNT1 .equ 04Ch ; Counter Reg.Lo
TPCNT2 .equ 04Dh ; Counter Reg.Hi
TPD .equ 04Eh ; Data Reg.
TPE .equ 04Fh ; Enable Reg.
;
.if Type=310 ; MSP430C31x?
TPIE .equ 004h ; ADC: Intrpt Enable Bit
.else
TPIE .equ 008h ; MSP430C32x configuration
.endif
IE2 .equ 001h ; Intrpt Enable Byte
TPSSEL1 .equ 080h ; Selects clock input (TPCTL)
TPSSEL0 .equ 040h ;
ENB .equ 020h ; Selects clock gate (TPCTL)
ENA .equ 010h ;
EN1 .equ 008h ; Gate for TPCNTx (TPCTL)
RC2FG .equ 004h ; Carry of HI counter (TPCTL)
RC1FG .equ 002h ; Carry of LO counter (TPCTL)
EN1FG .equ 001h ; End of Conversion Flag “
B16 .equ 080h ; Use 16–bit counter (TPD)
;
Rref0 .equ 001h ; TP.0: Reference Resistor
Rmeas0 .equ 002h ; TP.1: Sensor0
Rmeas1 .equ 004h ; TP.2: Sensor1
Rref1 .equ 008h ; TP.3: Reference Resistor
Rcharge .equ 010h ; TP.4: Charge Resistor
;
; RAM Definitions
;
ADCRESULT .equ 0200h ; ADC results (4 words)
MEASSTAT .equ ADCRESULT+8 ; Measurement Status Byte
;
;=========================================================
;
.sect “INIT”,0F000h ; Initialization Section
;
INIT MOV #0300h,SP ; Initialize Stack Pointer
MOV.B #DIV+IP2+IP0,&BTCTL ; Basic Timer: 2Hz
2–188
The Universal Timer/Port Module
2–190
The Universal Timer/Port Module
Cm
0V Cin
Rref
Shield TP.1
Rv/2
Rsens1 Rv/2
TP.0
Shield
MSP430C31x
Rsens2
TP.2
3rd Line
Vss Vcc
No shield, twisted wires
0V +5V
1.3 Grounding
The correct grounding is very important if ADCs with high resolution are used.
There are some basic rules that need to be observed.
With the MSP430C31x and the MSP430C33x only the Vss pin exists as a
common reference point.
1. Use of separate analog and digital ground planes wherever possible. No thin
connections from the battery to VSS pin.
2–192
The Universal Timer/Port Module
Rref
TP.0
Rsens1
TP.1
MSP430C31x
Rsens2
Battery Replacement
TP.2
5V Vcc CIN
Vss
Cm Vss Vcc
0V +3V
To metallization
AGND
For the voltage measurement with the MSP430x3xx family, the comparator input
CMPI—with its well defined threshold voltage 0.25 × Vcc—is used and not the
analog input CIN with its Schmitt-Trigger characteristic. The comparator input
CMPI has different names with the different MSP430 family members. This is due
to the fact that it normally uses the same pin as the highest numbered LCD select
line.
The LCD pin is switched from the select function to the comparator function by
a control bit located in the Universal Timer/Port Module (CPON, TPD.6, address
04Eh).
Figure 10 shows a voltage measurement circuit with two different input stages for
the input voltage Vmeas:
• Input voltages with a relatively low impedance are connected directly to the
input Vmeas0. The input impedance of the circuitry is approximately 106 Ohm
(see example Figure 12).
• Input voltages with a very high impedance are connected to the non-inverting
input of the operational amplifier (Vmeas1) with its input impedance of
approximately 109 Ohm.
Only one of the two input stages described in Figure 10 can be used. If more than
one input voltage is to be measured, than one of the circuits shown later is to be
used.
32kHz
Vmeas0
Vcc +5V
TP.3
R1 MSP430
R4
R1’ Vin
–
CMPI
Vmeas1 +
R2
Cm Vss
0V
This means for a supply voltage, Vcc = +5V, voltages between 0,26 × 5 V = 1.3
V and +5 V can be measured.
With the resistor divider consisting of the two resistors R1 and R2, a nominal input
voltage range for Vmeas0 results in
2–194
The Universal Timer/Port Module
R1+ R2 R1+ R2
Vref × < Vmeas0 ≤ Vcc × (2)
R2 R2
The sequence for the measurement of the voltage Vmeas is given in the
following. The numbers used for the sequence correspond to the numbers of the
Conversion States shown in Figure 11. The software is contained in this chapter.
V Cm
5 1 2 3 4 5 1 Conversion States
Vcc
High Vmeas
Vin
Medium Vmeas
Low Vmeas
V ref
0
tchv tmeas tchvcc tvcc
tconv Time
nx
tx =
fMCLK
Where fMCLK represents the CPU frequency MCLK of the MSP430.
The voltage Vmeas can be calculated with the two measured time intervals tmeas
and tvcc using the following formula:
tmeas – tvcc
R1 + R2 τ (3)
Vmeas = Vcc × ×e
R2
Where:
Vmeas Input voltage to be measured [V]
Vcc Supply voltage of the MSP430 (used for reference) [V]
R1,R2 Input resistor divider at input CMPI [Ω]
tmeas Discharge time of the divided Vmeas until Vref is reached [s]
tvcc Discharge time from Vcc to Vref [s]
τ Time constant of the discharge circuit (τ ≈ R4 × Cm) [s]
Vref Threshold voltage of the comparator input CMPI [V]
tconv Time between two complete voltage measurements [s]
To get a constant value for the value τ, an expensive, highly stable capacitor Cm
is necessary. To avoid this capacitor, the value τ of the equation (3) is substituted.
From the equation (4) for the discharge of the capacitor Cm
tvcc
–
Vref = Vcc × e τ (4)
τ is calculated:
tvcc Vcc
τ = where =4 (5)
Vcc Vref
ln
Vref
With equation 6, Vmeas is calculated. Equation 6 is also used with the software
example shown in Section 1.4.4.1.
For the capacitor Cm used for the voltage measurement, it is only important, that
it owns a constant or a very high isolation resistance. The isolation resistor of the
capacitor Cm is connected in parallel with the resistor R2 and changes the
resistor ratio (e.g. due to temperature).
Equation 6 shows the dependence of the voltage measurement to the supply
voltage Vcc (which is the reference), the threshold voltage Vref, the accuracy of
the resistors R1 and R2 and the temperature drift of these values. To get a
measurement accuracy of ±1% for Vmeas without calibration, the following
basics are necessary:
• Stable supply voltage Vcc: Vcc needs to be within ±25 mV for the defined
temperature range. The actual value of Vcc does not matter, if a two-point
calibration is used.
2–196
The Universal Timer/Port Module
• Input CMPI is used for the comparator input: the relatively good defined
threshold voltage Vref (0.25 × Vcc) allows better results than the normal
Schmitt-Trigger input CIN with its large tolerances for the threshold voltages.
• Temperature drift of the resistor divider maximum ±50 ppm/_C
• Sufficient charge-up times for the measurement capacitor Cm:
– For an accuracy of one per cent approximately 5τ are necessary (e5 =
148,41)
– For an accuracy of 0.1% approximately 7τ are necessary (e7 = 1096.63)
If a two-point calibration is used, the calculated values for slope and offset are
stored in an external EEPROM, or if the battery is connected continuously to the
MSP430 system, they are stored in the RAM.
1.4.2 Resolution of the Measurement
The resolution for one counter step nmeas of the voltage measurement is:
This means for the circuit shown in Figure 12 (worst case) (Vmeas = Vmeasmax):
dVmeas 18
≈ = 2.7 × 10 –3
dnmeas 47 × 10 × 47 × 10 – 9 × 3 × 10 6
3
The resolution is for the worst case 2.7 mV for Vaccu = 18 V, Cm = 47 nF, R4 =
47 kΩ, fMCLK = 3 MHz. This equals an analog-to-digital converter with a bit length
a of:
18V
a = ld = 12,703 (8)
2,7mV
(ld = log2) The previous result means, the resolution of this circuit ranges between
a 12-bit and a 13-bit analog-to-digital converter.
For the interesting voltage range at the input CMPI (Vref to Vcc) the non-linear
characteristic of the exponential function can be substituted by a hyperbola. This
method has the advantage of no time-consuming exponential function, only one
division:
A
Vmeas = +C (9)
(tmeas – tvcc) + B
The values for A, B, and C can be determined by the solution of three equations
or with a PC-software program like MATHCAD.
For the calculation of all of the previous formulas, the MSP430 floating point
package FPP4 is ideally suited. The package contains all necessary functions
like the exponential and the logarithm function. An example of its use is given in
Section 2.2.4.4.1.
With the values that determine the time intervals of equation 10, the worst case
value for the complete measurement time tconv can be calculated. The accuracy
is assumed to be 1%. If the accuracy needs to be higher, then the ln100 in
equation 11 must be replaced by the logarithm of the desired accuracy (e.g. by
ln1000 for 0.1%). The time tmeas is assumed to be the maximum one, this means
for Vin = Vcc
Vcc Vcc
tconv = ln100 × Cm × R1||R2 + τ × ln + τ × ln100 + τ × ln (11)
Vref Vref
With the components of Figure 12 (right circuit), the time interval tconv between
two complete voltage measurements is:
(
tconv = 47 × 10 –9 × 4,6 × 3 × 10 6 ||820 × 10 3 + 2 × 47 × 10 3 × 1,386 + 4,6 × 47 × 10 3 )
tconv = 0,155 s
If an accuracy of 0.1% is used (10–3), the time interval tconv gets 233 ms. With
a modification of the values for R1, R2, R4, and Cm, the time interval between
two complete measurements can be greatly changed. The component
calculation of Figure 12 was made for a high-precision voltage measurement.
The values of the components can be changed if the accuracy needs are less
important.
1.4.4 Applications
This section shows how to connect different voltage sources to the Universal
Timer/Port Module. Dependent on the structure of the external voltage source
different hardware configurations are necessary.
2–198
The Universal Timer/Port Module
32kHz 32kHz
2.7M R1 3.0M R1
+5V +5V
Vcc +5V Vcc +5V
TP.2
TP.3 TP.3
MSP430 MSP430
R4 R3 R4
47k 270k 47k
Vin
CMPI Vin CMPI
47n 47n
R2 R2
820k 820k
Vss Cm Vss Cm
0V
2–200
The Universal Timer/Port Module
32kHz
R1 Imeas
TP.0
R2
MSP430
R1 >> R2
CMPI
Cm Rshunt
Vss
0V
Vcc )
tmeas Vref
– × ln ( 1 – )
× (Vcc + (Vref – Vcc) × e tvcc
1
Imeas = (13)
Rshunt
where a and b are constants, given by the values of the supply voltage and the
shunt resistor.
Vin Vin
R2 R2 R2 R2 R2
Vcm Cm Cm
R2
Cm Cm Cm Cm
R2
Cm
0V 0V 0V 0V 0V 0V 0V
V ref
Vin0
0
Zeit
Vin1
tchv0 tm0 tchvcc tvcc tchv1 tm1 tchvcc
The first logarithm function shows the counter steps for the current Imeas, the
second one shows the counter steps for a zero current.
2–202
The Universal Timer/Port Module
32kHz
TP.0
TP.1 Vcc +5V
Rref
10k Rsens
MSP430
CIN
Cm
Vss
0V
2–204
The Universal Timer/Port Module
MOV SP,RPARG
CALL #CNV_BIN16U ; Calculate offset (C)
MOV #FLT5,RPARG
CALL #FLT_MUL ; x 5C
MOV #FLT90,RPRES ; To +90C
CALL #FLT_SUB ; 90C – lower temperature
ADD #FPL+2,RPARG ; To delta within 5C ratios
CALL #FLT_ADD ; minus offset = – 25 deg
MOV #FLT25,RPARG
CALL #FLT_SUB
MOV @SP+,2*FPL+4(SP) ; Sensor temperature to TOS
MOV @SP+,2*FPL+4(SP)
ADD #2*FPL,SP ; Free stack
RET ; Result on TOS
;
FLT5 .float 5.0 ; Delta T for table NTC_TAB
FLT90 .float 90.0 ; Temp. at table start NTC_TAB
FLT25 .float 25.0 ; offset –25 deg
;
; The NTC table contains the ratios for the temperature range
; –40C to +90C. Table values are for the ratio:
; Rref/(Rref||Rsens) = 1.0 + Rref/Rsens. Rref = 10kOhm
; The sensor resistance Rsens is shown after the temperature
; Temp Rsens
.float 1.0+1.0E4/0.9812E3 ; +95C: 0.9812Ω
NTC_TAB .float 1.0+1.0E4/0.1128E4 ; +90C: 1.128kΩ
.float 1.0+1.0E4/0.1301E4 ; +85C: 1.301kΩ
.float 1.0+1.0E4/0.1507E4 ; +80C: 1.507kΩ
.float 1.0+1.0E4/0.1751E4 ; +75C: 1.751kΩ
.float 1.0+1.0E4/0.2043E4 ; +70C: 2.043kΩ
.float 1.0+1.0E4/0.2393E4 ; +65C: 2.393kΩ
.float 1.0+1.0E4/0.2816E4 ; +60C: 2.816kΩ
.float 1.0+1.0E4/0.3327E4 ; +55C: 3.327kΩ
.float 1.0+1.0E4/0.3949E4 ; +50C: 3.949kΩ
.float 1.0+1.0E4/0.4708E4 ; +45C: 4.708kΩ
.float 1.0+1.0E4/0.5641E4 ; +40C: 5.641kΩ
.float 1.0+1.0E4/0.6792E4 ; +35C: 6.792kΩ
.float 1.0+1.0E4/0.8219E4 ; +30C: 8.219kΩ
.float 1.0+1.0E4/1.0000E4 ; +25C: 10.00kΩ
.float 1.0+1.0E4/1.223E4 ; +20C: 12.23kΩ
+5V Vcc
TP.0
TP.1
TP.2
TP.3
Rpoti
TP.4
MSP430
Rv
CIN
Cmeas
Vss
0V
t 4 – t5
Pre l =
t 3 – t5
2–206
The Universal Timer/Port Module
Where:
Prel Relative position of the moving arm (0 to 1)
t3 Result of the time measurement with TP.3 (Rpoti + Rv) [s]
t4 Result of the time measurement with TP.4 (Prel × Rpoti + Rv) [s]
t5 Result of the time measurement with TP.5 (Rv) [s]
Rref0 0V
Rmeas0 TP.0
MSP430x3xx
Rmeas1 TP.1
Rref1 TP.2
Rcharge TP.3
TP.4
CIN
Cm
Vss Vcc
0V +3V
AGND
TP.0...TP.3
Rmeas0
1B2
MSP430x3xx
Rmeas1 1A
1B3
Rref1
1B4
Rcharge
TP.4
CIN/CMPI
Cm
Vss Vcc
0V +3V
AGND
32kHz
R MSP430
CIN,CMPI
Cx
Cs Cref
TP.1
TP.2
Vss
0V
2–208
External Analog-To-Digital Converters
× (Cref + Cs) – Cs
tx
Cx =
tref
Where:
Vth Threshold voltage of the comparator [V]
Vcc Supply voltage of the MSP430 [V]
tref Discharge time with the reference capacitor Cref [s]
tx Discharge time with the unknown capacitor Cx [s]
tc Charge time for the capacitors [s]
Cx Capacitor to be measured [F]
Cref Reference capacitor [F]
Cs Circuit capacity (may be omitted) [F]
The voltage at the capacitors Cx and Cref during the measurement is shown in
Figure 20.
Vc
Vcc
Vcref Vx
Vth
0
tc tref tc tx
Time
32kHz
TP.x, Oyy
TP.5, P0.x
32kHz
XBUF
+5V
Temperature Circuit Vcc
TP.0 TP.x, Oyy
Rntc
TP.1 TP.x, Oyy
0V
TLC0834x
V/f–Converter Vin V0 V0 V3
V1
0V
2–210
External Analog-To-Digital Converters
LSB MSB
P4.7
P4.n
P4.2 4
P4.1
P4.0
2R 2R 2R 2R
.
MSP430C33x 0V
2R R R R
+
P0.7 Comparator
P0.x –
Vcc Vss 2
Ctrl
Vin0
+5V 0V Vin1
Out
Vin2
MUX
Vin3