04 Chapter 7
04 Chapter 7
04 Chapter 7
1
Control Unit Implementation
• Hardwired
Memory Instruction code
Combinational . Control
Sequence Counter
Logic Circuits . signals
• Microprogrammed
CAR: Control Address Register
Memory Instruction code CDR: Control Data Register
2
Microprogrammed Control Unit
• Control signals
– Group of bits used to select paths in multiplexers,
decoders, arithmetic logic units
• Control variables
– Binary variables specify microoperations
• Certain microoperations initiated while others idle
• Control word
– String of 1’s and 0’s represent control variables
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Microprogrammed Control Unit
• Control memory
– Memory contains control words
• Microinstructions
– Control words stored in control memory
– Specify control signals for execution of
microoperations
• Microprogram
– Sequence of microinstructions
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Control Memory
• Read-only memory (ROM)
• Content of word in ROM at given address specifies
microinstruction
• Each computer instruction initiates series of
microinstructions (microprogram) in control memory
• These microinstructions generate micro-operations to
– Fetch instruction from main memory
– Evaluate effective address
– Execute operation specified by instruction
– Return control to fetch phase for next instruction
Control
Address Control word
memory
(microinstruction)
(ROM)
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Microprogrammed Control
Organization
External Next Address Control
input CDR Control
Generator CAR Memory word
(sequencer) (ROM)
• Control memory
– Contains microprograms (set of microinstructions)
– Microinstruction contains
• Bits initiate microoperations
• Bits determine address of next microinstruction
• Control address register (CAR)
– Specifies address of next microinstruction
cpe 252: Computer Organization 6
Microprogrammed Control Organization
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Microprogrammed Control
Organization
• Control data register (CDR) - or pipeline register
– Holds microinstruction read from control memory
– Allows execution of microoperations specified by control
word simultaneously with the generation of next
microinstruction address.
• Control unit can operate without CDR
8
Microprogram Routines
• Routine
– Group of microinstructions stored in control
memory
• Each computer instruction has its own
microprogram routine to generate
microoperations that execute the
instruction
12
Mapping of Instruction
• Example
– Mapping 4-bit operation code to 7-bit address
OP-codes of Instructions
ADD 0000
AND 0001
LDA 0010 Control
memory
Mapping bits 0 xxxx 00
Address
0 0000 00 ADD Routine
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Address Sequencing
• Address sequencing capabilities required
in control unit
– Incrementing CAR
– Unconditional or conditional branch,
depending on status bit conditions
– Mapping from bits of instruction to address for
control memory
– Facility for subroutine call and return
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Address Sequencing
Instruction code
Mapping
logic
Subroutine
Register
Control Address Register (SBR)
(CAR)
Incrementer
select a status
bit
Microoperations
Branch address
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Microprogram Example
MUX
10 0
Computer AR
Configuration Address Memory
10 0 2048 x 16
PC
MUX
15 0
6 0 6 0 DR
SBR CAR
Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD
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Microinstruction Fields
F1 Microoperation Symbol F2 Microoperation Symbol
000 None NOP 000 None NOP
001 AC ← AC + DR ADD 001 AC ← AC - DR SUB
010 AC ← 0 CLRAC 010 AC ← AC ∨ DR OR
011 AC ← AC + 1 INCAC 011 AC ← AC ∧ DR AND
100 AC ← DR DRTAC 100 DR ← M[AR] READ
101 AR ← DR(0-10) DRTAR 101 DR ← AC ACTDR
110 AR ← PC PCTAR 110 DR ← DR + 1 INCDR
111 M[AR] ← DR WRITE 111 DR(0-10) ← PC PCTDR
F3 Microoperation Symbol
000 None NOP
001 AC ← AC ⊕ DR XOR
010 AC ← AC’ COM
011 AC ← shl AC SHL
100 AC ← shr AC SHR
101 PC ← PC + 1 INCPC
110 PC ← AR ARTPC
111 Reserved
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Microinstruction Fields
• The microoperations are distributed on three fields in
one microinstruction, so three microoperations can be
executed simultaneously.
• It is preferred to put the microoperations that have the
same destination in one group, so no more than one
microoperations can be chosen at the same time such
as load DR in group 2, increment PC in group 3.
• Load AC is too many instructions, so they are divided
among the groups.
• Example: What is wrong with the following instruction:
Microinstructions fields are: 100 011 010
F1 F2 F3
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Microinstruction Fields
BR Symbol Function
00 JMP CAR ← AD if condition = 1
CAR ← CAR + 1 if condition = 0
01 CALL CAR ← AD, SBR ← CAR + 1 if condition = 1
CAR ← CAR + 1 if condition = 0
10 RET CAR ← SBR (Return from subroutine)
11 MAP CAR(2-5) ← DR(11-14), CAR(0,1,6) ← 0
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Symbolic Microinstruction
Sample Format Label: Micro-ops CD BR AD
CD one of {U, I, S, Z}
U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC
ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH
OVER: NOP I CALL INDRCT
ARTPC U JMP FETCH
ORG 8
STORE: NOP I CALL INDRCT
ACTDR U JMP NEXT
WRITE U JMP FETCH
ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET 24
Binary Microprogram
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000
BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00 1000000
11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00 0001110
14 0001110 100 101 000 00 00 0001111
15 0001111 111 000 000 00 00 1000000
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Design of Control Unit
microoperation fields
F1 F2 F3
AND
ADD AC
Arithmetic
logic and DR
DRTAC shift unit
From From
PCTAR
DRTAR
PC DR(0-10) Load
AC
Select 0 1
Multiplexers
Load Clock
AR
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Microprogram Sequencer
External
(MAP)
L
I 3 2 1 0
Input Load
I
0 S1 MUX1 SBR
logic
T
1 S0
1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR
Control memory
Microops CD BR AD
... ...
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Input Logic for Microprogram
Sequencer
1 L L(load SBR with PC)
From I MUX2 Test
CPU S T for subroutine Call
BR field Input
Z Select I0 logic S0 for next address
of CS I
S1 selection
1
CD Field of CS
Input Logic
I1I0T Meaning Source of Address S1S0 L
S1 = I1
S0 = I0I1 + I1’T
L = I1’I0T
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