Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-1

LECTURE 15 – RESISTOR IMPLEMENTATIONS AND

CURRENT SINKS AND SOURCES
LECTURE ORGANIZATION
Outline
• Resistor implementations
• Simple current sinks and sources
• Improved performance current sinks and sources
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 128-138

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-2

RESISTOR IMPLEMENTATION USING MOSFETS

Real Resistors versus MOSFET Resistors
• Smaller in area than actual resistors
• Can pass a large current through a large resistance without a large voltage drop
iD
MOSFET (rds = 100kW)
100µA
100kW Resistor

10µA vDS
1V 10V 060526-10

vds 1
AC resistance = =
id gds
where

gds  2 (VGS-VT)2 = ID

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-3

MOS Diode as a Resistor

AC and DC resistance:

VDS VT 2
DC resistance = I = I +
D D  ID

Small-Signal Load (AC resistance):

D=G D=G
id
G
+ +D
vgs gmvgs rds vds
- -
S S
S S 120522-01

vds 1 1
AC resistance = i = g + g  g
d m ds m
where
gm = (VGS-VT) = 2ID
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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-4

Use of the MOSFET to Implement a Floating Resistor

In many applications, it is useful to implement a VBias
resistance using a MOSFET. First, consider the RAB
A B A B
simple, single MOSFET implementation.
L Fig. 4.2-9
RAB = K’W(V - V )
GS T
100mA
VGS=10V
VGS=9V
60mA
VGS=8V
VGS=7V

20mA

VGS=2V
-20mA
VGS=3V
VGS=4V
-60mA
VGS=5V
VGS=6V
-100mA
-1V -0.6V -0.2V 0.2V 0.6V 1V Fig. 4.2-95
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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-5

Cancellation of Second-Order Voltage Dependence – Parallel MOSFETs

Circuit:
M1
iAB VC VC iAB
A B A RAB B
M2
+ - + -
vAB
vAB 060526-12

Assume both devices are non-saturated

 vAB2

iD1 = ß1 (vAB + VC - VT)vAB - 2 
 
 vAB2

iD2 = ß2 (VC - VT)vAB - 2 
 
 vAB2 vAB2

iAB = iD1 + iD2 = ß v  AB2 + (VC - VT)vAB - 2 + (VC - VT)vAB - 2 
 

1
iAB = 2ß(VC - VT)vAB  RAB = 2ß(V - V )
C T

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-6

Parallel MOSFET Performance

Voltage-Current Characteristic:

SPICE Input File:

NMOS parallel transistor realization VDS 10 0
M1 2 1 0 5 MNMOS W=15U L=3U VSS 5 0 DC -5
M2 2 4 0 5 MNMOS W=15U L=3U .DC VDS -2.0 2.0 .2 VC 3 7 1
.MODEL MNMOS NMOS VTO=0.75, KP=25U, +LAMBDA=0.01, .PRINT DC I(VSENSE)
GAMMA=0.8 PHI=0.6 .PROBE
VC 1 2 .END
E1 4 0 1 2 1.0
VSENSE 10 2 DC 0

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-7

SIMPLE CURRENT SINKS AND SOURCES

Ideal Current Sinks and Sources
What is an ideal current sink or source?
i

Io
i +
Io v
- v
060527-01

• Current is fixed at a value of Io

• Voltage can be any value from +∞ to -∞
• Be careful when using a current sink or source to replace a MOSFET sink/source in
simulation

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-8

Characterization of MOSFET Sinks and Sources

A sink/source is characterized by two quantities:
• rout - a measure of the “flatness” of the current sink/source (its independence of
voltage)
• VMIN - the min. across the sink or source for which the current is no longer constant
NMOS Current Sink:
VDD VDD iDS= i
VMIN
VGG
Io
i Slope = 1/rout
i +
+ v
Io v -
VGG
- vDS = v
0
0 VGG-VT0 VDD
0601527-02

1 1+VDS 1
rout = di /dv =  ≈ and VMIN = VDS(sat) = VGS - VT0 = VGG - VT0
D DS D  ID
Note: The NMOS current sink can only have positive values of v.

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-9

PMOS Current Source

VDD VDD iSD= i
VMIN
+ VGG
Io v VGG +
- v Io
- Slope = 1/rout
i i

0 vSD = v
0 VGG-|VT0| VDD
0601527-03

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-10

Gate-Source Voltage Components

It is important to note that the gate-source voltage consists of two parts as illustrated
below:
iD
10W/L W/L 0.1W/L

ID

Enhance Provide
Channel Current

0 vGS
0 VT VGS Fig. 280-03

VGS = VT0 + VON = Part to enhance the channel + Part to cause current flow
where
VON = VDS(sat) = VGS - VT0
2ID
 VMIN = VON = VDS(sat) = for the simple current sink.
K’(W/L)
Note that VMIN can be reduced by using large values of W/L.

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-11

Simulation of a Simple MOS Current Sink

120

100
Slope = 1/Rout
80
iOUT (mA) iOUT
10mm
60 1mm +
VGS1 = vOUT
40 -
1.126V

20
Vmin
0
0 1 2 3 4 5
vOUT (Volts)
Comments:
VMIN is too large - desire VMIN to approach zero, at least approach VCE(sat)
Slope too high - desire the characteristic to be flat implying very large output
resistance
(KN’ = 110µA/V2, VT = 0.7Vand  = 0.04V-1)  rds = 250k
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-12

How is VGG Implemented?

The only voltage source assumed available is VDD.
Therefore, VGG, can be implemented in many ways with the example below being one
way.
VDD VDD
Current
VDD
R
R
IBias i i
IBias + +
+ v v
VBias=VGG - VGG -
-
VBias=VGG VDD Volts 140903-01

Better and more stable implementations of VGG will be shown later.

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-13

IMPROVED PERFORMANCE CURRENT SINKS

Improving the Performance of the Simple NMOS Current Sink
The simple NMOS current sink shown previously had two problems.
1.) The value of VMIN may be too large.
2.) The output resistance (250k) was too small.
How can the designer solve these problems?
1.) The first problem can be solved by increasing the W/L value of the NMOS
transistor.
2ID
VMIN = VON = VDS(sat) = K’(W/L)
In the simulation shown previously,
2·100µA
VMIN = = 0.426V
110µA/V2·10
We could decrease this to 0.1V with a W/L = 182.
2.) How can the small output resistance be increased? Answer is feedback.

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-14

Blackman’s Formula for Finding the Resistance at a Port with Feedback†

Blackman’s formula to find the resistance at a port X, is
based on the following circuit:

The resistance seen looking into port X is given as,

1 + RR(port shorted)
Rx = Rx(k=0) 1 + RR(port opened)
 

The return ratio, RR, is found by changing the dependent

source to an independent source as shown:
Therefore, the return ratio is defined as,
vc ic
RR = - v ' = - i '
c c
The key is to find a feedback circuit that when we calculate the RR, it is non-zero when
port X is shorted and zero when port X is opened. In this case, the resistance at port X
is
Rx = Rx(k=0)[1 + RR(port shorted)]

†
R.B. Blackman, “Effect of Feedback on Impedance,” Bell Sys. Tech.J., Vol. 23, pp. 269-277, October 1943.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-15

How to find the Proper Type of Feedback

For the port X, the circuit variables associated with the input port should be able to be
expressed as,
Input Variable to Port X = Signal variable to the circuit – Feedback variable
where the variables can be voltage or current.
1.) Series feedback (variables are voltage):
RR(Vx = 0) ≠ 0
RR(Ix = 0) = 0 (Vin is disconnected
from Vfb)
2.) Shunt feedback (variables are current):
RR(Vx = 0) = 0(Iin is disconnected
from Ifb)
RR(Ix = 0) ≠ 0
We see that for series feedback RR(port opened) will be zero and for shunt feedback
that RR(port shorted) will be zero.
Therefore, to boost the resistance at port X select series feedback!

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-16

Increasing the Output Resistance of the Simple Current Sink

Choosing series feedback, we select the following circuit to boost
the output resistance of the simple current sink:
Assume that we can neglect the bulk effect and find the input
resistance by 1.) small-signal analysis and 2.) return ratio method.
1.) Small-signal Analysis:
vx = (ix + gmvs)rds + ixR
vx = (ix + gmixR)rds + ixR = ix(rds + R + gmrdsR)
vx
 Rx = = rds + R + gmrdsR ≈ gmrdsR
ix
2.) Return Ratio:
Rx(k=0) = Rx(gm=0) = rds + R
vc  rdsR 
RR(vx = 0) = -v ' = gm  r +R
c  ds 
RR(ix = 0) = 0
  rdsR 
 Rx = (rds + R)1 + gm r +R = rds + R + gmrdsR ≈ gmrdsR
  ds 
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Cascode Current Sink iout

iOUT
+
Replacing R with the simple M2 + gm2vgs2 gmbs2vbs2 rds2
current sink leads to a practical
M1 vOUT vout
implementation shown as: VGG2 +
VGG1 gm1vgs1 rds1 vs2
- - -
vgs1 =vg2 = vb2 = 0
Small signal output resistance: Fig. 280-11

Noting that vgs1 = vg2 = vb2 = 0 and writing a loop equation we get,
vout = (iout - gm2vgs2 - gmbs2vbs2)rds2 + rds1iout
However,
vgs2 = 0 - vs2 = -ioutrds1 and vbs2 = 0 - vs2 = -ioutrds1
Therefore,
vout = iout[rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2]
or
vout
rout = i = rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2  gm2rds1rds2
out
A general principle is beginning to emerge:

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-18

The output resistance of a cascode circuit  R x (Common source voltage gain of the
cascoding transistor)

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-19

Design of VGG1 and VGG2

M2 +
+ VDS2 ≥VDS2(sat)
VGS2 - vOUT(min) = VDS1(sat)+VDS2(sat)
- +
VGG2
VDS1= VDS1(sat)
VGG1 -
060527-06

1.) VGG1 is selected to provide the desired current. M1 is assumed to be in saturation.

2.) VGG2 is selected to keep VDS1 as small as possible and still be in saturation.
VGG2 = VDS1(sat) + VGS2 = VDS1(sat) + VT + VDS2(sat)
If W1/L1 = W2/L2, then VGG2 = 2VDS(sat) + VT = 2VON + VT

Thus, for the previous NMOS current sink, VGG2 would be equal to,
VGG2 = 2(0.426) + 0.7 = 1.552V

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-20

Simulation of the Cascode CMOS Current Sink

Example 120
Slope = 1/Rout
Use the model parameters 100
KN’=110µA/V2, VT = 0.7 and N =
80 All W/Ls are iOUT
0.04V-1 to calculate (a) the small-

iOUT (mA)
10mm/1mm +
signal output resistance for the simple 60 VGG2 =
current sink if IOUT = 100µA and (b) 1.552V vOUT
the small-signal output resistance for 40
the cascode current sink with IOUT = VGG1 =
-
20 1.126V
100µA. Assume that all W/L values Vmin
are 1. 0
0 1 2 3 4 5
vOUT (Volts) Fig. 280-12
Solution
(a) Using  = 0.04 V-1 and IOUT = 100µA gives rds1 = 250k = rds2. (b) Ignoring the
bulk effect, we find that gm1 = gm2 = 469µS which gives rout =
(250k)(469µS)(250k) = 29.32M.

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-21

High-Swing Cascode Current Sink

This current sink achieves the smallest possible VMIN.
Since VDD VDD

2ID
VON = iOUT iOUT
K’(W/L) M2 + VMIN
M4 +
1/1 VON
then if L/W of M4 is 1/4 + +
VT+VON -
quadrupled, VON is VT+2VON M3 - vOUT
M1 +
doubled to get 1/1 + VON
-
VT+VON 1/1 -
VMIN = 2VON. - -
0 2VON vOUT
Example 060527-07

Use the cascode current sink configuration above to design a current sink of 100µA and
a VMIN = 1V. Assume the device parameters of Table 3.1-2.
Solution
With VMIN = 1V, choose VON = 0.5V. Assuming M1 and M2 are identical gives
W 2·IOUT 2·100x10-6 W1 W2 W3 W4
= = = 7.27  L = L = L = 7.27 and L = 1.82
L K’·VON2 110x10-6x0.25 1 2 3 4
Unfortunately, the drain voltages of M1 and M3 are not matched.
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Improved High-Swing Cascode Current Sink

Because the drain-source voltages of the VDD VDD
matching transistors, M1 and M3 are not
equal, iOUT ≠ IREF. R1 R2
iOUT
+ +
M4 M5 M2 +
VT 1/1 VON
To circumvent this problem the cascode 1/4 + 1/1 +
- VT+VON -
current sink shown is utilized: + M3 - + vOUT
VT+2VON M1
VON + VON
Note that the drain-source voltage of M1 and 1/1 VT+VON 1/1
- - - - --
M3 are identical causing iOUT to be a
060527-08
replication of IREF.
Design Procedure
1.) Since VMIN = 2VON = 2VDS(sat), let VON = 0.5VMIN.
2IREF W1 W2 W3 W5 2IREF 8IREF
2.) VON = 
K’(W/L) L1 = L2 = L3 = L5 = K’VON2 = K’VMIN2
W4 2IREF 2IREF IREF
3.) = = =
L4 K’(VGS4-VT)2 K’(2VON)2 2K’VON2

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-23

Signal Flow in Transistors

The last example brings up an interesting and important point. This point is
illustrated by the following question, “How does IREF flow into the M3-M5
combination of transistors since there is no path to the gate of M5?”
Consider how signals flow in transistors:
Output Only Output Only
D C
- + - +
+ +
Input Input
Only G Only B
+ +
+ + + + VDD
S E
Fig. 4.3-12B
IREF
Answer to the above question:
As VDD increases (i.e. the circuit begins to operate),
M5
IREF cannot flow into the drain of M5, so it flows through
the path indicated by the arrow to the gate of M3. It M3 VT +2VON
charges the stray capacitance and causes the gate-source +
voltage of M3 to increase to the exact value necessary to VGS3
-
cause IREF to flow through the M3-M5 combination. Fig. 4.3-12A
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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-24

Example 15-1 - Design of a Minimum VMIN Current Sink

Assume IREF = 100µA and design a cascode current sink with a VMIN = 0.3V using the
following parameters: VTO=0.7, KP=110U, LAMBDA=0.04, GAMMA=0.4, PHI=0.7
Solution
From the previous equations, we get
W1 W2 W3 W5 8IREF 8·100
L1 = L2 = L3 = L5 = K’VMIN 2 = 110·(0.3V)2 = 80.8 and
W4 IREF 100
L4 2K’VON 2 2·110·0.152 = 20.2
= =
120

Simulation Results: 100

Low Vmin Cascade Current Sink - Method No. 2
M1 5 1 0 0 MNMOS W=81U L=1U
M2 2 3 5 5 MNMOS W=81U L=1U
80
M3 4 1 0 0 MNMOS W=81U L=1U iOUT(mA)
M4 3 3 0 0 MNMOS W=20U L=1U 60
M5 1 3 4 4 MNMOS W=81U L=1U
.MODEL MNMOS NMOS VTO=0.7 KP=110U
+LAMBDA=0.04 GAMMA=0.4 PHI=0.7 40
VDD 6 0 DC 5V
IIN1 6 1 DC 100U
IIN2 6 3 DC 100U 20
VOUT 2 0 DC 5.0 VMIN
.OP
.DC VOUT 5 0 0.05 0
.PRINT DC ID(M2) 0 1 2 3 4 5
.END vOUT(V) Fig. 290-06

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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-25

Self-Biased Cascode Current Sink†

The VT + 2VON bias voltage is developed through a series VDD
resistor.
IREF
VT+2VON
Design procedure: +
Same as the previous except VON R
VON VMIN - VT+VON iOUT
R =I = 2I + M3 M4
REF REF
VT
For the previous example, -
0.3V + M1 M2 +
R = 2·100µA = 1.5k VON VON
- -
Fig. 290-07
If the reference current is small, R can become large.

†T.L. Brooks and A.L. Westwick, “A Low-Power Differential CMOS Bandgap Reference,” Proc. of IEEE Inter. Solid-State Circuits Conf., Feb.
1994, pp. 248-249.
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Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-26

Minimum Voltage Cascode Sinks

The following configuration gives increased output resistance with a fixed minimum
7
voltage drop of VDsat: Rout(4) = g + 8rds
m

3 +
Rout(3) = g + 4rds VDS(min)=VDSat
m
-
1 +
Rout(2) = g + 2rds +
m VDS(min)=VDSat VDS=0V
- -
+
+ +
VDS(min)=VDSat VDS=0V VDS=0V
- - -
+ + +
VDS=0V VDS=0V VDS=0V
- - -
150527-03

2n-1-1
It can be shown that Rout(n) is g + 2n-1rds if the gates are grounded. Therefore, the
m
output resistance is increasing by a factor of 2n-1 for each cascade device and the
minimum voltage across the sink remains constant at VDSat.
The upper transistor is in saturation while all the other transistors have VDS = 0 which
implies that gm = 0 and rds = 1/gm(sat).
This really only works well if the transistors are isolated and the bulk can be connected
to the source.
The area required for the sink will increase significantly because of the isolation.
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Minimum Voltage Cascode Current Mirrors

The previous technique can be used to create current mirrors with low minimum input
and output voltages as shown. iIN iOUT
3
iIN Rout(3) = g + 4rds
iOUT + m
1 +
Rout(2) = g + 2rds VDS=VGS VDS(min)=VDSat
+ m
+ - -
VDS=VGS VDS(min)=VDSat + +
- - VDS=0V VDS=0V
+ -
+ - -
+
VDS=0V + VDS=0V +
V - VDS=0V + VDS=0V
- - GS -
- VGS -
150527-04
n
The input resistance to the current mirrors can be written as Rin ≈
. This is illustrated
gm
by the following small signal model (remember when VDS = 0 that gm = 0 and rds =
1/gm(sat). Rin Rin
Rin Rin
gm3vgs3 +
M3 + vgs3 rds3 1/gm3 vgs3 rds3
VGS 1/gm3
- -
M2 +
VDS=0V rds2 = 1/gm(sat) rds2 = 1/gm(sat)
- rds2 = 1/gm(sat)
M1 +
+ VDS=0V rds1 = 1/gm(sat) rds1 = 1/gm(sat)
VGS - - rds1 = 1/gm(sat)
150527-05

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MOS Regulated Cascode Sink†

Comments:
• Achieves very high output resistance by increasing the loop gain (return-ratio) due to
the M4-M5 inverting amplifier.
 gm4  gm3rds2gm4rds4
LG = gm3rds2g +g  
 ds4 ds5 2
rds3gm3rds2gm4rds4
If rds4rds5, then rout 
2
• M3 maintains “constant” current even though it is no longer in the saturation region.

†E. Sackinger and W. Guggenbuhl, “A Versatile Building Block: The CMOS Differential Difference Amplifier,” IEEE J. of Solid-State Circuits,
vol. SC-22, no. 2, pp. 287-294, April 1987.
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Regulated Cascode Current Sink - Continued

Small signal model:
D2=
Solving for the output resistance: S3= iout
G3=D4=D5
iout = gm3vgs3 + gds3(vout-vgs4) + vgs3 - G4 gm3vgs3
+ D3 +
rds5 rds4 rds2 v vout
But gm4vgs4
gs4 r
ds3
- -
vgs4 = ioutrds2 S2 = G2= S4 Fig. 290-09
and
vgs3 = vg3 - vs3 = -gm4(rds4||rds5)vgs4 - vgs4 = -rds2[1 + gm4(rds4||rds5)]iout
 iout = -gm3rds2[1 + gm4(rds4||rds5)]iout + gds3vout - gds3rds2iout
vout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]iout
vout
 rout = = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]
iout
 rds3gm3rds2gm4(rds4||rds5)
If IREF = 100µA, all W/Ls are 10µm/1µm we get rds = 0.25M and gm = 469µS which
gives
rout  (0.25M)(469µS)(0.25M)(469µS)(0.125M) = 1.72G
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Can 1G Output Resistance Really be Achieved?

No, because of substrate currents. VG > V T
B S VD > VDS(sat)
Substrate currents are caused by impact Polysilicon
Depletion
ionization due to high electric fields cause Region
an impact which generates a hole-electron p+ n+ A
Free n+
electron
pair. The electrons flow out the drain and Fixed
Atom
the holes flow into the substrate causing a p- substrate Free
substrate current flow. hole
Fig130-7
Max. output resistance ≈ 500M-1G
Substrate current: D
iDB = K1(vDS - vDS(sat))iDe-[K2/(vDS-vDS(sat))]
where
iDB
K1 and K2 are process-dependent parameters G
-1
(typical values: K1 = 5V and K2 = 30V) B
Small-signal model:
S Fig130-8
iDB IDB
gdb = = K2 V - V (sat) ≈ 1nS
vDB DS DS
This conductance will prevent the realization of very high-output resistances.

CMOS Analog Circuit Design © P.E. Allen - 2016

 Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-31

Minimizing the VMIN of the Regulated Cascode Current Sink

VMIN:
Without the use of the VO1 battery shown, VMIN is pretty bad. It is,
VMIN = VGS4 + VDS3(sat) = VT + 2VON
Minimizing VMIN:
If VO1 = VT , then VMIN = 2VON. This is accomplished by the following circuit:
VDD VDD VDD
iOUT
IREF If VGS4A - VGS4B = VDS2(sat) = VON, then VMIN = 2VON
ID4A IB
+IB M3 + +
VDS2 2ID4 2IB 2IB+2IREF
KN’(W4A/L4A) - KN’(W4B/L4B) =
M4A M4B -
KN’(W2/L2)
+ + vOUT
VGS4AVGS4B IB
- - IREF+IB
ID4 IB IB+IREF
or
M1 M2 +
VDS2 W4A/L4A - W4B/L4B = W2/L2
- -
Fig. 290-10

A number of solutions exist. For example, let IB = IREF. This gives ID4A = 5.824IREF
assuming all W/L ratios are identical.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-32

Example 15-2 - Design of a Minimum VMIN Regulated Cascode Current Sink

Design a regulated cascode current sink for 100µA and minimum voltage of VMIN =
0.3V.
Solution
Let the W/L ratios of M1 through M5 be equal and let IB = 10µA. Therefore,
2·100µA 2·110µA
VMIN = 0.3V = VON3 + VON2 = +
110µA/V2(W/L) 110µA/V2(W/L)
2·100µA  
=  1 + 1.1  +5V +5V
110µA/V2(W/L) +5V
110mA 186mA 10mA iOUT
Therefore,
2·100µA M3 +
0.3V = (2.049) 85/1
110µA/V2(W/L)
M4A M4B
W 2·100µA·2.049 2
= = 84.8  85. 85/1 85/1
vOUT
L 110µA/V20.32 10mA

With IB = 10µA, then ID4A = M1 M2 110mA


 10 + 1102 = 186µA 85/1 85/1
-
Fig. 290-11

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-33

Comparison of the MOS Cascode and Regulated Cascode Current Sink

Close examination in the knee area reveals interesting differences.
Simulation results:
110

105
BJT Cascode
100 MOS Cascode
Regulated
iOUT (mA)

95 MOS
Cascode
90

85

80
0 0.1 0.2 0.3 0.4 0.5
vOUT (V) Fig. 290-12
Comments:
• The regulated cascode current is smaller than the cascode current because the drain-
source voltages of M1 and M2 are not equal.
• The regulated cascode current sink has a smaller VMIN due to the fact that M3 can
have a drain-source voltage smaller than VDS(sat)
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 15 – Resistor Implementations and Current Sinks and Sources 5/14/18) Page 15-34

SUMMARY
Summary of Both BJT and MOS Current Sinks/Sources
Current Sink/Source rOUT VMIN
Simple MOS Current Sink 1
rds = VDS(sat) =
D
VON
Simple BJT Current Sink VA VCE(sat)
ro =
C  0.2V
Cascode MOS  gm2rds2rds1 2VON
Cascode BJT  Fro 2VCE(sat)
Regulated Cascode Current Sink  rds3gm3rds2gm4(rds4||rds5)  VT +VON
Minimum VMIN Regulated  rds3gm3rds2gm4(rds4||rds5) VON
Cascode Current Sink
Resistor Implementations
• MOSFET resistors may use less area than actual resistors
• Linearity is the primary issue for MOSFET resistor realizations

CMOS Analog Circuit Design © P.E. Allen - 2016