Logic 2
Logic 2
Logic 2
1
Understanding Binary Numbers
Hexadecimal
(base16)
° Learn to convert between bases.
2
Decimal review
• Numbers consist of a bunch of digits, each with a weight
1 6 2 . 3 7 5 Digits
100 10 1 1/10 1/100 1/1000 Weights
• These weights are all powers of the base, which is 10. We can rewrite
this:
1 6 2 . 3 7 5 Digits
102 101 100 10-1 10-2 10-3 Weights
• To find the decimal value of a number, multiply each digit by its weight
and sum the products.
3
Converting decimal to binary
• To convert a decimal integer into binary, keep dividing by 2 until the
quotient is 0. Collect the remainders in reverse order.
• To convert a fraction, keep multiplying the fractional part by 2 until it
becomes 0. Collect the integer parts in forward order.
• Example: 162.375:
4
Binary and hexadecimal conversions
• Converting from hexadecimal to binary is easy: just replace each hex
digit with its equivalent 4-bit binary sequence.
261.3516 = 2 6 1 . 3 516
= 0010 0110 0001 . 0011 01012
• To convert from binary to hex, make groups of 4 bits, starting from the
binary point. Add 0s to the ends of the number if needed. Then, just
convert each bit group to its corresponding hex digit.
Hex to Decimal
8 7 C 9
x 16
128
+ 7
135
x 16
2,160
+ 12
2,172
x 16
34,752
+ 9
34,761Logic Circuits -Dr. Mohamad Alwan
10
5
Convert Decimal to Hex
34,76110 = 87C916
Questions
100101012 = ? (decimal)
6
Questions
100101012 = ? (decimal)
1 0 0 1 0 1 0 1
27 26 25 24 23 22 21 20
(149)10
Questions
85710 = ?16
7
Questions
BED16 = ?2
8
Logic Circuits -Dr. Mohamad Alwan 17
9
Exercise 1:
Convert these decimal numbers: 17.76 - 1958.56
- To binary
- To octal (directly from decimal)
- To hexadecimal (directly from decimal)
- To octal (from binary)
- To hexadecimal (from binary)
Exercise 2:
Find the decimal numerical values of:
- The binary numbers: 1101.1 - 101.0101 - 110101.101
- The octal numbers: 236 - 702.41 - 1011.1
- The hexadecimal numbers: A0B.5 – 1011.1 - FC3.0E
17.76=10001.11000010100011110101 1100
1958.56= 11110100110.100011110101110000101
0.56*2=1.12 0.64*2=1.28
0.12*2=0.24 0.28*2=0.56
0.24*2=0.48 0.56*2=1.12
0.48*2=0.96
0.96*2=1.92
0.92*2=1.84
0.84*2=1.68
0.68*2=1.36
0.36*2=0.72
0.72*2=1.44
0.44*2=0.88
0.88*2=1.76
0.76*2=1.52
0.52*2=1.04
0.04*2=0.08
0.08*2=0.16
0.16*2=0.32
Logic Circuits -Dr. Mohamad Alwan
0.32*2=0.64 20
10
17.76 = (21.60507534121727024365)8 0.76*8=6.08 0.72*8=5.76
0.08*8=0.64 0.76*8=6.08
0.64*8=5.12
0.12*8=0.96
0.96*8=7.68
0.68*8=5.44
0.44*8=3.52
0.52*8=4.16
0.16*8=1.28
0.28*8=2.24
0.24*8=1.92
0.92*8=7.36
0.36*8=2.88
0.88*8=7.04
0.04*8=0.32
0.32*8=2.56
0.56*8=4.48
0.48*8=3.84
0.84*8=6.72
Logic Circuits -Dr. Mohamad Alwan 21
(1958.56)10=(3646.43656050753412172703)8
0.76*16=C.16
-(17.76)10 = ? Base 16 = 11.C2F5 0.16*16=2.56
0.56*16=8.96
0.96*16=F.36
0.36*16=5.76
0.76*16=C.16
-(1958.56)10=? Base 16=7A6.8F5C2 8F5C2
16 0.56*16=8.96
1958
0.16*16=F.36
6 122 16 0.36*16=5.75
7 16 0.76*16=C.16
A 0.16*16=2.56
7 0
0.56*16=8.96
11
Exercise 1:
Convert these decimal numbers: 17.76 - 1958.56
- To binary
- To octal (directly from decimal)
- To hexadecimal (directly from decimal)
- To octal (from binary)
- To hexadecimal (from binary)
Exercise 2:
Find the decimal numerical values of:
- The binary numbers: 1101.1 - 101.0101 - 110101.101
- The octal numbers: 236 - 702.41 - 1011.1
- The hexadecimal numbers: A0B.5 – 1011.1 - FC3.0E
010/001.110/000/101/000/111/101/01 1/100
2 1 . 6 0 5 0 7 5 3 4
1958.56= 11110100110.100011110101110000101
0011/110/100/110.100/011/110/101/110/000/101
3 6 4 6 . 4 3 6 5 6 0 5
12
- To hexadecimal (from binary)
001/0001.1100/0010/1000/1111/0101/ 1100
1 1 . C 2 8 F 5 C
(1958.56)= 11110100110.100011110101110000101
0111/1010/0110.1000/1111/0101/1100/0010/1000
7 A 6 . 8 F 5 C 2 8
Exercise 2:
1101.1 =? Base 10
1 1 0 1 . 1
23 22 21 20 . 2-1 Weight of power 2
The decimal Value : (multiply each digit by its weight and sum the products)
- 101.0101=?Base 10
1 0 1 . 0 1 0 1
22 21 20 . 2-1 2-2 2-3 2-4
101.0101= (5.3125)10
13
110101.101= ? Base 10
1 1 0 1 0 1 . 1 0 1
25 24 23 22 21 20 . 2-1 2-2 2-3
2 3 6
82 81 80
(236)8= (158)10
(702.41)8 = (450.515625)
(1011.1)8= (521.125) Logic Circuits -Dr. Mohamad Alwan 27
A0B.5=2571.3125
1011.1=4113.0625
FC3.0E=4035.0546875
14
Chapter 2: Arithmetic Operations
we will focus our efforts on the basics that allow us to understand how digital
machines (i.e. computers) perform basic arithmetic operations.
Binary Addition
The addition of two binary numbers is perfectly analogous to the addition of
two decimal numbers.
However, there are only four cases, which can occur when adding two binary
digits . These four cases are:
15
• Binary addition is very simple.
• This is best shown in an example of adding two binary numbers…
Binary Addition
1 1 1 1 1
1 carries
1
1 1 1 0 1
+ 1 0 1 1 1
---------------------
1 0 1 0 1 0 0
16
Binary addition example worked out
• Some terms are given here
• Exercise: what are these numbers equivalent to in decimal?
1 1 1 0 (Carries)
1 0 1 1 (Augend)
+ 1 1 1 0 (Addend)
1 1 0 0 1 (Sum)
Subtraction
Binary Number Subtraction Value
0–0 0
1–0 1
1–1 0
17
Binary Subtraction
1 10 borrows
0 10 10 0 0 10
1 0 0 1 1 0 1
- 1 0 1 1 1
------------------------
1 1 0 1 1 0
• Example
18
Binary Multiplication
Binary Multiplication
1 0 1 1 1
X 1 0 1 0
-----------------------
0 0 0 0 0
1 0 1 1 1
0 0 0 0 0
1 0 1 1 1
-----------------------
1 1 1 0 0 1 1 0
19
Binary Division
1’s Complement
20
Two’s Complement Shortcuts
• Algorithm – Simply complement each bit and then add 1 to the
result.
• The value of 2’s complement (C2(N)) to represent negative
numbers.
21
Signed and unsigned numbers
22
Table 2.2
Positive and Negative Binary Numbers
Signed decimal Hex Binary Unsigned decimal
-128 80 10000000 128
-127 81 10000001 129
-126 82 10000010 130
… … … …
… … … …
… … … …
-3 FD 11111101 253
-2 FE 11111110 254
-1 FF 11111111 255
0 00 00000000 0
1 01 00000001 1
2 02 00000010 2
3 03 00000011 3
… … … …
… … …
… … …
125 7D 01111101 125
126 7E 01111110 126
127 7F 01111111 127
Signed Numbers
4-bit: 8H = -8 to 7H = +7
1000 to 0111
23
Subtract by Adding
Subtract by adding
73 73
-35 10’s complement +65
38 138
Ignore carry
Subtract by Adding
overflow (38)10
Sign bit
Logic Circuits -Dr. Mohamad Alwan 48
24
Subtract by Adding
Questions
25
BCD
Binary Coded
Decimal
Logic Circuits -Dr. Mohamad Alwan 51
0 0000 5 0101
1 0001 6 0110
2 0010 7 0111
3 0011 8 1000
4 0100 9 1001
• Binary coded decimal (BCD) represents each decimal digit with four bits
– Ex. 0011 0010 1001 = 329BCD
3 2 9
• This is NOT the same as 0011001010012
26
Putting It All Together
We have only 10
combinations of BCD.
° Easier to read?
27
The excess-3 code
• Take another exemple; convert 29 to an excess-3
2 9
+3 +3
__ __
5 12
0101 1100
After adding 9 and 3, do not carry 1 into the next column; instead, leave
the result intact as 12, and the convert as shown. Therefore :
Gray Code
• Each Gray code number differs from the preceding number by single
bit.
28
Transcoder
ASCII CODES
29
ASCII
ASCII Code
30
ASCII Properties
Q1:
What is relationship between a decimal digit (0, 1, …) and
its ASCII code?
Logic Circuits -Dr. Mohamad Alwan 61
Q2:
What is the difference between an upper-case letter
(A, B, …) and its lower-case equivalent (a, b, …)?
Logic Circuits -Dr. Mohamad Alwan 62
31
ASCII Properties (2)
Parity Bit
The ASCII code is used for sending digital data over telephone lines, 1-
bit errors my occur in transmitted data. To catch these errors, a parity
bit is usually transmitted along with the original bits. Then a parity
checker at the receiving end can test for even or add odd parity,
whichever parity has been prearranged between the sender and the
receiver. Since ASCII cide uses 7 bits, the addition of a parity bit to
the transmitted data produces an 8-bit number in this format:
X7X6X5X4X3X2X1X0
Parity bit
Exemple :
A computer sends a message to another computer using an odd-party
bit.Here is the message in ASCII code, plus parity bit :
1100 1000
0100 0101
0100 1100
0100 1100
0100 1111 -Dr. Mohamad Alwan
Logic Circuits 64
32
Logic Circuits -Dr. Mohamad Alwan 65
33
Logic Gates
• Manual Switch
• A switch is pushed manually, raised to a high voltage
• Which makes the current flow through the bulb
34
Using the switch
Output
Input Output
Input2
35
OR Gate
Input1
Output
Input2
Basic Gates
• There are three basic kinds of logic gates
Logic gate:
36
Describing Circuit Functionality: Inverter
Truth Table
A Y
A Y 0 1
1 0
Symbol
Input Output
• Basic logic functions have symbols.
• The same functionality can be represented with truth tables.
– Truth table completely specifies outputs for all input combinations.
• The above circuit is an inverter.
– An input of 0 is inverted to a 1.
– An input of 1 is inverted to a 0.
A
Y
B
1 0 0
1 1 1
37
The OR Gate
A
Y
B
• This is an OR gate. A B Y
• So, if either of the two
0 0 0
input signals are
asserted, or both of 0 1 1
them are, the output
1 0 1
will be asserted.
1 1 1
38
Consider three-input gates
3 Input OR Gate
39
Boolean Algebra
40
Distributivity of the Operators and Complements
• The Distributive Property:
For every a, b, and c in K,
– a+(b.c)=(a+b).(a+c)
– a.(b+c)=(a.b)+(a.c)
• The Existence of the Complement:
For every a in K there exists a unique element called a’
(complement of a) such that,
– a + a’ = 1
– a . a’ = 0
• To simplify notation, the . operator is frequently omitted. When
two elements are written next to each other, the AND (.) operator
is implied…
– a+b.c=(a+b).(a+c)
– a + bc = ( a + b )( a + c )
Duality
41
Involution
Absorption
42
DeMorgan’s Theorem
Additional gates
43
Additional Boolean operations
Logic gates:
44
XOR gates
• A two-input XOR gate outputs true when exactly one of its inputs is
true:
x y ⊕y
x⊕
0 0 0
0 1 1 x ⊕ y = x’ y + x y’
1 0 1
1 1 0
x⊕0=x x ⊕ 1 = x’
x⊕x=0 x ⊕ x’ = 1
x ⊕ (y ⊕ z) = (x ⊕ y) ⊕ z [ Associative ]
x⊕y=y⊕x [ Commutative ]
• XOR is especially useful for building adders (as we’ll see on later) and
error detection/correction circuits.
45
XNOR gates
• Finally, the complement of the XOR function is the XNOR function.
• A two-input XNOR gate is true when its inputs are equal:
x ⊕y)’
y (x⊕
0 0 1
0 1 0 (x ⊕ y)’ = x’y’ + xy
1 0 0
1 1 1
Implementation with
one Gate type
92
Logic Circuits -Dr. Mohamad Alwan
46
More Gates: NAND - NOR
X Y Z=(XY)’
0 0 1
X
NAND Z F = (XY)’ 0 1 1
Y 1 0 1
1 1 0
X Y Z=(X+Y)’
X 0 0 1
NOR Z F = (X+Y)’
Y 0 1 0
1 0 0
1 1 0
X X’ X
NOT X’
X
X X XY
AND XY
Y Y
X X X+Y
OR X+Y
Y Y
47
Implementation using NANDs
•Example: Consider F = AB + CD
A
A
B
F B F
C
C
D
D
Proof:
F = ((AB)’.(CD)’)’
= ((AB)’)’ + ((CD)’)’
= AB + CD
48
NOR Gate is Universal
X X’ X X’
NOT
X
X X (X’+Y’)’ = XY
AND XY
Y Y
X X (X+Y)’’ = X+Y
OR X+Y
Y Y
•Consider F = (A+B)(C+D)E
NOR
NOR
A A
B B
F F
C C
D D
E E’
49
Rules for 2-Level NOR Implementations
Normal Form
SOP/POS
50
Overview
Representation Conversion
Circuit Boolean
Expression
Truth
Table
51
Normal Form
52
Equivalent Representations of Circuits
• All three formats are equivalent
• Number of 1’s in truth table output column equals AND terms for Sum-of-
Products (SOP)
x y z G
0 0 0 0
x
0 0 1 0 x x
0 1 0 0 x
G
x
0 1 1 1 x
1 0 0 0 x
x x
1 0 1 0
1 1 0 1
1 1 1 1
x y z
G = xyz + xyz’ + x’yz
53
Reduced Hardware Implementation
• Reduced equation requires less hardware!
• Same function implemented!
x y z G
0 0 0 0
0 0 1 0 x x
0 1 0 0 G
0 1 1 1
1 0 0 0
1 0 1 0 x
x
1 1 0 1
1 1 1 1
x y z
G = xyz + xyz’ + x’yz = xy + yz
Logic Circuits -Dr. Mohamad Alwan 107
x y z Minterm x y z Maxterm
0 0 0 x’y’z’ m0 0 0 0 x+y+z M0
0 0 1 x’y’z m1 0 0 1 x+y+z’ M1
… …
1 0 0 xy’z’ m4 1 0 0 x’+y+z M4
… …
1 1 1 xyz m7 1 1 1 x’+y’+z’ M7
54
Representing Functions with Minterms
• Minterm number same as row position in truth table (starting from top
from 0)
• Shorthand way to represent functions
x y z G
0 0 0 0 G = xyz + xyz’ + x’yz
0 0 1 0
0 1 0 0
0 1 1 1
G = m7 + m6 + m3 = Σm(3, 6, 7)
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
55
Expression Reduction
Techniques
• 2 reduction techniques
– Algebric reduction technique
– Karnauph Map or K-Map technique
56
Algebric Reduction Technique
• Example:
• F(A,B,C)=A’B’C+A’BC+AB’C+ABC
=A’C(B’+B)+AC(B’+B)=A’C+AC=(A’+A)C=C
57
2-variable Karnaugh Maps
A B F B
0 1
Example 0 0 0 A
0 1 1 00 1
F(A,B)=AB +A′B +AB ′ 1 0 1
1 1 1 11 1
F=A +B
• Each circle represents minterm reduction
• Every cell containing a 1 must be included at least once.
• The largest possible “power of 2 rectangle” must be
enclosed.
• The 1’s must be enclosed in the smallest possible number
of rectangles.
•
A B C F
0 0 0 0 BC
0 0 1 1 00 01 11 10
0 1 0 1 A
0 1 1 0 00 1 0 1
1 0 0 1 F=A+B ′C +BC ′
1 0 1 1 11 1 1 1
1 1 0 1
+
1 1 1 1
58
Four variable Karnaugh Maps
A B C D f
0 0 0 0 0 CD
0 0 0 1 0 00 01 11 10
0 0 1 0 1
AB
0 0 1 1 0
00 0 0 0 1
0
0
1
1
0
0
0
1
1
1
01 1 1 0 1
0 1 1 0 1 11 1 1 1 1
0 1 1 1 0
+
1
+
0 0 0 1
10 1 0 1 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1 F=BC ′+CD ′+ AC+ AD ′
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
59
Karnaugh maps: Don’t cares
CD
AB 00 01 11 10 A B C D f
0 0 0 0 0
00 0 1 1 0
0 0 0 1 1
0 0 1 0 0
01 0 1 1 x
0 0 1 1 1
0 1 0 0 0
11 x x 0 0 0 1 0 1 1
10 0 1 1 0 X
0 1 0 0 0 1 1 1 1
+ +
1 0 0 0 0
1 0 0 1 1
F=A’D+C’D 1 0 1 0 0
1 0 1 1 0
1 1 0 0 X
1 1 0 1 X
1 1 1 0 0
1 1 1 1 0
CD
00 01 11 10
AB
00 0 1 0 0
01 x x x 1 F=A′C′D+B+AC
11 1 1 1 x
10 x 0 1 1
60
Use k-map to find the simplified logic function of outputs. Draw the
logic circuit using AND, OR, NOT gates.
Logic Circuits -Dr. Mohamad Alwan 121
B1B0
B3B2 00 01 11 10
00 0 0 0 0
01 0 1 1 1
11 x x x x
10 1 1 x x
X3=
B1B0
B3B2 00 01 11 10
00 0 1 1 1
01 1 0 0 0
11 x x x x
10 0 1 x x
X2=
61
B1B0
B3B2 00 01 11 10
00 1 0 1 0
01 1 0 1 0
11 X X X X
10 1 0 X X
X1=
B1B0
B3B2 00 01 11 10
00 1 0 0 1
01 1 0 0 1
11 X X X X
10 1 0 X X
X0=
• X3=B3+B2B0+B21
• X2=B2B1’B0’+B2’B0+B1B3’B2’
• X3=B1’B0’+B1B0
• X4=B1’B0’+B1B0’
62
Logic Circuits -Dr. Mohamad Alwan 125
B1B0 00 01 11 10
A1A0
00 0 0 0 0
01 1 0 0 0 G=A1.B1’+A0.B1’B0’+A1A0.B0’
11 1 1 0 1
10 1 1 0 0
B1B0
A1A0 00 01 11 10
S=A1’B1+A1’A0’B0+ A0’B1B0
00 0 1 1 1
01 0 0 1 1
11 0 0 0 0
10 0 0 1 0
B1B0 00 01 11 10
A1A0
00 1 0 0 0 E=A1’A0’B1’B0’+A1’A0B1’B0+A1A0B1B0+A1A0’B1B0’
01 0 1 0 0
11 0 0 1 0
10 0 0 0 1 Logic Circuits -Dr. Mohamad Alwan 126
63
Multiplexer/De-multiplexer
Multiplexers
• Multiplexers, or muxes, are used to choose between resources.
• A real-life example: in the old days before networking, several
computers could share one printer through the use of a switch.
64
Rotary Switch
C0
C1
Y
C2
C3
Rotary Switch
C0
C1
Y
C2
C3
65
Rotary Switch
C0
C1
Y
C2
C3
Rotary switch
C0
C1
Y
C2
C3
66
Multiplexers
n n
• A 2 -to-1 multiplexer sends one of 2 input lines to a single output line.
– A multiplexer has two sets of inputs:
• 2n data input lines
• n select lines, to pick one of the 2n data inputs
– The mux output is a single bit, which is one of the 2n data inputs.
Multiplexers
4x1
MUX
C0 s1 s0 Y
C1 0 0 C0
Y 0 1 C1
C2 1 0 C2
C3 1 1 C3
s1 s0
A multiplexer is a
0 0
digital switch (automatic switch)
67
Multiplexers
4x1
MUX
s1 s0 Y
C0
C1 0 0 C0
Y 0 1 C1
C2 1 0 C2
C3 1 1 C3
s1 s0
0 1
Multiplexers
4x1
MUX
s1 s0 Y
C0
C1 0 0 C0
Y 0 1 C1
C2 1 0 C2
C3 1 1 C3
s1 s0
1 0
68
Multiplexers
4x1
MUX
s1 s0 Y
C0
C1 0 0 C0
Y 0 1 C1
C2 1 0 C2
C3 1 1 C3
s1 s0
1 1
A 4-to-1 multiplexer
• Here is a block diagram and abbreviated truth table for a 4-to-1 mux.
S1 S0 Q
0 0 D0
0 1 D1
1 0 D2
1 1 D3
69
4-to-1 MUX Logic Diagram
S1
S0
D0
D1
Q
D2
D3
x y z f
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Logic Circuits -Dr. Mohamad Alwan
140
70
A more efficient way
• We can actually implement f(x,y,z) = Σm(1,2,6,7) with x y z f
just a 4-to-1 mux, instead of an 8-to-1.
0 0 0 0
• Step 1: Find the truth table for the function, and 0 0 1 1
group the rows into pairs. Within each pair of rows, x
0 1 0 1
and y are the same, so f is a function of z only.
0 1 1 0
– When xy=00, f=z 1 0 0 0
– When xy=01, f=z’ 1 0 1 0
– When xy=10, f=0
1 1 0 1
– When xy=11, f=1
1 1 1 1
• Step 2: Connect the first two input variables of the
truth table (here, x and y) to the select bits S1 S0 of
the 4-to-1 mux.
Rotary switch/Demultiplexers
Y0
Y1
YIN
Y2
Y3
71
Rotary Switch/Demultiplexers
Y0
Y1
YIN
Y2
Y3
Rotary Switch/Demultiplexers
Y0
Y1
YIN
Y2
Y3
72
Rotary Switch/Demultiplexers
Y0
Y1
YIN
Y2
Y3
S1 S0 Y0 Y1 Y2 Y3
Y0
1x4 Y1 0 0 YIN 0 0 0
YIN DeMUX 0 1 0 YIN 0 0
Y2 1 0 0 0 YIN 0
Y3 1 1 0 0 0 YIN
S1 S0
73
Demultiplexers
1x4
DeMUX
S1 S0 Y0 Y1 Y2 Y3
Y0
Y1 0 0 YIN 0 0 0
YIN 0 1 0 YIN 0 0
Y2 1 0 0 0 YIN 0
Y3 1 1 0 0 0 IN
S1 S0
0 0
Demultiplexers
1x4
DeMUX
S1 S0 Y0 Y1 Y2 Y3
Y0
Y1 0 0 YIN 0 0 0
YIN 0 1 0 YIN 0 0
Y2 1 0 0 0 YIN 0
Y3 1 1 0 0 0 YIN
S1 S0
0 1
74
Demultiplexers
1x4
DeMUX
S1 S0 Y0 Y1 Y2 Y3
Y0
Y1 0 0 YIN 0 0 0
YIN 0 1 0 YIN 0 0
Y2 1 0 0 0 YIN 0
Y3 1 1 0 0 0 YIN
S1 S0
1 0
Demultiplexers
1x4
DeMUX
S1 S0 Y0 Y1 Y2 Y3
Y0
Y1 0 0 YIN 0 0 0
YIN 0 1 0 YIN 0 0
Y2 1 0 0 0 YIN 0
Y3 1 1 0 0 0 YIN
S1 S0
1 1
75
Demultiplexers
S1 S0 Y0 Y1 Y2 Y3
0 0 YIN 0 0 0
Y0 0 1 0 YIN 0 0
1x4 Y1 1 0 0 0 YIN 0
YIN DeMUX 1 1 0 0 0 YIN
Y2
Y3
Y0 = YIN S1’ S0'
S1 S0 Y1 = YIN S1’ S0
Y2 = YIN S1 S0’
Y3 = YIN S1 S0
Y0
Y1
Y2
Y3
76
Mux-DeMux Combination (Communication Application)
C0 Y0
C1 4x 1 Y YIN 1x 4 Y1
MUX DeMUX
C2 Y2
C3 Y3
s1 s0 d1 d0
4x1 1x4
MUX DeMUX
C0 Y0
C1 Y YIN Y1
C2 Y2
C3 Y3
s1 s0
0 0
77
Mux-DeMux Combination (Communication Application)
4x1 1x4
MUX DeMUX
C0 Y0
C1 Y YIN Y1
C2 Y2
C3 Y3
s1 s0
0 1
4x1 1x4
MUX DeMUX
C0 Y0
C1 Y YIN Y1
C2 Y2
C3 Y3
s1 s0
1 0
78
Mux-DeMux Combination (Communication Application)
4x1 1x4
MUX DeMUX
C0 Y0
C1 Y YIN Y1
C2 Y2
C3 Y3
s1 s0
1 1
79
How can you build a 2-to-4 decoder?
• Follow the design procedures from last time! We have a truth table, so
we can write equations for each of the four outputs (Q0-Q3), based on
the two inputs (S0-S1).
S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
• In this case there’s not much to be simplified. Here are the equations:
Q0 = S1’ S0’
Q1 = S1’ S0
Q2 = S1 S0’
Q3 = S1 S0
S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
80
Enable inputs
• Many devices have an additional enable input, which is used to “activate”
or “deactivate” the device.
• For a decoder,
– EN=1 activates the decoder, so it behaves as specified earlier.
Exactly one of the outputs will be 1.
– EN=0 “deactivates” the decoder. By convention, that means all of
the decoder’s outputs are 0.
• We can include this additional input in the decoder’s truth table:
EN S1 S0 Q0 Q1 Q2 Q3
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
81
Blocks and abstraction
• Decoders are common enough that we want to encapsulate them and
treat them as an individual entity.
• Block diagrams for 2-to-4 decoders are shown here. The names of the
inputs and outputs, not their order, is what matters.
Q0 = S1’ S0’
Q1 = S1’ S0
Q2 = S1 S0’
Q3 = S1 S0
A 3-to-8 decoder
• Larger decoders are similar. Here is a 3-to-8 decoder.
– The block symbol is on the right.
– A truth table (without EN) is below.
– Output equations are at the bottom right.
• Again, only one output is true for any input combination.
S2 S1 S0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0 Q0 = S2’ S1’ S0’
0 0 1 0 1 0 0 0 0 0 0 Q1 = S2’ S1’ S0
0 1 0 0 0 1 0 0 0 0 0 Q2 = S2’ S1 S0’
0 1 1 0 0 0 1 0 0 0 0 Q3 = S2’ S1 S0
1 0 0 0 0 0 0 1 0 0 0 Q4 = S2 S1’ S0’
1 0 1 0 0 0 0 0 1 0 0 Q5 = S2 S1’ S0
1 1 0 0 0 0 0 0 0 1 0 Q6 = S2 S1 S0’
1 1 1 0 0 0 0 0 0 0 1 Q7 = S2 S1 S0
82
A variation of the standard decoder
• The decoders we’ve seen so far are active-high decoders.
EN S1 S0 Q0 Q1 Q2 Q3
0 x x 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
• Example:
S(x, y, z) = Σ (1,2,4,7) x y z C S
0 0 0 0 0
C(x, y, z) = Σ (3,5,6,7) 0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
3-to-8 0
Decode 1 S
r 2
x S2 3
y S1 4
5 C
z S0 6
7
83
Active-low decoder example
• So we can use active-low decoders to implement arbitrary functions
too, but as a product of maxterms.
• For example, here is an implementation of the function,
f(x,y,z) = ΠM(4,5,7), using an active-low decoder.
Encoders
I0 I0 I1 I2 I3 B A
I1 4-to-2 A
Encoder 1 0 0 0 0 0
I2 B 0 1 0 0 0 1
I3 0 0 1 0 1 0
0 0 0 1 1 1
84
Encoders
I2
I3
B = I2 + I3
8-to-3 Encoder
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Y2 = I7 + I6 + I5 + I4
Y1 = I7 + I6 + I3 + I2
Y0 = I7 + I5 + I3 + I1
Logic Circuits -Dr. Mohamad Alwan
170
85
Half-Adder and Full-Adder
• Arithmetic is the most basic thing you can do with a computer, but it’s
not as easy as you might expect!
• These next few lectures focus on addition, subtraction, multiplication
and arithmetic-logic units, or ALUs, which are the “heart” of CPUs.
• ALUs are a good example of many of the issues we’ve seen so far,
including Boolean algebra, circuit analysis, data representation, and
hierarchical, modular design.
86
Binary addition by hand
• You can add two binary numbers one column at a time starting from the
right, just as you add two decimal numbers.
• But remember that it’s binary. For example, 1 + 1 = 10 and you have to
carry!
The initial carry
in is implicitly 0
1 1 1 0 Carry in
1 0 1 1 Augend
+ 1 1 1 0 Addend
1 1 0 0 1 Sum
X Y C S
0 0 0 0 0 +0 =0
0 1 0 1 0 +1 =1
1 0 0 1 1 +0 =1
1 1 1 0 1 +1 = 10
C = XY
S = X’ Y + X Y’
=X⊕Y
87
Full adder equations
• A full adder circuit takes three bits of input, and produces a two-bit
output consisting of a sum and a carry out.
• Using Boolean algebra, we get the equations shown here.
– XOR operations simplify the equations a bit.
– We used algebra because you can’t easily derive XORs from K-maps.
X Y C in C out S S = Σm(1,2,4,7)
0 0 0 0 0
= X’ Y’ Cin + X’ Y Cin’ + X Y’ Cin’ + X Y Cin
= X’ (Y’ Cin + Y Cin’) + X (Y’ Cin’ + Y Cin)
0 0 1 0 1
= X’ (Y ⊕ Cin) + X (Y ⊕ Cin)’
0 1 0 0 1
= X ⊕ Y ⊕ Cin
0 1 1 1 0
1 0 0 0 1 Cout = Σm(3,5,6,7)
1 0 1 1 0 = X’ Y Cin + X Y’ Cin + X Y Cin’ + X Y Cin
1 1 0 1 0 = (X’ Y + X Y’) Cin + XY(Cin’ + Cin)
1 1 1 1 1 = (X ⊕ Y) Cin + XY
S = X ⊕ Y ⊕ Cin
Cout = (X ⊕ Y) Cin + XY
88
A 4-bit adder
• Four full adders together make a 4-bit adder.
• There are nine total inputs:
– Two 4-bit numbers, A3 A2 A1 A0 and B3 B2 B1 B0
– An initial carry in, CI
• The five outputs are:
– A 4-bit sum, S3 S2 S1 S0
– A carry out, CO
• Imagine designing a nine-input adder without this
hierarchical structure—you’d have a 512-row truth
table with five outputs!
1 1 1 0 1 1 0 1
0
1 1 0
1 1 0 0 1
89
Overflow
• In this case, note that the answer (11001) is five bits long, while the
inputs were each only four bits (1011 and 1110). This is called overflow.
• Although the answer 11001 is correct, we cannot use that answer in any
subsequent computations with this 4-bit adder.
• For unsigned addition, overflow occurs when the carry out is 1.
90
Comparator
Comparator
• The comparison of two numbers Truth table
– outputs: A>B, A=B, A<B A1 A0 B1 B0 E G L
– 2-bit numbers 0 0 0 0 1 0 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 0 1 0
A1
A0 A<B 0 1 0 1 1 0 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
Comparator A=B 1 0 0 0 0 1 0
B1 1 0 0 1 0 1 0
B0 A>B 1 0 1 0 1 0 0
1 0 1 1 0 0 1
1 1 0 0 0 1 0
1 1 0 1 0 1 0
1 1 1 0 0 1 0
1 1 1 1 1 0 0
91
K-MAP
B1B0
00 01 11 10 E=A1’A0’B1’B0’+A1’A0B1’B0+A1A0B1B0+A1A0’B1B0’
A1A0
00 1 0 0 0 =A1’B1’(A0’B0’+A0B0)+A1B1(A0B0+A0’B0’)
01 0 1 0 0 =(A1’B1’+A1B1)(A0’B0’+A0B0)
11 0 0 1 0 =(A1(+)B1)’ (A0(+)B0)’
10 0 0 0 1 = ((A1(+)B1)+(A0(+)B0))’
B1B0
00 01 11 10 B1B0
A1A0 00 01 11 10
A1A0
00 0 0 0 0 00 0 1 1 1
01 1 0 0 0 01 0 0 1 1
11 1 1 0 1 11 0 0 0 0
10 1 1 0 0 10 0 0 1 0
G=A1B1’+A0B1’B0’+A1A0B0’ L=A1’B1+A1’A0’B0+A0’B1B0
Magnitude Comparison
• Hardware chips
92
8-bit Comparator
A0
.
A3
7485
B0
.
In out
B3 A>B
A>B A<B
A<B
A=B
A=B
A>B
A<B
A>B
A=B
A<B
A4
A=B
.
A7 In out
B4
. 7485
B7
93
Seven Segment Displays
Retro
LED Watch
(Circa 1970s)
Segment Identification
f b
g
e c
94
SSD Display Possibilities
Decimal Digits 0-
9
Simple Messages
To Turn an LED ON . . .
• The ANODE must be at a
higher voltage potential (∼1.5v)
than the CATHODE.
• The amount of current flowing
through the LED will determine
CATHODE (‒) (+) ANODE
the brightness of the LED.
• The amount of current is
← Current Flow
controlled by a series resistor.
(not shown)
95
7-Segment Display (Common Anode display)
a
+5v
f b
g
e c a b c d e f g
a b c d e f g
f b
g
e c
96
BCD 7-Segment Display
a
wxyz a b c d e f g
0 0000 1 1 1 1 1 1 0
f b 1 0001 0 1 1 0 0 0 0
2 0010 1 1 0 1 1 0 1
g
3 0011 1 1 1 1 0 0 1
4 0100 0 1 1 0 0 1 1
5 0101 1 0 1 1 0 1 1
e c 6 0110 1 0 1 1 1 1 1
7 0111 1 1 1 0 0 0 0
8 1000 1 1 1 1 1 1 1
d 9 1001 1 1 1 1 0 1 1
A 1010 x x x x x x x
b 1011 x x x x x x x
Using common
C 1100 .
cathode display d 1101 .
E 1110 .
F 1111 x x x x x x x
K-Map
yz
wx
00 01 11 10 a=y+w+xz+x’z’
00 1 0 1 1
01 0 1 1 1 b=w+x’+y’z’+yz
11 x x x x
10 1 1 x x c=y’+z+x
d=xy’z+w+x’z’+yz’+x’y
e=yz’+x’z’
f=w+y’z’+xy’+xz’
g=w+xy’+x’y+yz’
Logic Circuits -Dr. Mohamad Alwan
194
97
Flip Flops
98
Sequential logic elements
99
SR Latch – NOR form
• Let’s use NOR gates . The SR latch below has two inputs S and R, which
will let us control the outputs Q and Q’.
• Here Q and Q’ feed back into the circuit. They’re not only outputs,
they’re also inputs!
• To figure out how Q and Q’ change, we have to look at not only the
inputs S and R, but also the current values of Q and Q’:
Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’
• Let’s see how different input values for S and R affect this thing.
SR Latch Representation
S R Q+
0 0 Q( no Reduced
change Characteristic Table
0 1 0 or
(reset)
Summarized state
1 0 1(set) transition table
Qnext = (R + Q’current)’
1 1 invalid
Q’next = (S + Qcurrent)’
S R Q Q+
0 0 0 0 Characteristic Table
or Timing Diagram
0 0 1 1
0 1 0 0 state transition table
S
0 1 1 0
R
1 0 0 1
1 0 1 1 Q
1 1 0 NV Equation of Q+ :
Q’
1 1 1 NV Q+=S+R’Q
100
SR latch using NAND Gates
S’ R’ Q+
Timing Diagram 1 1 Q(No change)
1 0 0 (reset)
S 0 1 1 (set)
0 0 Avoid!
R
Q’
C S R S’ R’ Q
0 x x 1 1 No change
1 0 0 1 1 No change
1 0 1 1 0 0 (reset)
1 1 0 0 1 1 (set)
1 1 1 0 0 Avoid!
101
Clocks and synchronization
• A clock is a special device that whose output continuously alternates
between 0 and 1.
clock period
• The time it takes the clock to change from 1 to 0 and back to 1 is called
the clock period, or clock cycle time.
• The clock frequency is the inverse of the clock period. The unit of
measurement for frequency is the hertz.
• Clocks are often used to synchronize circuits.
– They generate a repeating, predictable pattern of 0s and 1s that
can trigger certain events in a circuit, such as writing to a latch.
– If several circuits share a common clock signal, they can coordinate
their actions with respect to one another.
• This is similar to how humans use real clocks for synchronization.
Clock Edge
Lo-
Lo-Hi edge Hi
Hi--Lo edge
102
Positive Edge-triggered J-K Flip Flop
Characteristic Table
J
Q
CLK
Hi
Hi--Lo edge Q’
K
103
Asynchronous Inputs
104
Positive and Negative Edge D Flip-Flop
• D flops can be triggered on positive or negative edge
• Bubble before Clock (C) input indicates negative edge trigger
Lo-
Lo-Hi edge Hi
Hi--Lo edge
Logic Circuits -Dr. Mohamad Alwan
209
T Q+
CLK
0 Q(no change)
T
1 Toggle
Q
105
Asynchronous Counters
Overvie
w
106
Asynchronous Counters
2-bit Asynchronous
Counter
J and K inputs
are always tied
together to form
the T Flip Flop
107
4-bit Asynchronous Ripple
Counter
Down
counters
• The counters we have seen so far are up-counters. The falling edge
Flip-Flops makes them count up.
• If we use rising edge Flip-Flops, the counter would be a down
counter.
108
Logic Circuits -Dr. Mohamad Alwan 217
109
Timing Consideration
• Timing Diagram shows state transitions occurring exactly on
the falling edge of the clock. This is not true. It takes time
for the Flip-Flop to change state (say 40ns)
• Changing from state 00 01 would need to change 1 bit or
time delay=40ns.
• Changing from state 01 10 would need to change 2 bits or
time delay=80ns
• Since each Flip-Flop does not change state on a common
clock, and switching delay is incurred as the clock signal
ripples thru the string of Flip-Flops. This kind of counters is
called CAsynchronous ripple counter.
40ns Qa
Qb
80ns
Logic Circuits -Dr. Mohamad Alwan
219
Qb 1 1 0 0 0
Qc 1 1 1 0 0
Qd 1 1 1 1 0
15 14 12 8 0
110
Modifying the count
sequence
Reset Delay:
•Change state
from 100101
takes 40ns
•Switch for
NAND takes
10ns
•Clear Flip-Flops
takes 40ns
•Total:40+10+40=
90ns Logic Circuits -Dr. Mohamad Alwan
221
111
Logic Circuits -Dr. Mohamad Alwan 223
Synchronous Counters
112
Synchronous Counters
State Diagram
1
0
2
7
6 3
4
5
113
Excitation tables
Present Next
State state Inputs
Q(t) Q(t+1) D
0 0 0
0 1 1
1 0 0
1 1 1
Present Next
State state Inputs
Q(t) Q(t+1) J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
Qc Qb Qa Qc Qb Qa Jc Kc Jb Kb Ja Ka
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
114
3-bit counter - Continued
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 0 0 1 0 0 x x x x
1 x x x x 1 0 0 1 0
Jc=Qb Qa Kc=Qb Qa
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 0 1 x x
0 x x 1 0
1 0 1 x x
1 x x 1 0
Jb= Qa
Kb= Qa
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 1 X x 1
0 x 1 1 X
1 1 x x 1
1 x 1 1 x
Ja= 1
Ka= 1
115
Logic Circuit
Qa
Qc Jc Qb Jb Qa Ja
C
Qc‘ Kc Qb‘ Kb Qa ‘ Ka
State Sequencer
1
0
116
Sequencer Continued…
• We can now use the JK excitation table to find the correct
values for each flip-flop’s inputs, based on its present and next
states.
Qc Qb Qa Qc Qb Qa Jc Kc Jb Kb Ja Ka
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 1 0 0 1 X X 1 0 X
1 0 0 1 1 1 X 0 1 X 1 X
1 1 1 0 0 0 X 1 X 1 X 1
Sequencer - Continued
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 0 0 x 1 0 x x x x
1 x x x x 1 0 x 1 X
Jc=Qb Kc=Qb
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 0 1 x x
0 x x x 1
1 1 X x x
1 x x 1 X
Jb= Qa+Qc
Kb= 1
117
Sequencer - Continued
Qb Qa
Qb Qa
Qc 00 01 11 10
Qc 00 01 11 10
0 1 X x 0
0 x 1 X X
1 1 x x X
1 x X 1 x
Ja= Qb’
Ka= 1
Qc Jc Qb Jb Qa Ja
C
Qc‘ Kc Qb‘ Kb 1 Qa ‘ Ka
1
118
Unused states
0 1
2
7
4
Unused states
3 4
0 1
2
7
4 3
119
Unused states - continued
5 6
0 1
5 2
6
7
4 3
6 0
0 1
5 2
6
7
4 3
120
State Sequencer with External Control
1
0 3
0
x
x
0 1
2 5
1 4
x x
y Qc Qb Qa Qc Qb Qa Jc Kc Jb Kb Ja Ka
0 0 0 0 0 0 1 0 X 0 X 1 X
X 0 0 1 0 1 0 0 X 1 X X 1
X 0 1 0 0 0 0 0 X X 1 0 X
1 0 0 0 0 1 1 0 X 1 X 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
X 1 0 0 1 0 1 X 0 0 X 1 X
X 1 0 1 0 1 1 X 1 1 X X 0
0 0 1 1 0 0 0 0 X X 1 X 1
121
State Sequencer with external control - Continued
Qb Qa
Qb Qa
Y Qc 00 01 11 10
Y Qc 00 01 11 10
00 0 0 0 0
00 x x x x
01 x x x x
01 0 1 x x
11 x x x x
11 0 1 x x
10 0 0 1 0
10 X X X X
Jc=Y Qb Qa
Kc= Qa
Qb Qa
Qb Qa
Y Qc 00 01 11 10
Y Qc 00 01 11 10
00 0 1 x x
00 x x 1 x
01 0 1 x x
01 x x x 1
11 0 1 x x
11 x x x X
10 1 1 X X
10 X X 1 1
122
State Sequencer with external control - Continued
Qb Qa
Qb Qa
Y Qc 00 01 11 10
Y Qc 00 01 11 10
00 1 x x 0
00 x 1 1 x
01 1 x x x
01 x 0 x x
11 1 x x x
11 x 0 x x
10 1 X 1 0
10 X 1 1 X
Ja= Qb’+ Qa
Ka= Qc’
Logic Circuit
Y
Qc Jc Qb Jb Qa Ja
C
Qc‘ Kc Qb‘ Kb Qa ‘ Ka
1
123