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    The 80386 Microprocessor Updated

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    The 80386 Microprocessor Updated

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    3 views13 pages

    The 80386 Microprocessor Updated

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    The 80386 microprocessor, renowned for its 32-bit architecture, comprises six parts:

    1. Bus Interface Unit (BIU): The BIU acts as the intermediary between the
    80386 and the external environment. It manages internal requests for code
    fetching and data transfers from the Code Pre-fetch Unit and the Execution
    Unit. By prioritizing requests, it generates signals to execute bus cycles,
    facilitating communication with memory and I/O devices by transmitting
    address, data, and control signals.
    2. Code Pre-fetch Unit (CPU): Responsible for sequentially fetching instruction
    byte streams from memory, the CPU utilizes the Bus Control Unit to retrieve
    instruction bytes during idle periods. These prefetched instruction bytes are
    stored in a 16-byte code queue, optimizing the retrieval process.
    3. Instruction Decode Unit (IDU): The IDU translates the instruction stream
    bytes from the Prefetch Queue into microcode. Decoded instructions are then
    stored in a 3-instruction decoded instruction queue (FIFO), awaiting
    processing by the Execution Unit.
    4. Execution Unit (EU): The EU reads instructions from the instruction queue
    and executes them. It comprises three sub-units:
    • Control Unit: Contains microcode and special hardware to expedite
    the execution of multiply and divide instructions, as well as enhance
    effective address calculation.
    • Data Unit: Manages data operations requested by the Control Unit,
    featuring an ALU, eight 32-bit general-purpose registers, and a 64-bit
    barrel shifter for efficient shift and rotate operations.
    • Protection Test Unit: Checks for segmentation violations under
    microcode control.
    5. Memory Management Unit (MMU): The MMU is further divided into two
    units:
    • Segmentation Unit: Translates logical addresses into linear addresses
    at the Execution Unit's request, ensuring adherence to segment
    descriptor length limits and access rights. It provides a four-level
    protection mechanism, safeguarding system code and data from
    application programs.
    • Paging Unit: Translates linear addresses from the Segmentation Unit
    into physical addresses, organizing physical memory into 4 KB-sized
    pages. If the Paging Unit is inactive, physical and linear addresses
    coincide, and it provides physical addresses to the Bus Interface Unit
    for memory and I/O accesses.
    •
    Control Registers: The control registers CR0-CR3 control various features .
    CR0,CR1,and CR3 hold the global machine status which affect all the tasks in the
    system independent of executed task.
    Control Register 0 (CR0): CR0 contains system control flags, which control or
    indicate conditions that apply to the system as a whole , not to an individual task.
    Also known as MSW (Machine Status Word)
    The six control bits are
    1) PG (Paging):It enable or disable paging mechanism (PG=1,Enable)
    2) EM (Emulate co-processor ): This bit is made ‘1’ in the absence of a Math Co-
    processor so that if a co-processor instruction is encountered , then it will be
    executed by an on chip emulator. If this bit is ‘0’ then the co-processor instructions
    will be executed by 80387/80287 whichever is present in the system.
    3)MP (Math co-processor present):This bit is made ‘1’ to indicate that a math
    coprocessor is present.
    4)TS (Task Switched): If TS = 1 ,it means a task switch is performed. Now the TSS of
    the current task has a back- link to previous task.
    5)PE (Protection Enable):This bit is made to ‘1’ to enter protected mode . When PE =
    0, real address mode. It is the only bit of CR0 which is also available in Real mode .
    6) ET (Extension Type):This bit informs the 80386 DX whether the numeric processor is
    an 80287 or 80387. IF ET = 0, It selects the 80287 co-processor and if ET = 1, it selects
    the 80387 co-processor

    OR

    PG (Paging): Turns on or off paging (enabling when PG=1).


    • EM (Emulate co-processor): Helps when there's no Math Co-processor,
    allowing on-chip emulation.
    • MP (Math co-processor present): Indicates the presence of a math co-
    processor.
    • TS (Task Switched): Signals if a task switch has occurred.
    • PE (Protection Enable): Enables protected mode when set to '1'.
    • ET (Extension Type): Determines if the numeric processor is an 80287 or
    80387.
    • Control Register 1 (CR1):
    • Not used in the 80386 DX.
    • Control Register 2 (CR2):
    • Holds the linear address where a page fault (needed page not in
    physical memory) has occurred.
    • Helps the operating system load the required page from secondary
    memory into physical memory.
    • Control Register 3 (CR3):
    • Also called Page Directory Base Register (PDBR).
    • Implements a 2-level page translation mechanism.
    • Stores addresses of various page tables in the page directory.
    • CR3 gives the base address of the page directory, with PDBR having a
    20-bit size.

    Characteristic Real Mode Protected Mode Virtual Mode


    Memory 20-bit address bus, up 32-bit address bus,
    Addressing to 1 MB 32-bit address bus, up to 4 GB up to 4 GB
    Memory Memory protection
    Protection No memory protection Memory protection enabled enabled
    Limited general- Additional general-purpose
    purpose and segment registers (EAX, EBX, etc.) and Similar to Protected
    Registers registers control registers Mode
    Address Segment and offset Flat memory model simplifies Similar to Protected
    Calculation addressing address calculation Mode
    Hardware support for
    No hardware support multitasking and memory Similar to Protected
    Task Isolation for multitasking protection Mode
    Interrupt Supports only one Supports multiple interrupt tables Similar to Protected
    Handling interrupt table and privilege levels (rings) Mode
    Similar to Protected
    Access Control No privilege levels Four privilege levels (Rings 0-3) Mode
    Typically used for Enables modern operating Continues to
    Operating simpler operating systems with multitasking and support modern OS
    System systems memory protection features
    Memory Address Tranlation

    Segment Translation
    A segment selector is loaded into a segment register (cs, ds, etc.) to select one of the regular
    segments.

    Segment register contains a selector that selects a descriptor from the descriptor table
    Segment Descriptor

    • Describes a segment

    • Must be created for every segment

    • Is created by the programmer

    • Determines a base address of the segment

    • Determines a size of the segment

    • Determines a type of the segment


    Descriptor tables
    There are actually three different descriptor tables, GDT , LDT and IDT .

    Exactly one GDT and IDT must be defined for Protected Mode operation.

    1.Global Descriptor Table ( GDT ).

    The GDT is used by all program

    2.Local Descriptor Table ( LDT ).

    An LDT can optionally be defined on a per-task basis

    3.Interrupt Descriptor Table ( IDT ).

    The IDT is a direct replacement to the interrupt vector table used in 8086 systems.

    Note that references to IDT are done through the hardware interrupt mechanism , and not from a
    program via a selector.

    Programmer invisible registers: (Descriptor cache)


    • The cache is used to reduce the number of actual memory references needed to construct
    the physical address.

    • There is one cache register for each of the 6 segment registers, CS, DS, etc. and the LDTR
    (Local Descriptor Table Register) and TR (Task Register) selectors.

    • The base address, limit and access rights of the descriptor are loaded from memory every
    time the corresponding selector changes.

    • The LDTR and TR selectors refer to special system descriptors in the GDT.

    • These registers provide hardware acceleration support for task switching.


    • The base address, limit and access rights of the descriptor are loaded from memory every
    time the corresponding selector changes.

    • The LDTR and TR selectors refer to special system descriptors in the GDT.

    • These registers provide hardware acceleration support for task switching.

    •
    Address translation mechanism Protected Mode
    •
    The page directory can reside at any 4K boundary since the low order 12
    bits of the address are set to zero.
    • The page directory contains 1024 directory entries of 4 bytes each.
    • Each page directory entry addresses a page table that contains up to
    1024 entries.

    Translation Lookaside Buffer (TLB) or Page translation Cache:


    The 80386DX paging mechanism has designed to support demand paged
    virtual memory systems.
    Performance would degrade substantially if the processor was required to
    access two levels of tables (Page directory and page table) for every memory
    access.
    To solve this problem, the 80386DX stores the most recently used page table
    entries in an on-chip cache.
    This cache is called the Translation Lookaside Buffer (TLB).
    •
    Use of TLB:-
    Translation Look-aside Buffer (TLB) simplifies the process. TLB is a page table
    cache, which stores the 32 recently accessed page table entries.
    The paging unit receives a 32-bit linear address from the segmentation unit.
    The upper 20 bits of the linear address has compared with all 32-entries in the
    translation look-aside buffer (TLB) to check if it matches with any of the entries.
    If it matches, the 32-bit physical address has calculated from matching TLB
    entry and placed on the address bus.

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