The 80386 Microprocessor Updated
The 80386 Microprocessor Updated
The 80386 Microprocessor Updated
1. Bus Interface Unit (BIU): The BIU acts as the intermediary between the
80386 and the external environment. It manages internal requests for code
fetching and data transfers from the Code Pre-fetch Unit and the Execution
Unit. By prioritizing requests, it generates signals to execute bus cycles,
facilitating communication with memory and I/O devices by transmitting
address, data, and control signals.
2. Code Pre-fetch Unit (CPU): Responsible for sequentially fetching instruction
byte streams from memory, the CPU utilizes the Bus Control Unit to retrieve
instruction bytes during idle periods. These prefetched instruction bytes are
stored in a 16-byte code queue, optimizing the retrieval process.
3. Instruction Decode Unit (IDU): The IDU translates the instruction stream
bytes from the Prefetch Queue into microcode. Decoded instructions are then
stored in a 3-instruction decoded instruction queue (FIFO), awaiting
processing by the Execution Unit.
4. Execution Unit (EU): The EU reads instructions from the instruction queue
and executes them. It comprises three sub-units:
• Control Unit: Contains microcode and special hardware to expedite
the execution of multiply and divide instructions, as well as enhance
effective address calculation.
• Data Unit: Manages data operations requested by the Control Unit,
featuring an ALU, eight 32-bit general-purpose registers, and a 64-bit
barrel shifter for efficient shift and rotate operations.
• Protection Test Unit: Checks for segmentation violations under
microcode control.
5. Memory Management Unit (MMU): The MMU is further divided into two
units:
• Segmentation Unit: Translates logical addresses into linear addresses
at the Execution Unit's request, ensuring adherence to segment
descriptor length limits and access rights. It provides a four-level
protection mechanism, safeguarding system code and data from
application programs.
• Paging Unit: Translates linear addresses from the Segmentation Unit
into physical addresses, organizing physical memory into 4 KB-sized
pages. If the Paging Unit is inactive, physical and linear addresses
coincide, and it provides physical addresses to the Bus Interface Unit
for memory and I/O accesses.
•
Control Registers: The control registers CR0-CR3 control various features .
CR0,CR1,and CR3 hold the global machine status which affect all the tasks in the
system independent of executed task.
Control Register 0 (CR0): CR0 contains system control flags, which control or
indicate conditions that apply to the system as a whole , not to an individual task.
Also known as MSW (Machine Status Word)
The six control bits are
1) PG (Paging):It enable or disable paging mechanism (PG=1,Enable)
2) EM (Emulate co-processor ): This bit is made ‘1’ in the absence of a Math Co-
processor so that if a co-processor instruction is encountered , then it will be
executed by an on chip emulator. If this bit is ‘0’ then the co-processor instructions
will be executed by 80387/80287 whichever is present in the system.
3)MP (Math co-processor present):This bit is made ‘1’ to indicate that a math
coprocessor is present.
4)TS (Task Switched): If TS = 1 ,it means a task switch is performed. Now the TSS of
the current task has a back- link to previous task.
5)PE (Protection Enable):This bit is made to ‘1’ to enter protected mode . When PE =
0, real address mode. It is the only bit of CR0 which is also available in Real mode .
6) ET (Extension Type):This bit informs the 80386 DX whether the numeric processor is
an 80287 or 80387. IF ET = 0, It selects the 80287 co-processor and if ET = 1, it selects
the 80387 co-processor
OR
Segment Translation
A segment selector is loaded into a segment register (cs, ds, etc.) to select one of the regular
segments.
Segment register contains a selector that selects a descriptor from the descriptor table
Segment Descriptor
• Describes a segment
Exactly one GDT and IDT must be defined for Protected Mode operation.
The IDT is a direct replacement to the interrupt vector table used in 8086 systems.
Note that references to IDT are done through the hardware interrupt mechanism , and not from a
program via a selector.
• There is one cache register for each of the 6 segment registers, CS, DS, etc. and the LDTR
(Local Descriptor Table Register) and TR (Task Register) selectors.
• The base address, limit and access rights of the descriptor are loaded from memory every
time the corresponding selector changes.
• The LDTR and TR selectors refer to special system descriptors in the GDT.
• The LDTR and TR selectors refer to special system descriptors in the GDT.
•
Address translation mechanism Protected Mode
•
The page directory can reside at any 4K boundary since the low order 12
bits of the address are set to zero.
• The page directory contains 1024 directory entries of 4 bytes each.
• Each page directory entry addresses a page table that contains up to
1024 entries.