CH32V201

CH32V203 Datasheet
V2.6
Overview
CH32V series are industrial-grade general-purpose microcontrollers designed based on QingKe 32-bit RISC-
V. The whole series of products into the hardware stack area, fast interrupt entry and other designs, compared
to the standard greatly improved the interrupt response speed. CH32V203 is based on 32-bit RISC-V core
design of industrial-grade enhanced low-power general-purpose microcontrollers, high-performance, in the
product features support 144MHz main frequency zero-wait operation, equipped with V4B core, work and
sleep power consumption significantly reduced year-on-year. CH32V203 series integrated dual USB
interface, support USB Host and USB Device function, with 1 CAN interface (2.0B active), dual OPA, 4
groups of USART, dual I2C, 12-bit ADC, 10-way Touchkey and other rich peripheral resources.
Features
l Core: - Built-in PLL, optional CPU clock up to 144MHz
- QingKe 32-bit RISC-V core with multiple - High-speed external 3~25MHz oscillator
instruction set combinations - Low-speed external 32.768 KHz oscillator
- Fast programmable interrupt controller + - Power on/down reset, programmable voltage
hardware interrupt stack detector
- Branch prediction, conflict handling mechanism l Real-time clock (RTC): 32-bit independent
- Single cycle multiplication, hardware division, RTC timer
hardware FPU
l 1 groups of 8-channel general-purpose DMA
- System main frequency 144MHz
controllers
l Memory:
- 8 channels, support ring buffer
- Available with up to 64KB volatile data storage
- Support TIMx/ADC /USART/I2C/SPI
area SRAM
- Available with 224KB program memory l 2 groups of OPAs and comparators:
CodeFlash (zero-wait application area + non-zero- connected with ADC and TIMx
wait data area)
l 2 groups of 12-bit ADC
- 28KB BootLoader
- Analog input range: VSSA~VDDA
- 128B non-volatile system configuration memory
- 16 external signals + 2 internal signals
- 128B user-defined memory
- On-chip temperature sensor
l Power management and low-power - Dual ADC conversion mode
consumption: l 16-channels Touch-Key detection
- System power supply VDD: 3.3V l Multiple timers
- Independent power supply for GPIO unit VI/O: - 1 16-bit advanced-control timers, with dead zone
3.3V control and emergency brake; can offer PWM
- Low-power mode: Sleep, Stop, Standby complementary output for motor control
- VBAT independently powers RTC and backup - 3 16-bit general-purpose timers, provide input
register capture/output comparison/PWM/pulse
l Clock & Reset counting/incremental encoder input
- Built-in factory-trimmed 8MHz RC oscillator - 1 32-bit general-purpose timer (for
- Built-in 40 KHz RC oscillator CH32V203RBx)
- 2 watchdog timers (independent watchdog and - 1 CAN interfaces (2.0B active)
window watchdog) l Fast GPIO port
- SysTick: 64-bit counter - 37 I/O ports, with 16 external interrupts
l Communication interfaces: l Security features: CRC unit, 96-bit unique
- 4 USART interfaces
ID
- 2 I²C interfaces (support SMBus/PMBus)
- 2 SPI interfaces l Debug mode: 2-wire serial debug interface
- USB2.0 full-speed device interface (full-speed (SDI)
and low-speed)
l Package: LQFP, QFN, TSSOP or QSOP
- USB2.0 full-speed host/device interface
CH32V203 Datasheet http://wch.cn
Chapter 1 Series product description

CH32V series are industrial-grade general-purpose enhanced MCUs based on 32-bit RISC-V instruction set and
architecture. Its products are divided by function resources into categories such as general-purpose, connectivity, and
wireless communication. They extend each other in terms of package types, peripheral resources and quantities, pin
numbers, and device characteristics, but they are compatible with each other in software, functions, and hardware pin
configurations. The product iterations and rapid applications provide freedom and convenience for users in product
development.
For the features of this series of products, please refer to the datasheet.
For the peripheral function description, usage and register configuration, please refer to "CH32FV2_V3RM".
The datasheets and reference manuals can be downloaded on the official website of WCH:http://www.wch.cn/
Information about the RISC-V instruction set architecture can be downloaded from: https://riscv.org/
This manual is for CH32V203 series datasheet. Please refer to "CH32V307DS0" for V303_305_307 series and
"CH32V208DS0" for V208 series.
Table 1-1 Series overview

Small-and-medium capacity High-capacity general-purpose Connectivity Interconnectivity Wireless device
general-purpose device (V203) device (V303) device (V305) device (V307) (V208)
QingKe V4B QingKe V4F QingKe V4C
32K Flash 64K Flash 128K Flash 256K Flash 128K Flash 256K Flash 128K Flash
10K SRAM 20K SRAM 32K SRAM 64K SRAM 32K SRAM 64K SRAM 64K SRAM
2*ADC(TKey)
2*DAC
2*ADC(TKey)
2*ADC(TKey) 4*ADTM ADC(TKey)
2*DAC
2*DAC 4*GPTM ADTM
4*ADTM
2*ADC(TKey) 2*ADC(TKey) 2*ADC(TKey) 4*ADTM 2*BCTM 3*GPTM
4*GPTM
ADTM ADTM 2*DAC 4*GPTM 8*USART/UART GPTM (32)
2*BCTM
2*GPTM 3*GPTM ADTM 2*BCTM 3*SPI(2*I2S) 4*USART/UART
8*USART/UART
2*USART 4*USART 3*GPTM 5*USART/UART 2*I2C 2*SPI
3*SPI(2*I2S)
SPI 2*SPI 3*USART 3*SPI(2*I2S) USB-OTG 2*I2C
2*I2C
I2C 2*I2C 2*SPI 2*I2C USBHS(+PHY) USBD
USBHD
USBD USBD 2*I2C USB-OTG 2*CAN USBHD
CAN
USBHD USBHD USBHD USBHS(+PHY) RTC CAN
RTC
CAN CAN CAN 2*CAN 2*WDG RTC
2*WDG
RTC RTC RTC RTC 4*OPA 2*WDG
4*OPA
2*WDG 2*WDG 2*WDG 2*WDG RNG 2*OPA
RNG
2*OPA 2*OPA 4*OPA 4*OPA SDIO ETH-
SDIO
RNG FSMC 10M(+PHY)
FSMC
SDIO DVP BLE5.3
ETH-1000MAC
10M-PHY
V2.6 1
Note: The number of peripherals or functions of some products in the same category may be limited by the
package, please confirm the product package when selecting.
Abbreviations:
ADTM: Advanced-control Timer RNG: Random Number Generator
GPTM: General-purpose Timer USBD: Universal Serial Bus Full-speed Device
GPTM(32): 32-bit General-purpose Timer USBFS: Universal Serial Bus Full-speed
BCTM: Basic Timer Host/Device
TKey: Touch key USBHS: Universal Serial Bus High-speed
OPA: Operational Amplifier/Comparator Host/Device
Table 1-2 Overview of Cores

Number of
Hardware Interrupt Integer
Feature Instruction Fast Vector table Extended Memory
Stack Nesting Division
Core Set Interrupt mode instruction protection
Level Level Period
Channels
Address or
V4B IMAC 2 2 4 9 Support No
instruction
Address or
V4C IMAC 2 2 4 5 Support Standard
instruction
Address or
V4F IMAFC 3 8 4 5 Support Standard
instruction
Note: For information about the core, please refer to the QingKeV4 microprocessor manual
"QingKeV4_Processor_Manual".
V2.6 2
Chapter 2 Specification
CH32V203 series are 32-bit RISC core MCUs based on the RISC-V instruction set architecture (ISA), with
144MHz operating frequency, and built-in high-speed memory. It has multiple buses working synchronously,
and provides a wealth of peripheral functions and enhanced I/O ports. This series of products has built-in 2 12-
bit ADC modules, multiple timers, multi-channel capacitance touch key detection (TKey) and other functions. It
also contains standard and dedicated communication interfaces: I²C, SPI, USART, CAN controller, USB2.0 full-
speed host/device controller, USB2.0 full-speed device controller, etc.
The rated working voltage of the product is 3.3V, and the working temperature range is -40℃～85℃ in industrial
grade. It supports several power-saving operating modes to meet the product's low-power application
requirements. Various models in the series are different in terms of resource allocation, number of peripherals,
peripheral functions, etc., and can be selected as needed.
2.1 Model comparison

Table 2-1 CH32V low-and-medium-density general-purpose products resource allocation
Part No. CH32V203
Differences F6 F8 G6 G8 K6 K8 C6 C8 RB
Pin count 20 20 28 28 32 32 48 48 64
(1)
Flash (bytes) 32K 64K 32K 64K 32K 64K 32K 64K 128K(2)
SRAM (bytes) 10K 20K 10K 20K 10K 20K 10K 20K 64K
GPIO port count 16 17 24 24 26 26 37 37 51
Advanced-control
1(3) 1(3) 1(3) 1(3) 1 1 1 1 1
(16-bit)
General-purpose
3(3) 3(3) 3(3) 3(3) 3 3 3 3 3
(16-bit)
Timer General-purpose
- 1
(32-bit)
Watchdog 2 (WWDG + IWDG)
SysTick
supported
(64-bit)
RTC supported
ADC/TKey (channel@unit
9@2 9@2 10@2 10@2 10@2 10@2 10@2 10@2 16@1
count)
OPA 1 2 2 2 2 2 2 2 2
USART/UART 1 2 2 2 2 2 2 4 4
Communication interface
SPI 1 1 1 1 1 1 1 2 2
I2C 0 1 1 1 1 1 1 2 2
CAN 1 - 1 1 1 1 1 1 1
USB USBD 1 - 1 1 1 1 1 1 1 1
(FS) USBHD - 1 - - 1 - - 1 1 1
Ethernet - 10M
CPU clock speed Max: 144MHz
V2.6 3
Part No. CH32V203

Differences F6 F8 G6 G8 K6 K8 C6 C8 RB
Rated voltage 3.3V
Operating temperature Industrial-grade: -40℃～85℃
TSSOP20, TSSOP LQFP
Package QFN20 QFN28 QSOP28 LQFP32 LQFP48 QFN48 LQFP64M
QFN20 20
Note: 1. Flash bytes represent zero-wait run area R0WAIT. For the V203 series, non-zero-wait area is (224K-R0WAIT).
2. 128K FLASH+64K SRAM products support user-selected word configuration as one of several
combinations (128K FLASH+64K SRAM), (144K FLASH+48K SRAM), (160K FLASH+32K SRAM).
3. Timer PWM, capture and other functions involving pin signals need to be combined with the actual chip
package pins, some package chips do not lead to such functions cannot be used.
V2.6 4
2.2 System architecture

The microcontroller is based on the RISC-V instruction set architecture (ISA) in which the core, arbitration unit,
DMA module, SRAM storage and other parts are interacted through multiple sets of buses. A general-purpose
DMA controller is integrated in the chip to reduce the burden on the CPU and improve access efficiency. The
application of a multi-level clock management mechanism reduces the operating power consumption of
peripherals. At the same time, it has a data protection mechanism and measures such as automatic clock switching
protection to increase system stability. The following figure is a block diagram of the overall internal structure of
the series of products.
Figure 2-1 System block diagram
@VDD VDD: 2.4V~3.6V

RISC-V (V4B) FLASH VSS
I-code Bus
CTRL
PFIC RV32
SWCLK IMAC @VIO33 VIO: 2.4V~3.6V
SDI D-code Bus VSS
SWDIO MUX Flash
Memory
@VDDA VDDA: VIO
DMA 8Channels VSSA
System Bus
SYSCLK
MUX
SRAM Reset & AHBCLK

MUX & DIV APB1CLK
APB2CLK
FS_DP
FS_DM USBFS
HSI-RC
PLL
HSE OSC_IN
AH B Fmax = 144MHz
OSC_OUT
RCC
LSI-RC
RTC_CLK
OPAx_CHP IWDG_CLK
LSE OSC32_IN
OPAx_CHN
OPAx_OUT
OPA1-2 OSC32_OUT
(x=1,2)
AHB to APB1 @VBAT

Bridge
AHB to APB2 RTC/BKP TAMPER-RTC

Bridge TIM2 4 channels, ETR
TIM3 4 channels, ETR

EXTIT/WKUP
TIM4 4 channels, ETR
APB1: Fmax = 144MHz
PA0 ~ PA15 GPIOA

TIM5 4 channels(CH32V203RBx)
PB0 ~ PB15 GPIOB
USART2 RX, TX, CTS, RTS, CK
PC0 ~ PC15 GPIOC
APB2: Fmax = 144MHz
USART3 RX, TX, CTS, RTS, CK

PD0 ~ PD2 GPIOD
UART4 RX, TX
MOSI,MISO,SCK, NSS SPI1
RX, TX, CTS, RTS, CK USART1 SPI2 MOSI, MISO, SCK , NSS
4 channels
3 complementary Channels TIM1 IWDG I2C1 SCL, SDA, SMBA
ETR, BIKN
WWDG I2C2 SCL, SDA, SMBA
Tkey
AIN0 ~ AIN15
ADC1 bxCAN1 CAN1_TX,CAN1_RX
(VSSA)VREF -
ADC2
(2.4V~VDDA)VREF+
USBD USBDM,USBDP
Temp Sensor
V2.6 5
2.3 Memory map
Figure 2-2 Memory address map
0x5005 0400 Reserved

0x5005 0000
Reserved
0x5004 0000
USBFS
0x5000 0000
Reserved
0x4002 A000
Ethernet (CH203RBx)
0x4002 8000
0x4002 6000
Reserved
0x4002 4000
0x4002 3C00
EXTEND
0x4002 3800
Reserved
0x4002 3400
CRC
0x4002 3000
Reserved
0x4002 2400
Flash Interface
0x4002 2000
Reserved
0x4002 1400
RCC
0x4002 1000
0x4002 0400
DMA
0x4002 0000
0x4001 8400
Reserved
0x4001 8000
0x4001 5400
0x4001 5000
Reserved
0x4001 4C00
0x4001 3C00
USART1
0x4001 3800
Reserved
0x4001 3400
SPI1
0x4001 3000
TIM1
0x4001 2C00
ADC2/TouchKey
0x4001 2800
ADC1/TouchKey
0x4001 2400
0x4001 1C00 Reserved
0x4001 1800
Port D
0x4001 1400
Port C
0x4001 1000
Port B
0x4001 0C00
Port A
0xFFFF FFFFF 0x4001 0800
Reserved EXTI
0x4001 0400
AFIO
0xE010 0000 0x4001 0000
Core Private
Peripherals 0x4000 7800 Reserved
0xE000 0000
0x4000 7400
PWR
0x4000 7000
Reserved BKP
0x4000 6C00
Reserved
0x4000 6800
0xC000 0000 bxCAN1
0x4000 6400
share 512B SRAM
0x4000 6000
0x1FFF FFFF Reserved USBD
Reserved 0x4000 5C00
I2C2
0x1FFF F880 0x4000 5800
Option Bytes 0xA000 0000 I2C1
0x1FFF F800 0x4000 5400
Vendor Bytes Reserved
0x1FFF F700 0x4000 5000
Reserved UART4
Reserved 0x4000 4C00
0x1FFF F000 USART3
0x4000 4800
0x7000 0000 USART2
System FLASH 0x4000 4400
(BOOT_28KB) 0x4000 4000 Reserved
Reserved
0x4000 3C00
0x1FFF 8000 SPI2
0x4000 3800
0x4000 3400
Reserved IWDG
Reserved 0x4000 3000
WWDG
0x4000 2C00
RTC
Peripherals 0x4000 2800
0x4000 0000
Code FLASH Reserved
224KB max
Reserved
Includes 0 wait and non-0 0x2001 0000
waiting areas SRAM (64KBmax)
0x2000 0000
0x0800 0000
Aliased to Flash or 0x4000 1000
system memory FLASH TIM5 (CH203RBx)
depending on 0x4000 0C00
TIM4
BOOT pins 0x4000 0800
0x0000 0000 0x0000 0000 TIM3
0x4000 0400
4G linear address space TIM2
0x4000 0000
V2.6 6
2.4 Clock tree

Four groups of clock sources are introduced into the system: internal high-frequency RC oscillator (HSI), internal
low-frequency RC oscillator (LSI), external high-frequency oscillator (HSE), and external low-frequency
oscillator (LSE). Among them, the low-frequency clock source provides the clock reference for RTC and
independent watchdog. The high-frequency clock source is directly or indirectly multiplied by the PLL and output
as the system clock (SYSCLK). The system clock is then provided by each prescaler to provide the AHB domain,
APB1 domain, APB2 domain peripheral control clock and sampling or output clock. Some modules need to be
directly provided by the PLL clock.
V2.6 7
Figure 2-3 CH32V203 clock tree block diagram
40kHz IWDGCLK
LSI RC to independent watchdog
OSC32_IN 32.768kHz RTCCLK

to RTC
OSC32_OUT LSE OSC
/128
USB prescaler 48MHz

/1,/2,/3 USBCLK
PLLXTPRE PLLSRC perpheral clock enable

OSC_IN 3-25MHz PLLMUL
OSC_OUT HSE OSC SW
/2 to I2S2 interface
*3,*4,… PLLCLK
/2 *16,*18 to I2S3 interface
8MHz
HSI RC HSI SYSCLK
to TRNG
HSE
CSS
MCO[3:0]
AHB prescaler
/1,/2 to Flash prog IF
/1,/2…/512
HSI
MCO
HSE to AHB bus/core/memory/DMA
PLLCLK/2
FCLK core free running clock
/8 to Core System timer
APB1 prescaler PCLK1

HCLK to APB1 peripherals
144MHz max /1,/2…/16
perpheral clock enable
if(APB1 prescaler=1)*1 TIMxCLK

else *2 to TIM2,3,4,5,6,7

/1,/2…/16 to APB2 peripherals
ADC prescaler
ADCCLK
/2,/4,/6,/8 to ADC1,2

else *2 to TIM1,8,9,10
Note: 1. When using the USB function, the CPU frequency must be 48MHz or 96MHz or 144MHz. when the
system wakes up from downtime or standby, the system will automatically switch to HSI as the main frequency.
V2.6 8
Figure 2-4 CH32V203RB clock tree block diagram
40kHz IWDGCLK
LSI RC to independent watchdog
OSC32_IN 32.768kHz RTCCLK

to RTC
OSC32_OUT LSE OSC
/128
USB prescaler 48MHz

/1,/2,/3 USBCLK
PLLXTPRE PLLSRC perpheral clock enable

OSC_IN 32MHz /4 PLLMUL
OSC_OUT HSE OSC SW
/8 to I2S2 interface
*3,*4,… PLLCLK
/2 *16,*18 to I2S3 interface
8MHz
HSI RC HSI SYSCLK
to TRNG
HSE
CSS
MCO[3:0]
AHB prescaler /1,/2 to Flash prog IF
/1,/2…/512
HSI to AHB bus/core/memory/DMA
MCO
HSE FCLK core free running clock
PLLCLK/2
/8 to Core System timer
/1,/2 60MHz
ETH-PHY
ETH clock enable
HCLK
144MHz max
to APB1 peripherals
/1,/2…/16

else *2 to TIM2,3,4,5,6,7
/1,/2 60MHz
perpheral clock enable ETH-PHY
ETH clock enable
/1,/2…/16 to APB2 peripherals
ADC prescaler
ADCCLK
/2,/4,/6,/8 to ADC1,2

else *2 to TIM1,8,9,10
Note: 1. For CH32V203RB, the external crystal or clock (HSE) is 32M. When the external crystal is enabled, no
load capacitor is required as it is built in.
V2.6 9
2.5 Functional description

2.5.1 RISC-V4B processor
RISC-V4B supports the IMAC subset of the RISC-V instruction set. The processor is managed internally in a
modular fashion and contains units such as fast programmable interrupt controller (PFIC), memory protection,
branch prediction mode, and extended instruction support. Externally multiple buses are connected to external
unit modules to enable interaction between external function modules and the core.
The processor can be flexibly applied in different scenarios, such as small-area low-power embedded scenarios,
high-performance application operating system scenarios, etc., due to its minimal instruction set, multiple
working modes, and modular customization extensions.
l Support machine and user privilege mode
l Fast Programmable Interrupt Controller (FPIC)
l Multi-level hardware interrupt stack
l Serial 2-wire debug interface
l Standard memory protection design
l Static or dynamic branch prediction, efficient jump, conflict detection
l Custom extended instructions
2.5.2 On-chip memory and boot mode

Up to 128K bytes of built-in SRAM area, used to store data, data will be lost after power failure. The specific
capacity depends on the corresponding chip model.
Up to 480K bytes of built-in program Flash memory (Code FLASH), used for user application and constant data
storage, including zero-wait program run area and non-zero-wait area. The specific size depends on the
corresponding chip model.
Built-in 28K byte system memory (System FLASH), used for system boot program storage (manufacturer curing
boot loader).
128 bytes are used for system non-volatile configuration word storage, and 128 bytes are used for user selection
word storage.
At startup, one of 3 boot modes can be selected through the boot pins (BOOT0 and BOOT1):
l Boot from program flash
l Boot from system memory
l Boot from internal SRAM
The bootloader is stored in the system memory, and the contents of the program Flash memory storage can be
reprogrammed through the USART1 and USB interface.
2.5.3 Power supply scheme

l VDD = 2.4～3.6V: Power supply for some I/O pins and internal voltage regulator.
l VI/O = 2.4～3.6V: It supplies power to most of the I/O pins and the Ethernet module, which determines the
pin output high voltage amplitude. Normal work during operation, the VIO voltage cannot be higher than
the VDD voltage.
l VDDA = 2.4～3.6V: It supplies power to the analog part of the high-frequency RC oscillator, ADC,
temperature sensor, DAC and PLL. The VDDA voltage must be the same as the VI/O voltage (If VDD is
powered down and VI/O is live, Then VDDA must be live and consistent with VI/O). When using ADC, VDDA
V2.6 10
must not be less than 2.4V.

l VBAT = 1.8～3.6V: When VDD is turned off, (through the internal power switch) independently powers the
RTC, external low-frequency oscillator and backup registers. (Pay attention to VBAT power supply)
2.5.4 Power supply monitor

This product integrates a power-on reset (POR)/power-down reset (PDR) circuit, which is always in working
condition to ensure that the system is in supply. It works when the power exceeds 2.4V; when VDD is lower than
the set threshold (VPOR/PDR), the device is placed in the reset state without using an external reset circuit.
In addition, the system is equipped with a programmable voltage monitor (PVD), which needs to be turned on
by software to compare the voltage of VDD power supply with the set threshold VPVD.
Turn on the corresponding edge interrupt of PVD, and you can receive interrupt notification when VDD drops to
the PVD threshold or rises to the PVD threshold. Refer to Chapter 4 for the values of VPOR/PDR and VPVD.
2.5.5 Voltage regulator

After reset, the regulator is automatically turned on, and there are 3 operation modes according to the application
mode.
l ON mode: normal operation, providing stable core power.
l Low-power mode: When the CPU enters Stop mode, the regulator can be selected to run with low- power
consumption.
l OFF mode: When the CPU enters Standby mode, it automatically switches the regulator to this mode, the
voltage regulator output is in high impedance, and the core power.
The voltage regulator is always ON after reset. It is OFF in Standby mode, and the regulator output is in high
impedance.
2.5.6 Low-power mode

The system supports 3 low-power modes, which can be selected for low-power consumption, short start-up time
and multiple wake-up events to achieve the best balance.
l Sleep mode
In Sleep mode, only the CPU clock is stopped, but all peripheral clocks are powered normally and the peripherals
are in a working state. This mode is the shallowest low-power mode, but it is the fastest mode to wake-up the
system.
Exit condition: any interrupt or wake-up event.
l Stop mode
In this mode, the FLASH enters low-power mode, and the PLL, HSI RC oscillator and HSE crystal oscillator are
turned off. In the case of keeping the contents of SRAM and registers not lost, the Stop mode can achieve the
lowest power consumption.
Exit conditions: any external interrupt/event (EXTI signal), external reset signal on NRST, IWDG reset, among
which EXTI signal includes one of 16 external I/O ports, PVD output, RTC alarm clock, Ethernet wake-up signal
or USB wake-up signal.
l Standby mode
In this mode, the main LDO of the system is turned off, the low-power LDO supplies power to the wake-up
V2.6 11
circuit, all other digital circuits are powered off, and the FLASH is powered off. The system wakes up from
Standby mode will generate a reset, and SBF (PWR_CSR) will be set at the same time. After waking up, check
the SBF status to know the low-power mode before waking up. SBF is cleared by the CSBF (PWR_CR) bit. In
the Standby mode, the contents of 32KB of SRAM can be kept (depending on the planning and configuration
before going to bed), and the contents of the backup registers are kept.
Exit conditions: any external interrupt/event (EXTI signal), external reset signal on NRST, IWDG reset, a rising
edge on the WKUP pin, where EXTI signal includes one of 16 external I/O ports, RTC alarm clock, Ethernet
Wake-up signal, USB.
2.5.7 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit uses a fixed polynomial generator to generate a CRC code
from a 32-bit data word. In many applications, CRC-based technology is used to verify the consistency of data
transmission or storage. Within the scope of the EN/IEC 60335-1 standard, a means of detecting flash errors is
provided. The CRC calculation unit can be used to calculate the signature of the software in real time and compare
it with the signature generated when the software is linked and generated.
2.5.8 Fast programmable interrupt controller (FPIC)

The product has a built-in Fast Programmable Interrupt Controller (FPIC), which supports up to 255 interrupt
vectors, and provides flexible interrupt management functions with minimal interrupt latency. The current
product manages 8 core private interrupts and 88 peripheral interrupt management, and other interrupt sources
are reserved. FPIC registers can be accessed in user and machine privileged modes.
l 88+3 individual maskable interrupts
l A non-maskable interrupt NMI
l Support hardware interrupt stack (HPE) without instruction overhead
l 4-channel vector table free interrupts (VTF)
l Support vector table mode of address or instruction module
l Configurable interrupt nesting depth, up to 8 levels
l Support interrupt tail-chaining
2.5.9 External interrupt/event controller (EXTI)

The external interrupt/event controller contains a total of 19 edge detectors for generating interrupt/event requests.
Each interrupt line can independently configure its trigger event (rising edge or falling edge or both edges), and
can be individually masked; the suspend register maintains all interrupt request states. EXTI can detect that the
pulse width is smaller than the clock period of the internal APB2. Up to 37 general-purpose I/O ports can be
connected to 16 external interrupt lines.
2.5.10 General DMA controller

The system has built-in 2 groups of general-purpose DMA controllers, manages 18 channels in total, and flexibly
handles high-speed data transmission from memory to memory, peripherals to memory, and memory to
peripherals, and supports ring buffer mode. Each channel has a dedicated hardware DMA request logic to support
one or more peripherals' access requests to the memory. The access priority, transfer length, source address and
destination address of the transfer can be configured.
The main peripherals used by DMA include: general/advanced TIMx, ADC, USART, I²C and SPI.
Note: DMA and CPU access the system SRAM after arbitration by the arbiter.
V2.6 12
2.5.11 Clock and Boot

The system clock source HSI is turned on by default. After the clock is not configured or reset, the internal 8MHz
RC oscillator is used as the default CPU clock, and then an external 3～25MHz clock or PLL clock can be
additionally selected. When the clock security mode is turned on, if the HSE is used as the system clock (directly
or indirectly), the system clock will automatically switch to the internal RC oscillator when the external clock is
detected to be invalid, and the HSE and PLL will be automatically turned off at the same time; in low-power
consumption mode, the system will automatically switch to the internal RC oscillator after waking up. If the
clock interrupt is enabled, the software can receive the corresponding interrupt.
Multiple prescalers are used to configure the frequency of AHB. The high-speed APB (APB2) and low-speed
APB (APB1) regions provide peripheral clocks with a maximum frequency of 144MHz. Refer to the clock tree
block diagram in Figure 2-3.
2.5.12 Real time clock (RTC) and backup registers

The RTC and the backup register are in the backup power supply area inside the system. When VDD is valid, it is
powered by VDD, and when VDD is invalid, the internal power is automatically switched to the VBAT pin.
The RTC real-time clock is a set of 32-bit programmable counters, and the time base supports 20-bit prescaler
for measurement in a longer period of time. The clock reference source is a high-speed external clock divided by
128 (HSE/128), external crystal low-frequency oscillator (LSE) or internal low-power RC oscillator (LSI). The
LSE also has a backup power supply area, so when the LSE is selected as the RTC time base, the RTC setting
and time can remain unchanged after the system resets or wakes up from Standby mode.
The backup register contains up to 42 16-bit registers, which can be used to store 84 bytes of user application
data. This data can continue to be maintained after wake-up from Standby, or system Reset or power Reset. When
the intrusion detection function is turned on, once the intrusion detection signal is valid, all contents in the backup
register will be cleared.
2.5.13 Analog-to-digital converter (ADC) and touch key capacitance detection (TKey)
The product is embedded with 2 12-bit analog/digital converters (ADC), sharing up to 16 external channels and
2 internal channels for sampling. The programmable channel sampling time can realize single, continuous,
scanning or discontinuous conversion. And supports dual ADC conversion mode. The analog watchdog function
is provided to allow very precise monitoring of one or more selected channels for monitoring the signal voltage
of the channel. It supports external event-triggered conversion, the trigger source includes the internal signal and
external pin of the on-chip timer; it also supports the use of DMA operations.
ADC internal channel sampling includes 1 channel of built-in temperature sensor sampling and 1 channel of
internal reference power sampling. The temperature sensor generates a voltage that varies linearly with
temperature. The temperature sensor is internally connected to the IN16 input channel, which is used to convert
the output of the sensor to a digital value.
The capacitance touch key detection unit provides up to 16 detection channels, multiplexing the external channels
of the ADC module. The detection result is converted and output by the ADC module, and the state of the touch
key is recognized by the user software.
2.5.14 Timer and watchdog

The timers in the system include advanced timers, general timers, basic timers, watchdog timers, and system time
V2.6 13
base timers. The number of timers included in different products in the series is different, please refer to Table 2-
2 for details.
Table 2-2 Timer comparison

Count
Timer Resolution Time Base DMA Function
Type
PWM complementary output,
Advanced- Up APB2 time single pulse output
control TIM1 16 bits Down domain Supported Input capture
timer Up/down 16-bit divider Output compare
Timer count
TIM2
General- Up APB1 time Input capture
TIM3 16 bits
purpose Down domain Supported Output compare
TIM4
timer Up/down 16-bit divider Timer count
TIM5(1) 32 bits
APB1 time
domain
Not Timing
Window watchdog 7 bits Down 4 types of
supported Reset the system (normal work)
frequency
division
APB1 time
domain Timing
Independent Not
12 bits Down 7 types of Reset the system (normal work +
watchdog supported
frequency low-power work)
division
SYSCLK or Not
 SysTick Timer 64 bits Up/down Timing
SYSCLK/8 supported
Note 1: Applicable to CH32V203RBx.
l Advanced control timer

The advanced control timer is a 16-bit auto-loading up/down counter with a 16-bit programmable prescaler. In
addition to the complete general-purpose timer function, it can be regarded as a three-phase PWM generator
distributed to 6 channels, with a complementary PWM output function with dead zone insertion, allowing the
timer to be updated after a specified number of counter cycles to repeat counting cycle, braking function, etc.
Many functions of the advanced control timer are the same as the general timer, and the internal structure is also
the same. Therefore, the advanced control timer can cooperate with other TIM timers through the timer link
function to provide synchronization or event link functions.
l General-purpose timer
The general timer is a 16-bit or 32-bit auto-loading up/down counter with a programmable 16-bit prescaler and
4 independent channels. Each channel supports input capture, output comparison, and PWM generation and
single pulse mode output. It can also work with advanced control timers through the timer link function to provide
synchronization or event link functions. In Debug mode, the counter can be frozen while the PWM outputs are
disabled, thereby cutting off the switches controlled by these outputs. Any general-purpose timer can be used to
generate PWM output. Each timer has an independent DMA request mechanism. These timers can also process
V2.6 14
signals from incremental encoders, as well as digital outputs from 1 to 3 Hall sensors.
l Independent watchdog
The independent watchdog is a configurable 12-bit down counter that supports 7 frequency division factors. The
clock is provided by an internal independent 40 KHz RC oscillator (LSI); because the LSI is independent of the
main clock, it can run in Stop and Standby modes. IWDG is outside the main program and can work completely
independently. Therefore, it is used to reset the entire system when a problem occurs, or as a free timer to provide
timeout management for the application. It can be configured as software or hardware to start the watchdog
through the option byte. In Debug mode, the counter can be frozen.
l Window Watchdog
The window watchdog is a 7-bit down counter and can be set to free-running. It can be used to reset the entire
system when a problem occurs. It is driven by the main clock and has an early warning interrupt function; in
Debug mode, the counter can be frozen.
l SysTick Timer
This is a 64-bit optional increment or decrement counter that comes with the core controller. It is used to generate
SYSTICK anomalies (exception number: 15). It can be dedicated to the real-time operating system (RTOS) to
provide a "heartbeat" tick for the system, or it can be used as a standard 64-bit counter. It has an automatic reload
function and a programmable clock source.
2.5.15 Communication interface

2.5.15.1 Universal Synchronous/Asynchronous Receiver Transmitter (USART)
The product provides 4 sets of Universal Synchronous/Asynchronous Transceivers. Full duplex asynchronous
communication, synchronous unidirectional communication, and half duplex single line communication are
supported, as well as LIN (Local Interconnect Network), ISO7816 compatible smart card protocol and IrDA SIR
ENDEC transmission codec specification, and modem (CTS/RTS hardware flow control) operation. It also allows
multi-processor communication. It uses a fractional baud rate generator system and supports DMA operation for
continuous communication.
2.5.15.2 Serial Peripheral Interface (SPI)

Up to 2 groups of serial peripherals interface (SPI) provide master or slave operation, dynamic switching. Support
multi-master mode, full-duplex or half-duplex synchronous transmission, support basic SD card and MMC mode.
Programmable clock polarity and phase, data bit width provides 8 or 16-bit selection, hardware CRC
generation/check for reliable communication, and continuous communication support for DMA operation.
2.5.15.3 I2C bus

Up to 2 I²C bus interfaces can work in multi-master mode or Slave mode, perform all I²C Bus specific timing,
protocol, arbitration, etc. It supports both standard and fast speed, and is compatible with SMBus2.0.
The I²C interface provides 7-bit or 10-bit addressing, and supports dual slave addressing in 7-bit Slave mode. It
integrates built-in hardware CRC generator/checker. It also supports DMA operation and supports SMBus bus
version 2.0 / PMBus bus.
2.5.15.4 Controller Area Network (CAN)

The CAN interface is compatible with specifications 2.0A and 2.0B (active), the baud rate is up to 1Mbits/s, and it
V2.6 15
supports time-triggered communication functions. It can receive and send standard frames with 11-bit identifiers,
as well as extended frames with 29-bit identifiers. It has 3 sending mailboxes and 2 3-level deep receiving FIFOs.
With 1 set of CAN controller products, there are only 14 configurable filters, and share a dedicated 512-byte
SRAM memory with the USBD module for data transmission and reception. When USBD and CAN are used
at the same time, in order to prevent access to SRAM conflicts, USBD can only use the lower 384 bytes.
2.5.15.5 Universal Serial Bus device (USBD)

The product is embedded with a USB2.0 full-speed controller, which complies with the USB2.0 full-speed
standard. USBD provides 16 configurable USB device endpoints, supports low-speed devices and full-speed
devices, supports control/batch/synchronization/interrupt transmission, double buffer mechanism, USB
suspend/resume operations, and has standby/wake-up functions. The USB dedicated 48MHz clock is directly
generated by the internal main PLL frequency division.
2.5.15.6 Universal Serial Bus USB2.0 full-speed Host/Device controller (USBFS)

The USB2.0 full-speed host controller and device controller (USBFS) follow the USB2.0 full-speed standard. It
provides 16 configurable USB device endpoints and a set of host endpoints. Support
control/batch/synchronization/interrupt transmission, double buffer mechanism, USB bus suspend/resume
operation, and provide standby/wake-up functions. The 48MHz clock dedicated to the USBFS module is directly
generated by the internal main PLL frequency division (the PLL must be 144MHz or 96MHz or 48MHz).
2.5.16 General-purpose input and output (GPIO)

The system provides 4 groups of GPIO ports with a total of 37 GPIO pins. Each pin can be configured by software
as output (push-pull or open-drain), input (with or without pull-up or pull-down) or multiplexed peripheral function
port. Most GPIO pins are shared with digital or analog multiplexed peripherals. Except for ports with analog input
functions, all GPIO pins have high current passing capabilities. A locking mechanism is provided to freeze the IO
configuration to avoid accidental writing to the I/O register.
Most of the I/O pins in the system are provided by VI/O. Changing the VI/O power supply will change the high
value of the I/O pin output level to adapt to the external communication interface level. Please refer to the
pin description for specific pins.
2.5.17 Operational amplifier/comparator (OPA)

The product has built-in 2 groups of operational amplifiers/comparators, and the internal selection is linked to
the ADC and TIMx peripherals. Its input and output can be selected by changing the configuration to select
multiple channels. It supports to amplify the external analog small signal and send it to the ADC to realize the
small signal ADC conversion. It can also complete the signal comparator function. The comparison result is
output by GPIO or directly connected to the input channel of TIMx.
2.5.18 Serial debug interface (SDI)

The core comes with a 2-wire SDI, including SWDIO and SWCLK pins. After the system is powered on or reset,
the debug interface pin function is enabled by default.
V2.6 16
Chapter 3 Pinouts and pin definition
3.1 Small-and-medium capacity general-purpose device V203

CH32V203RBT6
64
63
CH32V203CxT6
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
PB3
PC11
VDD_VIO_3
PB8
PB5
VSS_3
PB9
PB4
PD2
PC12
BOOT0
PC10
PB7/USB2DP
PB6/USB2DM
PA15
PA14/SWCLK
PB3
VDD_VIO_3
PB8
PB5
VSS_3
PB9
PB4
BOOT0
PB7/USB2DP
PB6/USB2DM
PA15
PA14/SWCLK
1 48
VBAT NC
2 47 1 36
PC13/TAMPER-RTC NC VBAT VDD_2
3 46
PC14/OSC32IN PA13/SWDIO 2 35
4
PC15/OSC32OUT PA12/USB1DP
45 PC13/TAMPER_RTC VSS_2
5 44 3 34
OSC_IN PA11/USB1DM PC14/OSC32IN PA13/SWDIO
6 43 4 33
OSC_OUT PA10 PC15/OSC32OUT PA12/USB1DP
7 42 5 32
NRST @VDD&VIO power PA9 OSC_IN/PD0 PA11/USB1DM
8 41 6 @VDD&VIO power 31
PC0/ADC10 PA8 OSC_OUT/PD1 PA10
9
PC1/ADC11 PC9/TXN
40 7 30
10 @VDD&VBAT power 39 NRST PA9
PC2/ADC12 PC8/TXP 8 @VDD&VBAT power 29
11 38 VSSA PA8
PC3/ADC13 PC7/RXN 9 28
12 37 VDDA PB15
VSSA PC6/RXP 10 27
13 36 PA0/WKUP/ADC0 PB14
14
VDDA PB15
35
11 26
PA0/WKUP/ADC0 PB14 PA1/ADC1 PB13
15 34 12 25
PA1/ADC1 PB13 PA2/ADC2 PB12
16 33
PA2/ADC2 PB12
VDD_VIO_1
PB2/BOOT1
PB0/ADC8
PB1/ADC9
PA3/ADC3
PA4/ADC4
PA5/ADC5
PA6/ADC6
PA7/ADC7
VDD_VIO_4
VDD_VIO_1
PB2/BOOT1
PC4/ADC14
PC5/ADC15
PB0/ADC8
PB1/ADC9
PA3/ADC3
PA4/ADC4
PA5/ADC5
PA6/ADC6
PA7/ADC7
VSS_1
PB10
PB11
VSS_4
VSS_1
PB10
PB11
21
13
23
15
18
14
16
17
19
20
22
24
21
31
23
18
25
28
17
19
20
22
24
26
27
29
30
32
CH32V203CxU6 CH32V203KxT6
48
47
46
45
44
43
42
41
40
39
38
37
PB3
VDD_VIO_3
PB8
PB5
VSS_3
PB9
PB4
BOOT0
PB7/USB2DP
PB6/USB2DM
PA15
PA14/SWCLK
32
31
30
29
28
27
26
25
0
VSS PB3
PB5
PB7
PB6
PB4
VSS
PB8/BOOT0
PA15
1 36 1
VBAT VDD_2 VDD
2 35 2 24
PC13/TAMPER_RTC VSS_2 OSC_IN/PD0 PA14/SWCLK
3 34 3 23
PC14/OSC32IN PA13/SWDIO OSC_OUT/PD1 PA13/SWDIO
4 33 4 22
PC15/OSC32OUT PA12/USB1DP NRST PA12/USB1DP
5 32 5 BOOT1=GND 21
OSC_IN/PD0 PA11/USB1DM VDDA PA11/USB1DM
6 @VDD&VIO power 31 6 20
OSC_OUT/PD1 PA10 PA0/WKUP/ADC0 PA10
7 30 7 19
NRST PA9 PA1/ADC1 PA9
8 @VDD&VBAT power 29
VSSA PA8 8 18
9 28 PA2/ADC2 PA8
VDDA PB15 17
10 27 VDD
PA0/WKUP/ADC0 PB14
11 26
PA1/ADC1 PB13
PB0/ADC8
PB1/ADC9
PA3/ADC3
PA4/ADC4
PA5/ADC5
PA6/ADC6
PA7/ADC7
12 25
PA2/ADC2 PB12
VSS
VDD_VIO_1
PB2/BOOT1
PB0/ADC8
PB1/ADC9
PA3/ADC3
PA4/ADC4
PA5/ADC5
PA6/ADC6
PA7/ADC7
11
13
15
9
10
12
14
16
VSS_1
PB10
PB11
21
13
23
15
18
14
16
17
19
20
22
24
V2.6 17
CH32V203G8R6 CH32V203G6U6
28
27
26
25
24
23
22
1 28
PB3
PB5
PB7
PB6
PB4
PA15
PA14/SWC/PB5/TIM3_CH2 PA13/SWD/PA12/U1DP/CAN_TX/TIM1_ETR
PA14/SWCLK
2 27
PB6/U2DM/SCL/TIM4_CH1 PA11/U1DM/CAN_RX/TIM1_CH4 0
3 26 VSS
PB7/U2DP/SDA/TIM4_CH2 PA10/TIM1_CH3
4 25
BOOT0 PA9/TIM1_CH2
5 24 1 21
PB8/TIM4_CH3 PA8/TIM1_CH1 BOOT0/PB8 PA13/SWDIO
6 23 2 20
VDD PB15/OP1P0/TIM1_CH3N OSC_IN/PD0 PA12/USB1DP
7 22 3 19
VSS PB14/OP2P0/TIM1_CH2N 4
OSC_OUT/PD1 PA10/PA11/USB1DM
18
8 21 NRST PA9
NRST PB13/TIM1_CH1N 5 BOOT1=GND 17
9 20 VDDA VDD
PA0/WKUP/ADC0 PB1/ADC9/OP1O1/PB12/TIM1_BKIN 6 16
10 19 PA0/WKUP/ADC0 VSS
PA1/ADC1 PB11/OP1N0 7 15
11 18 PA1/ADC1 PB1/ADC9
PA2/ADC2/OP2O0 PB10/OP2N0
12 17
PB0/ADC8
PA3/ADC3/OP1O0 PA7/ADC7/OP2P1
PA2/ADC2
PA3/ADC3
PA4/ADC4
PA5/ADC5
PA6/ADC6
PA7/ADC7
13 16
PA6/ADC6/OP1N1 PA5/ADC5/OP2N1
14 15
PB0/ADC8/OP1P1 PA4/ADC4/OP2O1
BOOT1=GND
11
13
9
10
12
14
CH32V203F8P6 CH32V203F6P6
BOOT0=GND BOOT1=GND
1 20 1 20
PB6/UDM/PA13/SWDIO PA10/TIM1_CH3 BOOT0/PB8 PA14/SWCLK
2 19 2 19
PB7/UDP/PA14/SWCLK PA9/TIM1_CH2 OSC_IN/PD0 PA13/SWDIO
3 18 3 18
VSS PA8/TIM1_CH1 OSC_OUT/PD1 PA12/USB1DP
4 17 4 17
VDD PB15/TIM1_CH3N NRST PA11/USB1DM
5 16 5 16
NRST PB14/TIM1_CH2N VDDA VDD
6 15 6 15
PA0/WKUP/ADC0 PB13/TIM1_CH1N PA0/WKUP/ADC0 VSS
7 14 7 14
PA1/ADC1 PB0/ADC8/OP1P1 PA1/ADC1 PB1/ADC9
8 13 8 13
PA2/ADC2/OP2O0 PA7/ADC7/OP2P1 PA2/ADC2 PA7/ADC7
9 12 9 12
PA3/ADC3/OP1O0 PA5/ADC5/OP2N1 PA3/ADC3 PA6/ADC6
10 11 10 11
PA6/ADC6/OP1N1 PA4/ADC4/OP2O1 PA4/ADC4 PA5/ADC5
(TIM1_BKIN) PB12= PB1 (OP1O1)
CH32V203F8U6
20
19
18
17
16
VDD
PA10/CH3
PA6/ADC6/OP1N1/BKIN
PA13/SWD/PA12/UDP
PA14/SWC/PA11/UDM
0
GND
1 15
PA0/WKUP/ADC0 PA9/CH2
2 14
PA1/ADC1 PA8/CH1
3 13
PA2/ADC2/OP2O0 BOOT0=GND PB15/OP1P0
4 12
PA3/ADC3/OP1O0 PB14/OP2P0
5 11
PA4/ADC4/OP2O1 PB11/OP1N0
PB1/ADC9/OP1O1/CH3N
PB0/ADC8/OP1P1/CH2N
PA7/ADC7/OP2P1/CH1N
PA5/ADC5/OP2N1
PB10/OP2N0
8
6
7
9
10
V2.6 18
3.2 Pin description
Table 3-1 CH32V203xx pin definitions

Note: The pin function in the table below refer to all functions and do not involve specific model(s). There are
differences in peripheral resources between different models. Please confirm whether this function is available
according to the particular model's resource table before viewing this table.
Table 3-1-1 QFN20/LQFP32/LQFP48/QFN48 pin definitions

Pin No. Main
Pin type I/O function Default alternate Remapping
LQFP32
LQFP48
QFN20
QFN48
Pin name (1)

structure (after function function
reset)
- - 0 VSS P - VSS
- - 1 VBAT P - VBAT
PC13-
- - 2 TAMPER- I/O - PC13(3) TAMPER-RTC
RTC(2)
PC14-
- - 3 I/O/A - PC14(3) OSC32_IN
OSC32_IN(2)
PC15-
- - 4 OSC32_OUT I/O/A - PC15(3) OSC32_OUT
(2)
- 2 5 OSC_IN I/A - OSC_IN PD0(4)

OSC_OU
- 3 6 OSC_OUT O/A - PD1(4)
T
- 4 7 NRST I - NRST
- - 8 VSSA P - VSSA
- 5 9 VDDA P - VDDA
WKUP
USART2_CTS
TIM2_CH1_ETR_
1 6 10 PA0-WKUP I/O/A - PA0 ADC_IN0
2
TIM2_CH1
TIM2_ETR
USART2_RTS
2 7 11 PA1 I/O/A - PA1 ADC_IN1 TIM2_CH2_2
TIM2_CH2
USART2_TX
ADC_IN2
3 8 12 PA2 I/O/A - PA2 TIM2_CH3_1
TIM2_CH3
OPA2_OUT0
USART2_RX
ADC_IN3
4 9 13 PA3 I/O/A - PA3 TIM2_CH4_1
TIM2_CH4
OPA1_OUT0
V2.6 19
SPI1_NSS
USART2_CK
5 10 14 PA4 I/O/A - PA4
ADC_IN4
OPA2_OUT1
SPI1_SCK
6 11 15 PA5 I/O/A - PA5 ADC_IN5 USART4_TX_1
OPA2_CH1N
SPI1_MISO
ADC_IN6 TIM1_BKIN_1
20 12 16 PA6 I/O/A - PA6
TIM3_CH1 USART4_CK_1
OPA1_CH1N
SPI1_MOSI
ADC_IN7 TIM1_CH1N_1
7 13 17 PA7 I/O/A - PA7
TIM3_CH2 USART4_CTS_1
OPA2_CH1P
ADC_IN8
TIM3_CH3 TIM1_CH2N_1
8 14 18 PB0 I/O/A - PB0
OPA1_CH1P TIM3_CH3_2
USART4_TX
ADC_IN9
TIM3_CH4 TIM1_CH3N_1
9 15 19 PB1 I/O/A - PB1
OPA1_OUT1 TIM3_CH4_2
USART4_RX
PB2
- - 20 PB2(5) I/O FT USART4_CK
BOOT1(5)
I2C2_SCL
TIM2_CH3_2
10 - 21 PB10 I/O/A FT PB10 USART3_TX
TIM2_CH3_3
OPA2_CH0N
I2C2_SDA
TIM2_CH4_2
11 - 22 PB11 I/O/A FT PB11 USART3_RX
TIM2_CH4_3
OPA1_CH0N
- - 23 VSS_1 P - VSS_1
- 16 VSS P - VSS
- - 24 VDD_I/O_1 P - VDD_I/O_1
- 17 VDD_ P - VDD_
SPI2_NSS
I2C2_SMBA
- - 25 PB12 I/O/A FT PB12
USART3_CK
TIM1_BKIN
SPI2_SCK
- - 26 PB13 I/O/A FT PB13 USART3_CTS
TIM1_CH1N
V2.6 20
SPI2_MISO
TIM1_CH2N
12 - 27 PB14 I/O/A FT PB14
USART3_RTS
OPA2_CH0P
SPI2_MOSI
13 - 28 PB15 I/O/A FT PB15 TIM1_CH3N
OPA1_CH0P
USART1_CK
USART1_CK_1
14 18 29 PA8 I/O FT PA8 TIM1_CH1
TIM1_CH1_1
MCO
USART1_TX
15 19 30 PA9 I/O FT PA9 TIM1_CH2_1
TIM1_CH2
USART1_RX
18 20 31 PA10 I/O FT PA10 TIM1_CH3_1
TIM1_CH3
USART1_CTS
USBDM USART1_CTS_1
17 21 32 PA11 I/O/A FT PA11
CAN1_RX TIM1_CH4_1
TIM1_CH4
USART1_RTS
USBDP USART1_RTS_1
22 33 PA12 I/O/A FT PA12
16 CAN1_TX TIM1_ETR_1
TIM1_ETR
23 34 PA13 I/O FT SWDIO PA13
- - 35 VSS_2 P - VSS_2
- - 36 VDD_2 P - VDD_2
17 24 37 PA14 I/O FT SWCLK PA14
TIM2_CH1_ETR_
1
TIM2_CH1_ETR_
- 25 38 PA15 I/O FT PA15
3
SPI1_NSS
USART4_RTS_1
TIM2_CH2_1
- 26 39 PB3 I/O FT PB3 USART4_CTS TIM2_CH2_3
SPI1_SCK
TIM3_CH1_2
- 27 40 PB4 I/O FT PB4 USART4_RTS
SPI1_MISO
TIM3_CH2_2
- 28 41 PB5 I/O FT PB5 I2C1_SMBA SPI1_MOSI
USART4_RX_1
I2C1_SCL
- 29 42 PB6 I/O FT PB6 TIM4_CH1 USART1_TX_1
USBFS_DM
V2.6 21
I2C1_SDA
- 30 43 PB7 I/O FT PB7 TIM4_CH2 USART1_RX_1
USBFS_DP
- 44 BOOT0 I - BOOT0
31 I2C1_SCL
- 45 PB8 I/O/A FT PB8 TIM4_CH3
CAN1_RX
I2C1_SDA
- - 46 PB9 I/O/A FT PB9 TIM4_CH4
CAN1_TX
- - 47 VSS_3 P - VSS_3
- 32 - VSS P - VSS
- - 48 VDD_IO_3 P - VDD_IO_3
19 1 - VDD P - VDD
Table 3-1-2 TSSOP20(F8)/QSOP28(G8) pin definitions

Pin No.
(F8) (G8) I/O Main
(1)
Default alternate
Pin name Pin type structur function Remapping function
TSSOP20
QSOP28
function
e (after reset)
5 8 NRST I - NRST
WKUP
USART2_CTS
6 9 PA0-WKUP I/O/A - PA0 ADC_IN0 TIM2_CH1_ETR_2
TIM2_CH1
TIM2_ETR
USART2_RTS
7 10 PA1 I/O/A - PA1 ADC_IN1 TIM2_CH2_2
TIM2_CH2
USART2_TX
ADC_IN2
8 11 PA2 I/O/A - PA2 TIM2_CH3_1
TIM2_CH3
OPA2_OUT0
USART2_RX
ADC_IN3
9 12 PA3 I/O/A - PA3 TIM2_CH4_1
TIM2_CH4
OPA1_OUT0
SPI1_NSS
USART2_CK
11 15 PA4 I/O/A - PA4
ADC_IN4
OPA2_OUT1
SPI1_SCK
12 16 PA5 I/O/A - PA5 ADC_IN5
OPA2_CH1N
V2.6 22
Pin No.
(F8) (G8) I/O Main
(1)
Default alternate
TSSOP20
QSOP28
function
e (after reset)
SPI1_MISO
ADC_IN6
10 13 PA6 I/O/A - PA6 TIM1_BKIN_1
TIM3_CH1
OPA1_CH1N
SPI1_MOSI
ADC_IN7
13 17 PA7 I/O/A - PA7 TIM1_CH1N_1
TIM3_CH2
OPA2_CH1P
ADC_IN8
TIM1_CH2N_1
14 14 PB0 I/O/A - PB0 TIM3_CH3
TIM3_CH3_2
OPA1_CH1P
ADC_IN9
TIM1_CH3N_1
- 20 PB1 I/O/A - PB1 TIM3_CH4
TIM3_CH4_2
OPA1_OUT1
TIM2_CH3_2
- 18 PB10 I/O/A FT PB10 OPA2_CH0N
TIM2_CH3_3
TIM2_CH4_2
- 19 PB11 I/O/A FT PB11 OPA1_CH0N
TIM2_CH4_3
- 20 PB12 I/O/A FT PB12 TIM1_BKIN
15 21 PB13 I/O/A FT PB13 TIM1_CH1N
TIM1_CH2N
16 22 PB14 I/O/A FT PB14
OPA2_CH0P
TIM1_CH3N
17 23 PB15 I/O/A FT PB15
OPA1_CH0P
USART1_CK
USART1_CK_1
18 24 PA8 I/O FT PA8 TIM1_CH1
TIM1_CH1_1
MCO
USART1_TX
19 25 PA9 I/O FT PA9 TIM1_CH2_1
TIM1_CH2
USART1_RX
20 26 PA10 I/O FT PA10 TIM1_CH3_1
TIM1_CH3
USART1_CTS
USBDM USART1_CTS_1
- 27 PA11 I/O/A FT PA11
CAN1_RX TIM1_CH4_1
TIM1_CH4
USART1_RTS
USBDP USART1_RTS_1
- 28 PA12 I/O/A FT PA12
CAN1_TX TIM1_ETR_1
TIM1_ETR
V2.6 23
Pin No.
(F8) (G8) I/O Main
(1)
Default alternate
TSSOP20
QSOP28
function
e (after reset)

3 7 VSS P - VSS
4 6 VDD P - VDD
2 1 PA14 I/O FT SWCLK PA14
I2C1_SCL
1 2 PB6 I/O FT PB6 TIM4_CH1 USART1_TX_1
USBHD_DM
I2C1_SDA
2 3 PB7 I/O FT PB7 TIM4_CH2 USART1_RX_1
USBHD_DP
- 4 BOOT0 I - BOOT0
I2C1_SCL
- 5 PB8 I/O/A FT PB8 TIM4_CH3
CAN1_RX
Table 3-1-3 TSSOP20(F6)/QFN28(G6) pin definitions

Pin No.
(F6) (G6) Main
(1)
I/O Default alternate
Pin name Pin type function Remapping function
TSSOP20
QFN28
structure function
(after reset)
- 0 VSS P - VSS
2 2 OSC_IN I/A - OSC_IN PD0(4)
3 3 OSC_OUT O/A - OSC_OUT PD1(4)
4 4 NRST I - NRST
5 5 VDDA P - VDDA
WKUP
USART2_CTS
6 6 PA0-WKUP I/O/A - PA0 ADC_IN0 TIM2_CH1_ETR_2
TIM2_CH1
TIM2_ETR
USART2_RTS
7 7 PA1 I/O/A - PA1 ADC_IN1 TIM2_CH2_2
TIM2_CH2
USART2_TX
ADC_IN2
8 8 PA2 I/O/A - PA2 TIM2_CH3_1
TIM2_CH3
OPA2_OUT0
9 9 PA3 I/O/A - PA3 USART2_RX TIM2_CH4_1
V2.6 24
ADC_IN3
TIM2_CH4
OPA1_OUT0
SPI1_NSS
USART2_CK
10 10 PA4 I/O/A - PA4
ADC_IN4
OPA2_OUT1
SPI1_SCK
11 11 PA5 I/O/A - PA5 ADC_IN5
OPA2_CH1N
SPI1_MISO
ADC_IN6
12 12 PA6 I/O/A - PA6 TIM1_BKIN_1
TIM3_CH1
OPA1_CH1N
SPI1_MOSI
ADC_IN7
13 13 PA7 I/O/A - PA7 TIM1_CH1N_1
TIM3_CH2
OPA2_CH1P
ADC_IN8
TIM1_CH2N_1
- 14 PB0 I/O/A - PB0 TIM3_CH3
TIM3_CH3_2
OPA1_CH1P
ADC_IN9
TIM1_CH3N_1
14 15 PB1 I/O/A - PB1 TIM3_CH4
TIM3_CH4_2
OPA1_OUT1
15 16 VSS P VSS
16 17 VDD P VDD
USART1_TX
- 18 PA9 I/O FT PA9 TIM1_CH2_1
TIM1_CH2
USART1_RX
- 19 PA10 I/O FT PA10 TIM1_CH3_1
TIM1_CH3
USART1_CTS
USBDM USART1_CTS_1
17 19 PA11 I/O/A FT PA11
CAN1_RX TIM1_CH4_1
TIM1_CH4
USART1_RTS
USBDP USART1_RTS_1
18 20 PA12 I/O/A FT PA12
CAN1_TX TIM1_ETR_1
TIM1_ETR
20 22 PA14 I/O FT SWCLK PA14
TIM2_CH1_ETR_1
- 23 PA15 I/O FT PA15 TIM2_CH1_ETR_3
SPI1_NSS
- 24 PB3 I/O FT PB3 TIM2_CH2_1
V2.6 25
TIM2_CH2_3
SPI1_SCK
TIM3_CH1_2
- 25 PB4 I/O FT PB4
SPI1_MISO
TIM3_CH2_2
- 26 PB5 I/O FT PB5 I2C1_SMBA
SPI1_MOSI
- 27 PB6 I/O FT PB6 I2C1_SCL USART1_TX_1
- 28 PB7 I/O FT PB7 I2C1_SDA USART1_RX_1
BOOT0 I - BOOT0
1(6) 1(6) I2C1_SCL
PB8 I/O/A FT PB8
CAN1_RX
Table 3-1-4 LQFP64M pin definitions

Pin No. I/O Main function Default alternate
Pin name Pin type (1) Remapping function
LQFP64M structure (after reset) function
1 VBAT P - VBAT
PC13-
2 I/O - PC13(3) TAMPER-RTC
TAMPER-RTC(2)
PC14-
3 I/O/A - PC14(3) OSC32_IN
OSC32_IN(2)
PC15-
4 I/O/A - PC15(3) OSC32_OUT
OSC32_OUT(2)
5 OSC_IN I/A - OSC_IN
6 OSC_OUT O/A - OSC_OUT
7 NRST I - NRST
8 PC0 I/O/A - PC0 ADC_IN10
12 VSSA P - VSSA
13 VDDA P - VDDA
WKUP
USART2_CTS
ADC_IN0
14 PA0-WKUP I/O/A - PA0 TIM2_CH1_ETR_2
TIM2_CH1
TIM2_ETR
TIM5_CH1
USART2_RTS
ADC_IN1
15 PA1 I/O/A - PA1 TIM2_CH2_2
TIM2_CH2
TIM5_CH2
USART2_TX
16 PA2 I/O/A - PA2 TIM2_CH3_1
ADC_IN2
V2.6 26

TIM2_CH3
OPA2_OUT0
TIM5_CH3
USART2_RX
ADC_IN3
17 PA3 I/O/A - PA3 TIM2_CH4 TIM2_CH4_1
OPA1_OUT0
TIM5_CH4
18 VSS_4 P - VSS_4
19 VDD_IO_4 P - VDD_IO_4
SPI1_NSS
USART2_CK
20 PA4 I/O/A - PA4
ADC_IN4
OPA2_OUT1
SPI1_SCK
USART1_CTS_2
21 PA5 I/O/A - PA5 ADC_IN5
USART1_CK_3
OPA2_CH1N
SPI1_MISO
ADC_IN6 TIM1_BKIN_1
22 PA6 I/O/A - PA6
TIM3_CH1 USART1_TX_3
OPA1_CH1N
SPI1_MOSI
ADC_IN7 TIM1_CH1N_1
23 PA7 I/O/A - PA7
TIM3_CH2 USART1_RX_3
OPA2_CH1P
24 PC4 I/O/A PC4 ADC_IN14 USART1_CTS_3
25 PC5 I/O/A PC5 ADC_IN15 USART1_RTS_3
ADC_IN8 TIM1_CH2N_1
26 PB0 I/O/A - PB0 TIM3_CH3 TIM3_CH3_2
OPA1_CH1P UART4_TX_1
ADC_IN9 TIM1_CH3N_1
27 PB1 I/O/A - PB1 TIM3_CH4 TIM3_CH4_2
OPA1_OUT1 UART4_RX_1
PB2
28 PB2(5) I/O FT
BOOT1(5)
I2C2_SCL
TIM2_CH3_2
29 PB10 I/O/A FT PB10 USART3_TX
TIM2_CH3_3
OPA2_CH0N
I2C2_SDA
TIM2_CH4_2
30 PB11 I/O/A FT PB11 USART3_RX
TIM2_CH4_3
OPA1_CH0N
31 VSS_1 P VSS_1
V2.6 27

32 VDD_I/O_1 P VDD_I/O_1
SPI2_NSS
I2C2_SMBA
33 PB12 I/O/A FT PB12
USART3_CK
TIM1_BKIN
SPI2_SCK
34 PB13 I/O/A FT PB13 USART3_CTS USART3_CTS_1
TIM1_CH1N
SPI2_MISO
TIM1_CH2N
35 PB14 I/O/A FT PB14 USART3_RTS_1
USART3_RTS
OPA2_CH0P
SPI2_MOSI
36 PB15 I/O/A FT PB15 TIM1_CH3N USART1_TX_2
OPA1_CH0P
37 PC6 I/O/A FT PC6 ETH_RXP TIM3_CH1_3
38 PC7 I/O/A FT PC7 ETH_RXN TIM3_CH2_3
39 PC8 I/O/A FT PC8 ETH_TXP TIM3_CH3_3
40 PC9 I/O/A FT PC9 ETH_TXN TIM3_CH4_3
USART1_CK USART1_CK_1
41 PA8 I/O FT PA8 TIM1_CH1 USART1_RX_2
MCO TIM1_CH1_1
USART1_TX USART1_RTS_2
42 PA9 I/O FT PA9
TIM1_CH2 TIM1_CH2_1
USART1_RX USART1_CK_2
43 PA10 I/O FT PA10
TIM1_CH3 TIM1_CH3_1
USART1_CTS
USBDM USART1_CTS_1
44 PA11 I/O/A FT PA11
CAN1_RX TIM1_CH4_1
TIM1_CH4
USART1_RTS
USBDP USART1_RTS_1
45 PA12 I/O/A FT PA12
CAN1_TX TIM1_ETR_1
TIM1_ETR
46 PA13 I/O FT SWDIO PA13
- VSS_2 P - VSS_2
- VDD_2 P - VDD_2
47 NC NC
48 NC NC
49 PA14 I/O FT SWCLK PA14
TIM2_CH1_ETR_1
50 PA15 I/O FT PA15
TIM2_CH1_ETR_3
V2.6 28

SPI1_NSS
51 PC10 I/O FT PC10 UART4_TX USART3_TX_1

52 PC11 I/O FT PC11 UART4_RX USART3_RX_1
53 PC12 I/O FT PC12 USART3_CK_1
TIM3_ETR_2
54 PD2 I/O FT PD2 TIM3_ETR
TIM3_ETR_3
TIM2_CH2_1
55 PB3 I/O FT PB3 TIM2_CH2_3
SPI1_SCK
TIM3_CH1_2
56 PB4 I/O FT PB4
SPI1_MISO
TIM3_CH2_2
57 PB5 I/O FT PB5 I2C1_SMBA
SPI1_MOSI
I2C1_SCL
58 PB6 I/O FT PB6 TIM4_CH1 USART1_TX_1
USBHD_DM
I2C1_SDA
59 PB7 I/O FT PB7 TIM4_CH2 USART1_RX_1
USBHD_DP
60 BOOT0 I - BOOT0
I2C1_SCL
61 PB8 I/O/A FT PB8 TIM4_CH3
CAN1_RX
I2C1_SDA
68 PB9 I/O/A FT PB9 TIM4_CH4
CAN1_TX
63 VSS_3 P - VSS_3
64 VDD_IO_3 P - VDD_I/O_3
Note 1: Abbreviations in the table

I = TTL/CMOS Schmitt input;
O = CMOS tri-state output;
A = analog signal input or output;
P = power;
FT = 5V tolerance;
ANT = RF signal input and output (antenna);
Note 2: When the backup area is powered by VDD (internal analog switch connected to VDD): PC14 and PC15
can be used for GPIO or LSE pins, PC13 can be used as general-purpose I/O port, TAMPER pin, RTC calibration
clock, RTC alarm or second output; when used as output pin, it can only work in 2MHz mode with a maximum
drive load of 30pF; when the backup area is powered by VBAT (analog switch connected to BAT after VDD
disappears): PC14 and PC15 can only be used for LSE pin, PC13 can be used as TAMPER pin, RTC alarm or
second output.
Note 3: These pins are in the main function state when the backup area is powered on for the first time. Even
V2.6 29
after reset, the state of these pins is controlled by the backup area registers (these registers will not be reset by
the main reset system). For specific information on how to control these I/O ports, please refer to the relevant
chapters on the battery backup area and BKP register in the CH32FV2x_V3xRM datasheet.
Note 4: Pin 5 and pin 6 of those in LQFP64M package are configured as OSC_IN and OSC_OUT function pins
by default after chip reset. Software can reconfigure these 2 pins as PD0 and PD1. But for those in LQFP100
package, since PD0 and PD1 are inherent functional pins, there is no need to re-image settings by software.
For the CH32V203RBT6, the OSC_IN and OSC_OUT function pins have no alternate functions of PD0 and
PD1. For more detailed information, please refer to the chapters on Alternate Function I/O and Debug Setting
in the CH32FV2x_V3xRM datasheet.
Note 5: For devices without the BOOT0 pinout, they are pulled down to GND internally. For devices with the
BOOT0 pinout but no BOOT1/PB2 pinout, BOOT1/PB2 is pulled down to GND internally. In this case, it is
recommended that the BOOT1/PB2 pinout is set to input pull-down mode if a device goes into the low-power
mode and configures I/O port state, to avoid generating extra current.
Note 6: For devices with BOOT0 and PB8 pinouts shorted, it is recommended to be connected to an external
500K pull-down resistor, to ensure that the device is powered on stably and enters the mode of booting from
program Flash memory. In this case, the PB8 only supports output drive functions, with all input functions
disabled.
Note 7: For devices in 20-pin/28-pin package, several pins are shorted (at least 2 I/O function pins are
physically shorted as one pin). In this case, the driver should not configure the output function at the same
time, otherwise the pins may be damaged. Note pin states when there is a power consumption requirement.
V2.6 30
3.3 Pin alternate functions

Note: The pin function in the table below refer to all functions and does not involve specific model(s). There are differences in peripheral resources between different models.
Please confirm whether this function is available according to the particular model's resource table before viewing this table.
Table 3-2 CH32V203xx pin alternate functions

Alterate TIM UART
ADC TIM1 USB SYS I2C SPI ETH OPA CAN
Pin 2/3/4/5 USART
TIM2_CH1
PA0 ADC_IN0 TIM2_CH1_ETR_2 USART2_CTS WKUP
TIM2_ETR
TIM5_CH1
TIM2_CH2
PA1 ADC_IN1 TIM2_CH2_2 USART2_RTS
TIM5_CH2
TIM2_CH3
PA2 ADC_IN2 TIM2_CH3_1 USART2_TX OPA2_OUT0
TIM5_CH3
TIM2_CH4
PA3 ADC_IN3 TIM2_CH4_1 USART2_RX OPA1_OUT0
TIM5_CH4
PA4 ADC_IN4 USART2_CK SPI1_NSS OPA2_OUT1
USART1_CTS_2
PA5 ADC_IN5 USART1_CK_3 SPI1_SCK OPA2_CH1N
USART4_TX_1
PA6 ADC_IN6 TIM1_BKIN_1 TIM3_CH1 USART1_TX_3 SPI1_MISO OPA1_CH1N
USART4_CK_1
PA7 ADC_IN7 TIM1_CH1N_1 TIM3_CH2 USART1_RX_3 SPI1_MOSI OPA2_CH1P
USART4_CTS_1
TIM1_CH1 USART1_CK
PA8 TIM1_CH1_1 USART1_CK_1 MCO
USART1_RX_2
PA9 TIM1_CH2 USART1_TX
TIM1_CH2_1 USART1_RTS_2
PA10 TIM1_CH3 USART1_RX
TIM1_CH3_1 USART1_CK_2
PA11 TIM1_CH4 USART1_CTS USBDM CAN1_RX
TIM1_CH4_1 USART1_CTS_1
PA12 TIM1_ETR USART1_RTS USBDP CAN1_TX
TIM1_ETR_1 USART1_RTS_1
PA13 SWDIO
PA14 SWCLK
PA15 TIM2_CH1_ETR_1 USART4_RTS_1 SPI1_NSS

TIM2_CH1_ETR_3
PB0 ADC_IN8 TIM1_CH2N_1 TIM3_CH3 UART4_TX_1 OPA1_CH1P
TIM3_CH3_2 USART4_TX
PB1 ADC_IN9 TIM1_CH3N_1 TIM3_CH4 UART4_RX_1 OPA1_OUT1
TIM3_CH4_2 USART4_RX
PB2 USART4_CK BOOT1
PB3 TIM2_CH2_1 USART4_CTS SPI1_SCK

TIM2_CH2_3
PB4 TIM3_CH1_2 USART4_RTS SPI1_MISO
PB5 TIM3_CH2_2 USART4_RX_1 I2C1_SMBA SPI1_MOSI
PB6 TIM4_CH1 USART1_TX_1 USBFS_DM I2C1_SCL
PB7 TIM4_CH2 USART1_RX_1 USBFS_DP I2C1_SDA
V2.6 31
Alterate TIM UART

ADC TIM1 USB SYS I2C SPI ETH OPA CAN
Pin 2/3/4/5 USART
PB8 TIM4_CH3 I2C1_SCL CAN1_RX
PB9 TIM4_CH4 I2C1_SDA CAN1_TX
PB10 TIM2_CH3_2 USART3_TX I2C2_SCL OPA2_CH0N
TIM2_CH3_3
PB11 TIM2_CH4_2 USART3_RX I2C2_SDA OPA1_CH0N
TIM2_CH4_3
PB12 TIM1_BKIN USART3_CK I2C2_SMBA SPI2_NSS
PB13 TIM1_CHIN USART3_CTS SPI2_SCK
USART3_CTS_1
PB14 TIM1_CH2N USART3_RTS SPI2_MISO OPA2_CH0P
USART3_RTS_1
PB15 TIM1_CH3N USART1_TX_2 SPI2_MOSI OPA1_CH0P
PC0 ADC_IN10
PC1 ADC_IN11
PC2 ADC_IN12
PC3 ADC_IN13
PC4 ADC_IN14 USART1_CTS_3
PC5 ADC_IN15 USART1_RTS_3
PC6 TIM3_CH1_3 ETH_RXP
PC7 TIM3_CH2_3 ETH_RXN
PC8 TIM3_CH3_3 ETH_TXP
PC9 TIM3_CH4_3 ETH_TXN
PC10 UART4_TX
USART3_TX_1
PC11 UART4_RX
USART3_RX_1
PC12 USART3_CK_1
PC13 TAMPER-RTC
PC14 OSC32_IN
PC15 OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
TIM3_ETR
PD2 TIM3_ETR_2
TIM3_ETR_3
V2.6 32
Chapter 4 Electrical characteristics
4.1 Test conditions

Unless otherwise specified and marked, all voltages are referenced to VSS.
All minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and
clock frequency. Typical values are based on normal temperature (25℃) and VDD = 3.3V environment, which are
given only as design guidelines.
The data based on comprehensive evaluation, design simulation or technology characteristics are not tested in
production. On the basis of comprehensive evaluation, the minimum and maximum values refer to sample tests. Unless
otherwise specified that is tested, the characteristic parameters are guaranteed by comprehensive evaluation or design.
Power supply scheme:
Figure 4-1 Typical circuit for conventional power supply
VBAT
1.8-3.6V
VDD
VDDx/VIOx
0.1uF
VSSx
VDD
VDDA
0.1uF
VSSA
4.2 Absolute maximum ratings

Stresses at or above the absolute maximum ratings listed in the table below may cause permanent damage to the
device.
Table 4-1 Absolute maximum ratings

Symbol Description Min. Max. Unit
TA Ambient temperature during operation -40 85 ℃
TS Ambient temperature during storage -40 125 ℃
VDD-VSS External main supply voltage (includingVDDA and VDD) -0.3 4.0 V
VI/O-VSS I/O domain supply voltage -0.3 4.0 V
Input voltage on the FT (5V tolerance) pin VSS-0.3 5.5 V
VIN
Input voltage on other pins VSS-0.3 VDD+0.3
|△VDD_x| Variations between different main power supply pins 50 mV
|△VI/O_x| Variations between different I/O power supply pins 50 mV
|△VSS_x| Variations between different ground pins 50 mV
V2.6 33
Electrostatic discharge voltage (human body model, non-contact) 4K V

VESD(HBM)
USB pins (PA11, PA12) 3K V
IVDD Total current into VDD/VDDA/VI/O power lines (source) 150
IVss Total current out of VSS ground lines (sink) 150
Sink current on any I/O and control pin 25
II/O
Output current on any I/O and control pin -25
mA
Injected current on NRST pin +/-5
IINJ(PIN) Injected current on HSE's OSC_IN pin and LSE's OSC_IN pin +/-5
Injected current on other pins +/-5
∑IINJ(PIN) Total injected current on all I/Os and control pins +/-25
4.3 Electrical characteristics

4.3.1 Operating conditions
Table 4-2 General operating conditions
Symbol Parameter Condition Min. Max. Unit
FHCLK Internal AHB clock frequency 144 MHz
FPCLK1 Internal APB1 clock frequency 144 MHz
FPCLK2 Internal APB2 clock frequency 144 MHz
2.4 3.6
VDD Standard operating voltage V
Use USB 3.0 3.6
VI/O Output voltage on most I/O pins VI/O cannot be more than VDD 2.4 3.6 V
Analog operating voltage (ADC is VDDA must be the same as
not used) VI/O, VREF+ cannot be higher
VDDA 2.4 3.6 V
Analog operating voltage (ADC is than VDDA, VREF- is equal to
used) VSS.
VBAT(1) Backup operating voltage Cannot be more than VDD 1.8 3.6 V
TA Ambient temperature -40 85 ℃
TJ Junction temperature range -40 85 ℃
Note: 1. The connection line from the battery to VBAT should be as short as possible.
Table 4-3 Power-on and power-down conditions

VDD rise time rate 0 ∞
tVDD us/V
VDD fall time rate 30 ∞
V2.6 34
4.3.2 Embedded reset and power control block characteristics

Table 4-4 Reset and voltage monitor (For PDR, select high threshold gear)
Symbol Parameter Condition Min. Typ. Max. Unit
PLS[2:0] = 000 (rising edge) 2.39 V
PLS[2:0] = 000 (falling edge) 2.31 V
Programmable voltage PLS[2:0] = 011 (falling edge) 2.69 V
VPVD(1)
detector level selection PLS[2:0] = 100 (rising edge) 2.89 V
VPVDhyst PVD hysteresis 0.08 V
Power-on/power-down Rising edge 1.9 2.2 2.4 V
VPOR/PDR
reset threshold Falling edge 1.9 2.2 2.4 V
VPDRhyst PDR hysteresis 20 mV
Power on reset 24 28 30
tRSTTEMPO mS
Other resets 8 10 30
Note: 1. Normal temperature test value.
4.3.3 Embedded reference voltage

Table 4-5 Embedded reference voltage
VREFINT Internal reference voltage TA = -40℃~85℃ 1.17 1.2 1.23 V
ADC sampling time when
TS_vrefint reading the internal 17.1 us
reference voltage
4.3.4 Supply current characteristics

Current consumption is a comprehensive index of a variety of parameters and factors. These parameters and
factors include operating voltage, ambient temperature, I/O pin load, the software configuration of the product,
the operating frequency, flip rate of the I/O pin, the location of the program in memory and the executed code,
etc. The current consumption measurement method is as follows:
V2.6 35
Figure 4-2 Current consumption measurement
IBAT -VBAT
Electric current VBAT
measurement
IDD
Electric current VDD
measurement
VDDA
The microcontroller is in the following conditions:

Under normal temperature conditions and when VDD = 3.3V, all I/O ports are configured with pull-up inputs, only
one of HSE and HIS is enabled, HSE=8M, HIS=8M (calibrated), FPLCK1=FHCLK/2, FPLCK2=FHCLK, PLL is enabled
when FHCLK>8MHz. Enable or disable the power consumption of all peripheral clocks.
Table 4-6-1 Typical current consumption in Run mode, the data processing code runs from the internal Flash
(V203)
Typ.
Symbol Parameter Condition All peripherals All peripherals Unit
enabled disabled(2)
FHCLK = 144MHz 12.08 8.24
FHCLK = 72MHz 6.43 4.43
FHCLK = 48MHz 4.51 3.18
FHCLK = 36MHz 4.12 2.98
External clock FHCLK = 24MHz 2.72 1.95
FHCLK = 16MHz 2.18 1.68
FHCLK = 8MHz 1.21 0.99
FHCLK = 4MHz 0.92 0.80
Supply
FHCLK = 500KHz 0.65 0.64
IDD(1) current in mA
FHCLK = 144MHz 11.72 7.44
Run mode
FHCLK = 72MHz 6.02 3.86
Runs on the high-
FHCLK = 48MHz 4.13 2.69
speed internal RC
FHCLK = 36MHz 3.31 2.25
oscillator (HSI).
FHCLK = 24MHz 2.23 1.53
Uses AHB prescaler
FHCLK = 16MHz 1.68 1.18
to reduce the
FHCLK = 8MHz 0.86 0.63
frequency.
FHCLK = 4MHz 0.56 0.45
FHCLK = 500KHz 0.31 0.29
Note: 1. The above are measured parameters.
2. During the test, the clocks of USART1 and GPIOA are not disabled when all peripheral clocks are
disabled.
V2.6 36
Table 4-6-2 Typical current consumption in Run mode, the data processing code runs from the internal Flash
(V203RBT6)
Typ.
enabled disabled(2)
FHCLK = 144MHz 21.37 16.77
FHCLK = 72MHz 10.91 8.73
FHCLK = 48MHz 7.58 6.16
FHCLK = 36MHz 6.49 5.29
FHCLK = 16MHz 3.13 2.59
FHCLK = 8MHz 2.0 1.71
FHCLK = 4MHz 1.42 1.28
Supply
FHCLK = 500KHz 1.0 0.95
IDD(1) current in mA
FHCLK = 144MHz 20.75 16.27
Run mode
FHCLK = 72MHz 10.74 8.53
Runs on the high-
FHCLK = 48MHz 7.42 5.98
speed internal RC
FHCLK = 36MHz 5.96 5.05
oscillator (HSI).
FHCLK = 24MHz 4.62 3.41
Uses AHB prescaler
FHCLK = 16MHz 3.03 2.49
to reduce the
FHCLK = 8MHz 1.66 1.42
frequency.
FHCLK = 4MHz 1.11 1.0
FHCLK = 500KHz 0.63 0.62
2. During the test, the clocks of USART1 and GPIOA are not disabled when all peripheral clocks are
disabled.
Table 4-7-1 Typical current consumption in Sleep mode, data processing code runs from internal Flash or
SRAM (V203)
Typ.
enabled disabled(2)
FHCLK = 144MHz 7.37 3.05
FHCLK = 72MHz 4.0 1.88
Supply current FHCLK = 48MHz 2.9 1.7
in Sleep mode FHCLK = 36MHz 2.9 1.48
(In this case, External clock FHCLK = 24MHz 1.93 1.2
IDD (1) peripheral FHCLK = 16MHz 1.64 1.0 mA
power supply FHCLK = 8MHz 0.94 0.72
and clock are FHCLK = 4MHz 0.78 0.66
maintained) FHCLK = 500KHz 0.63 0.62
Runs on the high- FHCLK = 144MHz 7.1 2.72
speed internal FHCLK = 72MHz 3.65 1.56
V2.6 37
RC oscillator FHCLK = 48MHz 2.56 1.15

(HSI).Uses AHB FHCLK = 36MHz 2.17 1.06
prescaler to FHCLK = 24MHz 1.46 0.76
reduce the FHCLK = 16MHz 1.2 0.68
frequency. FHCLK = 8MHz 0.6 0.4
FHCLK = 4MHz 0.44 0.34
FHCLK = 500KHz 0.3 0.28
2. During the test, the clocks of USART1, GPIOA and power module are not disabled.
Table 4-7-2 Typical current consumption in Sleep mode, data processing code runs from internal Flash or
SRAM (V203RBT6)
Typ.
enabled disabled(2)
FHCLK = 144MHz 8.17 3.69
FHCLK = 72MHz 4.75 2.16
FHCLK = 48MHz 3.35 1.69
Supply FHCLK = 36MHz 3.29 1.89
current in
Sleep
FHCLK = 16MHz 1.63 1.11
mode
FHCLK = 8MHz 1.23 0.98
(In this
FHCLK = 4MHz 1.06 0.94
case,
FHCLK = 500KHz 0.97 0.91
IDD(1) peripheral mA
FHCLK = 144MHz 7.65 3.44
power
FHCLK = 72MHz 4.61 2.02
supply Runs on the high-
FHCLK = 48MHz 3.22 1.55
and clock speed internal RC
FHCLK = 36MHz 2.73 1.44
are oscillator (HSI).
maintaine
FHCLK = 24MHz 1.9 1.1
Uses AHB prescaler
d) FHCLK = 16MHz 1.48 0.95
to reduce the
FHCLK = 8MHz 0.93 0.69
frequency.
FHCLK = 4MHz 0.75 0.63
FHCLK = 500KHz 0.58 0.56
2. During the test, the clocks of USART1, GPIOA and power module are not disabled.
Table 4-8-1 Typical current consumption in Stop and Standby mode (V203)
Symbol Parameter Condition Typ. Unit
Voltage regulator in Run mode, low-
speed and high-speed internal RC
54
IDD Supply current in Stop mode oscillators and external oscillators off uA
(no independent watchdog)
Voltage regulator in low-power mode, 9.4
V2.6 38
low-speed and high-speed internal RC

oscillators and external oscillators off
(no independent watchdog, PVD off),
RAM enters low-power mode
Low-speed internal RC oscillator and
independent watchdog on, all RAM 1.3
not powered
Low-speed internal RC oscillator on,
independent watchdog off, all RAM 1.3
Supply current in Standby not powered
mode LSI/LSE/RTC/IWDG off, 2K_RAM
powered and in low-power mode 1.16
LSI/LSE/RTC/IWDG off, all RAM

not powered 0.5
Backup domain supply

Low-speed external oscillator and
IDD_VBAT current (Remove VDD and 1.3
RTC on
VDDA, only powered by VBAT
Note: The above are measured parameters.
Table 4-8-2 Typical current consumption in Stop and Standby mode (V203RBT6)
Voltage regulator in Run mode, low-
speed and high-speed internal RC
253.4
oscillators and external oscillators off
(no independent watchdog)
Supply current in Stop mode Voltage regulator in low-power mode,
low-speed and high-speed internal RC
oscillators and external oscillators off 23.8
(no independent watchdog, PVD off),
RAM enters low-power mode
Low-speed internal RC oscillator and
IDD independent watchdog on, all RAM 1.3 uA
not powered
Low-speed internal RC oscillator on,
independent watchdog off, all RAM 1.3
Supply current in Standby not powered
mode LSI/LSE/RTC/IWDG off, 32K_RAM
LSI/LSE/RTC/IWDG off, 2K_RAM

V2.6 39
LSI/LSE/RTC/IWDG off, all RAM

not powered 0.7
Backup domain supply

Low-speed external oscillator and
IDD_VBAT current (Remove VDD and 1.23
RTC on
VDDA, only powered by VBAT
Note: The above are measured parameters.
4.3.5 External clock source characteristics

Table 4-9 From external high-speed clock
3 8 25
FHSE_ext External clock frequency MHz
Applied for V203RBT6 32
OSC_IN input pin high level
VHSEH(1) 0.8VI/O VIO V
voltage
OSC_IN input pin low-level
VHSEL(1) 0 0.2VIO V
voltage
Cin(HSE) OSC_IN input capacitance 5 pF
DuCy(HSE) Duty cycle 50 %
IL OSC_IN input leakage current ±1 uA
Note: 1. Failure to meet this condition may cause level recognition error.
Figure 4-3 External high-frequency clock source circuit

External clock source
fHS E_ext
OSC_IN
OSC_OUT
Table 4-10 From external low-speed clock

FLSE_ext User external clock frequency 32.768 1000 KHz
OSC32_IN input pin high level
VLSEH 0.8VDD VDD V
voltage
VLSEL OSC32_IN input pin low voltage 0 0.2VDD V
Cin(LSE) OSC32_IN input capacitance 5 pF
DuCy(LSE) Duty cycle 50 %
IL OSC32_IN input leakage current ±1 uA
V2.6 40
Figure 4-4 External low-frequency clock source circuit

External clock source
fLSE_ext
OSC_IN
OSC_OUT
Table 4-11 High-speed external clock generated from a crystal/ceramic resonator

3 8 25
FOSC_IN Resonator frequency (2)
MHz
Applied for V203RBT6 32
RF Feedback resistance 250 kΩ
Recommended load
C capacitance and corresponding RS=60Ω(1) 20 pF
crystal series impedance RS
I2 HSE drive current VDD = 3.3V，20p load 0.53 mA
gm Oscillator transconductance Startup 17.5 mA/V
tSU(HSE) Startup time VDD is stable, 8M crystal 2.5 ms
Note 1: It is recommended that the ESR of 25M crystal should not exceed 60 Ω, and it can be relaxed if it is lower
than 25M.
2. No external load capacitor is required.
Circuit reference design and requirements:

The load capacitance of the crystal is subject to the recommendation of the crystal manufacturer, generally
CL1=CL2.
For CH32V203RB, they are connected with external 32M crystals, and they have built-in load capacitor, so the
external circuit is not necessary.
Figure 4-5 Typical circuit of external 8M crystal

CL1
OSC_IN
8MHz
Crystal
Oscillator
OSC_OUT
CL2
Table 4-12 Low-speed external clock generated by generated from a crystal/ceramic resonator
(fLSE=32.768KHz)
RF Feedback resistance 5 MΩ
Recommended load capacitance
C and corresponding crystal serial RS<70kΩ 15 pF
impedance RS
V2.6 41
i2 LSE drive current VDD = 3.3V 0.35 uA

gm Oscillator transconductance Startup 25.3 uA/V
tSU(LSE) Startup time VDD is stable 800 mS

The load capacitance of the crystal is subject to the recommendation of the crystal manufacturer, usually CL1=CL2,
which is about 12pF.
Figure 4-6 Typical circuit of external 32.768K crystal

CL1
OSC_IN
32.768KHz
crystal
oscillator
OSC_OUT
CL2
Note: The load capacitance CL is calculated by the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray. Cstray
is the capacitance of the pin and the PCB board or PCB-related capacitance. Its typical value is between 2pF
and 7pF.
4.3.6 Internal clock source characteristics

Table 4-13 Internal high-speed (HSI) RC oscillator characteristics
FHSI Frequency (after calibration) 8 MHz
DuCyHSI Duty cycle 45 50 55 %
Accuracy of HSI oscillator (after TA = 0℃～70℃ -1.0 1.6 %
ACCHSI
calibration) TA = -40℃～85℃ -2.2 2.2 %
HSI oscillator startup stabilization 10
tSU(HSI) us
time
IDD(HSI) HSI oscillator power consumption 120 180 270 uA
Table 4-14 Internal low-speed (LSI) RC oscillator characteristics

25 39 60
FLSI Frequency KHz
applied for V203RBT6 25 32 45
DuCyLSI Duty cycle 45 50 55 %

LSI oscillator startup
tSU(LSI) 100 us
stabilization time
LSI oscillator power
IDD(LSI) 0.6 uA
consumption
V2.6 42
4.3.7 PLL characteristics

Table 4-15 PLL characteristics
3 8 25
PLL input clock MHz
FPLL_IN applied for V203RBT6 4 8 25
PLL input clock duty cycle 40 60 %
(1)
18 144
FPLL_OUT PLL multiplier output clock MHz
applied for V203RBT6 40 240(1)
tLOCK PLL lock time 200 us
Note 1: The frequency multiplier must be selected to meet the PLL output frequency range.
4.3.8 Wakeup time from low-power mode

Table 4-16-1 Wakeup time from low-power mode(1) (V203x)
twusleep Wakeup from Sleep mode Wake up using HSI RC clock 1.44 us
Wakeup from Stop mode (voltage
Wake on HSI RC clock 22.87 us
regulator is in Run mode)
twustop Voltage regulator wake-up time from
low-power mode + HSI RC clock 75.53 us
regulator is in low-power mode)
wake up
LDO stabilization time + HSI RC
tWUSTDBY Wakeup from Standby mode 4.82 ms
clock wake up + code load time(2)
Note: 1. The above parameters are measured parameters.
2. The code load time is calculated based on the current zero-wait area capacity configured by the chip
and the size of the loading configuration clock.
Table 4-16-2 Wakeup time from low-power mode(1) (V203RBT6)

twusleep Wakeup from Sleep mode Wake up using HSI RC clock 2.6 us
Wake on HSI RC clock 23.1 us
regulator is in Run mode)
twustop Voltage regulator wakeup time from
low-power mode + HSI RC clock 299 us
regulator is in low-power mode)
wake up
LDO stabilization time + HSI RC
tWUSTDBY Wakeup from Standby mode clock wake up + code load time(2) 5.0 ms
(take 128K as example)
Note: 1. The above parameters are measured parameters.
2. The code load time is calculated based on the current zero-wait area capacity configured by the chip
and the size of the loading configuration clock.
V2.6 43
4.3.9 Memory characteristics

Table 4-17 Flash memory characteristics
(1)
Fprog Programming frequency TA = -40℃～85℃ 60 MHz
tprog_page Page (256 bytes) programming time TA = -40℃～85℃ 2 ms
terase_page Page (256 bytes) erase time TA = -40℃～85℃ 16 ms
terase_sec Sector (4K bytes) erase time TA = -40℃～85℃ 16 ms
Vprog Programming voltage 2.4 3.6 V
Note: 1. For the programming frequency of flash, read operation, program operation and erase operation are
included. The clock is from HCLK.
Table 4-18 Flash memory endurance and data retention

NEND Endurance TA = 25℃ 10K 80K(1) times
tRET Data retention 20 year
Note: The endurance parameter is actual measured, which is not guaranteed.
4.3.10 I/O port characteristics

Table 4-19 General-purpose I/O static characteristics
Standard I/O pin, input high level 0.41*(VDD-
VDD+0.3 V
voltage 1.8)+1.3
VIH
0.42*(VDD-
FT I/O pin, input high level voltage 5.5 V
1.8)+1
Standard I/O pin, input low-level 0.28*(VDD-
-0.3 V
voltage 1.8)+0.6
VIL
0.32*(VDD-
FT I/O pin, input low-level voltage -0.3 V
1.8)+0.55
Standard I/O pin Schmitt trigger voltage
150
hysteresis
Vhys mV
FT I/O pin Schmitt trigger voltage
90
hysteresis
Standard I/O port 1
Ilkg Input leakage current uA
FT I/O port 3
RPU Weak pull-up equivalent resistance 30 40 50 kΩ
RPD Weak pull-down equivalent resistance 30 40 50 kΩ
CIO I/O pin capacitance 5 pF
Output drive current characteristics

GPIO (General-Purpose Input/Output Port) can sink or output up to ±8mA current, and sink or output ±20mA
current (not strictly to VOL/VOH). In user applications, the total driving current of all I/O pins cannot exceed the
absolute maximum ratings given in Section 4.2:
V2.6 44
Table 4-20 Output voltage characteristics

VOL Output low level when 8 pins are sunk TTL port, IIO = +8mA 0.4
V
VOH Output high level when 8 pins are sourced 2.7V< VDD <3.6V VDD-0.4
VOL Output low level when 8 pins are sunk CMOS port, IIO = +8mA 0.4
V
VOH Output high level when 8 pins are sourced 2.7V< VDD <3.6V 2.3
VOL Output low level when 8 pins are sunk IIO = +20mA 1.3
V
VOL Output low level when 8 pins are sunk IIO = +6mA 0.4
V
Note: In the above conditions, if multiple I/O pins are driven at the same time, the total current cannot exceed
the absolute maximum ratings given in Table 4.2. In addition, when multiple I/O pins are driven at the same time,
the current on the power/ground point is very large, which will cause the voltage drop to make the internal I/O
voltage not reach the power supply voltage in the table, resulting in the drive current being less than the nominal
value.
Table 4-21 Input/output AC characteristics

MODEx[1:0]
configuration
Fmax(I/O)out Maximum frequency CL=50pF,VDD=2.7-3.6V 2 MHz
10
tf(I/O)out Output high to low fall time 125 ns
（2MHz） CL=50pF,VDD=2.7-3.6V
tr(I/O)out Output low to high rise time 125 ns
Fmax(I/O)out Maximum frequency CL=50pF,VDD=2.7-3.6V 10 MHz
01
tf(I/O)out Output high to low fall time 25 ns
（10MHz） CL=50pF,VDD=2.7-3.6V
tr(I/O)out Output low to high rise time 25 ns
CL=30pF,VDD=2.7-3.6V 50 MHz
Fmax(I/O)out Maximum frequency
CL=50pF,VDD=2.7-3.6V 30 MHz
11 CL=30pF,VDD=2.7-3.6V 20 ns
tf(I/O)out Output high to low fall time
（50MHz） CL=50pF,VDD=2.7-3.6V 5 ns
CL=30pF,VDD=2.7-3.6V 8 ns
tr(I/O)out Output low to high rise time
CL=50pF,VDD=2.7-3.6V 12 ns
The EXTI controller detects
tEXTIpw the pulse width of the 10 ns
external signal
4.3.11 NRST pin characteristics

Table 4-22 External reset pin characteristics
NRST input low-level
VIL(NRST) -0.3 0.28*(VDD-1.8)+0.6 V
voltage
NRST input high-level
VIH(NRST) 0.41*(VDD-1.8)+1.3 VDD+0.3 V
voltage
Vhys(NRST) NRST Schmitt Trigger 150 mV
V2.6 45
voltage hysteresis
Weak pull-up equivalent
RPU(1) 30 40 50 kΩ
resistance
NRST input filtered pulse
VF(NRST) 100 ns
width
NRST input not filtered
VNF(NRST) 300 ns
pulse width
Note: 1. The pull-up resistor is a real resistor in series with a switchable PMOS implementation. The resistance
of this PMOS/NMOS switch is very small (approximately 10%).

Figure 4-7 Typical circuit of external reset pin
VDD
RPU
NRST
Filter
0.1μF
4.3.12 TIM timer characteristics

Table 4-23 TIMx characteristics
1 tTIMxCLK
tres(TIM) Timer reference clock
fTIMxCLK = 72MHz 13.9 ns
Timer external clock frequency on 0 fTIMxCLK/2 MHz
FEXT
CH1 to CH4 fTIMxCLK = 72MHz 0 36 MHz
ResTIM Timer resolution 16 bit
16-bit counter clock cycle when the 1 65536 tTIMxCLK
tCOUNTER
internal clock is selected fTIMxCLK = 72MHz 0.0139 910 us
65535 tTIMxCLK
tMAX_COUNT Maximum possible count
fTIMxCLK = 72MHz 59.6 s
4.3.13 I2C interface characteristics

Figure 4-8 I2C bus timing diagram
tw(SCKH)
tr(SCL)
tw(SCKL)
SCL th(STA) tf(SCL)
tSU(STO)
tSU(SDA) th(SDA)
tf(SDA)
Repeat start condition
SDA tw(STO:STA)
tr(SDA) Stop condition
Start condition tSU(STA)
V2.6 46
Table 4-24 I²C interface characteristics

Standard I2C Fast I2C
Symbol Parameter Unit
Min. Max. Min. Max.
tw(SCKL) SCL clock low time 4.7 1.2 us
tw(SCKH) SCL clock high time 4.0 0.6 us
tSU(SDA) SDA data setup time 250 100 ns
th(SDA) SDA data hold time 0 0 900 ns
tr(SDA)/tr(SCL) SDA and SCL rise time 1000 20 ns
tf(SDA)/tf(SCL) SDA and SCL fall time 300 ns
th(STA) Start condition hold time 4.0 0.6 us
tSU(STA) Repeated start condition setup time 4.7 0.6 us
tSU(STO) Stop condition setup time 4.0 0.6 us
Time from stop condition to start condition
tw(STO:STA) 4.7 1.2 us
(bus free)
Cb Capacitive load for each bus 400 400 pF
4.3.14 SPI interface characteristics

Figure 4-9 SPI timing diagram in Master mode
tSCK tr(SCK)
tf(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
tw(SCKL)
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
th(MI)
tsu(MI)
MISO Input Input highest bit Input 6-1 bit Input lowest bit
tV(MO) th(MO)
MOSI Output Output highest bit Output 6-1 bit Output lowest bit
V2.6 47
Figure 4-10 SPI timing diagram in Slave mode (CPHA=0)

NSS Input
th(NSS)
tSCK tr(SCK)
tf(SCK)
SCK Input tsu(NSS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO) tV(SO)
th(SO)
tdis(SO)
MISO Output Output highest bit Output 6-1 bit Output lowest bit
tsu(SI) th(SI)
MOSI Input Input highest bit Input 6-1 bit Input lowest bit
Figure 4-11 SPI timing diagram in Slave mode (CPHA=1)

NSS Input
th(NSS)
tSCK tr(SCK)
tf(SCK)
SCK Input tsu(NSS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO) tV(SO)
th(SO)
tdis(SO)
MISO Output Output highest bit Output 6-1 bit Output lowest bit
tsu(SI) th(SI)
MOSI Input Input highest bit Input 6-1 bit Input lowest bit
Table 4-25 SPI interface characteristics

Master mode 36 MHz
fSCK/tSCK SPI clock frequency
Slave mode 36 MHz
tr(SCK)/tf(SCK) SPI clock rise and fall time Load capacitance:C = 30pF 20 ns
tSU(NSS) NSS setup time Slave mode 2tPCLK ns
th(NSS) NSS hold time Slave mode 2tPCLK ns
Master mode, fPCLK = 36MHz,
tw(SCKH)/tw(SCKL) SCK high and low time 40 60 ns
Prescaler factor = 4
tSU(MI) Data input setup time Master mode 5 ns
V2.6 48
tSU(SI) Slave mode 5 ns

th(MI) Master mode 5 ns
Data input hold time
th(SI) Slave mode 4 ns
ta(SO) Data output access time Slave mode, fPCLK = 20MHz 0 1tPCLK ns
tdis(SO) Data output disable time Slave mode 0 10 ns
tV(SO) Slave mode (After enable edge) 25 ns
Data output valid time
tV(MO) Master mode (After enable edge) 5 ns
th(SO) Slave mode (After enable edge) 15 ns
Data output hold time
th(MO) Master mode (After enable edge) 0 ns
4.3.15 USB interface characteristics

Table 4-26 USB characteristics
VDD USB operating voltage 3.0 3.6 V
VSE Single-ended receiver threshold VDD = 3.3V 1.2 1.9 V
VOL Static output low level 0.3 V
VOH Static output high level 2.8 3.6 V
High-speed suppression
VHSSQ 100 150 mV
information detection threshold
High-speed disconnection
VHSDSC 500 625 mV
detection threshold
VHSOI High-speed idle level -10 10 mV
VHSOH High-speed data high level 360 440 mV
VHSOL High-speed data low level -10 10 mV
4.3.16 12-bit ADC characteristics

Table 4-27 ADC characteristics
VDDA Supply voltage 2.4 3.6 V
Positive reference voltage VREF+ cannot be
VREF+ 2.4 VDDA V
more than VDDA
IVREF Reference current 160 220 uA
IDDA Supply current 480 530 uA
fADC ADC clock frequency 14 MHz
fS Sampling rate 0.05 1 MHz
fTRIG External trigger frequency 16 1/fADC
VAIN Conversion voltage range 0 VREF+ V
RAIN External input impedance 50 kΩ
RADC Sampling switch resistance 0.6 1 kΩ
Internal sample and hold
CADC 8 pF
capacitor
V2.6 49
tCAL Calibration time 100 1/fADC
tIat Injected trigger conversion latency 2 1/fADC

tIatr Regular trigger conversion latency 2 1/fADC
ts Sampling time 1.5 239.5 1/fADC
tSTAB Power-on time 1 us
Total conversion time (including
tCONV 14 252 1/fADC
sampling time)
Note: Above parameters are guaranteed by design.
Formula: Maximum RAIN

Ts
R < −R
f ×C × ln 2
The above formula is used to determine the maximum external impedance so that the error can be less than 1/4
LSB. Where N=12 (representing 12-bit resolution).
Table 4-28 Maximum RAIN when fADC = 14MHz

TS(cycle) tS (us) Maximum RAIN(kΩ)
1.5 0.11 0.4
7.5 0.54 5.9
13.5 0.96 11.4
28.5 2.04 25.2
41.5 2.96 37.2
55.5 3.96 50
71.5 5.11 Invalid
239.5 17.1 Invalid
Table 4-29 ADC error

EO Offset error fPCLK2 = 56 MHz, ±2
ED Differential nonlinearity error fADC = 14 MHz, ±0.5 ±3
LSB
RAIN < 10 kΩ,
EL Integral nonlinearity error ±1 ±4
VDDA = 3.3V
Cp represents the parasitic capacitance on the PCB and the pad (about 5pF), which may be related to the quality
of the pad and PCB layout. A larger Cp value will reduce the conversion accuracy, the solution is to reduce the
fADC value.
V2.6 50
Figure 4-12 ADC typical connection diagram
VDD
VT Sample and hold ADC converter

RAIN AINx 0.6V RADC
12-bit
converter
VT CADC
CP 0.6V
VAIN Parasitic
capacitance
Figure 4-13 Analog power supply and decoupling circuit reference
VDDA
0.1μF
VSSA
4.3.17 Temperature sensor characteristics

Table 4-30 Temperature sensor characteristics
Measurement range of temperature
RTS -40 85 ℃
sensor
Measurement range of temperature
ATSC ±12 ℃
sensor after software calibration
Average slope (negative
Avg_Slope 3.8 4.3 4.7 mV/℃
temperature coefficient)
V25 Voltage at 25℃ 1.34 1.40 1.46 V
ADC sampling time when reading
TS_temp fADC = 14MHz 17.1 us
temperature
4.3.18 OPA characteristics

Table 4-31 OPA characteristics
VDDA Supply voltage 2.4 3.3 3.6 V
CMIR Common mode input voltage 0 VDDA-0.9 V
VIOFFSET Input offset voltage 1.5 6 mV
ILOAD Drive current 600 uA
IDDOPAMP Current consumption No load, static mode 195 uA
CMRR(1) Common mode rejection ratio @1KHz 96 dB
PSRR(1) Power supply rejection ratio @1KHz 86 dB
V2.6 51
AV(1) Open loop gain CLOAD=5pF 136 dB

(1)
GBW Unit gain bandwidth CLOAD=5pF 19 MHz
PM(1) Phase margin CLOAD=5pF 93
SR(1) Slew rate limited CLOAD=5pF 8 V/us
Setup time from shutdown to
tWAKUP(1) Input VDDA/2, CLOAD=5pF,RLOAD=4kΩ 368 ns
wake up, 0.1%
RLOAD Resistive load 4 kΩ
CLOAD Capacitive load 50 pF
RLOAD=4kΩ, input
VDDA-45
(2)
VDDA
VOHSAT High saturation output voltage mV
RLOAD=20kΩ, input
VDDA-10
VDDA
RLOAD=4kΩ, input 0 0.5
VOLSAT(2) Low saturation output voltage mV
RLOAD=20kΩ, input 0 0.5
RLOAD=4kΩ,@1KHz 83 nv
EN(1) Equivalent input voltage noise
RLOAD=4kΩ,@10KHz 42 Hz
Note: 1. The source simulation is not a real measurement.
2. The load current limits the saturated output voltage.
V2.6 52
Chapter 5 Package and ordering information
Packages
Part No. Package Body size Lead pitch Description Packing type
Thin shrink small outline
CH32V203F6P6 TSSOP20 4.4*6.5mm 0.65mm Tube
20-pin patch
Thin shrink small outline
CH32V203F8P6 TSSOP20 4.4*6.5mm 0.65mm Tube
20-pin patch
CH32V203F8U6 QFN20X3 3*3mm 0.4mm Quad no-lead 20-pin Tray
CH32V203G6U6 QFN28X4 4*4mm 0.4mm Quad no-lead 28-pin Tray
CH32V203G8R6 QSOP28 3.9*9.9mm 0.635mm 28-pin patch Tube
CH32V203K6T6 LQFP32 7*7mm 0.8mm LQFP32 (7*7) patch Tray
CH32V203K8T6 LQFP32 7*7mm 0.8mm LQFP32 (7*7) patch Tray
CH32V203C6T6 LQFP48 7*7mm 0.5mm LQFP48 (7*7) patch Tray
CH32V203C8T6 LQFP48 7*7mm 0.5mm LQFP48 (7*7) patch Tray
CH32V203C8U6 QFN48X7 7*7mm 0.5mm Quad no-lead 48-pin Tray
CH32V203RBT6 LQFP64M 10*10mm 0.5mm LQFP64M (10*10) patch Tray
Note: 1. The packing type of QFP/QFN is usually tray. Please confirm with the packaging factory for specific
part number.
2. Size of tray: The size of Tray is generally a uniform size (322.6*135.9*7.62). There are differences in
the size of the restriction holes for different package types, and there are differences between different packaging
factories for tubes, please confirm with the manufacturer for details.
V2.6 53
Note: All dimensions are in millimeters. The pin center spacing values are nominal values, with no error. Other
than that, the dimensional error is not greater than the greater of ±0.2mm or 10%.
Figure 5-1 TSSOP20 package
Figure 5-2 QFN20X3 package
V2.6 54
Figure 5-5 LQFP32 package
Figure 5-6 LQFP48 package
V2.6 55
Figure 5-7 LQFP64M package
Figure 5-8 QSOP28 package
V2.6 56
Series product naming rules

Example: CH32 V 3 03 R 8 T 6
Device family
F = ARM-based
V = QingKe RISC-V-based
Product type
0 = QingKe V2 core
1 = M3/ QingKe V3A core, clock speed @72M
2 = M3/ QingKe V4B_C core, clock speed @144M
3 = QingKe V4F floating-point core, clock speed @144M
Device subfamily
03 = General-purpose
05 = Connectivity (USB high-speed, SDIO, dual CAN)
07 = Interconnectivity (USB high-speed, dual CAN, Ethernet, DVP, SDIO, FSMC)
08 = Wireless (BLE5.3, CAN, USB, Ethernet)
Pin count
J = 8 pins A = 16 pins F = 20 pins
G = 28 pins K = 32 pins T = 36 pins
C = 48 pins R = 64 pins W = 68 pins
V = 100 pins Z = 144 pins
Flash memory size

4 = 16 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
C = 256 Kbytes of Flash memory
Package
T = LQFP
U = QFN R = QSOP
P = TSSOP M = SOP
Temperature range
6 = -40℃～85℃ (industrial-grade)
7 = -40℃～105℃ (automotive-grade 2)
3 = -40℃～125℃ (automotive-grade 1)
D = -40℃～150℃ (automotive-grade 0)
V2.6 57

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CH32V203 Datasheet

Chapter 1 Series product description

Table 1-1 Series overview

Table 1-2 Overview of Cores

2.1 Model comparison

Part No. CH32V203

2.2 System architecture

Figure 2-1 System block diagram

@VDD VDD: 2.4V~3.6V

SRAM Reset & AHBCLK

AHB to APB1 @VBAT

AHB to APB2 RTC/BKP TAMPER-RTC

TIM3 4 channels, ETR

PA0 ~ PA15 GPIOA

USART3 RX, TX, CTS, RTS, CK

2.3 Memory map

Figure 2-2 Memory address map

0x5005 0400 Reserved

2.4 Clock tree

Figure 2-3 CH32V203 clock tree block diagram

OSC32_IN 32.768kHz RTCCLK

USB prescaler 48MHz

PLLXTPRE PLLSRC perpheral clock enable

/8 to Core System timer

APB1 prescaler PCLK1

if(APB1 prescaler=1)*1 TIMxCLK

perpheral clock enable

APB2 prescaler PCLK2

if(APB2 prescaler=1)*1 TIMxCLK

perpheral clock enable

Figure 2-4 CH32V203RB clock tree block diagram

OSC32_IN 32.768kHz RTCCLK

USB prescaler 48MHz

PLLXTPRE PLLSRC perpheral clock enable

if(APB1 prescaler=1)*1 TIMxCLK

if(APB2 prescaler=1)*1 TIMxCLK

perpheral clock enable

2.5 Functional description

2.5.2 On-chip memory and boot mode

2.5.3 Power supply scheme

must not be less than 2.4V.

2.5.4 Power supply monitor

2.5.5 Voltage regulator

2.5.6 Low-power mode

2.5.7 CRC (cyclic redundancy check) calculation unit

2.5.8 Fast programmable interrupt controller (FPIC)

2.5.9 External interrupt/event controller (EXTI)

2.5.10 General DMA controller

2.5.11 Clock and Boot

2.5.12 Real time clock (RTC) and backup registers

2.5.14 Timer and watchdog

Table 2-2 Timer comparison

l Advanced control timer

2.5.15 Communication interface

2.5.15.2 Serial Peripheral Interface (SPI)

2.5.15.3 I2C bus

2.5.15.4 Controller Area Network (CAN)

2.5.15.5 Universal Serial Bus device (USBD)

2.5.15.6 Universal Serial Bus USB2.0 full-speed Host/Device controller (USBFS)

2.5.16 General-purpose input and output (GPIO)