SN 74 Avc 16 T 245

SN74AVC16T245
SCES551F – FEBRUARY 2004 – REVISED MARCH 2024
SN74AVC16T245 16-Bit Dual-Supply Bus Transceiver

with Configurable Level-Shifting / Voltage Translation and Tri-State Outputs
1 Features 3 Description
• Control Inputs VIH/VIL Levels Are Referenced to This 16-bit noninverting bus transceiver uses
VCCA Voltage two separate configurable power-supply rails. The
• VCC Isolation Feature – If Either VCC Input Is at SN74AVC16T245 device is optimized to operate
GND, Both Ports Are in the High-Impedance State with VCCA/VCCB set at 1.4V to 3.6V. The device is
• Overvoltage-Tolerant Inputs and Outputs Allow operational with VCCA/VCCB as low as 1.2V. The A port
Mixed-Voltage-Mode Data Communications is designed to track VCCA. VCCA accepts any supply
• Fully Configurable Dual-Rail Design Allows Each voltage from 1.2V to 3.6V. The B port is designed
Port to Operate Over the Full 1.2V to 3.6V Power- to track VCCB. VCCB accepts any supply voltage from
Supply Range 1.2V to 3.6V. This allows for universal low-voltage
• Ioff Supports Partial-Power-Down Mode Operation bidirectional translation between any of the 1.2V, 1.5V,
• I/Os Are 4.6V Tolerant 1.8V, 2.5V, and 3.3V voltage nodes.
• Maximum Data Rates
The SN74AVC16T245 device is designed for
– 380Mbps (1.8V to 3.3V Level-Shifting) asynchronous communication between data buses.
– 200Mbps (<1.8V to 3.3V Level-Shifting) The device transmits data from the A bus to the B
– 200Mbps (Level-Shifting to 2.5V or 1.8V) bus or from the B bus to the A bus, depending on
– 150Mbps (Level-Shifting to 1.5V) the logic level at the direction-control (DIR) input. The
– 100Mbps (Level-Shifting to 1.2V) output-enable ( OE) input can be used to disable the
• Latch-Up Performance Exceeds 100mA Per JESD outputs so the buses effectively are isolated.
78, Class II
• ESD Protection Exceeds JESD 22 The SN74AVC16T245 control pins (1DIR, 2DIR, 1
– 8000V Human-Body Model (A114-A) OE, and 2 OE) are supplied by VCCA.
– 200V Machine Model (A115-A) Device Information
– 1000V Charged-Device Model (C101) PART NUMBER PACKAGE(1) BODY SIZE (NOM)
2 Applications TSSOP (48) 12.50 mm × 6.10mm
TVSOP (48) 9.70 mm × 4.40mm
• Personal Electronics SN74AVC16T245
• Industrial BGA MICROSTAR
7.00 mm × 4.50mm
JUNIOR (56)
• Enterprise
• Telecom (1) For all available packages, see the orderable addendum at
the end of the data sheet.
1 24
1DIR 2DIR
48 25
1OE 2OE
47 36
1A1 2A1
2 13
1B1 2B1
To Seven Other Channels To Seven Other Channels
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AVC16T245
SCES551F – FEBRUARY 2004 – REVISED MARCH 2024 www.ti.com
Table of Contents
1 Features............................................................................1 8 Detailed Description......................................................14
2 Applications..................................................................... 1 8.1 Overview................................................................... 14
3 Description.......................................................................1 8.2 Functional Block Diagram......................................... 14
4 Description (continued).................................................. 3 8.3 Feature Description...................................................14
5 Pin Configuration and Functions...................................4 8.4 Device Functional Modes..........................................15
6 Specifications.................................................................. 6 9 Application and Implementation.................................. 16
6.1 Absolute Maximum Ratings........................................ 6 9.1 Application Information............................................. 16
6.2 ESD Ratings............................................................... 6 9.2 Typical Application.................................................... 17
6.3 Recommended Operating Conditions.........................7 9.3 Power Supply Recommendations.............................18
6.4 Thermal Information....................................................7 9.4 Layout....................................................................... 18
6.5 Electrical Characteristics.............................................8 10 Device and Documentation Support..........................20
6.6 Switching Characteristics: VCCA = 1.2 V..................... 9 10.1 Documentation Support.......................................... 20
6.7 Switching Characteristics: VCCA = 1.5 V ± 0.1 V.........9 10.2 Support Resources................................................. 20
6.8 Switching Characteristics: VCCA = 1.8 V ± 0.15 V.......9 10.3 Trademarks............................................................. 20
6.9 Switching Characteristics: VCCA = 2.5 V ± 0.2 V.......10 10.4 Electrostatic Discharge Caution..............................20
6.10 Switching Characteristics: VCCA = 3.3 V ± 0.3 V.....10 10.5 Glossary..................................................................20
6.11 Operating Characteristics........................................10 11 Revision History.......................................................... 20
6.12 Typical Characteristics............................................ 11 12 Mechanical, Packaging, and Orderable
7 Parameter Measurement Information.......................... 13 Information.................................................................... 21
2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: SN74AVC16T245

SN74AVC16T245
www.ti.com SCES551F – FEBRUARY 2004 – REVISED MARCH 2024
4 Description (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCCA through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

SN74AVC16T245
5 Pin Configuration and Functions

1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
Figure 5-1. GQL or ZQL Package 56-Pin BGA MICROSTAR JUNIOR Top View
1DIR 1 48 1OE
1B1 2 47 1A1
1B2 3 46 1A2
GND 4 45 GND
1B3 5 44 1A3
1B4 6 43 1A4
VCCB 7 42 VCCA
1B5 8 41 1A5
1B6 9 40 1A6
GND 10 39 GND
1B7 11 38 1A7
1B8 12 37 1A8
2B1 13 36 2A1
2B2 14 35 2A2
GND 15 34 GND
2B3 16 33 2A3
2B4 17 32 2A4
VCCB 18 31 VCCA
2B5 19 30 2A5
2B6 20 29 2A6
GND 21 28 GND
2B7 22 27 2A7
2B8 23 26 2A8
2DIR 24 25 2OE
Figure 5-2. DGG or DGV Package 48-Pin TSSOP or TVSOP Top View

SN74AVC16T245
Pin Functions
PIN
TSSOP, BGA I/O DESCRIPTION
NAME
TVSOP MICROSTAR
1DIR, 2DIR 1, 24 A1, K1 I Direction-control signal
2, 3, 5, 6, 8, 9, B2, B1, C2, C1,
1B1 to 1B8 I/O Input/Output. Referenced to VCCB
11, 12 D2, D1, E2, E1
13, 14, 16, 17, F1, F2, G1, G2,
2B1 to 2B8 I/O Input/Output. Referenced to VCCB
19, 20, 22, 23 H1, H2, J1, J2
4, 10, 15, 21, B3, D3, G3, J3,
GND — Ground
45, 39, 34, 28 J4, G4, D4, B4
VCCB 7, 18 C3, H3 — B-port supply voltage. 1.2 V ≤ VCCB ≤ 3.6 V
Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State
1 OE, 2 OE 48, 25 A6, K6 —
mode. Referenced to VCCA
47, 46, 44, 43, B5, B6, C5, C6,
1A1 to 1A8 I/O Input/Output. Referenced to VCCA
41, 40, 38, 37 D5, D6, E5, E6
36, 35, 33, 32, F6, F5, G6, G5,
2A1 to 2A8 I/O Input/Output. Referenced to VCCA
30, 29, 27, 26 H6, H5, J6, J5
VCCA 42, 31 C4, H4 — A-port supply voltage. 1.2 V ≤ VCCB ≤ 3.6 V
A2, A3, A4, A5,
N.C. — — No internal connection
K2, K3, K4, K5

SN74AVC16T245
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCCA
Supply voltage –0.5 4.6 V
VCCB
I/O ports (A port) –0.5 4.6
VI Input voltage(2) I/O ports (B port) –0.5 4.6 V
Control inputs –0.5 4.6
Voltage range applied to any output in the high-impedance or power- A port –0.5 4.6
VO V
off state(2) B port –0.5 4.6
A port –0.5 VCCA + 0.5
VO Voltage range applied to any output in the high or low state(2) (3) V
B port –0.5 VCCB + 0.5
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through each VCCA, VCCB, and GND ±100 mA
DGG package 70
RθJA Package thermal impedance(4) DGV package 58 °C/W
GQL/ZQL package 42
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input voltage (VI ) and output negative-voltage ( VO) ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±8000
Charged-device model (CDM), per JEDEC specification JESD22-
V(ESD) Electrostatic discharge ±1000 V
C101(2)
Machine model (A115-A) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.

SN74AVC16T245
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
VCCI VCCO MIN MAX UNIT
VCCA Supply voltage 1.2 3.6 V
VCCB Supply voltage 1.2 3.6 V
1.2 V to 1.95 V VCCI × 0.65
High-level
VIH Data inputs(4) 1.95 V to 2.7 V 1.6 V
input voltage
2.7 V to 3.6 V 2
1.2 V to 1.95 V VCCI × 0.35
Low-level
VIL Data inputs(4) 1.95 V to 2.7 V 0.7 V
input voltage
2.7 V to 3.6 V 0.8
1.2 V to 1.95 V VCCA × 0.65
DIR
High-level
VIH (referenced to 1.95 V to 2.7 V 1.6 V
input voltage
VCCA)(5)
2.7 V to 3.6 V 2
1.2 V to 1.95 V VCCA × 0.35
DIR
Low-level
VIL (referenced to 1.95 V to 2.7 V 0.7 V
input voltage
VCCA)(5)
2.7 V to 3.6 V 0.8
VI Input voltage 0 3.6 V
Active state 0 VCCO
VO Output voltage V
Tri-State 0 3.6
1.2 V –3
1.4 V to 1.6 V –6
IOH High-level output current 1.65 V to 1.95 V –8 mA
2.3 V to 2.7 V –9
3 V to 3.6 V –12
1.2 V 3
1.4 V to 1.6 V 6
IOL Low-level output current 1.65 V to 1.95 V 8 mA
2.3 V to 2.7 V 9
3 V to 3.6 V 12
Δt/Δv Input transition rise or fall rate 5 ns/V
TA Operating free-air temperature –40 85 °C
(1) VCCI is the VCC associated with the data input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
(4) For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
(5) For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
6.4 Thermal Information

SN74AVC16T245
DGV DGG ZQL
THERMAL METRIC(1) UNIT
(TVSOP) (TSSOP) (BGA MICROSTAR JUNIOR)
48 PINS 48 PINS 56 PINS
RθJA Junction-to-ambient thermal resistance 82.5 69.9 64.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34.2 23.9 16.6 °C/W
RθJB Junction-to-board thermal resistance 45.1 36.6 30.8 °C/W
ψJT Junction-to-top characterization parameter 2.7 1.7 0.9 °C/W

SN74AVC16T245
6.4 Thermal Information (continued)

SN74AVC16T245
DGV DGG ZQL
THERMAL METRIC(1) UNIT
(TVSOP) (TSSOP) (BGA MICROSTAR JUNIOR)
48 PINS 48 PINS 56 PINS
ψJB Junction-to-board characterization parameter 44.6 36.2 64.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)(1) (2)
TA = 25°C TA = –40°C to 85°C
PARAMETER TEST CONDITIONS VCCA VCCB UNIT
MIN TYP MAX MIN TYP MAX
IOH = –100 μA 1.2 V to 3.6 V 1.2 V to 3.6 V VCCO – 0.2
IOH = –3 mA 1.2 V 1.2 V 0.95
IOH = –6 mA 1.4 V 1.4 V 1.05
VOH VI = VIH V
IOH = –8 mA 1.65 V 1.65 V 1.2
IOH = –9 mA 2.3 V 2.3 V 1.75
IOH = –12 mA 3V 3V 2.3
IOL = 100 μA 1.2 V to 3.6 V 1.2 V to 3.6 V 0.2
IOL = 3 mA 1.2 V 1.2 V 0.15
IOL = 6 mA 1.4 V 1.4 V 0.35
VOL VI = VIL V
IOL = 8 mA 1.65 V 1.65 V 0.45
IOL = 9 mA 2.3 V 2.3 V 0.55
IOL = 12 mA 3V 3V 0.7
Control
II VI = VCCA or GND 1.2 V to 3.6 V 1.2 V to 3.6 V ±0.025 ±0.25 ±1 μA
inputs
A or B port 0V 0 to 3.6 V ±0.1 ±2.5 ±5
Ioff VI or VO = 0 to 3.6 V μA
A or B port 0 to 3.6 V 0V ±0.5 ±2.5 ±5
VO = VCCO or GND,
IOZ (3) A or B port VI = VCCI or GND, 3.6 V 3.6 V ±0.5 ±2.5 ±5 μA
OE =VIH
1.2 V to 3.6 V 1.2 V to 3.6 V 25
VI = VCCI or GND,
ICCA 0V 3.6 V –5 μA
IO = 0
3.6 V 0V 25
1.2 V to 3.6 V 1.2 V to 3.6 V 25
VI = VCCI or GND,
ICCB 0V 3.6 V 25 μA
IO = 0
3.6 V 0V –5
VI = VCCI or GND,
ICCA + ICCB 1.2 V to 3.6 V 1.2 V to 3.6 V 45 μA
IO = 0
Control
Ci VI = 3.3 V or GND 3.3 V 3.3 V 3.5 pF
inputs
Cio A or B port VO = 3.3 V or GND 3.3 V 3.3 V 7 pF
(1) VCCO is the VCC associated with the output port.

(2) VCCI is the VCC associated with the input port.
(3) For I/O ports, the parameter IOZ includes the input leakage current.

SN74AVC16T245
6.6 Switching Characteristics: VCCA = 1.2 V

over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 7-1)
FROM TO VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V
PARAMETER UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
tPLH 4.1 3.3 3 2.8 3.2
A B ns
tPHL 4.1 3.3 3 2.8 3.2
tPLH 4.4 4 3.8 3.6 3.5
B A ns
tPHL 4.4 4 3.8 3.6 3.5
tPZH 6.4 6.4 6.4 6.4 6.4
OE A ns
tPZL 6.4 6.4 6.4 6.4 6.4
tPZH 6 4.6 4 3.4 3.2
OE B ns
tPZL 6 4.6 4 3.4 3.2
tPHZ 6.6 6.6 6.6 6.6 6.8
OE A ns
tPLZ 6.6 6.6 6.6 6.6 6.8
tPHZ 6 4.9 4.9 4.2 5.3
OE B ns
tPLZ 6 4.9 4.9 4.2 5.3
6.7 Switching Characteristics: VCCA = 1.5 V ± 0.1 V

over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 7-1)
FROM TO VCCB = 1.2 V VCCB = 1.5 V ± 0.1 V VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V
PARAMETER UNIT
tPLH 3.6 0.5 6.2 0.5 5.2 0.5 4.1 0.5 3.7
A B ns
tPHL 3.6 0.5 6.2 0.5 5.2 0.5 4.1 0.5 3.7
tPLH 3.3 0.5 6.2 0.5 5.9 0.5 5.6 0.5 5.5
B A ns
tPHL 3.3 0.5 6.2 0.5 5.9 0.5 5.6 0.5 5.5
tPZH 4.3 1 10.1 1 10.1 1 10.1 1 10.1
OE A ns
tPZL 4.3 1 10.1 1 10.1 1 10.1 1 10.1
tPZH 5.6 1 10.1 0.5 8.1 0.5 5.9 0.5 5.2
OE B ns
tPZL 5.6 1 10.1 0.5 8.1 0.5 5.9 0.5 5.2
tPHZ 4.5 1.5 9.1 1.5 9.1 1.5 9.1 1.5 9.1
OE A ns
tPLZ 4.5 1.5 9.1 1.5 9.1 1.5 9.1 1.5 9.1
tPHZ 5.5 1.5 8.7 1.5 7.5 1 6.5 1 6.3
OE B ns
tPLZ 5.5 1.5 8.7 1.5 7.5 1 6.5 1 6.3

PARAMETER UNIT
tPLH 3.4 0.5 5.9 0.5 4.8 0.5 3.7 0.5 3.3
A B ns
tPHL 3.4 0.5 5.9 0.5 4.8 0.5 3.7 0.5 3.3
tPLH 3 0.5 5.2 0.5 4.8 0.5 4.5 0.5 4.4
B A ns
tPHL 3 0.5 5.2 0.5 4.8 0.5 4.5 0.5 4.4
tPZH 3.4 1 7.8 1 7.8 1 7.8 1 7.8
OE A ns
tPZL 3.4 1 7.8 1 7.8 1 7.8 1 7.8
tPZH 5.4 1 9.2 0.5 7.4 0.5 5.3 0.5 4.5
OE B ns
tPZL 5.4 1 9.2 0.5 7.4 0.5 5.3 0.5 4.5
tPHZ 4.2 1.5 7.7 1.5 7.7 1.5 7.7 1.5 7.7
OE A ns
tPLZ 4.2 1.5 7.7 1.5 7.7 1.5 7.7 1.5 7.7
tPHZ 5.2 1.5 8.4 1.5 7.1 1 5.9 1 5.7
OE B ns
tPLZ 5.2 1.5 8.4 1.5 7.1 1 5.9 1 5.7

SN74AVC16T245

PARAMETER UNIT
tPLH 3.2 0.5 5.6 0.5 4.5 0.5 3.3 0.5 2.8
A B ns
tPHL 3.2 0.5 5.6 0.5 4.5 0.5 3.3 0.5 2.8
tPLH 2.6 0.5 4.1 0.5 3.7 0.5 3.3 0.5 3.2
B A ns
tPHL 2.6 0.5 4.1 0.5 3.7 0.5 3.3 0.5 3.2
tPZH 2.5 0.5 5.3 0.5 5.3 0.5 5.3 0.5 5.3
OE A ns
tPZL 2.5 0.5 5.3 0.5 5.3 0.5 5.3 0.5 5.3
tPZH 5.2 0.5 9.4 0.5 7.3 0.5 5.1 0.5 4.5
OE B ns
tPZL 5.2 0.5 9.4 0.5 7.3 0.5 5.1 0.5 4.5
tPHZ 3 1 6.1 1 6.1 1 6.1 1 6.1
OE A ns
tPLZ 3 1 6.1 1 6.1 1 6.1 1 6.1
tPHZ 5 1 7.9 1 6.6 1 6.1 1 5.2
OE B ns
tPLZ 5 1 7.9 1 6.6 1 6.1 1 5.2

PARAMETER UNIT
tPLH 3.2 0.5 5.5 0.5 4.4 0.5 3.2 0.5 2.7
A B ns
tPHL 3.2 0.5 5.5 0.5 4.4 0.5 3.2 0.5 2.7
tPLH 2.8 0.5 3.7 0.5 3.3 0.5 2.8 0.5 2.7
B A ns
tPHL 2.8 0.5 3.7 0.5 3.3 0.5 2.8 0.5 2.7
tPZH 2.2 0.5 4.3 0.5 4.2 0.5 4.1 0.5 4
OE A ns
tPZL 2.2 0.5 4.3 0.5 4.2 0.5 4.1 0.5 4
tPZH 5.1 0.5 9.3 0.5 7.2 0.5 4.9 0.5 4
OE B ns
tPZL 5.1 0.5 9.3 0.5 7.2 0.5 4.9 0.5 4
tPHZ 3.4 0.5 5 0.5 5 0.5 5 0.5 5
OE A ns
tPLZ 3.4 0.5 5 0.5 5 0.5 5 0.5 5
tPHZ 4.9 1 7.7 1 6.5 1 5.2 0.5 5
OE B ns
tPLZ 4.9 1 7.7 1 6.5 1 5.2 0.5 5
6.11 Operating Characteristics

TA = 25°C
VCCA = VCCB = 1.2
TEST VCCA = VCCB = 1.5 V VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V VCCA = VCCB = 3.3 V
PARAMETER V UNIT
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Outputs
1 1 1 1 2
enabled
A to B
Outputs
CL = 0, 1 1 1 1 1
disabled
CpdA (1) f = 10 MHz, pF
Outputs tr = tf = 1 ns 13 13 14 15 16
enabled
B to A
Outputs
1 1 1 1 1
disabled
Outputs
13 13 14 15 16
enabled
A to B
Outputs
CL = 0, 1 1 1 1 1
disabled
CpdB (1) f = 10 MHz, pF
Outputs tr = tf = 1 ns 1 1 1 1 2
enabled
B to A
Outputs
1 1 1 1 1
disabled
(1) Power dissipation capacitance per transceiver. Refer to the TI application report, CMOS Power Consumption and Cpd Calculation,
SCAA035

SN74AVC16T245
6.12 Typical Characteristics

TA = 25°C
6 6
5 5
tPHL − Propagation Delay − ns

tPLH − Propagation Delay − ns
4 4
3 3
2 2
VCCB = 1.2 V VCCB = 1.2 V
1 VCCB = 1.8 V 1 VCCB = 1.8 V
0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
CL − Load Capacitance − pF CL − Load Capacitance − pF
VCCA = 1.2 V VCCA = 1.2 V

Figure 6-1. Typical Propagation Delay tPLH (A to B) vs Load Figure 6-2. Typical Propagation Delay tPHL (A to B) vs Load
Capacitance Capacitance
6 6
5 5

4 4
3 3
2 2
1 VCCB = 1.8 V 1 VCCB = 1.8 V
0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60

6 6
5 5
4 4
3 3
2 2
1 VCCB = 1.8 V 1 VCCB = 1.8 V
0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60

SN74AVC16T245
6.12 Typical Characteristics (continued)

TA = 25°C
6 6
VCCB = 1.2 V
VCCB = 1.5 V
5 VCCB = 1.8 V
5
VCCB = 2.5 V

VCCB = 3.3 V
4 4
3 3
2 2
VCCB = 1.2 V
VCCB = 1.5 V
1 VCCB = 1.8 V 1
VCCB = 2.5 V
VCCB = 3.3 V
0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
6 6
VCCB = 1.2 V
VCCB = 1.5 V
5 5 VCCB = 1.8 V
VCCB = 2.5 V
tPHL − Propagation Delay − ns VCCB = 3.3 V

4 4
3 3
2 2
VCCB = 1.2 V
VCCB = 1.5 V
1 VCCB = 1.8 V 1
VCCB = 2.5 V
VCCB = 3.3 V
0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60

SN74AVC16T245
7 Parameter Measurement Information

2 × VCCO
TEST S1
RL S1 Open tpd Open
From Output
GND tPLZ/tPZL 2 × VCCO
Under Test
tPHZ/tPZH GND
CL RL
(see Note A)
LOAD CIRCUIT tw
VCCI
Input VCCI/2 VCCI/2
VCCO CL RL VTP 0V
1.2 V 15 pF 2 kW 0.1 V
VOLTAGE WAVEFORMS
1.5 V ± 0.1 V 15 pF 2 kW 0.1 V PULSE DURATION
1.8 V ± 0.15 V 15 pF 2 kW 0.15 V
2.5 V ± 0.2 V 15 pF 2 kW 0.15 V
3.3 V ± 0.3 V 15 pF 2 kW 0.3 V VCCA
Output
Control VCCA/2 VCCA/2
(low-level
enabling) 0V
tPZL tPLZ
Output VCCO
VCCI
Input VCCI/2 VCCI/2 Waveform 1 VCCO/2 VOL + VTP
S1 at 2 × VCCO VOL
0V
(see Note B)
tPLH tPHL tPZH tPHZ
Output
VOH
VOH Waveform 2 VOH − VTP
S1 at GND VCCO/2
Output VCCO/2 VCCO/2
(see Note B) 0V
VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t PLH and tPHL are the same as tpd.
F. VCCI is the VCC associated with the input port.
G. VCCO is the VCC associated with the output port.
Figure 7-1. Load Circuit and Voltage Waveforms

SN74AVC16T245
8 Detailed Description
8.1 Overview
The SN74AVC16T245 is a 16-bit, dual-supply noninverting bidirectional voltage level translation. Pins A and
control pins (DIR and OE) are supported by VCCA and pins B are supported by VCCB. The A port can accept I/O
voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.2 V to 3.6 V. A high on DIR
allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to
low. When OE is set to high, both A and B are in the high-impedance state.
This device is fully specified for partial-power-down applications using off output current (Ioff).
The VCC isolation feature ensures that if either VCC input is at GND, both ports are put in a high-impedance
state.
8.2 Functional Block Diagram
1 24
1DIR 2DIR
48 25
1OE 2OE
47 36
1A1 2A1
2 13
1B1 2B1
To Seven Other Channels To Seven Other Channels
8.3 Feature Description

8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full
1.2-V to 3.6-V Power-Supply Range
Both VCCA and VCCB can be supplied at any voltage from 1.2 V to 3.6 V making the device suitable for translating
between any of the low voltage nodes (1.2 V, 1.8 V, 2.5 V, and 3.3 V).
8.3.2 Partial-Power-Down Mode Operation
This device is fully specified for partial-power-down applications using off output current (Ioff). The Ioff circuitry will
prevent backflow current by disabling I/O output circuits when device is in partial power-down mode.
8.3.3 VCC Isolation
The VCC isolation feature ensures that if either VCCA or VCCB are at GND, both ports will be in a high-impedance
state (IOZ shown in Section 6.5). This prevents false logic levels from being presented to either bus.

SN74AVC16T245
8.4 Device Functional Modes

The SN74AVC16T245 is a voltage level translator that can operate from 1.2 V to 3.6 V (VCCA) and 1.2 V to 3.6
V (VCCB). The signal translation between 1.2 V and 3.6 V requires direction control and output enable control.
When OE is low and DIR is high, data transmission is from A to B. When OE is low and DIR is low, data
transmission is from B to A. When OE is high, both output ports will be high-impedance.
Table 8-1. Functions Table
CONTROL INPUTS(1) OUTPUT CIRCUITS
OPERATION
OE DIR A PORT B PORT
L L Enabled Hi-Z B data to A bus
L H Hi-Z Enabled A data to B bus
H X Hi-Z Hi-Z Isolation
(1) Input circuits of the data I/Os always are active.

SN74AVC16T245
9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information

The SN74AVC16T245 device can be used in level-shifting applications for interfacing devices and addressing
mixed voltage incompatibility. The SN74AVC16T245 device is ideal for data transmission where direction is
different for each channel.
9.1.1 Enable Times
Calculate the enable times for the SN74AVC16T45 using the following formulas:
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) (1)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) (2)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) (3)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) (4)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVC16T245 initially is transmitting from A to B,
then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After
the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.

SN74AVC16T245
9.2 Typical Application

1.8 V 3.3 V
0.1 µF 0.1 µF 1 µF
VCCA VCCB
1DIR/2DIR
1OE/2OE
1.8-V 3.3-V
SN74AVC16T245
Controller System
1A1/2A1 1B1/2B1
1A2/2A2 1B2/2B2
1A3/2A3 1B3/2B3
1A4/2A4 1B4/2B4
Data Data
1A5/2A5 1B5/2B5
1A6/2A6 1B6/2B6
1A7/2A7 1B7/2B7
1A8/2A8 1B8/2B8
GND GND GND
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements

This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the
intended flow of data and take care not to violate any of the high or low logic levels. Unused data inputs must not
be floating, as this can cause excessive internal leakage on the input CMOS structure. Tie any unused input and
output ports directly to ground.
For this design example, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 1.2 V to 3.6 V
Output voltage range 1.2 V to 3.6 V

SN74AVC16T245
9.2.2 Detailed Design Procedure

To begin the design process, determine the following:
9.2.2.1 Input Voltage Ranges
Use the supply voltage of the device that is driving the SN74AVC16T245 device to determine the input voltage
range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must
be less than the VIL of the input port.
9.2.2.2 Output Voltage Range
Use the supply voltage of the device that the SN74AVC16T245 device is driving to determine the output voltage
range.
9.2.3 Application Curve
Input (1.2 V)
Output (3.3 V)
Figure 9-2. Translation Up (1.2 V to 3.3 V) at 2.5 MHz
9.3 Power Supply Recommendations

The SN74AVC16T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts
any supply voltage from 1.2 V to 3.6 V and VCCB accepts any supply voltage from 1.2 V to 3.6 V. The A port
and B port are designed to track VCCA and VCCB, respectively, allowing for low-voltage bidirectional translation
between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.3-V voltage nodes.
The output-enable OE input circuit is designed so that it is supplied by VCCA and when the OE input is high, all
outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power
up or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be enabled until
VCCA and VCCB are fully ramped and stable. The minimum value of the pullup resistor to VCCA is determined by
the current-sinking capability of the driver.
9.4 Layout
9.4.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit-board layout guidelines is recommended.
• Bypass capacitors should be used on power supplies.
• Short trace lengths should be used to avoid excessive loading.
• Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals depending on the system requirements.

SN74AVC16T245
9.4.2 Layout Example

LEGEND
VIA to Power Plane Polygonal Copper Pour
VIA to GND Plane (Inner Layer)
Keep OE high until VCCA and

VCCB are powered up
VCCA
1 1DIR 1OE 48
VCCA
From
To 2 1B1 1A1 47 Controller
System
To From
3 1B2 1A2 46
System Controller
4 GND GND 45
To From
5 1B3 1A3 44
System Controller
VCCB To From VCCA

6 1B4 1A4 43
System Controller
7 VCCB VCCA 42
Bypass Capacitor
From
To 8 1B5 1A5 41
Controller
System
From
System
10 GND GND 39
From
System
From
System
To SN74AVCH16T245 From
13 2B1 2A1 36
System Controller
From
System
15 GND GND 34
To 16 33 From
2B3 2A3
System Controller
To 17 32 From VCCA
VCCB 2B4 2A4
System Controller
18 VCCB VCCA 31
Bypass Capacitor
From
To 19 31 Controller
2B5 2A5
System
From
System
21 GND GND 28
To From
22 2B7 2A7 27
System Controller
From
To 23 2B8 26
2A8 Controller
System
VCCA
24 2DIR 2OE
VCCA
25
Keep OE high until VCCA and

VCCB are powered up
Figure 9-3. Recommended Layout Example

SN74AVC16T245
10 Device and Documentation Support

10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• CMOS Power Consumption and Cpd Calculation, SCAA035
• Implications of Slow or Floating CMOS Inputs, SCBA004
10.1.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
11 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (July 2015) to Revision F (March 2024) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 4
Changes from Revision D (February 2015) to Revision E (July 2015) Page

• Updated Pin Functions Table. ............................................................................................................................4
Changes from Revision C (August 2005) to Revision D (February 2015) Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1

SN74AVC16T245
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 27-Feb-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
74AVC16T245DGVRE4 ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WF245 Samples
AVC16T245DGGR-D ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AVC16T245 Samples
SN74AVC16T245DGG ACTIVE TSSOP DGG 48 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AVC16T245 Samples
SN74AVC16T245DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AVC16T245 Samples
SN74AVC16T245DGVR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 WF245 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AVC16T245 :
• Automotive : SN74AVC16T245-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AVC16T245DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
SN74AVC16T245DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AVC16T245DGGR TSSOP DGG 48 2000 367.0 367.0 45.0
SN74AVC16T245DGVR TVSOP DGV 48 2000 356.0 356.0 35.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74AVC16T245DGG DGG TSSOP 48 40 530 11.89 3600 4.9
PACKAGE OUTLINE
DGG0048A SCALE 1.350
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
C
8.3 SEATING PLANE
TYP
7.9
PIN 1 ID 0.1 C
A
AREA
46X 0.5
48
1
12.6 2X
12.4 11.5
NOTE 3
24
25
0.27
48X
6.2 0.17 1.2
B
6.0 0.08 C A B 1.0
(0.15) TYP
0.25
SEE DETAIL A GAGE PLANE
0.15
0 -8 0.75 0.05
0.50
DETAIL A
TYPICAL
4214859/B 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0048A TSSOP - 1.2 mm max height
48X (1.5) SYMM

1
48
48X (0.3)
46X (0.5)
(R0.05) SYMM
TYP
24 25
(7.5)
LAND PATTERN EXAMPLE

SCALE:6X
SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214859/B 11/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0048A TSSOP - 1.2 mm max height
48X (1.5) SYMM

1
48
48X (0.3)
46X (0.5)
SYMM
(R0.05) TYP
24 25
(7.5)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4214859/B 11/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN
0,27
0,50 0,08 M
0,17
48 25
6,20 8,30
6,00 7,90 0,15 NOM
Gage Plane
0,25
1 24
0°– 8°
A 0,75
0,50
Seating Plane
0,15
1,20 MAX 0,10
0,05
PINS **
48 56 64
DIM
A MAX 12,60 14,10 17,10
A MIN 12,40 13,90 16,90
4040078 / F 12/97
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated

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SN74AVC16T245

SCES551F – FEBRUARY 2004 – REVISED MARCH 2024

SN74AVC16T245 16-Bit Dual-Supply Bus Transceiver

To Seven Other Channels To Seven Other Channels

Logic Diagram (Positive Logic)

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Product Folder Links: SN74AVC16T245

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

5 Pin Configuration and Functions

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6.2 ESD Ratings

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6.3 Recommended Operating Conditions

6.4 Thermal Information

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6.4 Thermal Information (continued)

6.5 Electrical Characteristics

(1) VCCO is the VCC associated with the output port.

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6.6 Switching Characteristics: VCCA = 1.2 V

6.7 Switching Characteristics: VCCA = 1.5 V ± 0.1 V

6.8 Switching Characteristics: VCCA = 1.8 V ± 0.15 V

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9

6.9 Switching Characteristics: VCCA = 2.5 V ± 0.2 V

6.10 Switching Characteristics: VCCA = 3.3 V ± 0.3 V

6.11 Operating Characteristics

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Product Folder Links: SN74AVC16T245

6.12 Typical Characteristics

tPHL − Propagation Delay − ns

VCCA = 1.2 V VCCA = 1.2 V

tPHL − Propagation Delay − ns

CL − Load Capacitance − pF CL − Load Capacitance − pF

VCCA = 1.5 V VCCA = 1.5 V

tPHL − Propagation Delay − ns

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11

6.12 Typical Characteristics (continued)

tPHL − Propagation Delay − ns

CL − Load Capacitance − pF CL − Load Capacitance − pF

VCCA = 2.5 V VCCA = 2.5 V

tPHL − Propagation Delay − ns VCCB = 3.3 V

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7 Parameter Measurement Information

NOTES: A. CL includes probe and jig capacitance.

Figure 7-1. Load Circuit and Voltage Waveforms

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To Seven Other Channels To Seven Other Channels

8.3 Feature Description

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8.4 Device Functional Modes

(1) Input circuits of the data I/Os always are active.

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9 Application and Implementation