Network-on-Chip The Next Generation of System-on-C

Network-on-Chip
The
Next Generation
of System-on-Chip
Integration
Santanu Kundu
Santanu Chattopadhyay
Network-on-Chip
The Next Generation
of System-on-Chip
Integration
Network-on-Chip
The Next Generation
of System-on-Chip
Integration
Santanu Kundu
CRC Press
Taylor & Francis Group
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Contents
Preface.................................................................................................................... xiii
Authors................................................................................................................. xvii
1. Introduction......................................................................................................1
1.1 System-on-Chip Integration and Its Challenges............................... 1
1.2 SoC to Network-on-Chip: A Paradigm Shift..................................... 3
1.3 Research Issues in NoC Development................................................5
1.4 Existing NoC Examples........................................................................ 8
1.5 Summary............................................................................................... 10
References........................................................................................................ 10
2. Interconnection Networks in Network-on-Chip.................................... 13

2.1 Introduction.......................................................................................... 13
2.2 Network Topologies............................................................................. 14
2.2.1 Number of Edges.................................................................... 25
2.2.2 Average Distance.................................................................... 25
2.3 Switching Techniques......................................................................... 29
2.4 Routing Strategies................................................................................ 30
2.4.1 Routing-Dependent Deadlock.............................................. 31
2.4.1.1 Deterministic Routing in M × N MoT
Network................................................................33
2.4.2 Avoidance of Message-Dependent Deadlock..................... 41
2.5 Flow Control Protocol.........................................................................43
2.6 Quality-of-Service Support................................................................. 45
2.7 NI Module............................................................................................. 46
2.8 Summary............................................................................................... 48
References........................................................................................................ 48
3. Architecture Design of Network-on-Chip............................................... 53

3.1 Introduction.......................................................................................... 53
3.2 Switching Techniques and Packet Format....................................... 53
3.3 Asynchronous FIFO Design...............................................................54
3.4 GALS Style of Communication.......................................................... 57
3.5 Wormhole Router Architecture Design............................................ 57
3.5.1 Input Channel Module........................................................... 58
3.5.2 Output Channel Module....................................................... 58
3.6 VC Router Architecture Design.........................................................63
3.6.1 Input Channel Module...........................................................65
3.6.2 Output Links........................................................................... 66
v
vi Contents
3.6.2.1 VC Allocator............................................................. 66
3.6.2.2 Switch Allocator...................................................... 69
3.7 Adaptive Router Architecture Design.............................................. 70
3.8 Summary............................................................................................... 73
References........................................................................................................ 73
4. Evaluation of Network-on-Chip Architectures....................................... 75

4.1 Evaluation Methodologies of NoC.................................................... 75
4.1.1 Performance Metrics.............................................................. 78
4.1.2 Cost Metrics.............................................................................80
4.2 Traffic Modeling................................................................................... 81
4.3 Selection of Channel Width and Flit Size.........................................84
4.4 Simulation Results and Analysis of MoT Network
with WH Router...................................................................................84
4.4.1 Accepted Traffic versus Offered Load................................. 85
4.4.2 Throughput versus Locality Factor...................................... 85
4.4.3 Average Overall Latency at Different Locality Factors..... 86
4.4.4 Energy Consumption at Different Locality Factors........... 88
4.5 Impact of FIFO Size and Placement in Energy and
Performance of a Network.................................................................. 90
4.6 Performance and Cost Comparison of MoT with Other NoC
Structures Having WH Router under Self-Similar Traffic............. 93
4.6.1 Network Area Estimation...................................................... 94
4.6.2 Network Aspect Ratio............................................................ 96
4.6.3 Performance Comparison...................................................... 97
4.6.3.1 Accepted Traffic versus Offered Load................. 97
4.6.3.2 Throughput versus Locality Factor...................... 98
4.6.3.3 Average Overall Latency under
Localized Traffic................................................... 99
4.6.4 Comparison of Energy Consumption................................ 102
4.7 Simulation Results and Analysis of MoT
Network with Virtual Channel Router........................................... 103
4.7.1 Throughput versus Offered Load...................................... 104
4.7.2 Latency versus Offered Load.............................................. 104
4.7.3 Energy Consumption........................................................... 105
4.7.4 Area Required....................................................................... 108
4.8 Performance and Cost Comparison of MoT with Other
NoC Structures Having VC Router................................................. 109
4.8.1 Accepted Traffic versus Offered Load............................... 109
4.8.2 Throughput versus Locality Factor.................................... 109
4.8.3 Average Overall Latency under Localized Traffic........... 110
4.8.4 Energy Consumption........................................................... 111
4.8.5 Area Overhead...................................................................... 113
4.9 Limitations of Tree-Based Topologies............................................. 114
Contents vii
4.10 Summary............................................................................................. 115

References...................................................................................................... 116
5. Application Mapping on Network-on-Chip.......................................... 119

5.1 Introduction........................................................................................ 119
5.2 Mapping Problem.............................................................................. 120
5.3 ILP Formulation................................................................................. 123
5.3.1 Other ILP Formulations....................................................... 127
5.4 Constructive Heuristics for Application Mapping....................... 128
5.4.1 Binomial Merging Iteration................................................. 130
5.4.2 Topology Mapping and Traffic Surface Creation............. 131
5.4.3 Hardware Cost Optimization............................................. 132
5.5 Constructive Heuristics with Iterative Improvement................... 134
5.5.1 Initialization Phase............................................................... 134
5.5.2 Shortest Path Computation.................................................. 135
5.5.3 Iterative Improvement Phase.............................................. 136
5.5.4 Other Constructive Strategies............................................. 137
5.6 Mapping Using Discrete PSO.......................................................... 141
5.6.1 Particle Structure.................................................................. 141
5.6.2 Evolution of Generations..................................................... 142
5.6.3 Convergence of DPSO.......................................................... 143
5.6.4 Overall PSO Algorithm........................................................ 144
5.6.5 Augmentations to the DPSO............................................... 144
5.6.5.1 Multiple PSO.......................................................... 144
5.6.5.2 Initial Population Generation.............................. 145
5.6.6 Other Evolutionary Approaches......................................... 148
5.7 Summary............................................................................................. 150
References...................................................................................................... 150
6. Low-Power Techniques for Network-on-Chip...................................... 155

6.1 Introduction........................................................................................ 155
6.2 Standard Low-Power Methods for NoC Routers.......................... 158
6.2.1 Clock Gating.......................................................................... 158
6.2.2 Gate Level Power Optimization......................................... 159
6.2.3 Multivoltage Design............................................................. 160
6.2.3.1 Challenges in Multivoltage Design.................... 161
6.2.4 Multi-VT Design..................................................................... 164
6.2.5 Power Gating......................................................................... 165
6.3 Standard Low-Power Methods for NoC Links.............................. 166
6.3.1 Bus Energy Model................................................................. 167
6.3.2 Low-Power Coding............................................................... 168
6.3.3 On-Chip Serialization.......................................................... 170
6.3.4 Low-Swing Signaling........................................................... 171
viii Contents
6.4 System-Level Power Reduction........................................................ 172

6.4.1 Dynamic Voltage Scaling..................................................... 172
6.4.1.1 History-Based DVS................................................ 174
6.4.1.2 Hardware Implementation.................................. 178
6.4.1.3 Results and Discussions....................................... 179
6.4.2 Dynamic Frequency Scaling............................................... 179
6.4.2.1 History-Based DFS................................................ 181
6.4.2.2 DFS Algorithm....................................................... 183
6.4.2.3 Link Controller...................................................... 183
6.4.2.4 Results and Discussions....................................... 184
6.4.3 VFI Partitioning.................................................................... 185
6.4.4 Runtime Power Gating......................................................... 186
6.5 Summary............................................................................................. 188
References...................................................................................................... 188
7. Signal Integrity and Reliability of Network-on-Chip......................... 191

7.1 Introduction........................................................................................ 191
7.2 Sources of Faults in NoC Fabric....................................................... 193
7.2.1 Permanent Faults.................................................................. 194
7.2.2 Faults due to Aging Effects................................................. 194
7.2.2.1 Negative-Bias Temperature Instability.............. 194
7.2.2.2 Hot Carrier Injection............................................. 195
7.2.3 Transient Faults..................................................................... 195
7.2.3.1 Capacitive Crosstalk............................................. 195
7.2.3.2 Soft Errors............................................................... 199
7.2.3.3 Some Other Sources of Transient Faults............ 203
7.3 Permanent Fault Controlling Techniques....................................... 204
7.4 Transient Fault Controlling Techniques......................................... 205
7.4.1 Intra-Router Error Control................................................... 205
7.4.1.1 Soft Error Correction............................................ 206
7.4.2 Inter-Router Link Error Control......................................... 210
7.4.2.1 Capacitive Crosstalk Avoidance Techniques.......210
7.4.2.2 Error Detection and Retransmission.................. 216
7.4.2.3 Error Correction.................................................... 220
7.5 Unified Coding Framework.............................................................. 221
7.5.1 Joint CAC and LPC Scheme (CAC + LPC)........................222
7.5.2 Joint LPC and ECC Scheme (LPC + ECC).........................223
7.5.3 Joint CAC and ECC Scheme (CAC + ECC)........................ 224
7.5.4 Joint CAC, LPC, and ECC Scheme
(CAC + LPC + ECC)........................................................... 227
7.6 Energy and Reliability Trade-Off in Coding Technique.............. 227
7.7 Summary............................................................................................. 230
References...................................................................................................... 231
Contents ix
8. Testing of Network-on-Chip Architectures........................................... 235

8.1 Introduction........................................................................................ 235
8.2 Testing Communication Fabric........................................................ 236
8.2.1 Testing NoC Links................................................................ 237
8.2.2 Testing NoC Switches.......................................................... 238
8.2.3 Test Data Transport.............................................................. 239
8.2.4 Test Transport Time Minimization—A Graph
Theoretic Formulation.......................................................... 241
8.2.4.1 Unicast Test Scheduling....................................... 242
8.2.4.2 Multicast Test Scheduling.................................... 244
8.3 Testing Cores...................................................................................... 245
8.3.1 Core Wrapper Design........................................................... 246
8.3.2 ILP Formulation.................................................................... 250
8.3.3 Heuristic Algorithms........................................................... 253
8.3.4 PSO-Based Strategy.............................................................. 258
8.3.4.1 Particle Structure and Fitness............................. 258
8.3.4.2 Evolution of Generations...................................... 259
8.4 Summary............................................................................................. 260
References...................................................................................................... 260
9. Application-Specific Network-on-Chip Synthesis............................... 263

9.1 Introduction........................................................................................ 263
9.2 ASNoC Synthesis Problem............................................................... 264
9.3 Literature Survey............................................................................... 265
9.4 System-Level Floorplanning............................................................ 268
9.4.1 Variables................................................................................. 268
9.4.1.1 Independent Variables.......................................... 268
9.4.1.2 Dependent Variables............................................. 268
9.4.2 Objective Function................................................................ 269
9.4.3 Constraints............................................................................. 269
9.4.4 Constraints for Mesh Topology.......................................... 270
9.5 Custom Interconnection Topology and Route Generation.......... 271
9.5.1 Variables................................................................................. 272
9.5.1.1 Independent Variables.......................................... 272
9.5.1.2 Derived Variables.................................................. 273
9.5.2 Objective Function................................................................ 273
9.5.3 Constraints............................................................................. 274
9.6 ASNoC Synthesis with Flexible Router Placement....................... 277
9.6.1 ILP for Flexible Router Placement...................................... 278
9.6.1.1 Variables................................................................. 278
9.6.1.2 Objective Function................................................ 279
9.6.1.3 Constraints............................................................. 279
x Contents
9.6.2 PSO for Flexible Router Placement................................. 281

9.6.2.1 Particle Structure and Fitness Function...... 282
9.6.2.2 Local and Global Bests................................... 282
9.6.2.3 Evolution of Generation................................. 283
9.6.2.4 Swap Operator................................................. 283
9.6.2.5 Swap Sequence................................................ 283
9.7 Summary.............................................................................................284
References......................................................................................................284
10. Reconfigurable Network-on-Chip Design............................................. 289

10.1 Introduction...................................................................................... 289
10.2 Literature Review............................................................................. 290
10.3 Local Reconfiguration Approach................................................... 291
10.3.1 Routers................................................................................ 292
10.3.2 Multiplexers....................................................................... 293
10.3.3 Selection Logic.................................................................. 294
10.3.4 Area Overhead.................................................................. 294
10.3.5 Design Flow....................................................................... 296
10.3.5.1 Construction of CCG...................................... 298
10.3.5.2 Mapping of CCG............................................. 299
10.3.5.3 Configuration Generation.............................. 299
10.3.6 ILP-Based Approach......................................................... 299
10.3.6.1 Parameters and Variables..............................300
10.3.6.2 Objective Function..........................................300
10.3.6.3 Constraints.......................................................300
10.3.7 PSO Formulation............................................................... 301
10.3.7.1 Particle Formulation and Fitness Function.... 302
10.3.8 Iterative Reconfiguration................................................. 303
10.4 Topology Reconfiguration..............................................................304
10.4.1 Modification around Routers..........................................305
10.4.2 Reconfiguration Architecture......................................... 306
10.4.2.1 Application Mapping..................................... 307
10.4.2.2 Core-to-Network Mapping............................309
10.4.2.3 Topology and Route Generation................... 310
10.5 Link Reconfiguration....................................................................... 311
10.5.1 Estimating Channel Bandwidth Utilization................. 311
10.6 Summary........................................................................................... 312
References...................................................................................................... 314
11. Three-Dimensional Integration of Network-on-Chip......................... 317

11.1 Introduction...................................................................................... 317
11.2 3D Integration: Pros and Cons....................................................... 318
11.2.1 Opportunities of 3D Integration..................................... 319
11.2.2 Challenges of 3D Integration.......................................... 321
Contents xi
11.3 Design and Evaluation of 3D NoC Architecture......................... 323

11.3.1 3D Mesh-of-Tree Topology............................................... 326
11.3.1.1 Number of Directed Edges............................ 326
11.3.1.2 Average Distance............................................ 327
11.3.2 Performance and Cost Evaluation.................................. 331
11.3.2.1 Network Area Estimation.............................. 336
11.3.2.2 Network Aspect Ratio.................................... 339
11.3.3 Simulation Results with Self-Similar Traffic.................340
11.3.3.1 Accepted Traffic versus Offered Load.........340
11.3.3.2 Throughput versus Locality Factor.............. 341
11.3.3.3 Average Overall Latency under
Localized Traffic..............................................342
11.3.3.4 Energy Consumption.....................................345
11.3.4 Simulation Results with Application-Specific Traffic..... 349
11.4 Summary........................................................................................... 350
References...................................................................................................... 351
12. Conclusions and Future Trends................................................................ 353

12.1 Conclusions....................................................................................... 353
12.2 Future Trends................................................................................... 354
12.2.1 Photonic NoC.................................................................... 354
12.2.2 Wireless NoC.....................................................................354
12.3 Comparison between Alternatives................................................ 355
References...................................................................................................... 357
Preface
System-on-chip (SoC) is a paradigm for designing today’s integrated circuit

(IC) chips that put an entire system onto a single silicon floor (instead of
printed circuit boards containing a number of chips accomplishing the sys-
tem task). With the increasing number of cores integrated on such a chip,
on-chip communication efficiency has become one of the key factors in
determining the overall system performance and cost. The communication
medium used in most of the modern SoCs is a shared global bus. In spite of
its fairly simple structure, extensibility, and low area cost, at the system level,
it can be used for only up to tens of cores on a single chip. This restriction is
mainly due to the following reasons: nonscalable wire delay with technology
shrinking, nonscalable system performance with number of cores attached,
decrease in operating frequency with each additional core attached, high
power consumption in long wires, and so on. In many-core-based SoCs, the
major challenge that designers face today is to come up with a scalable, reus-
able, and high-performance communication backbone.
Network-on-chip (NoC) is an emerging alternative that overcomes the
above-mentioned bottlenecks for integrating a large number of cores on a
single SoC. NoC is a specific flavor of interconnection networks where the
cores communicate with each other using a router-based packet-switched
network. Interconnection networks have been studied for more than the past
two decades and a solid foundation of design techniques has been reported
in the literature. NoC is today becoming an emerging research and develop-
ment topic including hardware communication infrastructure design, soft-
ware and operating system services, computer aided design (CAD) tools for
NoC synthesis, NoC testing, and so on.
However, two-dimensional (2D) IC design has limited floorplanning
choices with increasing number of cores attached. An attractive solution to
this problem is the three-dimensional (3D) IC technology that stacks mul-
tiple layers of active silicon using special vertical interconnects, known as
through-silicon via (TSV). The introduction of 2D NoC in a 3D IC platform is
a gradual process and is known as 3D NoC. Although a number of 2D NoC
implementations have already been fabricated in industries (e.g., Intel, IBM,
Arteris, Tilera, etc.), research in 3D NoC is still in its infancy and demands
more concentration from academia and industries.
Aim and scope: This book aims to cover the important aspects of NoC
design: communication infrastructure design, communication methodology,
evaluation framework, mapping of applications onto NoC, and so on. Apart
from these, it also proposes to focus on other upcoming NoC issues, such
as low-power NoC design, signal integrity issues, NoC testing, synthesis,
reconfiguration, and 3D NoC design.
xiii
xiv Preface
Organization: The book consists of 12 chapters. The contents of various

chapters are as follows:
• Chapter 1 presents the evolution of NoC from SoC—its research and

developmental challenges.
• Chapter 2 discusses NoC protocols, elaborating flow control, avail-
able network topologies, routing mechanisms, fault tolerance,
quality-of-service support, and the design of network interfaces.
• Chapter 3 presents the router design strategies followed in NoCs.
It elaborates on clocking strategies, first-in first-out (FIFO) design,
globally asynchronous and locally synchronous style of communi-
cation, router architecture design for both single- and virtual chan-
nel wormhole routers, adaptive router design, and so on.
• Chapter 4 describes the evaluation mechanism of NoC architec-
tures. After introducing the performance and cost metrics, it pres-
ents a detailed discussion on traffic modeling, simulator design, and
performance evaluation and comparison between different NoC
structures.
• Chapter 5 presents the application mapping strategies followed in
NoCs. Given an application task graph, several mapping strategies
have been developed to associate the intellectual properties (IPs)
carrying out these tasks with the routers. The chapter enumerates
various strategies such as integer linear programming, constructive
and iterative heuristics, and meta-search techniques for the mapping
problem.
• Chapter 6 reports on low-power design techniques specifically
followed in NoCs. These include various low-power approaches
adopted for NoC design, for example, low-power encoding, on-chip
serialization, low-swing signaling, static voltage scaling, dynamic
voltage scaling, dynamic frequency scaling, voltage–frequency
island partitioning, clock gating, and so on. This chapter also
includes energy–performance trade-offs.
• Chapter 7 discusses on the signal integrity and reliability issues of
NoC. As technology shrinks toward ultra-deep submicron level,
crosstalk, electromagnetic interference, synchronization failures,
and soft errors are the most important factors affecting the system
reliability. This chapter surveys different protection techniques that
have been adopted for NoC design until now. It also focuses on
energy–reliability trade-offs.
• Chapter 8 presents the details of NoC testing strategies reported so
far. NoC testing can be broadly classified into three subproblems:
testing the IP cores, testing the routers, and testing the links. It has a
detailed discussion on each of the three issues.
Preface xv
• Chapter 9 discusses the problem of synthesizing application-specific

NoCs. The NoC synthesis problem addresses the issue of evolving
the best possible NoC topology for a given application task graph. It
includes the issues such as topology generation, router placement,
and scheduling algorithm development on the designed topology.
• Chapter 10 deals with reconfigurable NoC design issues. The sub-
topics include using field programmable gate array (FPGA) for NoC
reconfiguration, designing a router architecture that aids in dynamic
change of interconnection pattern between the routers, reconfigu-
rable link design, and revisiting the application mapping problem
from the reconfiguration viewpoint.
• Chapter 11 highlights the limited floorplanning choices of 2D NoC
and also focuses on 3D NoC design, which is the amalgamation of
2D NoC and 3D IC. In 3D IC, multiple layers of active silicon are
stacked using special vertical interconnects, known as through-silicon
via. The actual benefit of 3D IC relies on the fact that the relatively
long wires (approximately in millimeters) of 2D IC can be replaced
by these TSVs whose lengths are about tens of microns. This chapter
explores the design space of integrating multiple cores onto different
silicon layers focusing on the performance and cost metrics.
• Finally, Chapter 12 presents the conclusions and enumerates the
directions for future research and development in the field of NoC.
Santanu Kundu
LSI India Research and Development Pvt. Ltd.
(An Avago Technologies Company)
Indian Institute of Technology, Kharagpur
Authors
Santanu Kundu received his BTech degree in instrumentation engineering

from Vidyasagar University, Medinipur, West Bengal, India, in 2002.
Thereafter, he served in industry for a couple of years as an electronics
engineer and returned to academia for pursuing higher studies in 2004. He
received his MTech in instrumentation and electronics engineering from
Jadavpur University, Kolkata, West Bengal, India, in 2006. Immediately after
that he joined the electronics and electrical communication engineering
department at the Indian Institute of Technology, Kharagpur, West Bengal,
India, for pursuing a PhD with specialization in microelectronics and very
large scale integration (VLSI) design. He received his PhD degree in 2011.
Currently he is working as a system-on-chip (SoC) senior design engineer at
LSI India R&D Pvt. Ltd., Bangalore, Karnataka, India. His research interests
include network-on-chip architecture design in 2D and 3D environments,
performance and cost evaluation, signal integrity in nanometer regime,
fault-tolerant schemes, and power–performance–reliability trade-off.
Santanu Chattopadhyay received his BE in computer science and tech-

nology from Calcutta University (BE College), Kolkata, West Bengal, in 1990.
In 1992 and 1996, he received his MTech in computer and information
technology and PhD in computer science and engineering, respectively, both
from the Indian Institute of Technology (IIT), Kharagpur, West Bengal, India.
Before joining the IIT, Kharagpur, he was a faculty member at BE College,
Howrah, West Bengal, India, and the IIT, Guwahati, Assam, India. He is cur-
rently a professor in the electronics and electrical communication engineer-
ing department at the IIT, Kharagpur. His research interests include CAD
tools for low-power circuit design and test, system-on-chip testing, and
network-on-chip design and test. He has more than hundred publications
in refereed international journals and conferences. He is the coauthor of the
book Additive Cellular Automata—Theory and Applications published by the
IEEE Computer Society Press in 1997. He has also written textbooks such as
Compiler Design, System Software, and Embedded System Design, all published
by PHI Learning, New Delhi, India. He is a member of the editorial board of
the journal IET Circuits, Devices and Systems.
xvii
1
Introduction
1.1 System-on-Chip Integration and Its Challenges

Continuous reduction in time to market, required by the multimedia and
consumer electronics commodities, makes full-custom design inappro-
priate. It has led to the design based on reuse of intellectual property (IP)
cores. With the growing complexity in consumer-embedded products, a
single-chip implementation integrating numerous IP cores performing vari-
ous functions and possibly operating at different clock frequencies is now
a well-established one. Such an implementation is conveniently known as
system-on-chip (SoC). Depending on application domains and versatility, SoC
can be classified into two categories: (1) general-purpose multiprocessor SoC
(MPSoC) and (2) application-specific SoC.
Improving the performance and efficiency of a traditional large unipro-
cessor architecture is no longer achievable, thus enhancing the demand
for parallel processing. This, in turn, has resulted in a revolution in micro-
processor architecture—chip multiprocessing (CMP) system. For boosting
up the performance of CMP-based systems, researchers have adopted SoC
platform to build a general-purpose MPSoC for supporting a wide range of
applications. This type of SoC is categorized by having a homogeneous set
of processing elements and storage arrays. Application-specific SoC, as the
name suggests, is dedicated to a specific application. This type of SoC, in
many cases, contains heterogeneous processing elements (e.g., processors,
controllers, and digital signal processors) and a number of domain-specific
hardware accelerators. This heterogeneity may lead to a specific traffic pat-
tern requirement. Hence, a prior knowledge of traffic pattern is required
when the system is designed.
Shared medium arbitrated bus is the commonly used communication back-
bone in modern SoCs. Although this architecture has the advantages of sim-
ple topology, extensibility, and low area cost, a shared bus allows only one
communication at a time that may block all other buses in the h ierarchy. Thus,
bus-based SoC does not scale the system performance with the n umber of
cores attached. Its bandwidth is also shared by all the cores (Grecu et al. 2004).
1
2 Network-on-Chip
Usage of segmented bus architecture where a shared bus is segmented to

multiple buses using bridges also suffers from the same problem of band-
width sharing. There is also a problem of distributing a synchronous clock
signal over the whole chip. In deep submicron (DSM) technologies, accord-
ing to the International Technology Roadmap for Semiconductors (ITRS)
report (ITRS 2001), the delay of local wires and logic gates reduces with
every process generation, whereas global wire delay increases exponen-
tially, or at best linearly, by inserting repeaters as shown in Figure 1.1. For a
relatively long bus, this delay is significant due to its high intrinsic parasitic
resistance and capacitance. As the IP blocks are connected to the bus, they
will add more capacitance to it, which may enhance the delay. In ultra-DSM
processes, it has been observed that long wires mostly fall in the critical
path of the design (Sylvester and Keutzer 2000; Kapur et al. 2002). The long
wires in DSM regime also introduce many signal integrity problems, such
as crosstalk noise, crosstalk delay, IR drop, and electromagnetic interference
(EMI). Moreover, the power consumption of the global wires along with
their drivers and repeaters can be a significant portion of the overall SoC
power budget. Therefore, in DSM technologies, on-chip communication
efficiency has become one of the key factors determining the overall system
performance and cost. The major challenge, SoC researchers face today, is
to come up with structured, scalable, reusable, and high-performance inter-
connection architectures.
100
Gate delay
(fan-out of 4)
Local
(scaled)
Global with
10
repeaters
Relative delay
Global without
repeaters
0.1
250 180 130 90 65 45 32
Process technology node (nm)
FIGURE 1.1
Projected relative delay for local and global wires and for logic gates at different technologies.
(Data from ITRS, International technology roadmap for semiconductors, Technical report,
International Technology Roadmap for Semiconductors, 2001.)
Introduction 3
1.2 SoC to Network-on-Chip: A Paradigm Shift

Several research groups from academia and industry have started to find
out the communication backbone of next-generation many-core-based SoCs
for supporting the new inter-core communication demands. Point-to-point
dedicated links can be a good alternative to global bus for a limited number
of cores in a SoC in terms of bandwidth, latency, and power consumption.
However, the number of links needed increases exponentially as the number
of cores increases. Thus, for a large system, it may create a routing problem
(Bjerregaard and Mahadevan 2006). A centralized crossbar switch overcomes
some of the limitations of the buses. Again, connecting large number of cores
to a single switch is not very effective as it is not ultimately scalable and,
thus, is an intermediate solution only (Bjerregaard and Mahadevan 2006).
At the system level, up to a certain number of cores on a single chip, the per-
formance of traditional bus-based SoCs are expected to be satisfactory. But
in a many-core regime, as the number of cores residing on a SoC increases
significantly, it has a profound effect in shifting the focus from computation
to communication.
To overcome the above-mentioned problems, several research groups have
started to investigate systematic platform-based approaches to design the
communication backbone of MPSoC. On-chip interconnection network is
one solution to integrate IPs in complex SoCs. Network-on-chip (NoC) has
emerged as the viable alternative for the design of modular and scalable
communication architectures. The IP cores communicate with each other via
the router-based network. A core is attached to a router through a network
interface (NI) module (Benini and Micheli 2002). The network is used for
packet-switched on-chip communication among routers, whereas the NIs
enable seamless communication between various cores and the network.
The need for global synchronization can thus disappear. NoC supports the
globally asynchronous locally synchronous (GALS) style for multicore communi-
cation in SoCs.
The concept of on-chip network has been borrowed from off-chip intercon-
nection networks where a single router is implemented per chip (Gratz et al.
2006). The bandwidth of off-chip networks is typically lower than that of
on-chip networks. Off-chip networks are constrained by bit width, as each
extra bit incurs one more pin. Also, the off-chip routers need to be connected
by explicit board traces. This affects the overall system latency and aggra-
vates the synchronization problem (Jerger and Peh 2009).
The introduction of on-chip networks in SoC design is an evolution of bus
interconnect technology. Figure 1.2 shows a NoC structure where heteroge-
neous IP cores (CPU, DSP, etc.) communicate with each other via a network
and NI modules. The function of NI is to isolate the computation from com-
munication. The network consists of switches (routers) and point-to-point
4 Network-on-Chip
CPU NI
NI DSP
DMA NI
Switch Switch
Switch
Switch
NoC Switch
Switch
NI MPEG
DRAM NI Accel NI
FIGURE 1.2
The NoC paradigm. (Data from Angiolini, F., NoC Architectures, n.d., http://www-micrel.deis
.unibo.it/MPHS/slidecorso0607/nocsynth.pdf.)
communication links between them. Routers route the packets from the
source node to the destination node depending on the underlying network
topology and routing strategy. The length of the point-to-point links should
be small to reduce wire delay.
To mitigate the ever increasing design productivity gap and to meet the
time-to-market requirement, reuse of IP cores is widely used in SoC develop-
ment. Besides IP cores, the bus interface protocol can also be reused to inte-
grate the IPs. While reuse is one of the key challenges that IC design houses
try to address, reuse of IPs, NI, and communication infrastructure such as
routers, underlying network, and flow control protocols can be adopted
in the NoC paradigm. Although selection of network topology and router
architecture is purely application specific, reusing these in different appli-
cations will not give the optimal solution. Hence, the reusability is limited
to a particular type of applications. For example, the network topology and
router architecture used for mobile application cannot be same as those of
video processing application. For similar applications, the design and verifi-
cation effort due to reuse will be drastically reduced.
NoC is a specific flavor of interconnection networks and involves several
abstraction layers such as physical, data link, network, and transport layers
(Jantsch and Tenhunen 2003), which are described as follows:
• The physical layer determines the number and length of wires con-
necting resources and switches.
• The data link layer defines the protocol of communication between
a resource and a switch, and between the two switches. Both the
Introduction 5
physical and data link layers are dependent on the technology. Thus,
for each new technology, these layers are defined.
• The network layer defines how a packet is transmitted over the net-
work from an arbitrary sender to an arbitrary receiver directed by the
receiver’s network address. This layer is also technology dependent.
• The transport layer is technology independent. In this layer, message
size can be variable. This layer breaks the message into network
layer packets.
Interconnection networks have been studied for more than the past two
decades and a solid foundation of design techniques has been described in
several text books (Duato et al. 2003; Dally and Towles 2004). With increasing
communication demand, the introduction of interconnection network in SoC
design has paved the route to NoC research almost a decade ago. Mullins
(2009) has listed more than 400 related articles addressing all these aspects.
NoC is today becoming an emerging research topic including hardware com-
munication infrastructure, software and operating system services, CAD
tools for NoC synthesis, and so on.
1.3 Research Issues in NoC Development

The major research problems in NoC design can be broadly classified into
four different dimensions—communication infrastructure, communication
paradigm, evaluation framework, and application mapping—as addressed
in the works of Ogras et al. (2005) and Marculescu et al. (2009). This section
first highlights these issues briefly followed by other associated issues.
The first dimension of research is focused on choice of communication infra-
structure. The communication infrastructure design essentially points to
the design of underlying hardware acting as the backbone for the on-chip
communication network. Selection of network topology, design of router
architecture with proper buffer organization, determining inter-router link
width, clocking strategies, floorplanning, and layout design are the key
design aspects of this dimension. The routers are often connected in certain
topologies whose performance behaviors are well known to the distributed
system design community and suit well for on-chip realizations. Individual
routers are designed using some specific switching techniques, such as
wormhole and virtual cut-through. Flow control is performed via handshak-
ing signals between adjacent routers. The router’s buffer space minimization
and simplified buffer control mechanisms are two important features of the
NoC design, as they directly affect the overall area–power overheads and
network latency. To solve the problem of clock skew, the individual cores
6 Network-on-Chip
and routers are allowed to operate at their own clocks, giving rise to a GALS
scheme. Another important hardware aspect in designing a complete NoC
is the integration of cores with the routers. This needs the design of NI mod-
ules between the two.
The second dimension of research deals with the communication paradigm
on a given NoC platform. Once the infrastructure has been finalized, the next
important task is to design the communication methodology between the
cores via the established network. Routing policies, switching techniques,
congestion control, power and thermal management, and fault tolerance
and reliability issues are the main focus of this set. It, first of all, necessi-
tates the fixing of routing strategy. This is one of the very rich areas of
research in NoC design. It has profound effect on the performance of the
NoC as this chiefly determines the number of hops to be traversed in each
communi cation, congestion, traffic load distribution in different routers,
and so on. The domain is often complicated by the requirement to s upport
the quality-of-service (QoS). Arbitration of network resources in terms of
FIFOs and channels between the contending simultaneous communica-
tions is essential to ensure freedom from problems such as livelock and
deadlock. Like off-chip communications, on-chip communications also suf-
fer from capacitive crosstalk and electromagnetic radiations, corrupting the
data being transmitted. This makes it essential to adopt some fault-tolerant
schemes in the communication. As all designs are now invariably power
aware, the same is the requirement for NoC as well. It is required to judge
very critically the voltages and frequencies at which individual cores and
routers are made to operate to satisfy the overall performance requirement
with a minimum power budget.
The third dimension of research is paying attention to the design of an
evaluation framework for NoC by applying stochastic and application-specific
traffic. As the MPSoCs contain a large number of cores connected in some
topology via routers and interconnection links, it is mandatory to have a
clear idea about their performance before any investment is made in manu-
facturing the systems. The potential faults and drawbacks, if any, must be
identified at the design phase to avoid huge loss after getting the silicon
chips. Though many theoretical studies exist that can predict the behavior of
such a system, they are mostly for congestion-free environment and under
the assumption that all cores are equally active in producing traffic load to
the network. Both of these assumptions are highly optimistic for any prac-
tical design of moderate size. This necessitates the design of high-quality
NoC simulators to produce a behavior similar to that of the actual NoC. The
simulator should model the network at the granularity of individual hard-
ware blocks and wires in terms of functionality, delay, power, and so on.
In the absence of the actual traffic pattern for applications, often synthetic
traffic is used. This synthetic traffic should mimic the behavior of the actual
core that it corresponds to. With confidence gained after determining the
throughput, latency, and bandwidth of the network through simulation,
Introduction 7
the designer can quickly proceed to accurate estimation of area and power
consumption of the network, as it can be a significant portion of the overall
SoC cost budget.
The fourth dimension of research is related to application mapping. Mapping
of cores with regular and irregular sizes onto an underlying NoC platform
to achieve the required performance for a specific application is the major
issue of this dimension. Performance and energy-aware task scheduling for
heterogeneous NoC is another important problem of this class of research.
Figure 1.3 summarizes the major dimensions of NoC research as discussed
above.
Another important aspect is NoC testing. In any system development
process, testing occupies a major part of its turnaround time. The problem
is further complicated by the fact that the test volume becomes huge for
a NoC. It is necessary to apply test patterns to all the cores and get their
responses. The test patterns are to be transported from the system inputs
to the core inputs and the responses are to be carried through the network
from the core outputs to the system outputs. This gives rise to test schedule
optimization problems. The NoC infrastructure itself needs to be tested. The
power consumption during test is also a major concern.
While attempting to realize an application, or a set of applications, in
NoC, it is imperative to use a NoC infrastructure most suitable for the
application(s). This gives rise to the issue of application-specific NoC syn-
thesis. Unlike general standard topologies (such as mesh), NoC synthesis
approaches an attempt to derive the topology, routing policy, and so on to
obtain the best possible performance of the NoC implementation. While the
architecture may be synthesized for a single application, for a set of applica-
tions it is quite common to evolve a reconfigurable architecture. Depending
upon the communication needs of various applications running at different
points in time, a reconfigurable architecture can adapt itself to make it suit-
able for the currently running application. The reconfiguration may be in the
form of link reconfiguration, router port reconfiguration, buffer reconfigura-
tion, and so on.
NoC architecture design
Communication Communication Evaluation framework Application

infrastructure design methodology design design mapping
Network topology Routing strategies Interconnection

modeling
Switching techniques Quality of service
Flow control protocol Arbitration Traffic configuration
Buffering Fault-tolerant scheme NoC simulator
Clocking strategies Power minimization
Network interface techniques
FIGURE 1.3
Major NoC research dimensions.
8 Network-on-Chip
In the many-core era, integrating large number of cores on a two-dimensional

integrated circuit (2D IC) has limited the floor planning choice. Although the
size of an individual core is reduced up to a certain level due to technology
shrinking, chip sizes may become larger for incorporating huge number of
cores on a single silicon die. After the advent of three-dimensional (3D) IC
(Davis et al. 2005) that stacks multiple layers of active silicon using special ver-
tical interconnects, known as through-silicon vias (TSVs), the above-mentioned
problem of long interconnects can be solved. The actual benefit of 3D IC relies
on the fact that the relatively long wires (approximately in millimeters) of 2D
IC can be replaced by these TSVs whose lengths are about tens of microns.
These shorter TSVs minimize the link delay and link energy consumption sig-
nificantly and at the same time more immunity to noise (Topol et al. 2006; Flic
and Bertozzi 2010). Due to increased connectivity, 3D ICs have the potential for
enhancing system performance, achieving better functionality, and producing
higher packaging density compared to their traditional 2D counterpart (Davis
et al. 2005). Combining these two emerging paradigms, NoC and 3D IC, a new
area of research, 3D NoC, has evolved (Pavlidis and Friedman 2007). In a 3D
NoC, an entire 2D NoC is divided into a number of blocks, and each block is
placed on a separate silicon layer. The 3D NoC research is still in its infancy
and needs attention of more researchers to exploit its full potential for using as
communication backbone for future many-core-based SoCs.
1.4 Existing NoC Examples

Several research groups from academia and industry have implemented NoC
to support MPSoC platform. Intel has introduced 80-core-based Teraflops
research chip (Vangal et al. 2008) where each core is placed inside a tile of
dimension 2 mm × 1.5 mm. The cores are connected in a 2D mesh topology
and support wormhole switching of 32-bit flit size with two virtual channels.
The routers have been implemented in 65-nm technology with five-stage pipe-
lining. The operating frequency of the router has been found to be 4.27 GHz
when implemented on a chip. IBM launched Cyclops-64 (C64), a peta-flop
supercomputer, built on a multicore system-on-a-chip technology. Each C64
chip has 80 custom-designed 64-bit processor cores, which are connected in
a 3D mesh fashion (Zhang et al. 2006). The routers have been implemented
using two virtual channels to support two service classes. It uses both input
and output queuing with seven-stage pipelining and operates at 533 MHz. It
can transfer bidirectional data in parallel. Tilera Inc. has introduced a 64-core-
based TILE64 processor (Wentzlaff et al. 2007). The routers are connected in an
8 × 8 2D mesh fashion and follow XY routing having a 32-bit link width with
no virtual channel. The routers are working at 1 GHz when implemented
on silicon in 90-nm technology having both input and output buffering. For
Introduction 9
supporting highly local traffic inside a node, Intel has introduced single-chip
cloud computer (SCC) having 48 cores (SCC 2010). Two cores are connected
with each router of a 6 × 4 2D mesh. The operating frequency of each core is
1 GHz, whereas the routers are targeted to work with 2 GHz in 45-nm technol-
ogy. The routers have been implemented with eight virtual channels and four-
cycle latency. The link width has been taken as 128 bits. ST Microelectronics
have implemented STNoC (Coppola et al. 2004), a spidergon topology-based
NoC that follows a credit-based flow control. Philips have developed a topol-
ogy-independent NoC, Æthereal (Rijpkema et al. 2003), for supporting guar-
anteed throughput (GT) and best effort (BE) services. The router has been
implemented by an input-buffering scheme with first-in first-out (FIFO)
depth of 8 bits and width of 32 bits. It uses a standard credit-based end-to-
end flow control. Both the routers and the NI operate at 500 MHz in 130-nm
technology at the layout level. Arteris is another custom NoC that operates at
750 MHz in 90-nm technology (Arteris 2005). It has a set of configuration and
modeling tools—NoC compiler, NoC verifier, and NoC explorer—for getting
optimized performance and power result for any application.
Kumar et al. (2007) implemented a 36-core shared memory chip multi-
processing (CMP) system in 65-nm technology targeting 3.6 GHz router with
single-cycle latency. The cores are connected in a 6 × 6 2D mesh having a flit size
of 128 bits. The router has 12 unreserved virtual channels and 1 reserved virtual
channel for each of three message classes. It has been implemented with single-
stage pipelining. Lee et al. (2004) implemented a hierarchical star-connected
on-chip network by using a 16:1 serialized link. The routers and cores operate
at 1.6 GHz and 100 MHz, respectively, in 180-nm technology. The authors have
also implemented a custom NoC, Slim-spider (Lee et al. 2006), ensuring low-
power consumption where each router operates at 1.6 GHz in 180-nm technol-
ogy taking a flit size of 8 bits. Adriahantenaina et al. (2003) implemented a fat
tree-based NoC, scalable, programmable, integrated network (SPIN ), in 130-nm
technology taking a flit size of 32 bits. The operating frequency of routers is
found to be 200 MHz at the layout level. Another fat tree-based NoC, extended
generalized fat-tree (XGFT) (Kariniemi et al. 2006), uses a flit size of 32 bits and
operates at 400 MHz. Xpipes (Bertozzi et al. 2005), a custom NoC, consists of
soft macros of switches, NIs, and links. It takes a flit width of 32 bits and sup-
ports error detection and retransmission. Kavaldjiev et al. (2006) modified the
traditional virtual channel router and the new router is working at 500 MHz
in 180-nm technology supporting the 2D mesh topology with 16-bit flit size.
Pande et al. (2005) reported that the area overhead of the routers is reason-
ably low compared to that of full SoC. Feero and Pande (2009) designed a 3D
NoC architecture based on 3D mesh, 3D butterfly fat-tree (BFT), and 3D fat tree
topologies having 64 IP cores of size 2.5 mm × 2.5 mm each. They used a flit size
of 32 bits and four virtual channels each of two flits deep. The frequency of each
router is found to be 1.66 GHz in 90-nm technology after synthesis.
Some asynchronous NoCs have also been reported in the literature.
MANGO (Bjerregaard and Sparsoe 2005), a clock-less NoC, uses the 2D mesh
10 Network-on-Chip
topology with a flit size of 32 bits. The NIs synchronize the clocked open core
protocol (OCP) interfaces to the clock-less network in a GALS fashion and the
overall network is running at 795 MHz in 130-nm technology at the regis-
ter transfer level (RTL) level. Silistix Inc. has introduced its industry leading
asynchronous NoC, CHAINworks (Rostislav et al. 2005), for the design and syn-
thesis of complex devices. FAUST (Lattard et al. 2008), another asynchronous
NoC implemented in 130-nm technology for telecom requirements, uses the
2D mesh technology with a flit size of 32 bits. In the work of Salminen et al.
(2008), a list of NoC proposals has been presented in a tabular form that effec-
tively characterizes many of the NoCs that are not covered here.
1.5 Summary
NoC is a very active research field with many practical applications in
industry as it is expected to be an efficient communication backbone of next-
generation many-core-based SoCs. This chapter focuses on the upcoming
technology trends and the needs of NoC in designing many-core-based
SoCs. It also briefly covers different horizons of research in the field of NoC
design. Finally, a set of NoCs that has been designed till date from the indus-
try and academia has also been covered.
The research dimensions of NoC noted in this chapter have been taken up
in subsequent chapters and discussed in detail.
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Network-on-Chip The Next Generation of System-on-C

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Network-on-Chip

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International Standard Book Number-13: 978-1-4665-6527-2 (eBook - PDF)

2. Interconnection Networks in Network-on-Chip.................................... 13

3. Architecture Design of Network-on-Chip............................................... 53

4. Evaluation of Network-on-Chip Architectures....................................... 75

4.10 Summary............................................................................................. 115

5. Application Mapping on Network-on-Chip.......................................... 119

6. Low-Power Techniques for Network-on-Chip...................................... 155

6.4 System-Level Power Reduction........................................................ 172

7. Signal Integrity and Reliability of Network-on-Chip......................... 191

8. Testing of Network-on-Chip Architectures........................................... 235

9. Application-Specific Network-on-Chip Synthesis............................... 263

9.6.2 PSO for Flexible Router Placement................................. 281

10. Reconfigurable Network-on-Chip Design............................................. 289

11. Three-Dimensional Integration of Network-on-Chip......................... 317

11.3 Design and Evaluation of 3D NoC Architecture......................... 323

12. Conclusions and Future Trends................................................................ 353

System-on-chip (SoC) is a paradigm for designing today’s integrated circuit

Organization: The book consists of 12 chapters. The contents of various

• Chapter 1 presents the evolution of NoC from SoC—its research and

• Chapter 9 discusses the problem of synthesizing application-specific

Santanu Kundu received his BTech degree in instrumentation ­engineering

Santanu Chattopadhyay received his BE in computer science and tech-

1.1 System-on-Chip Integration and Its Challenges

Usage of segmented bus architecture where a shared bus is segmented to

1.2 SoC to Network-on-Chip: A Paradigm Shift

1.3 Research Issues in NoC Development

NoC architecture design

Communication Communication Evaluation framework Application

Network topology Routing strategies Interconnection

In the many-core era, integrating large number of cores on a two-dimensional

1.4 Existing NoC Examples

Bjerregaard, T. and Sparsoe, J. 2005. A router architecture for connection-oriented

platform. Proceedings of the IEEE International Solid-State Circuits Conference, San

Interconnection Networks in Network-on-Chip

Architecture Design of Network-on-Chip

Evaluation of Network-on-Chip Architectures

Low-Power Techniques for Network-on-Chip

Signal Integrity and Reliability of Network-on-Chip

Testing of Network-on-Chip Architectures

Application-Specific Network-on-Chip Synthesis

Reconfigurable Network-on-Chip Design

Three-Dimensional Integration of Network-on-Chip

Conclusions and Future Trends

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Santanu Kundu received his BTech degree in instrumentation engineering