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UCC27200, UCC27201
SLUS746C – DECEMBER 2006 – REVISED APRIL 2016

UCC2720x, 120-V Boot, 3-A Peak, High Frequency, High-Side and Low-Side Driver
1 Features 3 Description
1• Drives Two N-Channel MOSFETs in High-Side The UCC2720x family of high-frequency N-channel
and Low-Side Configuration MOSFET drivers include a 120-V bootstrap diode and
high-side and low-side drivers with independent
• Negative Voltage Handling on HS (–5 V) inputs for maximum control flexibility. This allows for
• Maximum Boot Voltage of 120 V N-channel MOSFET control in half-bridge, full-bridge,
• Maximum VDD Voltage of 20 V two-switch forward, and active clamp forward
converters. The low-side and the high-side gate
• On-Chip 0.65-V VF, 0.6-Ω RD Bootstrap Diode
drivers are independently controlled and matched to
• Greater than 1 MHz of Operation 1 ns between the turnon and turnoff of each other.
• 20-ns Propagation Delay Times An on-chip bootstrap diode eliminates the external
• 3-A Sink and 3-A Source Output Currents discrete diodes. Undervoltage lockout is provided for
• 8-ns Rise and 7-ns Fall Time With 1000-pF Load both the high-side and the low-side drivers forcing the
• 1-ns Delay Matching outputs low if the drive voltage is below the specified
threshold.
• Undervoltage Lockout for High-Side and Low-Side
Driver Two versions of the UCC27200 are offered. The
UCC27200 has high noise immune CMOS input
• Specified from –40°C to 140°C thresholds while the UCC27201 has TTL compatible
thresholds.
2 Applications
• Power Supplies for Telecom, Datacom, and Device Information(1)
Merchant Markets PART NUMBER PACKAGE BODY SIZE (NOM)
• Half-Bridge Applications and Full-Bridge SOIC (8) 3.91 mm × 4.90 mm
Converters UCC2720x SO PowerPAD™ (8) 3.90 mm × 4.89 mm
• Isolated Bus Architecture VSON (8) 4.00 mm × 4.00 mm

• Two-Switch Forward Converters (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Active-Clamp Forward Converters
• High-Voltage Synchronous-Buck Converters
• Class-D Audio Amplifiers
Simplified Application Diagram
12 V 100 V

VDD Secondary
Side
HB Circuit

HI Drive HO
High
Control

PWM HS
Controller
LI
Drive LO
Low

UCC2720x

VSS

Isolation and
Feedback
Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27200, UCC27201
SLUS746C – DECEMBER 2006 – REVISED APRIL 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 13
2 Applications ........................................................... 1 8 Application and Implementation ........................ 14
3 Description ............................................................. 1 8.1 Application Information............................................ 14
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 15
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 20
6 Specifications......................................................... 4 10 Layout................................................................... 21
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 21
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 21
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 22
6.4 Thermal Information .................................................. 5 11.1 Documentation Support ........................................ 22
6.5 Electrical Characteristics........................................... 5 11.2 Related Links ........................................................ 22
6.6 Typical Characteristics .............................................. 8 11.3 Community Resources.......................................... 22
7 Detailed Description ............................................ 12 11.4 Trademarks ........................................................... 22
7.1 Overview ................................................................. 12 11.5 Electrostatic Discharge Caution ............................ 22
7.2 Functional Block Diagram ....................................... 12 11.6 Glossary ................................................................ 22
7.3 Feature Description................................................. 12 12 Mechanical, Packaging, and Orderable
Information ........................................................... 22

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (November 2008) to Revision C Page

• Added Device Information table, Revision History section, Pin Configuration and Functions section, Specifications
section, Detailed Description section, Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................. 1

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5 Pin Configuration and Functions

D Package
8-Pin SOIC DDA Package
Top View 8-Pin SO PowerPAD
Top View

VDD 1 8 LO
VDD 1 8 LO
HB 2 7 VSS
HB 2 7 VSS
PAD
HO 3 6 LI
HO 3 6 LI
HS 4 5 HI
HS 4 5 HI

DRM Package
8-Pin VSON
Top View

VDD 1 8 LO

HB 2 7 VSS
PAD
HO 3 6 LI

HS 4 5 HI

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required.
HB 2 I Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is
0.022 μF to 0.1 μF, the value is dependant on the gate charge of the high-side MOSFET however.
HI 5 I High-side input.
HO 3 O High-side output. Connect to the gate of the high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of
HS 4 I
bootstrap capacitor to this pin.
LI 6 I Low-side input.
LO 8 O Low-side output. Connect to the gate of the low-side power MOSFET.
Positive supply to the lower gate driver. Decouple this pin to VSS (GND). Typical decoupling capacitor
VDD 1 I
range is 0.22 μF to 1 μF.
VSS 7 O Negative supply terminal for the device which is generally grounded.
Used on the DDA and DRM packages only. Electrically referenced to VSS (GND) (1). Connect to a large
PowerPAD PAD —
thermal mass trace or GND plane to dramatically improve thermal performance.

(1) VSS pin and the exposed thermal die pad are internally connected.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature, unless noted, all voltages are with respect to VSS. (1)
MIN MAX UNIT
Supply voltage, VDD (2) –0.3 20 V
Input voltages on LI and HI, VLI, VHI –0.3 20 V
DC –0.3 VDD + 0.3
Output voltage on LO, VLO V
Repetitive pulse < 100 ns (3) –2 VDD + 0.3
DC VHS – 0.3 VHB + 0.3
Output voltage on HO, VHO V
Repetitive pulse < 100 ns (3) VHS – 2 VHB + 0.3
DC –1 120
Voltage on HS, VHS (3)
V
Repetitive pulse < 100 ns –5 120
Voltage on HB, VHB –0.3 120 V
Voltage on HB-HS –0.3 20 V
(D package) (4) 1.3
Power dissipation at TA = 25°C (DDA package) (4) 2.7 W
(DRM package) (4) 3.3
Lead temperature (soldering, 10 s) 300 °C
Operating virtual junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal.
(3) Values are verified by characterization and are not production tested.
(4) This data was taken using the JEDEC proposed high-K test PCB. See Thermal Information for details.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 8 12 17 V
–1 105
VHS Voltage on HS V
repetitive pulse < 100 ns –5 110
VHB Voltage on HB VHS + 8 115 V
Voltage slew rate on HS 50 V/ns
TJ Operating junction temperature –40 140 °C

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6.4 Thermal Information

PDISS = (150 – TA) / θJA, unless otherwise noted.
UCC27200, UCC27201
(1)
THERMAL METRIC D (SOIC) DDA (HSOP) DRM (VSON) UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 106.5 40.5 36.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.9 49 41.6 °C/W
RθJB Junction-to-board thermal resistance 46.6 10.2 13.2 °C/W
ψJT Junction-to-top characterization parameter 9.6 3.1 0.6 °C/W
ψJB Junction-to-board characterization parameter 46.1 9.7 13.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 1.5 3.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = –40°C to
140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD quiescent current VLI = VHI = 0 0.4 0.8
UCC27200 2.5 4
IDDO VDD operating current f = 500 kHz, CLOAD = 0
UCC27201 3.8 5.5 mA
IHB Boot voltage quiescent current VLI = VHI = 0 V 0.4 0.8
IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 2.5 4
IHBS HB to VSS quiescent current VHS = VHB = 110 V 0.0005 1 uA
IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 0.1 mA
INPUT
VHIT Input rising threshold 5.8 8
VLIT Input falling threshold UCC27200 3 5.4
VIHYS Input voltage hysteresis 0.4 V
VHIT Input voltage threshold 1.7 2.5
VLIT Input voltage threshold UCC27201 0.8 1.6
VIHYS Input voltage Hysteresis 100 mV
RIN Input pulldown resistance 100 200 350 kΩ
UNDERVOLTAGE PROTECTION (UVLO)
VDD rising threshold 6.2 7.1 7.8
VDD threshold hysteresis 0.5
V
VHB rising threshold 5.8 6.7 7.2
VHB threshold hysteresis 0.4

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Electrical Characteristics (continued)

over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = –40°C to
140°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BOOTSTRAP DIODE
VF Low-current forward voltage I VDD – HB = 100 μA 0.65 0.85
V
VFI High-current forward voltage I VDD – HB = 100 mA 0.85 1.1
RD Dynamic resistance, ΔVF / ΔI I VDD – HB = 100 mA and 80 mA 0.6 1 Ω
LO GATE DRIVER
VLOL Low-level output voltage ILO = 100 mA 0.18 0.4
ILO = –100 mA, TJ = –40 to 125°C 0.25 0.4 V
VLOH High-level output voltage
VLOH = VDD – VLO TJ = –40 to 140°C 0.25 0.42
Peak pullup current VLO = 0 V 3
A
Peak pulldown current VLO = 12 V 3
HO GATE DRIVER
VHOL Low-level output voltage IHO = 100 mA 0.18 0.4
IHO = –100 mA, TJ = –40 to 125°C 0.25 0.4 V
VHOH High-level output voltage
VHOH = VHB – VHO TJ = –40 to 140°C 0.25 0.42
Peak pullup current VHO = 0 V 3
A
Peak pulldown current VHO = 12 V 3
PROPAGATION DELAYS
TJ = –40 to 125°C 20 45
TDLFF VLI falling to VLO falling CLOAD = 0
TJ = –40 to 140°C 20 50
TJ = –40 to 125°C 20 45
TDHFF VHI falling to VHO falling CLOAD = 0
TJ = –40 to 140°C 20 50
ns
TJ = –40 to 125°C 20 45
TDLRR VLI rising to VLO rising CLOAD = 0
TJ = –40 to 140°C 20 50
TJ = –40 to 125°C 20 45
TDHRR VHI rising to VHO rising CLOAD = 0
TJ = –40 to 140°C 20 50
DELAY MATCHING
TMON LI ON, HI OFF 1 7
ns
TMOFF LI OFF, HI ON 1 7
OUTPUT RISE AND FALL TIME
tR LO, HO CLOAD = 1000 pF 8
ns
tF LO, HO CLOAD = 1000 pF 7
tR LO, HO (3 V to 9 V) CLOAD = 0.1 μF 0.35 0.6
us
tF LO, HO (3 V to 9 V) CLOAD = 0.1 μF 0.3 0.6
MISCELLANEOUS
Minimum input pulse width that
50
changes the output ns
(1) (2)
Bootstrap diode turn-off time IF = 20 mA, IREV = 0.5 A 20

(1) Typical values for TA = 25°C

(2) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.

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LI

Input
(HI, LI) HI

TDLRR, TDHRR

LO

Output
(HO, LO)

TDLFF, TDHFF
HO

TMON TMOFF

Figure 1. Timing Diagrams

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6.6 Typical Characteristics

10.0 10.0
VDD = 12 V VDD = 12 V 150oC
No Load on Outputs No Load on Outputs
25oC

IDDO - Operating Current - mA

IDDO - Operating Current - mA

150oC o
125 C

125oC

1.0 1.0

-40oC
o
25 C
-40oC

0.1 0.1
10 100 1000 10 100 1000
Frequency - kHz Frequency - kHz

Figure 2. UCC27200 IDD Operating Current vs Frequency Figure 3. UCC27201 IDD Operating Current vs Frequency

10.0 1.0
HB = 12 V HB = 12 V
No Load on Outputs No Load on Outputs
IHBSO - Operating Current - mA
IHBO - Operating Current - mA

150oC

0.1 150oC
125oC

1.0

0.01 25oC
25oC

-40oC

125oC
o
-40 C
0.1 0.001
10 100 1000 10 100 1000
Frequency - kHz Frequency - kHz

Figure 4. Boot Voltage Operating Current vs Frequency Figure 5. HB to VSS Operating Current vs Frequency

50 2.0
T = 25oC T = 25oC
HI, LI - Input Threshold Voltage/VDD Voltage - %

HI, LI - Input Threshold Voltage - V

48 Rising 1.8

Rising

46 1.6 Falling

44 Falling 1.4

42 1.2

40 1.0
8 10 12 14 16 18 20 8 10 12 14 16 18 20
VDD - Supply Voltage - V VDD - Supply Voltage - V

Figure 6. UCC27200 Input Threshold vs Supply Voltage Figure 7. UCC27201 Input Threshold vs Supply Voltage

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Typical Characteristics (continued)

50 2.0
HI, LI - Input Threshold Voltage/VDD Voltage - %

VDD = 12 V VDD = 12 V

HI, LI - Input Threshold Voltage - V

48 1.8

Rising Rising

46 1.6

Falling Falling

44 1.4

42 1.2

40 1.0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA - Temperature - oC TA - Temperature - oC

Figure 8. UCC27200 Input Threshold vs Temperature Figure 9. UCC27201 Input Threshold vs Temperature

0.45 0.45

ILO = IHO = -100 mA VDD = VHB = 16 V ILO = IHO = 100 mA

0.40 0.40
VOH - LO/HO Output Voltage - V

0.35 VDD = VHB = 12 V VOL - LO/HO Output Voltage - V 0.35

VDD = VHB = 16 V

0.30 0.30
VDD = VHB = 8 V VDD = VHB = 12 V
0.25 0.25
VDD = VHB = 8 V
0.20 0.20

0.15 0.15

0.10 VDD = VHB = 20 V 0.10

0.05 0.05
VDD = VHB = 20 V

0.0 0.0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA - Temperature - oC TA - Temperature - oC

Figure 10. LO and HO High-Level Output Voltage vs Figure 11. LO and HO Low-Level Output Voltage vs
Temperature Temperature

7.8 0.8

7.6 0.7
7.4
0.6 VDD UVLO Hysteresis
VDD Rising Threshold
7.2
0.5
Hysteresis - V
Threshold - V

7.0

6.8 0.4

6.6
0.3 HB UVLO Hysteresis

6.4 HB Rising Threshold

0.2
6.2
0.1
6.0

5.8 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA - Temperature - oC TA - Temperature - oC

Figure 12. Undervoltage Lockout Threshold vs Temperature Figure 13. Undervoltage Lockout Threshold Hysteresis vs
Temperature

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Typical Characteristics (continued)

36 36
VDD = VHD = 12 V VDD = VHB = 12 V
34 34
TDHFF
32 32

30 30

Propagation Delay - ns
TDHRR
Propagation Delay - ns

28 28

26 26

24 24 TDLFF
22 22
TDLRR
20 20

18 TDLFF 18 TDHFF
16 16
TDLRR TDHRR
14 14
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TA - Temperature - oC TA - Temperature - oC

Figure 14. UCC27200 Propagation Delays vs Temperature Figure 15. UCC27201 Propagation Delays vs Temperature

26 26
T = 25oC T = 25oC

24
24
Propagation Delay - ns

Propagation Delay - ns

22
LI Falling
22 LI Falling
LI Rising
20 LI Rising
HI Falling

20 HI Rising
18 HI Rising

HI Falling

16 18
8 10 12 14 16 18 20 8 10 12 14 16 18 20
VDD = VHB - Supply Voltage - V VDD = VHB - Supply Voltage - V

Figure 16. UCC27200 Propagation Delay vs Supply Voltage Figure 17. UCC27201 Propagation Delay vs Supply Voltage

3.5
7
VDD = VHB = 12 V
VDD = VHB = 12 V
3.0
6
ILO, IHO - Output Current - A

2.5 Pull-Up Current Pull-Down Current

5
Delay Matching - ns

2.0
4
UCC27200TMOFF
1.5
3 UCC27201TMOFF
UCC27201TMON UCC27200TMON
1.0
2

0.5
1

0 0
-50 -25 0 25 50 75 100 125 150 0 2 4 6 8 10 12
TA - Temperature - oC VLO, VHO - Output Voltage - V

Figure 18. Delay Matching vs Temperature Figure 19. Output Current vs Output Voltage

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Typical Characteristics (continued)

100.0 700

Inputs Low
600 T = 25oC
10.0

IDD, IHB - Supply Current - mA

500
Diode Current - mA

1.0 400 IHB

300 IDD
0.1

200

0.01
100

0.001 0
0.5 0.6 0.7 0.8 0.9 0 4 8 12 16 20
Diode Voltage - V VDD, VHB - Supply Voltage - V

Figure 20. Diode Current vs Diode Voltage Figure 21. Quiescent Current vs Supply Voltage

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7 Detailed Description

7.1 Overview
The UCC27200 and UCC27201 are high-side and low-side drivers. The high-side and low-side each have
independent inputs which allow maximum flexibility of input control signals in the application. The boot diode for
the high-side driver bias supply is internal to the UCC27200 and UCC27201. The UCC27200 is the CMOS
compatible input version and the UCC27201 is the TTL or logic compatible version. The high-side driver is
referenced to the switch node (HS) which is typically the source pin of the high-side MOSFET and drain pin of
the low-side MOSFET. The low-side driver is referenced to VSS which is typically ground. The functions
contained are the input stages, UVLO protection, level shift, boot diode, and output driver stages.

7.2 Functional Block Diagram

2 HB

UVLO
Level 3 HO
Shift

4 HS
HI 5

VDD 1

UVLO
8 LO

LI 6 7 VSS

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7.3 Feature Description

7.3.1 Input Stages
The input stages provide the interface to the PWM output signals. The input impedance of the UCC27200 is
200‑kΩ nominal and input capacitance is approximately 2 pF. The 200 kΩ is a pulldown resistance to VSS
(ground). The CMOS compatible input of the UCC27200 provides a rising threshold of 48% of VDD and falling
threshold of 45% of VDD. The inputs of the UCC27200 are intended to be driven from 0 to VDD levels.
The input stages of the UCC27201 incorporate an open drain configuration to provide the lower input thresholds.
The input impedance is 200-kΩ nominal and input capacitance is approximately 4 pF. The 200 kΩ is a pulldown
resistance to VSS (ground). The logic level compatible input provides a rising threshold of 1.7 V and a falling
threshold of 1.6 V.

7.3.2 Undervoltage Lockout (UVLO)

The bias supplies for the high-side and low-side drivers have undervoltage lockout (UVLO) protection. VDD as
well as VHB to VHS differential voltages are monitored. The VDD UVLO disables both drivers when VDD is
below the specified threshold. The rising VDD threshold is 7.1 V with 0.5-V hysteresis. The VHB UVLO disables
only the high-side driver when the VHB to VHS differential voltage is below the specified threshold. The VHB
UVLO rising threshold is 6.7 V with 0.4-V hysteresis.

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Feature Description (continued)

7.3.3 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.

7.3.4 Boot Diode

The boot diode necessary to generate the high-side bias is included in the UCC2720x family of drivers. The
diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and
the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The
boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and
reliable operation.

7.3.5 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and
high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-
side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS.

7.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Undervoltage Lockout (UVLO) for more information
on UVLO operation mode. In normal mode, the output stage is dependent on the sates of the HI and LI pins.

Table 1. Device Logic Table

HI PIN LI PIN HO (1) LO (2)
L L L L
L H L H
H L H L
H H H H

(1) HO is measured with respect to the HS.

(2) LO is measured with respect to the VSS.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

To effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation is often encountered because the PWM signal from the
digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) to fully turn on the power
device and minimize conduction losses. Traditional buffer drive circuits based on NPN and PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.

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8.2 Typical Application

+ +

Copyright © 2016, Texas Instruments Incorporated

Figure 22. Open-Loop Half-Bridge Converter

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8.2.1 Design Requirements

For this design example, use the parameters listed in Table 2.

Table 2. UCC27201 Design Requirements

DESIGN PARAMETER EXAMPLE VALUE
Supply Voltage, VDD 12 V
Voltage on HS, VHS 0 V to 100 V
Voltage on HB, VHB 12 V to 112 V
Output 4 V, 20 A
Frequency 200 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Switching the MOSFETs

Achieving optimum drive performance at high frequency efficiently requires special attention to layout and
minimizing parasitic inductances. Take care at the driver die and package level as well as the PCB layout to
reduce parasitic inductances as much as possible. Figure 23 shows the main parasitic inductance elements and
current flow paths during the turn ON and OFF of the MOSFET by charging and discharging its CGS
capacitance.

L bond wire L pin L trace

1
VDD

Rsource I SOURCE Cvdd

Driver L bond wire L pin L trace Rg

Output 8
Stage LO
Rsink I sink
Cgs
L bond wire L pin L trace L trace
7
Vss

Figure 23. MOSFET Drive Paths and Circuit Parasitics

The ISOURCE current charges the CGS gate capacitor and the ISINK current discharges it. The rise and fall time of
the voltage across the gate to source defines how quickly the MOSFET can be switched. Based on actual
measurements, the analytical curves in Figure 24 and Figure 25 indicate the output voltage and current of the
drivers during the discharge of the load capacitor. Figure 24 shows voltage and current as a function of time.
Figure 25 indicates the relationship of voltage and current during fast switching. These figures demonstrate the
actual switching process and limitations due to parasitic inductances.

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12 12
11
11
10
9 10
8 9
7
6 8
LO Falling, V or A

5 7
4
6

LO Voltage, V
3
2 5
1 4
0
1
3
2 2
3
1
4
5 0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1
t, ns
2
Voltage
3
Current 2 1 0 1 2 3 4 5

LO Current, A

Figure 24. Turnoff Voltage and Current vs Time Figure 25. Turnoff Voltage and Current Switching Diagram

Turning off the MOSFET must be achieved as fast as possible to minimize switching losses. For this reason the
UCC2720x drivers are designed for high peak currents and low output resistance. The sink capability is specified
as 0.18 V at 100-mA DC current implying 1.8-Ω RDS(on). With 12-V drive voltage, no parasitic inductance and a
linear resistance, one would expect initial sink current amplitude of 6.7 A for both high-side and low-side drivers.
Assuming a pure R-C discharge circuit of the gate capacitor, one would expect the voltage and current
waveforms to be exponential. Due to the parasitic inductances and non-linear resistance of the driver
MOSFET’S, the actual waveforms have some ringing and the peak-sink current of the drivers is approximately
3.3 A as shown in Figure 19. The overall parasitic inductance of the drive circuit is estimated at 4 nH. The
internal parasitic inductance of the 8-pin SOIC package is estimated to be 2 nH including bond wires and leads.
The 8-pin VSON package reduces the internal parasitic inductances by more than 50%.
Actual measured waveforms are shown in Figure 26 and Figure 27. As shown, the typical rise time of 8 ns and
fall time of 7 ns is conservatively rated.

Figure 26. VLO and VHO Rise Time, 1-nF Load, 5 ns/Div Figure 27. VLO and VHO Fall Time, 1-nF Load, 5-ns/Div

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8.2.2.2 Dynamic Switching of the MOSFETs

The true behavior of MOSFETS presents a dynamic capacitive load primarily at the gate to source threshold
voltage. Using the turnoff case as the example, when the gate to source threshold voltage is reached the drain
voltage starts rising, the drain to gate parasitic capacitance couples charge into the gate resulting in the turnoff
plateau. The relatively low threshold voltages of many MOSFETS and the increased charge that has to be
removed (Miller charge) makes good driver performance necessary for efficient switching. An open-loop half
bridge power converter was used to evaluate performance in actual applications. The schematic of the half-
bridge converter is shown in Figure 22. The turnoff waveforms of the UCC27200 driving two MOSFETs in parallel
is shown in Figure 28 and Figure 29.

Figure 28. VLO Fall Time in Half-Bridge Converter Figure 29. VHO Fall Time in Half-Bridge Converter

8.2.2.2.1 Delay Matching and Narrow Pulse Widths

The total delays encountered in the PWM, driver and power stage must be considered for a number of reasons,
primarily delay in current limit response. Also to be considered are differences in delays between the drivers
which can lead to various concerns depending on the topology. The sync-buck topology switching requires
careful selection of dead time between the high-side and low-side switches to avoid cross conduction and
excessive body diode conduction. Bridge topologies can be affected by a resulting V/s imbalance on the
transformer if there is imbalance in the high and low-side pulse widths in a steady state condition.
Narrow pulse width performance is an important consideration when transient and short circuit conditions are
encountered. Although there may be relatively long steady state PWM output-driver-MOSFET signals, very
narrow pulses may be encountered in soft start, large load transients, and short-circuit conditions.
The UCC2720x driver family offers excellent performance regarding high and low-side driver delay matching and
narrow pulse width performance. The delay matching waveforms are shown in Figure 30 and Figure 31. The
UCC2720x driver narrow pulse performance is shown in Figure 32 and Figure 33.

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Figure 30. VLO and VHO Rising Edge Delay Matching Figure 31. VLO and VHO Falling Edge Delay Matching

Figure 32. 20-ns Input Pulse Delay Matching Figure 33. 10-ns Input Pulse Delay Matching

8.2.2.3 Boot Diode Performance

The UCC2720x family of drivers incorporates the bootstrap diode necessary to generate the high-side bias
internally. The characteristics of this diode are important to achieve efficient, reliable operation. The DC
characteristics to consider are VF and dynamic resistance. A low VF and high dynamic resistance results in a
high forward voltage during charging of the bootstrap capacitor. The UCC2720x has a boot diode rated at 0.65-V
VF and dynamic resistance of 0.6 Ω for reliable charge transfer to the bootstrap capacitor. The dynamic
characteristics to consider are diode recovery time and stored charge. Diode recovery times that are specified
with no conditions can be misleading. Diode recovery times at no forward current (IF) can be noticeably less than
with forward current applied. The UCC2720x boot diode recovery is specified at 20 ns at IF = 20 mA,
IREV = 0.5 A. At 0-mA IF the reverse recovery time is 15 ns.
Another less obvious consideration is how the stored charge of the diode is affected by applied voltage. On every
switching transition when the HS node transitions from low to high, charge is removed from the boot capacitor to
charge the capacitance of the reverse biased diode. This is a portion of the driver power losses and reduces the
voltage on the HB capacitor. At higher applied voltages, the stored charge of the UCC2720x PN diode is often
less than a comparable Schottky diode.

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8.2.3 Application Curves

Figure 34. VLO Fall Time in Half-Bridge Converter Figure 35. VHO Fall Time in Half-Bridge Converter

9 Power Supply Recommendations

The bias supply voltage range for which the device is rated to operate is from 8 V to 17 V. The lower end of this
range is governed by the internal UVLO protection feature on the VDD pin supply circuit blocks. Whenever the
driver is in UVLO condition when the VDD pin voltage is below the V(ON) supply start threshold, this feature
holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 20-V
absolute maximum voltage rating of the VDD pin of the device (which is a stress rating). Keeping a 3-V margin to
allow for transient voltage spikes, the maximum voltage for the VDD pin is 17 V. The UVLO protection feature
also involves a hysteresis function. This means that when the VDD pin bias voltage has exceeded the threshold
voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal
functionality unless the voltage drop exceeds the hysteresis specification VDD(hys). Therefore, ensuring that,
while operating at or near the 8-V range, the voltage ripple on the auxiliary power supply output is smaller than
the hysteresis specification of the device is important to avoid triggering device shutdown. During system
shutdown, the device operation continues until the VDD pin voltage has dropped below the V(OFF) threshold
which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system
start-up, the device does not begin operation until the VDD pin voltage has exceeded above the V(ON) threshold.
The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin.
Although this fact is well known, recognizing that the charge for source current pulses delivered by the HO pin is
also supplied through the same VDD pin is important. As a result, every time a current is sourced out of the HO
pin a corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that a local
bypass capacitor is provided between the VDD and GND pins and located as close to the device as possible for
the purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is a must. TI recommends
using a capacitor in the range of 0.22 uF to 4.7 uF between VDD and GND. In a similar manner, the current
pulses delivered by the LO pin are sourced from the HB pin. Therefore, TI recommends a 0.022-uF to 0.1-uF
local decoupling capacitor between the HB and HS pins.

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 UCC27200, UCC27201
www.ti.com SLUS746C – DECEMBER 2006 – REVISED APRIL 2016

10 Layout

10.1 Layout Guidelines

To improve the switching characteristics and efficiency of a design, the following layout rules must be followed.
• Place the driver as close as possible to the MOSFETs.
• Place the VDD and VHB (bootstrap) capacitors as close as possible to the driver.
• Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by
connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the
MOSFET but must not be in the high current path of the MOSFET(s) drain or source current.
• Use similar rules for the HS node as for GND for the high-side driver.
• Use wide traces for LO and HO closely following the associated GND or HS traces. 60-mil to 100-mil width is
preferable where possible.
• Use as least two or more vias if the driver outputs or SW node must be routed from one layer to another. For
GND the number of vias must be a consideration of the thermal pad requirements as well as parasitic
inductance.
• Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce
significant noise into the relatively high impedance leads.
• Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can
even lead to decreased reliability of the whole system.

10.2 Layout Example

Figure 36. Example Component Placement

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UCC27200, UCC27201
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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
• QFN/SON PCB Attachment, SLUA271
• PowerPAD Thermally Enhanced Package, SLMA002
• PowePAD Made Easy, SLMA004

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 3. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
UCC27200 Click here Click here Click here Click here Click here
UCC27201 Click here Click here Click here Click here Click here

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

22 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated

Product Folder Links: UCC27200 UCC27201

 PACKAGE OPTION ADDENDUM

www.ti.com 22-Sep-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

UCC27200D LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27200
UCC27200DDA LIFEBUY SO PowerPAD DDA 8 75 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27200
UCC27200DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27200 Samples

UCC27200DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27200 Samples

UCC27200DRMR ACTIVE VSON DRM 8 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 140 27200 Samples

UCC27200DRMT LIFEBUY VSON DRM 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 140 27200
UCC27201D LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27201
UCC27201DDA LIFEBUY SO PowerPAD DDA 8 75 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201
UCC27201DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201 Samples

UCC27201DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27201 Samples

UCC27201DRMR ACTIVE VSON DRM 8 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201 Samples

UCC27201DRMT LIFEBUY VSON DRM 8 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 22-Sep-2023

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UCC27200 :

• Automotive : UCC27200-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 31-Oct-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27200DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
PowerPAD
UCC27200DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27200DRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27200DRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27201DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
PowerPAD
UCC27201DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27201DRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC27201DRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 31-Oct-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC27200DDAR SO PowerPAD DDA 8 2500 364.0 364.0 27.0
UCC27200DR SOIC D 8 2500 340.5 338.1 20.6
UCC27200DRMR VSON DRM 8 3000 356.0 356.0 35.0
UCC27200DRMT VSON DRM 8 250 210.0 185.0 35.0
UCC27201DDAR SO PowerPAD DDA 8 2500 364.0 364.0 27.0
UCC27201DR SOIC D 8 2500 340.5 338.1 20.6
UCC27201DRMR VSON DRM 8 3000 367.0 367.0 35.0
UCC27201DRMT VSON DRM 8 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 31-Oct-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
UCC27200D D SOIC 8 75 507 8 3940 4.32
UCC27200DDA DDA HSOIC 8 75 517 7.87 635 4.25
UCC27200DDA DDA HSOIC 8 75 506.6 8 3940 4.32
UCC27201D D SOIC 8 75 507 8 3940 4.32
UCC27201DDA DDA HSOIC 8 75 506.6 8 3940 4.32
UCC27201DDA DDA HSOIC 8 75 517 7.87 635 4.25

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4202561/G
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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