Product Order Technical Tools & Support &

Folder Now Documents Software Community

TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018

TLV62085 High Efficiency 3-A Step-Down Converter in 2-mm × 2-mm VSON Package
1 Features 3 Description
•
1 DCS-Control™ Topology The TLV62085 device is a high-frequency
synchronous step-down converter optimized for small
• Up to 95% Efficiency solution size and high efficiency. With an input
• 17-μA Operating Quiescent Current voltage range of 2.5 V to 6.0 V, common battery
• 31mΩ and 23mΩ Power MOSFET Switch technologies are supported. The devices focus on
• 2.5-V to 6.0-V Input Voltage Range high-efficiency step-down conversion over a wide
output current range. At medium to heavy loads, the
• 0.8-V to VIN Adjustable Output Voltage converter operates in PWM mode and automatically
• Power Save Mode for Light Load Efficiency enters Power Save Mode operation at light load to
• 100% Duty Cycle for Lowest Dropout maintain high efficiency over the entire load current
range.
• Hiccup Short-Circuit Protection
• Output Discharge To address the requirements of system power rails,
the internal compensation circuit allows a large
• Power Good Output selection of external output capacitor values ranging
• Thermal Shutdown Protection from 10 µF to 150 µF and above. Together with its
• Available in 2-mm × 2-mm VSON Package DCS-Control™ architecture, excellent load transient
performance and output voltage regulation accuracy
• For Improved Feature Set, See TPS62085
are achieved. The device is available in a 2-mm × 2-
• Create a Custom Design using the TLV62085 with mm VSON package.
the WEBENCH® Power Designer
Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)
• Battery-Powered Applications TLV62085 VSON (7) 2.00 mm × 2.00 mm
• Point-of-Load (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Processor Supplies
• Hard Disk Drives (HDD) / Solid State Drives
(SSD)
spacer
spacer
spacer
Typical Application Schematic
L1
Efficiency at VIN = 5 V
TLV62085
0.47µH 100
VIN VOUT
VIN SW
2.5V to 6V C1 C2 1.8V
EN VOS R1 R3
10µF 22µF
138k 1M
FB
R2
90
GND PG
110k
Efficiency (%)

POWER GOOD

80

70
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 3.3 V
60
1m 10m 100m 1 5
Load (A) D008

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018 www.ti.com

Table of Contents
1 Features .................................................................. 1 8 Application and Implementation .......................... 9
2 Applications ........................................................... 1 8.1 Application Information.............................................. 9
3 Description ............................................................. 1 8.2 Typical Application ................................................... 9
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 15
5 Pin Configuration and Functions ......................... 3 10 Layout................................................................... 15
6 Specifications......................................................... 4 10.1 Layout Guidelines ................................................. 15
6.1 Absolute Maximum Ratings ...................................... 4 10.2 Layout Example .................................................... 15
6.2 ESD Ratings.............................................................. 4 10.3 Thermal Considerations ........................................ 15
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 16
6.4 Thermal Information .................................................. 4 11.1 Development Support ........................................... 16
6.5 Electrical Characteristics.......................................... 5 11.2 Documentation Support ........................................ 16
6.6 Typical Characteristics .............................................. 5 11.3 Receiving Notification of Documentation Updates 16
7 Detailed Description .............................................. 6 11.4 Community Resources.......................................... 16
7.1 Overview ................................................................... 6 11.5 Trademarks ........................................................... 16
7.2 Functional Block Diagram ......................................... 6 11.6 Electrostatic Discharge Caution ............................ 17
7.3 Feature Description................................................... 7 11.7 Glossary ................................................................ 17
7.4 Device Functional Modes.......................................... 8 12 Mechanical, Packaging, and Orderable
Information ........................................................... 17

4 Revision History
Changes from Revision A (January 2017) to Revision B Page

• Added Figure 3 to power save mode section......................................................................................................................... 7

Changes from Original (October 2015) to Revision A Page

• Added WEBENCH™ information and hyperlinks to Features, Detailed Design Procedure, and Device Support sections .. 1
• Added SW (AC) to the Absolute Maximum Rating table ....................................................................................................... 4
• Added Table 1, PG Pin Logic ................................................................................................................................................. 8

2 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated

Product Folder Links: TLV62085

 TLV62085
www.ti.com SLVSD63B – OCTOBER 2015 – REVISED JULY 2018

5 Pin Configuration and Functions

RLT Package
7-Pin VSON
Top View

EN 1
7 VIN
PG 2
6 SW
FB 3
5 GND
VOS 4

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
EN 1 IN Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables the
device. This pin has a pulldown resistor of typically 400 kΩ when the device is disabled.
FB 3 IN Feedback pin. Connect a resistor divider to set the output voltage.
GND 5 Ground pin.
PG 2 OUT Power good open drain output pin. The pullup resistor can not be connected to any voltage higher than 6 V. If
unused, leave it floating.
SW 6 PWR Switch pin of the power stage.
VIN 7 PWR Input voltage pin.
VOS 4 IN Output voltage sense pin. This pin must be directly connected to the output capacitor.

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: TLV62085
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018 www.ti.com

6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN MAX UNIT
VIN, FB, VOS, EN, PG – 0.3 7
Voltage at Pins (2) SW (DC) – 0.3 VIN + 0.3 V
SW (AC, less than 100ns) (3) –3 11
Operating Junction, TJ – 40 150 °C
Temperature
Storage, Tstg – 65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) While switching.

6.2 ESD Ratings

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions (1)

MIN NOM MAX UNIT
VIN Input voltage range 2.5 6 V
VOUT Output voltage range 0.8 VIN V
ISINK_PG Sink current at PG pin 1 mA
VPG Pullup resistor voltage 6 V
TJ Operating junction temperature –40 125 °C

(1) Refer to Application and Implementation for further information.

6.4 Thermal Information

TLV62085
THERMAL METRIC (1) RLT [VSON] UNIT
7 PINS
RθJA Junction-to-ambient thermal resistance 107.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 66.2 °C/W
RθJB Junction-to-board thermal resistance 17.1 °C/W
ψJT Junction-to-top characterization parameter 2.1 °C/W
ψJB Junction-to-board characterization parameter 17.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

4 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated

Product Folder Links: TLV62085

 TLV62085
www.ti.com SLVSD63B – OCTOBER 2015 – REVISED JULY 2018

6.5 Electrical Characteristics

TJ = 25 °C, and VIN = 3.6 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current into VIN No load, device not switching 17 µA
ISD Shutdown current into VIN EN = Low 0.7 µA
Under voltage lock out threshold VIN falling 2.1 2.2 2.3 V
VUVLO
Under voltage lock out hysteresis VIN rising 200 mV
Thermal shutdown threshold TJ rising 150 °C
TJSD
Thermal shutdown hysteresis TJ falling 20 °C
LOGIC INTERFACE EN
VIH High-level input voltage VIN = 2.5 V to 6.0 V 1.0 V
VIL Low-level input voltage VIN = 2.5 V to 6.0 V 0.4 V
IEN,LKG Input leakage current into EN pin EN = High 0.01 µA
RPD Pull-down resistance at EN pin EN = Low 400 kΩ
SOFT START, POWER GOOD
tSS Soft start time Time from EN high to 95% of VOUT nominal 0.8 ms
VOUT rising, referenced to VOUT nominal 95%
VPG Power good threshold
VOUT falling, referenced to VOUT nominal 90%
VPG,OL Low-level output voltage Isink = 1 mA 0.4 V
IPG,LKG Input leakage current into PG pin VPG = 5.0 V 0.01 µA
OUTPUT
PWM mode, 2.5 V ≤ VIN ≤ 6 V
VFB Feedback regulation voltage 792 800 808 mV
TJ = 0°C to 85 °C
IFB,LKG Feedback input leakage current VFB = 1 V 0.01 µA
RDIS Output discharge resistor EN = LOW, VOUT = 1.8 V 260 Ω
POWER SWITCH
High-side FET on-resistance ISW = 500 mA 31 mΩ
RDS(on)
Low-side FET on-resistance ISW = 500 mA 23 mΩ
ILIM High-side FET switch current limit 3.7 4.6 5.5 A
fSW PWM switching frequency IOUT = 1 A 2.4 MHz

6.6 Typical Characteristics

5x106

106
Switching Frequency (Hz)

105

104
VIN = 2.5 V
VIN = 3.6 V
VIN = 6.0 V
103
1m 10m 100m 1 5
Load (A) D007

VOUT = 1.2 V
Figure 1. Switching Frequency

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: TLV62085
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018 www.ti.com

7 Detailed Description

7.1 Overview
The TLV62085 synchronous step-down converter is based on the DCS-Control (Direct Control with Seamless
transition into Power Save Mode) topology. This is an advanced regulation topology that combines the
advantages of hysteretic, voltage, and current mode control schemes.
The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions
and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal switching
frequency of 2.4 MHz, having a controlled frequency variation over the input voltage range. As the load current
decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC's
current consumption to achieve high efficiency over the entire load current range. Because DCS-Control supports
both operation modes (PWM and PFM) within a single building block, the transition from PWM mode to Power
Save Mode is seamless and without effects on the output voltage. The device offers both excellent DC voltage
and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with
RF circuits.

7.2 Functional Block Diagram

PG
Hiccup
Counter VIN
VFB

VREF High Side

Current Sense

Bandgap
EN Undervoltage Lockout
(1) Thermal Shutdown
400kΩ
MOSFET Driver SW
Control Logic

GND
Ramp Direct Control
Comparator and VOS
Compensation
Timer
ton
FB

Error Amplifier VREF 260Ω

TM
DCS - Control

EN Output Discharge
Logic
Note:
(1) When the device is enabled, the 400 kΩ resistor is disconnected.

Figure 2. Functional Block Diagram

6 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated

Product Folder Links: TLV62085

 TLV62085
www.ti.com SLVSD63B – OCTOBER 2015 – REVISED JULY 2018

7.3 Feature Description

7.3.1 Power Save Mode
As the load current decreases, the TLV62085 enters Power Save Mode (PSM) operation. During Power Save
Mode, the converter operates with reduced switching frequency and with a minimum quiescent current
maintaining high efficiency. Power Save Mode occurs when the inductor current becomes discontinuous. Power
Save Mode is based on a fixed on-time architecture, as related in Equation 1. The switching frequency over the
whole load current range is also shown in Figure 1 for a shown typical application.
V
t ON = 420 ns ´ OUT
VIN
2 ´ IOUT
fPFM =
VIN V - VOUT
t ON2 ´ ´ IN
VOUT L (1)
In PSM, the output voltage rises slightly above the nominal output voltage, as shown in Figure 10. This effect is
minimized by increasing the output capacitor or inductor value.
During PAUSE period in PSM (shown in Figure 3), the device does not change the PG pin state nor does it
detect an UVLO event, in order to achieve a minimum quiescent current and maintain high efficiency at light
loads.

VOUT
tPAUSE

IINDUCTOR
tON

Figure 3. Power Save Mode Waveform Diagram

7.3.2 100% Duty Cycle Low Dropout Operation

The device offers low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This is particularly
useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage to maintain output regulation, depending on the load current
and output voltage can be calculated as:
VIN,MIN = VOUT + IOUT,MAX ´ (RDS(on) + RL )

with
• VIN,MIN = Minimum input voltage to maintain an output voltage
• IOUT,MAX = Maximum output current
• RDS(on) = High-side FET ON-resistance
• RL = Inductor ohmic resistance (DCR) (2)

7.3.3 Soft Start

The TLV62085 has an internal soft-start circuitry which monotonically ramps up the output voltage and reaches
the nominal output voltage during a soft-start time of typically 0.8 ms. This avoids excessive inrush current and
creates a smooth output voltage slope. It also prevents excessive voltage drops of primary cells and
rechargeable batteries with high internal impedance. The device is able to start into a prebiased output capacitor.
The device starts with the applied bias voltage and ramps the output voltage to its nominal value.

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: TLV62085
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018 www.ti.com

Feature Description (continued)

7.3.4 Switch Current Limit and Hiccup Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET
is turned off and the low-side MOSFET is turned on to ramp down the inductor current. When this switch current
limits is triggered 32 times, the device stops switching and enables the output discharge. The device then
automatically starts a new start-up after a typical delay time of 66 µs has passed. This is named HICCUP short-
circuit protection. The device repeats this mode until the high load condition disappears.

7.3.5 Undervoltage Lockout

To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) is implemented,
which shuts down the device at voltages lower than VUVLO with a hysteresis of 200 mV.

7.3.6 Thermal Shutdown

The device goes into thermal shutdown and stops switching when the junction temperature exceeds TJSD. When
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.

7.4 Device Functional Modes

7.4.1 Enable and Disable
The device is enabled by setting the EN pin to a logic HIGH. Accordingly, shutdown mode is forced if the EN pin
is pulled LOW with a shutdown current of typically 0.7 μA.
In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal
resistor of 260 Ω discharges the output through the VOS pin smoothly. The output discharge function also works
when thermal shutdown, UVLO, or short-circuit protection are triggered.
An internal pulldown resistor of 400 kΩ is connected to the EN pin when the EN pin is LOW. The pulldown
resistor is disconnected when the EN pin is HIGH.

7.4.2 Power Good

The TLV62085 has a power good output. The power good goes high impedance once the output is above 95%
of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.
The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 6 V. The PG signal can be used for sequencing of multiple rails
by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used. Table 1 shows
the PG pin logic.

Table 1. PG Pin Logic

LOGIC STATUS
DEVICE CONDITIONS
HIGH Z LOW
EN = High, VFB ≥ VPG √
Enable
EN = High, VFB ≤ VPG √
Shutdown EN = Low √
Thermal Shutdown TJ > TJSD √
UVLO 0.5 V < VIN < VUVLO √
Power Supply Removal VIN ≤ 0.5 V √

8 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated

Product Folder Links: TLV62085

 TLV62085
www.ti.com SLVSD63B – OCTOBER 2015 – REVISED JULY 2018

8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TLV62085 is a synchronous step-down converter in which output voltage is adjusted by component
selection. The following section discusses the design of the external components to complete the power supply
design for several input and output voltage options by using the typical applications as a reference.

8.2 Typical Application

TLV62085 L1
0.47µH
VIN VOUT
VIN SW
2.5V to 6V C1 C2 1.8V
EN VOS R1 R3
10µF 22µF
138k 1M
FB
GND PG R2
110k
POWER GOOD

Figure 4. 1.8-V Output Voltage Application

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the input parameters.

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage 2.5 V to 6 V
Output voltage 1.8 V
Output current ≤3A
Output ripple voltage <30 mV

Table 3 lists the components used for the example.

Table 3. List of Components (1)

REFERENCE DESCRIPTION MANUFACTURER
C1 10 µF, Ceramic capacitor, 10 V, X7R, size 0805, GRM21BR71A106ME51L Murata
C2 22 µF, Ceramic capacitor, 6.3 V, X5R, size 0805, GRM21BR60J226ME39L Murata
L1 0.47 µH, Power Inductor, size 4 mm × 4 mm × 1.5 mm, XFL4015-471ME Coilcraft
R1 Depending on the output voltage, 1%, size 0603; Std
R2 110 kΩ, Chip resistor, 1/16 W, 1%, size 0603; Std
R3 1 MΩ, Chip resistor, 1/16 W, 1%, size 0603 Std

(1) See Third-Party Products discalimer.

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: TLV62085
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018 www.ti.com

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design with WEBENCH® Tools

Click here to create a custom design using the TLV62085 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Setting The Output Voltage

The output voltage is set by an external resistor divider according to Equation 3:
æ R1 ö æ R1 ö
VOUT = VFB ´ ç 1 + ÷ = 0.8 V ´ ç 1 + R2 ÷
è R2 ø è ø (3)
R2 must not be higher than 180 kΩ to achieve high efficiency at light load while providing acceptable noise
sensitivity.

8.2.2.3 Output Filter Design

The inductor and the output capacitor together provide a low-pass filter. To simplify the selection process,
Table 4 outlines possible inductor and capacitor value combinations for most applications.

Table 4. Matrix of Output Capacitor and Inductor Combinations

NOMINAL COUT [µF] (2)
NOMINAL L [µH] (1)
10 22 47 100 150
0.47 + (3) + + +
1 + + + + +
2.2

(1) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and
–30%.
(2) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by
20% and –50%.
(3) Typical application configuration. Other '+' mark indicates recommended filter combinations.
8.2.2.4 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, Equation 4 is given.
DI
IL,MAX = IOUT,MAX + L
2

VOUT
1-
VIN
DIL = VOUT ´
L ´ fSW

where
• IOUT,MAX = Maximum output current
• ΔIL = Inductor current ripple
10 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated

Product Folder Links: TLV62085

 TLV62085
www.ti.com SLVSD63B – OCTOBER 2015 – REVISED JULY 2018

• fSW = Switching frequency

• L = Inductor value (4)
TI recommends choosing the saturation current for the inductor 20% to 30% higher than the IL,MAX, out of
Equation 4. A higher inductor value is also useful to lower ripple current but increases the transient response
time as well. The following inductors are recommended to be used in designs.

Table 5. List of Recommended Inductors (1)

INDUCTANCE CURRENT RATING DIMENSIONS DC RESISTANCE
PART NUMBER
[µH] [A] L × W × H [mm3] [mΩ typical]
0.47 6.6 4 × 4 × 1.5 7.6 Coilcraft XFL4015-471
0.47 4.7 3.2 × 2.5 × 1.2 21 TOKO DFE322512-R47N
1 5.1 4×4×2 10.8 Coilcraft XFL4020-102

(1) See Third-Party Products disclaimer.

8.2.2.5 Capacitor Selection

The input capacitor is the low-impedance energy source for the converter which helps to provide stable
operation. A low ESR multilayer ceramic capacitor is recommended for best filtering and must be placed between
VIN and GND as close as possible to those pins. For most applications, 10 μF is sufficient, though a larger value
reduces input current ripple.
The architecture of the TLV62085 allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends
using X7R or X5R dielectrics. The recommended typical output capacitor value is 22 μF; this capacitance can
vary over a wide range as outline in the output filter selection table. Output capacitors above 150uF may be used
with a reduced load current during startup to avoid triggering the short circuit protection.
A feed-forward capacitor is not required for device proper operation.

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: TLV62085
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018 www.ti.com

8.2.3 Application Curves

VIN = 3.6 V, TA = 25 ºC, unless otherwise noted

100 100

90 90

Efficiency (%)
Efficiency (%)

80 80

70 VIN = 2.5 V 70 VIN = 2.5 V

VIN = 3.3 V VIN = 3.3 V
VIN = 4.2 V VIN = 4.2 V
VIN = 5.0 V VIN = 5.0 V
60 60
1m 10m 100m 1 5 1m 10m 100m 1 5
Load (A) D001 Load (A) D002
VOUT = 0.95 V VOUT = 1.2 V

Figure 5. Efficiency Figure 6. Efficiency

100 100

90 90
Efficiency (%)

Efficiency (%)

80 80

70 70 VIN = 2.5 V
VIN = 3.6 V VIN = 3.3 V
VIN = 4.2 V VIN = 4.2 V
VIN = 5.0 V VIN = 5.0 V
60 60
1m 10m 100m 1 5 1m 10m 100m 1 5
Load (A) D003 Load (A) D004
VOUT = 3.3 V VOUT = 1.8 V

Figure 7. Efficiency Figure 8. Efficiency

1.212 1.212

1.206 1.206
Output Voltage (V)

Output Voltage (V)

1.200 1.200

1.194 1.194
TA = -40°C TA = -40°C
TA = 25°C TA = 25°C
TA = 85°C TA = 85°C
1.188 1.188
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1m 10m 100m 1 5
Input Voltage (V) D005
Load (A) D006
IOUT = 1 A

Figure 9. Line Regulation Figure 10. Load Regulation

12 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated

Product Folder Links: TLV62085

 TLV62085
www.ti.com SLVSD63B – OCTOBER 2015 – REVISED JULY 2018

t -- 300ns/div t -- 500ns/div

Vout (AC, 20mV/div)

Vout (AC, 20mV/div)

Icoil (DC, 1A/div)

Icoil (DC, 1A/div)

SW (DC, 5V/div) SW (DC, 5V/div)

IOUT = 3 A VOUT = 1.2 V IOUT = 0.1 A VOUT = 1.2 V

Figure 11. PWM Operation Figure 12. PFM Operation

t -- 200μs/div t -- 200μs/div

Load (DC, 2A/div)

EN (DC, 5V/div)

Vout (AC, 50mV/div)

PG (DC, 5V/div)

Vout (DC, 0.5V/div)

Icoil (DC, 2A/div)

Icoil (DC, 2A/div)

IOUT = 0 A to 3 A VOUT = 1.2 V ROUT = 0.47 Ω VOUT = 1.2 V

Figure 13. Load Sweep Figure 14. Start-Up with Load

t -- 200μs/div t -- 5μs/div

EN (DC, 5V/div)

EN (DC, 5V/div)

Vout (DC, 0.5V/div)

PG (DC, 5V/div)

PG (DC, 5V/div)

Vout (DC, 0.5V/div)

Icoil (DC, 2A/div)

Icoil (DC, 0.5A/div)

VOUT = 1.2 V ROUT = 0.47 Ω VOUT = 1.2 V

Figure 15. Start-Up without Load Figure 16. Shutdown with Load

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: TLV62085
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018 www.ti.com

t -- 5ms/div t -- 2μs/div

EN (DC, 5V/div) Load (DC, 2A/div)

Vout (DC, 0.5V/div)

PG (DC, 5V/div)
PG (DC, 5V/div)

Vout (DC, 0.1V/div)

Icoil (DC, 0.5A/div)

Icoil (DC, 2A/div)

VOUT = 1.2 V IOUT = 0.5 A to 3 A VOUT = 1.2 V

Figure 17. Shutdown without Load Figure 18. Load Transient

t -- 3μs/div t -- 200μs/div

Load (DC, 2A/div) PG (DC, 5V/div)

Vout (DC, 0.5V/div)

PG (DC, 5V/div)

Vout (DC, 0.1V/div)

Icoil (DC, 2A/div)

Icoil (DC, 2A/div)

IOUT = 50mA to 3A VOUT = 1.2 V ROUT = 0.47 Ω VOUT = 1.2 V

Figure 19. Load Transient Figure 20. Output Short-Circuit Protection, Entry

t -- 200μs/div t -- 5μs/div

PG (DC, 5V/div) PG (DC, 5V/div)

Vout (DC, 0.5V/div) Vout (DC, 0.5V/div)

Icoil (DC, 2A/div) Icoil (DC, 2A/div)

ROUT = 0.47 Ω VOUT = 1.2 V ROUT = 0.47 Ω VOUT = 1.2 V

Figure 21. Output Short-Circuit Protection, Recovery Figure 22. Output Short-Circuit Protection,
HICCUP Zoom In

14 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated

Product Folder Links: TLV62085

 TLV62085
www.ti.com SLVSD63B – OCTOBER 2015 – REVISED JULY 2018

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 2.5 V to 6 V. Ensure that the input
power supply has a sufficient current rating for the application.

10 Layout

10.1 Layout Guidelines

The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the TLV62085
device.
The input and output capacitors and the inductor must be placed as close as possible to the IC. This keeps the
traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance.
The low side of the input and output capacitors must be connected directly to the GND pin to avoid a ground
potential shift. The sense traces connected to FB and VOS pins are signal traces. Special care must be taken to
avoid noise being induced. By a direct routing, parasitic inductance can be kept small. GND layers might be used
for shielding. Keep these traces away from SW nodes. See Figure 23 for the recommended PCB layout.

10.2 Layout Example

L1

VOUT

VIN
C1 C2
Solution Size
GND
VIN

SW

62 mm
2
GND
VOS
PG
EN

FB

R2

R1

Figure 23. PCB Layout Recommendation

10.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are:
• Improving the power dissipation capability of the PCB design
• Introducing airflow in the system
The big copper planes connecting to the pads of the IC on the PCB improve the thermal performance of the
device. For more details on how to use the thermal parameters, see the Thermal Characteristics Application
Notes, SZZA017 and SPRA953.

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TLV62085
TLV62085
SLVSD63B – OCTOBER 2015 – REVISED JULY 2018 www.ti.com

11 Device and Documentation Support

11.1 Development Support

11.1.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TLV62085 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.1.2 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation
For related documentation, see the following:
• Thermal Characteristics Application Note, SZZA017
• Thermal Characteristics Application Note, SPRA953

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.5 Trademarks
DCS-Control, WEBENCH, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.

16 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated

Product Folder Links: TLV62085

 TLV62085
www.ti.com SLVSD63B – OCTOBER 2015 – REVISED JULY 2018

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2015–2018, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TLV62085
 PACKAGE OPTION ADDENDUM

www.ti.com 18-Jul-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TLV62085RLTR ACTIVE VSON-HR RLT 7 3000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 12Q5 Samples

TLV62085RLTT ACTIVE VSON-HR RLT 7 250 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 12Q5 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 18-Jul-2022

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 31-Jan-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV62085RLTR VSON- RLT 7 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
HR
TLV62085RLTT VSON- RLT 7 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
HR
TLV62085RLTT VSON- RLT 7 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
HR

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 31-Jan-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV62085RLTR VSON-HR RLT 7 3000 210.0 185.0 35.0
TLV62085RLTT VSON-HR RLT 7 250 210.0 185.0 35.0
TLV62085RLTT VSON-HR RLT 7 250 182.0 182.0 20.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RLT0007A VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

B 2.1 A
1.9

PIN 1
INDEX AREA 2.1
1.9

C
1 MAX

SEATING PLANE
0.08
0.05
0.00

(0.2) TYP 3X 0.5

0.3 (0.2) TYP

3X 0.5
4 2X 0.6
5

1.2
1.5

7
1
4X 0.3
0.2 3X 0.35
3X 1.4 0.25
0.1 C A B 1.2
0.1 C A B
0.05 C PIN 1 ID 0.05 C
0.5
0.3

4220429/A 09/2014
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
RLT0007A VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

PKG
(0.6)
℄
1
(0.25)
7

2X (0.6)

PKG
3X (0.5)
℄

3X (0.25)
5
3X (0.3)
4
3X (1.5)
3X (0.6)

(0.9) (0.45)

LAND PATTERN EXAMPLE

SCALE: 30X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK
METAL
OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
PADS 1 - 4 PADS 5 - 7

SOLDER MASK DETAILS 4220429/A 09/2014

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
5. Vias should not be placed on soldering pads unless they are plugged or plated shut.

www.ti.com
 EXAMPLE STENCIL DESIGN
RLT0007A VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

PKG 6X (0.65)
℄
(0.6)
(0.21)

1
7

EXPOSED METAL
TYP
2X (0.6)

PKG
3X (0.5) ℄
METAL UNDER
SOLDER MASK
TYP
3X (0.21)
6X (0.3)

4
5

3X (0.025) 3X
3X (0.6) EXPOSED METAL

(0.9) (0.875) SOLDER MASK EDGE

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

FOR ALL EXPOSED PADS

85% PRINTED SOLDER COVERAGE BY AREA
SCALE: 40X

4220429/A 09/2014
NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated