Can Communication PDF

Product Sample & Technical Tools & Support &
Folder Buy Documents Software Community
SN65HVD233, SN65HVD234, SN65HVD235

SLLS557G – NOVEMBER 2002 – REVISED JANUARY 2015
SN65HVD23x 3.3-V CAN Bus Transceivers

1 Features 3 Description
•
1 Single 3.3-V Supply Voltage The SN65HVD233, SN65HVD234, and SN65HVD235
are used in applications employing the controller area
• Bus Pins Fault Protection Exceeds ±36 V network (CAN) serial communication physical layer in
• Bus Pins ESD Protection Exceeds ±16 kV HBM accordance with the ISO 11898 standard. As a CAN
• Compatible With ISO 11898-2 transceiver, each provides transmit and receive
• GIFT/ICT Compliant capability between the differential CAN bus and a
CAN controller, with signaling rates up to 1 Mbps.
• Data Rates up to 1 Mbps
Designed for operation in especially harsh
• Extended –7 V to 12 V Common Mode Range
environments, the devices feature cross-wire
• High-Input Impedance Allows for 120 Nodes protection, overvoltage protection up to ±36 V, loss of
• LVTTL I/Os are 5-V Tolerant ground protection, overtemperature (thermal
• Adjustable Driver Transition Times for Improved shutdown) protection, and common-mode transient
Emissions Performance protection of ±100 V. These devices operate over a
wide –7 V to 12 V common-mode range. These
• Unpowered Node Does Not Disturb the Bus transceivers are the interface between the host CAN
• Low Current Standby Mode, 200-μA (Typical) controller on the microprocessor and the differential
• SN65HVD233: Loopback Mode CAN bus used in industrial, building automation,
transportation, and automotive applications.
• SN65HVD234: Ultra Low Current Sleep Mode
– 50-nA Typical Current Consumption Device Information(1)
• SN65HVD235: Autobaud Loopback Mode PART NUMBER PACKAGE BODY SIZE (NOM)
• Thermal Shutdown Protection SN65HVD233
• Power up and Down With Glitch-Free Bus Inputs SN65HVD234 SOIC (8) 4.90 mm × 3.91 mm
and Outputs SN65HVD235
– High-Input Impedance With Low VCC (1) For all available packages, see the orderable addendum at
the end of the datasheet.
– Monolithic Output During Power Cycling
Block Diagram
2 Applications VCC
• Industrial Automation, Control, Sensors, and Drive VCC
Systems VCC
VCC
• Motor and Robotic Control D
• Building and Climate Control (HVAC)
BIAS UNIT
• Backplane Communication and Control
• CAN Bus Standards such as CANopen,
DeviceNet, CAN Kingdom, ISO 11783, NMEA VCC
2000, SAE J1939
RS SLOPE CONTROL
and MODE
LOGIC
LBK / EN /AB
GND
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLLS557G – NOVEMBER 2002 – REVISED JANUARY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 10 Detailed Description ........................................... 19
2 Applications ........................................................... 1 10.1 Overview ............................................................... 19
3 Description ............................................................. 1 10.2 Functional Block Diagrams ................................... 19
4 Revision History..................................................... 2 10.3 Feature Description............................................... 19
10.4 Device Functional Modes...................................... 21
5 Description (continued)......................................... 4
6 Device Options....................................................... 4 11 Application and Implementation........................ 23
11.1 Application Information.......................................... 23
7 Pin Configuration and Functions ......................... 5
11.2 Typical Application ................................................ 24
8 Specifications......................................................... 5
11.3 System Example ................................................... 26
8.1 Absolute Maximum Ratings ..................................... 5
12 Power Supply Recommendations ..................... 28
8.2 ESD Ratings.............................................................. 6
8.3 Recommended Operating Conditions....................... 6 13 Layout................................................................... 28
13.1 Layout Guidelines ................................................. 28
8.4 Thermal Information .................................................. 6
13.2 Layout Example .................................................... 29
8.5 Power Dissipation Ratings ........................................ 6
8.6 Electrical Characteristics: Driver ............................... 7 14 Device and Documentation Support ................. 29
8.7 Electrical Characteristics: Receiver .......................... 8 14.1 Related Links ........................................................ 29
8.8 Switching Characteristics: Driver .............................. 8 14.2 Trademarks ........................................................... 29
8.9 Switching Characteristics: Receiver.......................... 9 14.3 Electrostatic Discharge Caution ............................ 29
8.10 Switching Characteristics: Device ........................... 9 14.4 Glossary ................................................................ 29
8.11 Typical Characteristics .......................................... 10 15 Mechanical, Packaging, and Orderable
9 Parameter Measurement Information ................ 12 Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (August 2008) to Revision G Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Changed the Functional Block Diagrams ............................................................................................................................... 4
• Added the THERMAL SHUTDOWN paragraph to the Application Information section ....................................................... 21
• Changed the BUS CABLE paragraph to BUS LOADING, LENGTH AND NUMBER OF NODES paragraph in the
Application Information section............................................................................................................................................. 24
• Added the CAN TERMINATION paragraph to the Application Information section ............................................................. 24
Changes from Revision E (October 2007) to Revision F Page
• Changed Figure 17, Receiver Test Circuit and Voltage Waveform. From: CL = 50 pF ±20% to: CL = 15 pF ±20% ........... 13
Changes from Revision D (June 2005) to Revision E Page
• Added 60-Ω load test condition to Figure 3 ......................................................................................................................... 10

• Deleted INTEROPERABILITY WITH 5-V CAN SYSTEMS section...................................................................................... 26
• Added ISO 11898 COMPLIANCE OF SN65HVD230 FAMILY OF 3.3-V CAN TRANSCEIVERS section .......................... 26
Changes from Revision C (March 2005) to Revision D Page
• Added Features Bullet: GIFT/ICT Compliant (SN65HVD234)................................................................................................ 1
2 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVD233 SN65HVD234 SN65HVD235

www.ti.com SLLS557G – NOVEMBER 2002 – REVISED JANUARY 2015
Changes from Revision B (June 2003) to Revision C Page
• Added IO, Receiver output current to the Abs Max Table ...................................................................................................... 5
Changes from Revision A (March 2003) to Revision B Page
• Changed the data sheet from Product Preview to Production for part number SN65HVD234 and SN65HVD235. .............. 1
• Added , Thermal Characteristics ............................................................................................................................................ 5
• Changed the APPLICATION INFORMATION section.......................................................................................................... 23
Changes from Original (November 2002) to Revision A Page
• Changed the data sheet from Product Preview to Production for part number SN65HVD233.............................................. 1
Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

5 Description (continued)
Modes: The RS pin (pin 8) of the SN65HVD233, SN65HVD234, and SN65HVD235 provides three modes of
operation: high-speed, slope control, and low-power standby mode. The high-speed mode of operation is
selected by connecting pin 8 directly to ground, allowing the driver output transistors to switch on and off as fast
as possible with no limitation on the rise and fall slope. The rise and fall slope can be adjusted by connecting a
resistor between the RS pin and ground. The slope will be proportional to the pin's output current. With a resistor
value of 10 kΩ the device driver will have a slew rate of ~15 V/μs and with a value of 100 kΩ the device will have
~2.0 V/μs slew rate. For more information about slope control, refer to Feature Description.
The SN65HVD233, SN65HVD234, and SN65HVD235 enter a low-current standby (listen only) mode during
which the driver is switched off and the receiver remains active if a high logic level is applied to the RS pin. If the
local protocol controller needs to transmit a message to the bus it will have to return the device to either high-
speed mode or slope control mode via the RS pin.
Loopback (SN65HVD233): A logic high on the loopback (LBK) pin (pin 5) of the SN65HVD233 places the bus
output and bus input in a high-impedance state. Internally, the D to R path of the device remains active and
available for driver to receiver loopback that can be used for self-diagnostic node functions without disturbing the
bus. For more information on the loopback mode, refer to Feature Description.
Ultra Low-Current Sleep (SN65HVD234): The SN65HVD234 enters an ultra low-current sleep mode in which
both the driver and receiver circuits are deactivated if a low logic level is applied to EN pin (pin 5). The device
remains in this sleep mode until the circuit is reactivated by applying a high logic level to pin 5.
Autobaud Loopback (SN65HVD235): The AB pin (pin 5) of the SN65HVD235 implements a bus listen-only
loopback feature which allows the local node controller to synchronize its baud rate with that of the CAN bus. In
autobaud mode, the bus output of the driver is placed in a high-impedance state while the bus input of the
receiver remains active. There is an internal D pin to R pin loopback to assist the controller in baud rate
detection, or the autobaud function. For more information on the autobaud mode, refer to Feature Description.
6 Device Options (1)
SLOPE DIAGNOSTIC AUTOBAUD

PART NUMBER LOW POWER MODE
CONTROL LOOPBACK LOOPBACK
SN65HVD233D 200-μA standby mode Adjustable Yes No
SN65HVD234D 200-μA standby mode or 50-nA sleep mode Adjustable No No
SN65HVD235D 200-μA standby mode Adjustable No Yes
(1) For the most current package and ordering information, see Mechanical, Packaging, and Orderable Information, or see the TI web site
at www.ti.com.

7 Pin Configuration and Functions

SN65HVD233D SN65HVD234D SN65HVD235D
(Marked as VP233) (Marked as VP234) (Marked as VP235)
(TOP VIEW) (TOP VIEW) (TOP VIEW)
D 1 8 RS D 1 8 RS D 1 8 RS
GND 2 7 CANH GND 2 7 CANH GND 2 7 CANH
VCC 3 6 CANL VCC 3 6 CANL VCC 3 6 CANL
R 4 5 LBK R 4 5 EN R 4 5 AB
Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
CAN transmit data input (LOW for dominant and HIGH for recessive bus states), also called TXD, driver
D 1 I
input
GND 2 GND Ground connection
VCC 3 Supply Transceiver 3.3-V supply voltage
CAN receive data output (LOW for dominant and HIGH for recessive bus states), also called RXD, receiver
R 4 O
output
LBK I SN65HVD233: Loopback mode input pin
SN65HVD234: Enable input pin. Logic high for enabling a normal mode (high speed or slope control)
EN 5 I
mode. Logic low for sleep mode.
AB I SN65HVD235: Autobaud loopback mode input pin
CANL 6 I/O Low level CAN bus line
CANH 7 I/O High level CAN bus line
Mode select pin: strong pulldown to GND = high speed mode, strong pullup to VCC = low power mode, 10-
RS 8 I
kΩ to 100-kΩ pulldown to GND = slope control mode
8 Specifications
8.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range unless otherwise noted
MIN MAX UNIT
VCC Supply voltage –0.3 7 V
Voltage at any bus terminal (CANH or CANL) –36 36 V
Voltage input, transient pulse, CANH and CANL, through 100 Ω (see
–100 100 V
Figure 18)
VI Input voltage, (D, RS, EN, LBK, AB) –0.5 7 V
VO Output voltage –0.5 7 V
IO Receiver output current –10 10 mA
Continuous total power dissipation See Power Dissipation Ratings
TJ Operating junction temperature 150
°C
Tstg Storage temperature 125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground pin.

8.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS- CANH, CANL and GND ±16000
Electrostatic 001 (1)
V(ESD) All pins 3000 V
discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 3 3.6
Voltage at any bus terminal (separately or common mode) –7 12
VIH High-level input voltage D, EN, AB, LBK 2 5.5 V
VIL Low-level input voltage D, EN, AB, LBK 0 0.8
VID Differential input voltage between CANH and CANL –6 6
Resistance from RS to ground 0 100 kΩ
VI(Rs) Input Voltage at RS for standby 0.75 VCC 5.5 V
Driver –50
IOH High-level output current mA
Receiver –10
Driver 50
IOL Low-level output current mA
Receiver 10
TJ Operating junction temperature HVD233, HVD234, HVD235 150 °C
(1)
TA Operating free-air temperature HVD233, HVD234, HVD235 –40 125 °C
(1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
8.4 Thermal Information

over operating free-air temperature range (unless otherwise noted)
PARAMETERS TEST CONDITIONS VALUE UNIT
Low-K (2) board, no air flow 185
RθJA Junction-to-ambient thermal resistance (1) °C/W
High-K (3) board, no air flow 101
RθJB Junction-to-board thermal resistance High-K (3) board, no air flow 82.8 °C/W
RθJC Junction-to-case thermal resistance 26.5 °C/W
RL = 60 Ω, RS at 0 V, input to D a 1-MHz 50% duty
P(AVG) Average power dissipation 36.4 mW
cycle square wave VCC at 3.3 V, TA = 25°C
T(SD) Thermal shutdown junction temperature 170 °C
(1) See SZZA003 for an explanation of this parameter.

(2) JESD51-3 low effective thermal conductivity test board for leaded surface mount packages.
(3) JESD51-7 high effective thermal conductivity test board for leaded surface mount packages.
8.5 Power Dissipation Ratings

CIRCUIT TA ≤ 25°C DERATING FACTOR (1) TA = 85°C TA = 125°C
PACKAGE
BOARD POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
D Low-K 596.6 mW 5.7 mW/°C 255.7 mW 28.4 mW
D High-K 1076.9 mW 10.3 mW/°C 461.5 mW 51.3 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

8.6 Electrical Characteristics: Driver

PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
Bus output voltage CANH D at 0 V, RS at 0 V, See Figure 12 and 2.45 VCC
VO(D) V
(Dominant) CANL Figure 13 0.5 1.25
Bus output voltage CANH D at 3 V, RS at 0 V, See Figure 12 and 2.3
VO V
(Recessive) CANL Figure 13 2.3
D at 0 V, RS at 0 V, See Figure 12 and
1.5 2 3
Figure 13
VOD(D) Differential output voltage (Dominant) V
1.2 2 3
Figure 14
–120 12 mV
VOD Differential output voltage (Recessive) Figure 13
D at 3 V, RS at 0 V, No Load –0.5 0.05 V
VOC(pp) Peak-to-peak common-mode output voltage See Figure 21 1 V
D, EN, LBK,
IIH High-level input current D = 2 V or EN = 2 V or LBK = 2 V or AB = 2 V –30 30 μA
AB
D, EN, LBK, D = 0.8 V or EN = 0.8 V or LBK = 0.8 V or AB
IIL Low-level input current –30 30 μA
AB = 0.8 V
VCANH = –7 V, CANL Open, See Figure 26 –250
VCANH = 12 V, CANL Open, See Figure 26 1
IOS Short-circuit output current mA
VCANL = –7 V, CANH Open, See Figure 26 –1
VCANL = 12 V, CANH Open, See Figure 26 250
CO Output capacitance See receiver input capacitance
IIRs(s) RS input current for standby RS at 0.75 VCC –10 μA
Sleep EN at 0 V, D at VCC, RS at 0 V or VCC 0.05 2
RS at VCC, D at VCC, AB at 0 V, LBK at 0 V, μA
Standby 200 600
EN at VCC
ICC Supply current D at 0 V, No Load, AB at 0 V, LBK at 0 V,
Dominant 6
RS at 0 V, EN at VCC
mA
D at VCC, No Load, AB at 0 V, LBK at 0 V,
Recessive 6
RS at 0 V, EN at VCC
(1) All typical values are at 25°C and with a 3.3-V supply.

8.7 Electrical Characteristics: Receiver

VIT+ Positive-going input threshold voltage 750 900
VIT– Negative-going input threshold voltage AB at 0 V, LBK at 0 V, EN at VCC, See Table 1 500 650 mV
Vhys Hysteresis voltage (VIT+ – VIT–) 100
VOH High-level output voltage IO = –4 mA, See Figure 17 2.4
V
VOL Low-level output voltage IO = 4 mA, See Figure 17 0.4
CANH or CANL at 12 V 150 500
CANH or CANL at 12 V, Other bus pin at 0 V, 200 600
VCC at 0 V D at 3 V, AB at 0 V,
II Bus input current μA
CANH or CANL at –7 V LBK at 0 V, RS at 0 V, –610 –150
EN at VCC
CANH or CANL at –7 V,
–450 –130
VCC at 0 V
Pin-to-ground, VI = 0.4 sin (4E6πt) + 0.5 V, D at 3 V,
CI Input capacitance (CANH or CANL) 40
AB at 0 V, LBK at 0 V, EN at VCC
pF
Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5 V, D at 3 V,
CID Differential input capacitance 20
AB at 0 V, LBK at 0 V, EN at VCC
RID Differential input resistance 40 100
Input resistance (CANH or CANL) to D at 3 V, AB at 0 V, LBK at 0 V, EN at VCC kΩ
RIN 20 50
ground
Sleep EN at 0 V, D at VCC, RS at 0 V or VCC 0.05 2
μA
Standby RS at VCC, D at VCC, AB at 0 V, LBK at 0 V, EN at VCC 200 600
ICC Supply current D at 0 V, No Load, RS at 0 V, LBK at 0 V, AB at 0 V,
Dominant 6
EN at VCC
mA
D at VCC, No Load, RS at 0 V, LBK at 0 V, AB at 0 V,
Recessive 6
EN at VCC
8.8 Switching Characteristics: Driver

RS at 0 V, See Figure 15 35 85
Propagation delay time,
tPLH RS with 10 kΩ to ground, See Figure 15 70 125 ns
low-to-high-level output
RS with 100 kΩ to ground, See Figure 15 500 870
Propagation delay time,
tPHL RS with 10 kΩ to ground, See Figure 15 130 180 ns
high-to-low-level output
RS at 0 V, See Figure 15 35
tsk(p) Pulse skew (|tPHL – tPLH|) RS with 10 kΩ to ground, See Figure 15 60 ns
RS with 100 kΩ to ground, See Figure 15 370
tr Differential output signal rise time 20 70
RS at 0 V, See Figure 15 ns
tf Differential output signal fall time 20 70
RS with 10 kΩ to ground, See Figure 15 ns
RS with 100 kΩ to ground, See Figure 15 ns
ten(s) Enable time from standby to dominant 0.6 1.5
See Figure 19 and Figure 20 μs
ten(z) Enable time from sleep to dominant 1 5

8.9 Switching Characteristics: Receiver

tPLH Propagation delay time, low-to-high-level output 35 60
tPHL Propagation delay time, high-to-low-level output 35 60
tsk(p) Pulse skew (|tPHL – tPLH|) See Figure 17 7 ns
tr Output signal rise time 2 5
tf Output signal fall time 2 5
8.10 Switching Characteristics: Device

Loopback delay, driver input to
t(LBK) HVD233 See Figure 23 7.5 12 ns
receiver output
Loopback delay, driver input to
t(AB1) See Figure 24 10 20 ns
receiver output
HVD235
Loopback delay, bus input to
t(AB2) See Figure 25 35 60 ns
receiver output
Total loop delay, driver input to receiver output,
t(loop1) RS with 10 kΩ to ground, See Figure 22 105 190 ns
recessive to dominant
Total loop delay, driver input to receiver output,
t(loop2) RS with 10 kΩ to ground, See Figure 22 105 190 ns
dominant to recessive

8.11 Typical Characteristics

Rs, LBK, AB = 0 V; EN = VCC
t (LOOPL2)− Dominant−To−Recessive Loop Time − ns

90 95
t (LOOPL1)− Ressive−To−Dominant Loop Time − ns
Rs, LBK, AB = 0 V Rs, LBK, AB = 0 V

EN = VCC EN = VCC
85 90
VCC = 3 V
80 85
VCC = 3.3 V VCC = 3.6 V
75 VCC = 3.6 V 80
VCC = 3.3 V
70 75
65 70 VCC = 3 V
60 65
−40 5 45 80 125 −40 5 45 80 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 1. Recessive-to-Dominant Loop Time vs Free-Air Figure 2. Dominant-to-Recessive Loop Time vs Free-Air
Temperature Temperature
20 160
VCC = 3.3 V, VCC = 3.3 V,
Rs, LBK, AB = 0 V, Rs, LBK, AB = 0 V,
140
EN = VCC, EN = VCC,
I OL − Driver Output Current − mA

19 TA = 25°C, TA = 25°C
I CC − Supply Current − mA
60-W Load 120
100
18
80
17 60
40
16
20
15 0
200 300 500 700 1000 0 1 2 3 4
f − Frequency − kbps VOL − Low-Level Output Voltage − V
VCC = 3.3 V TA = 25°C 60-Ω Load VCC = 3.3 V TA = 25°C
Figure 3. Supply Current vs Frequency Figure 4. Driver Low-Level Output Current vs Low-Level
Output Voltage
0.12 2.2
VCC = 3.3 V,
I OH − Driver High-Level Output Current − mA
VCC = 3.6 V
Rs, LBK, AB = 0 V,
VOD − Differential Output Voltage − V
0.1 EN = VCC, 2
TA = 25°C
VCC = 3.3 V
0.08 1.8
VCC = 3 V
0.06 1.6
0.04 1.4
0.02 1.2 RL = 60 Ω
Rs, LBK, AB = 0 V
EN = VCC
0 1
0 0.5 1 1.5 2 2.5 3 3.5 −40 5 45 80 125
VOH − High-Level Output Voltage − V TA − Free-Air Temperature − °C
VCC = 3.3 V TA = 25°C RL = 60-Ω
Figure 5. Driver High-Level Output Current vs High-Level Figure 6. Differential Output Voltage vs Free-Air
Output Voltage Temperature

Typical Characteristics (continued)

Rs, LBK, AB = 0 V; EN = VCC
45 38
t PLH − Receiver Low-To-High Propagation Delay − ns
t PHL− Receiver High-To-Low Propagation Delay − ns

Rs, LBK, AB = 0 V Rs, LBK, AB = 0 V
44 EN = VCC EN = VCC
See Figure 6 37 See Figure 6
43
VCC = 3.3 V
42 VCC = 3 V
36
41
40 35 VCC = 3 V
39
34 VCC = 3.3 V
38
VCC = 3.6 V
37
33
VCC = 3.6 V
36
35 32
−40 5 45 80 125 −40 5 45 80 125
See Figure 3 See Figure 3
Figure 7. Receiver Low-to-High Propagation Delay vs Free- Figure 8. Receiver High-to-Low Propagation Delay vs Free-
Air Temperature Air Temperature
55 65
t PLH − Driver Low-To-High Propagation Delay − ns
t PHL− Driver High-To-Low Proragation Delay − ns

Rs, LBK, AB = 0 V
EN = VCC
See Figure 4 60
50 VCC = 3 V
VCC = 3 V VCC = 3.3 V 55

45
50 VCC = 3.3 V
40
45
35
40 VCC = 3.6 V
VCC = 3.6 V
30 Rs, LBK, AB = 0 V
35
EN = VCC
See Figure 4
25 30
−40 5 45 80 125 −40 5 45 80 125
See Figure 1 See Figure 1
Figure 9. Driver Low-to-High Propagation Delay vs Free-Air Figure 10. Driver High-to-Low Propagation Delay vs Free-Air
Temperature Temperature
35
Rs, LBK, AB = 0 V,
30 EN = VCC,
TA = 25°C
I O − Driver Output Current − mA
RL = 60 Ω
25
20
15
10
−5
0 0.6 1.2 1.8 2.4 3 3.6
VCC − Supply Voltage − V
RL = 60-Ω TA = 25°C
Figure 11. Driver Output Current vs Supply Voltage

9 Parameter Measurement Information

IO(CANH)
II D
60 Ω ±1%
VOD
VO(CANH)
VO(CANH) + VO(CANL)
RS IIRs
VI 2
+ IO(CANL) VOC
VI(Rs) VO(CANL)
-
Figure 12. Driver Voltage, Current, and Test Definition
Dominant
≈3V VO(CANH)
Recessive
≈ 2.3 V
≈1V VO(CANL)
Figure 13. Bus Logic State Voltage Definitions
CANH 330 Ω ±1%
D
VI VOD 60 Ω ±1%
+
RS _ -7 V ≤ VTEST ≤ 12 V
CANL
330 Ω ±1%
Figure 14. Driver VOD
CANH
VCC
CL = 50 pF ±20% VI
VCC/2 VCC/2
D (see Note B) 0V
VO
RL = 60 Ω ±1% tPLH tPHL
VI RS + VO(D)
0.9 V 90%
VI(Rs) VO 0.5 V
(see Note A) CANL 10% VO(R)
-
tr tf
A. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz,
50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes fixture and instrumentation capacitance.
Figure 15. Driver Test Circuit and Voltage Waveforms

Parameter Measurement Information (continued)

CANH
R
IO
VI(CANH + VI(CANL) VI(CANH) VID
VIC =
2
CANL VO
VI(CANL)
Figure 16. Receiver Voltage and Current Definitions
2.9 V
CANH 2.2 V 2.2 V
VI
R IO 1.5 V
VI tPLH tPHL
CL = 15 pF ±20%
(see Note A) 1.5 V VO VOH
CANL (see Note B) 90% 90%
VO 50% 50%
10% 10%
VOL
tr tf
A. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz,
50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes fixture and instrumentation capacitance.
Figure 17. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test

INPUT OUTPUT MEASURED
VCANH VCANL R |VID|
–6.1 V –7 V L 900 mV
12 V 11.1 V L 900 mV
VOL
–1 V –7 V L 6V
12 V 6V L 6V
–6.5 V –7 V H 500 mV
12 V 11.5 V H 500 mV
–7 V –1 V H VOH 6V
6V 12 V H 6V
Open Open H X
CANH
100 Ω CANL
Pulse Generator D at 0 V or VCC

15 µs Duration
1% Duty Cycle
Rs, AB, EN, LBK, at 0 V or VCC
tr, tf ≤ 100 ns
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 18. Test Circuit, Transient Overvoltage Test

HVD233 or HVD235 HVD234
RS RS
VI CANH VI CANH
D D 60 Ω ±1%
0V 60 Ω ±1% 0V
AB or LBK EN
VCC
CANL CANL
R
VO VO
+ +
15 pF ±20% 15 pF ±20%
- -
VCC
VI 50%
0V
VOH
50%
VO
VOL
ten(s)
NOTE: All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate
(PRR) = 125 kHz, 50% duty cycle.
Figure 19. Ten(s) Test Circuit and Voltage Waveforms
HVD234
RS VCC
CANH
VI 50%
D 60 Ω ±1%
0V 0V
EN
VI VOH
CANL
50%
VO
R VOL
VO ten(z)
+
15 pF ±20%
-
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 50 kHz, 50% duty cycle.
Figure 20. Ten(z) Test Circuit and Voltage Waveforms
CANH 27 Ω ±1%
VOC(PP)
D
VI VOC
RS CANL VOC
27 Ω ±1% 50 pF ±20%
Figure 21. VOC(pp) Test Circuit and Voltage Waveforms

0Ω, 10 kΩ,
or 100 kΩ ±5% RS DUT
CANH VCC
D VI 50% 50%
VI 60 Ω ±1%
0V
LBK or AB
t(loop2) t(loop1)
HVD233/235 CANL VOH
EN
VCC VO 50% 50%
HVD234
VOL
R
+
VO 15 pF ±20%
-
Figure 22. T(loop) Test Circuit and Voltage Waveforms
RS HVD233 VCC
CANH
VI 50% 50%
D +
VI VOD 60 Ω ±1% 0V
- t(LBK1) t(LBK2)
LBK VOH
VCC CANL
VO 50% 50%
R VOL
t(LBK) = t(LBK1) = t(LBK2)
VOD ≈ 2.3 V
+
VO 15 pF ±20%
-
Figure 23. T(LBK) Test Circuit and Voltage Waveforms
RS HVD235 VOD ≈ 2.3 V

CANH
VCC
D +
VI VOD 60 Ω ±1% VI 50% 50%
- 0V
CANL t(ABH) t(ABL)
AB VOH
VCC
VO 50% 50%
R
VOL
t(AB1) = t(ABH) = t(ABL)
+
VO 15 pF ±20%
-
NOTE: All VI input pulses are supplied by a generator having the following characteristics: tr
or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 24. T(AB1) Test Circuit and Voltage Waveforms

RS HVD235
CANH 2.9 V
VI 2.2 V 2.2 V
D
VCC VI 60 Ω ±1% 1.5 V
1.5 V t(ABH) t(ABL)
AB CANL VOH
VCC
VO 50% 50%
R VOL
t(AB2) = t(ABH) = t(ABL)
+
VO 15 pF ±20%
-
Figure 25. T(AB2) Test Circuit and Voltage Waveforms
 IOS 
IOS
15 s
D CANH
0V
0 V or VCC IOS +
_ VI 12 V
CANL
VI
0V
and 10 µs
0V
VI
-7 V
Figure 26. IOS Test Circuit and Waveforms

3.3 V
TA = 25°C
VCC = 3.3 V
R2 ± 1% R1 ± 1%
R CANH +
VID
CANL - Vac
R2 ± 1% R1 ± 1% VI
The R Output State Does Not Change During

Application of the Input Waveform.
VID R1 R2
500 mV 50 Ω 280 Ω
900 mV 50 Ω 130 Ω
12 V
VI
-7 V
NOTE: All input pulses are supplied by a generator with f ≤ 1.5 MHz.
Figure 27. Common-Mode Voltage Rejection

D INPUT RS INPUT CANH INPUT

VCC VCC VCC
100 kΩ 110 kΩ 9 kΩ
1 kΩ 45 kΩ
INPUT INPUT
9V 40 V 9 kΩ
+
_
INPUT
CANL INPUT CANH and CANL OUTPUTS R OUTPUT

VCC VCC VCC
110 kΩ 9 kΩ
45 kΩ 5Ω
INPUT OUTPUT
OUTPUT
9 kΩ 9V
40 V 40 V
EN INPUT LBK or AB INPUT

VCC VCC
1 kΩ 1 kΩ
INPUT INPUT
9V 100 kΩ 9V 100 kΩ
Figure 28. Equivalent Input and Output Schematic Diagrams

10 Detailed Description
10.1 Overview
This family of CAN transceivers is compatible with the ISO11898-2 High-Speed CAN (controller area network)
physical layer standard. They are designed to interface between the differential bus lines in CAN and the CAN
protocol controller at data rates up to 1 Mpbs.
10.2 Functional Block Diagrams

RS
CANH
D
CANL
LBK
R
LBK
Figure 29. SN65HVD33 Functional Block Diagram
RS
CANH
D
CANL
EN
R
RS
CANH
D
CANL
AB
R
10.3 Feature Description

10.3.1 Diagnostic Loopback (SN65HVD233)
The diagnostic loopback or internal loopback function of the SN65HVD233 is enabled with a high-level input on
pin 5, LBK. This mode disables the driver output while keeping the bus pins biased to the recessive state. This
mode also redirects the D data input (transmit data) through logic to the received data output pin), thus creating
an internal loopback of the transmit to receive data path. This mimics the loopback that occurs normally with a
CAN transceiver because the receiver loops back the driven output to the R (receive data) pin. This mode allows
the host protocol controller to input and read back a bit sequence or CAN messages to perform diagnostic
routines without disturbing the CAN bus. A typical CAN bus application is displayed in Figure 36.

Feature Description (continued)

If the LBK pin is not used it may be tied to ground (GND). However, it is pulled low internally (defaults to a low-
level input) and may be left open if not in use.
10.3.2 Autobaud Loopback (SN65HVD235)

The autobaud loopback mode of the SN65HVD235 is enabled by placing a high level input on pin 5, AB. In
autobaud mode, the driver output is disabled, thus blocking the D pin to bus path and the bus transmit function of
the transceiver. The bus pins remain biased to recessive. The receiver to R pin path or the bus receive function
of the device remains operational, allowing bus activity to be monitored. In addition, the autobaud mode adds an
internal logic loopback path from the D pin to R pin so the local node may transmit to itself in sync with bus traffic
while not disturbing messages on the bus. Thus if the local node’s CAN controller generates an error frame, it is
not transmitted to the bus, but is detected only by the local CAN controller. This is especially helpful to determine
if the local node is set to the same baud rate as the network, and if not adjust it to the network baud rate
(autobaud detection).
Autobaud detection is best suited to applications that have a known selection of baud rates. For example, a
popular industrial application has optional settings of 125 kbps, 250 kbps, or 500 kbps. Once the SN65HVD235
is placed into autobaud loopback mode the application software could assume the first baud rate of 125 kbps. It
then waits for a message to be transmitted by another node on the bus. If the wrong baud rate has been
selected, an error message is generated by the local CAN controller because the sample times will not be at the
correct time. However, because the bus-transmit function of the device has been disabled, no other nodes
receive the error frame generated by this node's local CAN controller.
The application would then make use of the status register indications of the local CAN controller for message
received and error warning status to determine if the set baud rate is correct or not. The warning status indicates
that the CAN controller error counters have been incremented. A message received status indicates that a good
message has been received. If an error is generated, the application would then set the CAN controller with the
next possibly valid baud rate, and wait to receive another message. This pattern is repeated until an error free
message has been received, thus the correct baud rate has been selected. At this point the application would
place the SN65HVD235 in a normal transmitting mode by setting pin 5 to a low-level, thus enabling bus-transmit
and bus-receive functions to normal operating states for the transceiver.
If the AB pin is not used it may be tied to ground (GND). However, it is pulled low internally (defaults to a low-
level input) and may be left open if not in use.
10.3.3 Slope Control

The rise and fall slope of the SN65HVD233, SN65HVD234, and SN65HVD235 driver output can be adjusted by
connecting a resistor from the Rs (pin 8) to ground (GND), or to a low-level input voltage as shown in Figure 32.
The slope of the driver output signal is proportional to the pin's output current. This slope control is implemented
with an external resistor value of 10 kΩ to achieve a ~15 V/μs slew rate, and up to 100 kΩ to achieve a
~2.0 V/μs slew rate . A typical slew rate verses pulldown resistance graph is shown in Figure 33. Typical driver
output waveforms with slope control are displayed in Figure 39.
10 kΩ
to
100 kΩ
Rs IOPF6
D 1 8
2 TMS320LF2407
GND 7 CANH
Vcc 3 6 CANL
R 4 5 LBK
Figure 32. Slope Control/Standby Connection to a DSP

Feature Description (continued)
25
20
Slope (V/us)
15
10
0
0 4.7 6.8 10 15 22 33 47 68 100
Slope Control Resistance - kΩ
Figure 33. HVD233 Driver Output Signal Slope vs Slope Control Resistance Value
10.3.4 Standby
If a high-level input (> 0.75 VCC) is applied to RS (pin 8), the circuit enters a low-current, listen only standby mode
during which the driver is switched off and the receiver remains active. If using this mode to save system power
while waiting for bus traffic, the local controller can monitor the R output pin for a falling edge which indicates that
a dominant signal was driven onto the CAN bus. The local controller can then drive the RS pin low to return to
slope control mode or high-speed mode.
10.3.5 Thermal Shutdown

If the junction temperature of the device exceeds the thermal shut down threshold the device turns off the CAN
driver circuits thus blocking the D pin to bus transmission path. The shutdown condition is cleared when the
junction temperature drops below the thermal shutdown temperature of the device. The CAN bus pins are high
impedance biased to recessive level during a thermal shutdown, and the receiver to R pin path remains
operational.
10.4 Device Functional Modes
Table 2. Driver (SN65HVD233 or SN65HVD235)

INPUTS OUTPUTS
D LBK/AB Rs CANH CANL BUS STATE
X X > 0.75 VCC Z Z Recessive
L L or open H L Dominant
≤ 0.33 VCC
H or open X Z Z Recessive
X H ≤ 0.33 VCC Z Z Recessive

Table 3. Receiver (SN65HVD233)

INPUTS OUTPUT
BUS STATE VID = V(CANH)–V(CANL) LBK D R
Dominant VID ≥ 0.9 V L or open X L
Recessive VID ≤ 0.5 V or open L or open H or open H
? 0.5 V < VID <0.9 V L or open H or open ?
X X L L
H
X X H H
Table 4. Receiver (SN65HVD235) (1)

INPUTS OUTPUT
BUS STATE VID = V(CANH)–V(CANL) AB D R
Dominant VID ≥ 0.9 V L or open X L
Recessive VID ≤ 0.5 V or open L or open H or open H
? 0.5 V < VID <0.9 V L or open H or open ?
Dominant VID ≥ 0.9 V H X L
Recessive VID ≤ 0.5 V or open H H H
Recessive VID ≤ 0.5 V or open H L L
? 0.5 V < VID <0.9 V H L L
(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
Table 5. Driver (SN65HVD234)

INPUTS OUTPUTS
D EN Rs CANH CANL BUS STATE
L H ≤ 0.33 VCC H L Dominant
H X ≤ 0.33 VCC Z Z Recessive
Open X X Z Z Recessive
X X > 0.75 VCC Z Z Recessive
X L or open X Z Z Recessive
Table 6. Receiver (SN65HVD234) (1)

INPUTS OUTPUT
BUS STATE VID = V(CANH)–V(CANL) EN R
Dominant VID≥ 0.9 V H L
Recessive VID ≤ 0.5 V or open H H
? 0.5 V < VID <0.9 V H ?
X X L or open H
(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate

11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information

The CAN bus has two states during powered operation of the device; dominant and recessive. A dominant bus
state is when the bus is driven differentially, corresponding to a logic low on the D and R pin. A recessive bus
state is when the bus is biased to VCC / 2 via the high-resistance internal resistors RIN and RID of the receiver,
corresponding to a logic high on the D and R pins. See Figure 34 and Figure 35.
4
Typical Bus Voltage (V)
CANH
3
Vdiff(D)
2
Vdiff(R)
CANL
1
Time, t
Recessive Dominant Recessive
Logic H Logic L Logic H
Figure 34. Bus States (Physical Bit Representation)
CANH
VCC/2 RXD
CANL
Figure 35. Simplified Recessive Common Mode Bias and Receiver
These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the
link layer portion of the CAN protocol. The different nodes on the network are typically connected through the use
of a 120-Ω characteristic impedance twisted-pair cable with termination on both ends of the bus.

11.2 Typical Application

Bus Lines -- 40 m max CANH
120 Ω Stub Lines -- 0.3 m max 120 Ω
CANL
5V 3.3 V 3.3 V
Vref Vcc Rs Vcc Vref Vcc
SN65HVD251 0.1µ F SN65HVD233 0.1µ F SN65HVD230 0.1µ F
Rs Rs
GND GND GND
D R LBK D R D R
CANTX CANRX GPIO CANTX CANRX CANTX CANRX
TMS320LF243 TMS320F2812 TMS320LF2407A
Sensor, Actuator, or Control Sensor, Actuator, or Control Sensor, Actuator, or Control

Equipment Equipment Equipment
Figure 36. Typical HVD233 Application
11.2.1 Design Requirements
11.2.1.1 Bus Loading, Length and Number of Nodes

The ISO 11898 Standard specifies up to a data rate of 1 Mbps, maximum CAN bus cable length of 40 m,
maximum drop line (stub) length of 0.3 m and a maximum of 30 nodes. However, with careful network design,
the system may have longer cables, longer stub lengths, and many more nodes to a bus. Many CAN
organizations and standards have scaled the use of CAN for applications outside the original ISO 11898
standard. They have made system level trade-offs for data rate, cable length, and parasitic loading of the bus.
Examples of some of these specifications are ARINC825, CANopen, CAN Kingdom, DeviceNet and NMEA200.
A high number of nodes requires a transceiver with high input impedance and wide common mode range such
as the SN65HVD23x CAN family. ISO 11898-2 specifies the driver differential output with a 60-Ω load (two 120-
Ω termination resistors in parallel) and the differential output must be greater than 1.5 V. The SN65HVD23x
devices are specified to meet the 1.5-V requirement with a 60-Ω load, and additionally specified with a differential
output voltage minimum of 1.2 V across a common mode range of –2 V to 7 V through a 330-Ω coupling
network. This network represents the bus loading of 120 SN65HVD23x transceivers based on their minimum
differential input resistance of 40 kΩ. Therefore, the SN65HVD23x supports up to 120 transceivers on a single
bus segment with margin to the 1.2-V minimum differential input voltage requirement at each node.
For CAN network design, margin must be given for signal loss across the system and cabling, parasitic loadings,
network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes may be
lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 m by careful system
design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1
km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898 CAN standard.
11.2.1.2 CAN Termination

The ISO 11898 standard specifies the interconnect to be a twisted-pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used to
terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes
to the bus should be kept as short as possible to minimize signal reflections. The termination may be on the
cable or in a node, but if nodes may be removed from the bus the termination must be carefully placed so that it
is not removed from the bus.

Typical Application (continued)

11.2.2 Detailed Design Procedure
Node n
Node 1 Node 2 Node 3 (with termination)
MCU or DSP
MCU or DSP MCU or DSP MCU or DSP
CAN
CAN CAN CAN Controller
Controller Controller Controller
CAN
CAN CAN CAN Transceiver
Transceiver Transceiver Transceiver
RTERM
RTERM
Figure 37. Typical CAN Bus
Termination is typically a 120-Ω resistor at each end of the bus. If filtering and stabilization of the common mode
voltage of the bus is desired, then split termination may be used (see Figure 38). Split termination uses two 60-Ω
resistors with a capacitor in the middle of these resistors to ground. Split termination improves the
electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common mode voltages
at the start and end of message transmissions.
Care should be taken in the power ratings of the termination resistors used. Typically the worst case condition
would be if the system power supply was shorted across the termination resistance to ground. In most cases the
current flow through the resistor in this condition would be much higher than the transceiver's current limit.
Standard Termination Split Termination
CANH CANH
RTERM/2
CAN CAN
RTERM
Transceiver Transceiver
CSPLIT
RTERM/2
CANL CANL
Figure 38. CAN Bus Termination Concepts
11.2.3 Application Curve

Figure 39 shows 3 typical output waveforms for the SN65HVD233 device with three different connections made
to the RS pin. The top waveform show the typical differential signal when transitioning from a recessive level to a
dominant level on the CAN bus with RS tied to GND through a 0-Ω resistor. The second waveform shows the
same signal for the condition with a 10-kΩ resistor tied from RS to ground. The bottom waveform shows the
typical differential signal for the case where a 100-kΩ resistor is tied from the RS pin to ground.

Typical Application (continued)
Rs = 0 Ω
Rs = 10 k Ω
Rs = 100 k Ω
Figure 39. Typical SN65HVD233 Output Waveforms With Different Slope Control Resistor Values
11.3 System Example

11.3.1 ISO 11898 Compliance of SN65HVD23x Family of 3.3-V CAN Transceivers
11.3.1.1 Introduction
Many users value the low power consumption of operating their CAN transceivers from a 3.3-V supply. However,
some are concerned about the interoperability with 5 V supplied transceivers on the same bus. This report
analyzes this situation to address those concerns.
11.3.1.2 Differential Signal

CAN is a differential bus where complementary signals are sent over two wires and the voltage difference
between the two wires defines the logical state of the bus. The differential CAN receiver monitors this voltage
difference and outputs the bus state with a single ended logic level output signal.

System Example (continued)
NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW 75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN
Figure 40. Typical SN65HVD230 Differential Output Voltage Waveform
The CAN driver creates the differential voltage between CANH and CANL in the dominant state. The dominant
differential output of the SN65HVD23x is greater than 1.5 V and less than 3 V across a 60 ohm load as defined
by the ISO 11898 standard. These are the same limiting values for 5 V supplied CAN transceivers. The bus
termination resistors drive the recessive bus state and not the CAN driver.
A CAN receiver is required to output a recessive state when less than 500 mV of differential voltage exists on the
bus, and a dominant state when more than 900 mV of differential voltage exists on the bus. The CAN receiver
must do this with common-mode input voltages from –2 V to 7 V. The SN65HVD23x family receivers meet these
same input specifications as 5 V supplied receivers.
11.3.1.3 Common-Mode Signal

A common-mode signal is an average voltage of the two signal wires that the differential receiver rejects. The
common-mode signal comes from the CAN driver, ground noise, and coupled bus noise. Since the bias voltage
of the recessive state of the device is dependent on VCC, any noise present or variation of VCC will have an effect
on this bias voltage seen by the bus. The SN65HVD23x family has the recessive bias voltage set higher than
0.5*VCC to comply with the ISO 11898-2 CAN standard. The caveat to this is that the common mode voltage will
drop by a couple hundred millivolts when driving a dominant bit on the bus. This means that there is a common
mode shift between the dominant bit and recessive bit states of the device. While this is not ideal, this small
variation in the driver common-mode output is rejected by differential receivers and does not effect data, signal
noise margins or error rates.
11.3.1.4 Interoperability of 3.3-V CAN in 5-V CAN Systems

The 3.3-V supplied SN65HVD23x family of CAN transceivers are fully compatible with 5-V CAN transceivers.
The differential output voltage is the same, the recessive common mode output bias is the same, and the
receivers have the same input specifications. The only slight difference is in the dominant common mode output
voltage which is a couple hundred millivolts lower for 3.3-V CAN transceiver than 5-V supplied transceiver.
To help ensure the widest interoperability possible, the SN65HVD23x family has successfully passed the
internationally recognized GIFT/ICT conformance and interoperability testing for CAN transceivers. Electrical
interoperability does not always assure interchangeability however. Most implementers of CAN buses recognize
that ISO 11898 does not sufficiently specify the electrical layer and that strict standard compliance alone does
not ensure full interchangeability. This comes only with thorough equipment testing.

12 Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100-
nF ceramic capacitor located as close to the VCC supply pins as possible. The TPS76333 is a linear voltage
regulator suitable for the 3.3 V supply.
13 Layout
13.1 Layout Guidelines

In order for the PCB design to be successful, start with design of the protection and filtering circuitry. Because
ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency
layout techniques must be applied during PCB design. On chip IEC ESD protection is good for laboratory and
portable equipment but is usually not sufficient for EFT and surge transients occurring in industrial environments.
Therefore robust and reliable bus node design requires the use of external transient protection devices at the bus
connectors. Placement at the connector also prevents these harsh transient events from propagating further into
the PCB and system.
Use VCC and ground planes to provide low inductance.
NOTE
High frequency current follows the path of least inductance and not the path of least
resistance.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
An example placement of the Transient Voltage Suppression (TVS) device indicated as D1 (either bi-directional
diode or varistor solution) and bus filter capacitors C8 and C9 are shown in Figure 41.
The bus transient protection and filtering components should be placed as close to the bus connector,
J1, as possible. This prevents transients, ESD and noise from penetrating onto the board and disturbing
other devices.
Bus termination: Figure 41 shows split termination. This is where the termination is split into two resistors, R5
and R6, with the center or split tap of the termination connected to ground via capacitor C7. Split termination
provides common mode filtering for the bus. When termination is placed on the board instead of directly on the
bus, care must be taken to ensure the terminating node is not removed from the bus as this will cause signal
integrity issues of the bus is not properly terminated on both ends. See the application section for information on
power ratings needed for the termination resistor(s).
Bypass and bulk capacitors should be placed as close as possible to the supply pins of transceiver, examples
C2, C3 (VCC).
Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to minimize
trace and via inductance.
To limit current of digital lines, serial resistors may be used. Examples are R1, R2, R3 and R4.
To filter noise on the digital IO lines, a capacitor may be used close to the input side of the IO as shown by C1
and C4.
Since the internal pullup and pulldown biasing of the device is weak for floating pins, an external 1-kΩ to 10-kΩ
pullup or pulldown resistor should be used to bias the state of the pin more strongly against noise during
transient events.
Pin 1: If an open drain host processor is used to drive the D pin of the device an external pull-up resistor
between 1 kΩ and 10 kΩ and VCC should be used to drive the recessive input state of the device.
Pin 8: is shown assuming the mode pin, RS, will be used. If the device will only be used in normal mode or slope
control mode, R3 is not needed and the pads of C4 could be used for the pulldown resistor to GND.

13.2 Layout Example
Figure 41. Layout Example Schematic
14 Device and Documentation Support
14.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN65HVD233 Click here Click here Click here Click here Click here
14.2 Trademarks
All trademarks are the property of their respective owners.
14.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
SN65HVD233D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 VP233
& no Sb/Br)
SN65HVD233DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 VP233
& no Sb/Br)
SN65HVD233DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 VP233
& no Sb/Br)
SN65HVD233DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 VP233
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
SN65HVD234DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 VP234
& no Sb/Br)
& no Sb/Br)
SN65HVD235DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 VP235
& no Sb/Br)
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD233, SN65HVD234, SN65HVD235 :
• Automotive: SN65HVD233-Q1, SN65HVD234-Q1, SN65HVD235-Q1

• Enhanced Product: SN65HVD233-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Dec-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD233DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD234DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD235DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Dec-2012
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD233DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD234DR SOIC D 8 2500 340.5 338.1 20.6
SN65HVD235DR SOIC D 8 2500 340.5 338.1 20.6
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated

Can Communication PDF

Uploaded by

Copyright:

Available Formats

Can Communication PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Can Communication PDF

Uploaded by

Copyright:

Available Formats

Product Sample & Technical Tools & Support &

Folder Buy Documents Software Community

SN65HVD233, SN65HVD234, SN65HVD235

SN65HVD23x 3.3-V CAN Bus Transceivers

• Building and Climate Control (HVAC)

Changes from Revision F (August 2008) to Revision G Page

Changes from Revision E (October 2007) to Revision F Page

Changes from Revision D (June 2005) to Revision E Page

• Added 60-Ω load test condition to Figure 3 ......................................................................................................................... 10

Changes from Revision C (March 2005) to Revision D Page

• Added Features Bullet: GIFT/ICT Compliant (SN65HVD234)................................................................................................ 1

2 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated

Product Folder Links: SN65HVD233 SN65HVD234 SN65HVD235

Changes from Revision B (June 2003) to Revision C Page

Changes from Revision A (March 2003) to Revision B Page

Changes from Original (November 2002) to Revision A Page

Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

6 Device Options (1)

SLOPE DIAGNOSTIC AUTOBAUD

4 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated

Product Folder Links: SN65HVD233 SN65HVD234 SN65HVD235

7 Pin Configuration and Functions

Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback 5

8.2 ESD Ratings

8.3 Recommended Operating Conditions

8.4 Thermal Information

(1) See SZZA003 for an explanation of this parameter.

8.5 Power Dissipation Ratings

6 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated

Product Folder Links: SN65HVD233 SN65HVD234 SN65HVD235

8.6 Electrical Characteristics: Driver

Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback 7

8.7 Electrical Characteristics: Receiver

8.8 Switching Characteristics: Driver

8 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated

Product Folder Links: SN65HVD233 SN65HVD234 SN65HVD235

8.9 Switching Characteristics: Receiver

8.10 Switching Characteristics: Device

Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback 9

8.11 Typical Characteristics

t (LOOPL2)− Dominant−To−Recessive Loop Time − ns

Rs, LBK, AB = 0 V Rs, LBK, AB = 0 V

I OL − Driver Output Current − mA

60-W Load 120

VCC = 3.3 V TA = 25°C 60-Ω Load VCC = 3.3 V TA = 25°C

10 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated

Product Folder Links: SN65HVD233 SN65HVD234 SN65HVD235

Typical Characteristics (continued)

t PHL− Receiver High-To-Low Propagation Delay − ns

t PHL− Driver High-To-Low Proragation Delay − ns

VCC = 3 V VCC = 3.3 V 55

See Figure 1 See Figure 1

Figure 11. Driver Output Current vs Supply Voltage

Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback 11

9 Parameter Measurement Information

Figure 12. Driver Voltage, Current, and Test Definition

Figure 13. Bus Logic State Voltage Definitions

CANH 330 Ω ±1%

Figure 14. Driver VOD