M25P16

16 Mbit, Low Voltage, Serial Flash Memory

With 50 MHz SPI Bus Interface

FEATURES SUMMARY
■ 16Mbit of Flash Memory Figure 1. Packages
■ Page Program (up to 256 Bytes) in 1.4ms
(typical)
■ Sector Erase (512 Kbit)
■ Bulk Erase (16Mbit)
■ 2.7 to 3.6V Single Supply Voltage
■ SPI Bus Compatible Serial Interface
■ 50MHz Clock Rate (maximum)
■ Deep Power-down Mode 1µA (typical) VDFPN8 (ME)
■ Electronic Signatures 8x6mm (MLP8)

– JEDEC Standard Two-Byte Signature

(2015h)
– RES Instruction, One-Byte, Signature
(14h), for backward compatibility
■ More than 100,000 Erase/Program Cycles per
Sector
■ More than 20 Year Data Retention

SO16 (MF)
300 mil width

May 2004 1/39

M25P16

TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. VDFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SPI MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Active Power, Stand-by Power and Deep Power-Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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 M25P16

Figure 10.Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11.Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . 15
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12.Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . 16
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13.Write Status Register (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14.Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . 19
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15.Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Se-
quence 20
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16.Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17.Sector Erase (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18.Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19.Deep Power-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Release from Deep Power-down and Read Electronic Signature (RES) . . . . . . . . . . . . . . . . . 25
Figure 20.Release from Deep Power-down and Read Electronic Signature (RES) Instruction Se-
quence and Data-Out Sequence25
Figure 21.Release from Deep Power-down (RES) Instruction Sequence . . . . . . . . . . . . . . . . . . . . 26

POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 22.Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 23.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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M25P16

Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 24.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 25.Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . 33
Figure 26.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 27.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 28.MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline . . . . . . . 35
Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Mechanical Data35
Figure 29.SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Package Outline . . . . 36
Table 16. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Mechanical Data. . . . 36

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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 M25P16

SUMMARY DESCRIPTION Figure 3. VDFPN Connections

The M25P16 is a 16Mbit (2M x 8) Serial Flash
Memory, with advanced write protection mecha-
nisms, accessed by a high speed SPI-compatible
bus.
The memory can be programmed 1 to 256 bytes at
a time, using the Page Program instruction.
M25P16
The memory is organized as 32 sectors, each con-
taining 256 pages. Each page is 256 bytes wide. S 1 8 VCC
Thus, the whole memory can be viewed as con-
Q 2 7 HOLD
sisting of 8192 pages, or 2,097,152 bytes.
W 3 6 C
The whole memory can be erased using the Bulk
Erase instruction, or a sector at a time, using the VSS 4 5 D
Sector Erase instruction. AI08517

Figure 2. Logic Diagram

VCC

Note: 1. There is an exposed die paddle on the underside of the

D Q MLP8 package. This is pulled, internally, to V SS, and
must not be allowed to be connected to any other voltage
C or signal line on the PCB.
2. See PACKAGE MECHANICAL section for package di-
S M25P16 mensions, and how to identify pin-1.

W Figure 4. SO Connections

HOLD M25P16

HOLD 1 16 C
VCC 2 15 D
VSS
AI05762
DU 3 14 DU
DU 4 13 DU
DU 5 12 DU
DU 6 11 DU
Table 1. Signal Names S 7 10 VSS
C Serial Clock Q 8 9 W
AI08594B
D Serial Data Input

Q Serial Data Output

Note: 1. DU = Don’t Use
2. See PACKAGE MECHANICAL section for package di-
S Chip Select
mensions, and how to identify pin-1.
W Write Protect

HOLD Hold

VCC Supply Voltage

VSS Ground

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M25P16

SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is (this is not the Deep Power-down mode). Driving
used to transfer data serially out of the device. Chip Select (S) Low enables the device, placing it
Data is shifted out on the falling edge of Serial in the active power mode.
Clock (C). After Power-up, a falling edge on Chip Select (S)
Serial Data Input (D). This input signal is used to is required prior to the start of any instruction.
transfer data serially into the device. It receives in- Hold (HOLD). The Hold (HOLD) signal is used to
structions, addresses, and the data to be pro- pause any serial communications with the device
grammed. Values are latched on the rising edge of without deselecting the device.
Serial Clock (C).
During the Hold condition, the Serial Data Output
Serial Clock (C). This input signal provides the (Q) is high impedance, and Serial Data Input (D)
timing of the serial interface. Instructions, address- and Serial Clock (C) are Don’t Care.
es, or data present at Serial Data Input (D) are
To start the Hold condition, the device must be se-
latched on the rising edge of Serial Clock (C). Data
lected, with Chip Select (S) driven Low.
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C). Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output ory that is protected against program or erase
instructions (as specified by the values in the BP2,
(Q) is at high impedance. Unless an internal Pro-
BP1 and BP0 bits of the Status Register).
gram, Erase or Write Status Register cycle is in
progress, the device will be in the Standby mode

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 M25P16

SPI MODES
These devices can be driven by a microcontroller is available from the falling edge of Serial Clock
with its SPI peripheral running in either of the two (C).
following modes: The difference between the two modes, as shown
– CPOL=0, CPHA=0 in Figure 6., is the clock polarity when the bus
– CPOL=1, CPHA=1 master is in Stand-by mode and not transferring
data:
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data – C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. Bus Master and Memory Devices on the SPI Bus

SDO
SPI Interface with
SDI
(CPOL, CPHA) =
(0, 0) or (1, 1) SCK

C Q D C Q D C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory SPI Memory SPI Memory
Device Device Device
CS3 CS2 CS1

S W HOLD S W HOLD S W HOLD

AI03746D

Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 6. SPI Modes Supported

CPOL CPHA

0 0 C

1 1 C

D MSB

Q MSB

AI01438B

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M25P16

OPERATING FEATURES
Page Programming Erase, Write Status Register). The device then
To program one data byte, two instructions are re- goes in to the Stand-by Power mode. The device
quired: Write Enable (WREN), which is one byte, consumption drops to I CC1.
and a Page Program (PP) sequence, which con- The Deep Power-down mode is entered when the
sists of four bytes plus data. This is followed by the specific instruction (the Enter Deep Power-down
internal Program cycle (of duration tPP). Mode (DP) instruction) is executed. The device
To spread this overhead, the Page Program (PP) consumption drops further to ICC2. The device re-
instruction allows up to 256 bytes to be pro- mains in this mode until another specific instruc-
grammed at a time (changing bits from 1 to 0), pro- tion (the Release from Deep Power-down Mode
vided that they lie in consecutive addresses on the and Read Electronic Signature (RES) instruction)
same page of memory. is executed.
Sector Erase and Bulk Erase All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
The Page Program (PP) instruction allows bits to
used as an extra software protection mechanism,
be reset from 1 to 0. Before this can be applied, the
when the device is not in active use, to protect the
bytes of memory need to have been erased to all device from inadvertent Write, Program or Erase
1s (FFh). This can be achieved either a sector at a
instructions.
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk Status Register
Erase (BE) instruction. This starts an internal The Status Register contains a number of status
Erase cycle (of duration tSE or tBE). and control bits that can be read or set (as appro-
The Erase instruction must be preceded by a Write priate) by specific instructions.
Enable (WREN) instruction. WIP bit. The Write In Progress (WIP) bit indicates
Polling During a Write, Program or Erase Cycle whether the memory is busy with a Write Status
Register, Program or Erase cycle.
A further improvement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or WEL bit. The Write Enable Latch (WEL) bit indi-
BE) can be achieved by not waiting for the worst cates the status of the internal Write Enable Latch.
case delay (tW, tPP, tSE, or tBE). The Write In BP2, BP1, BP0 bits. The Block Protect (BP2,
Progress (WIP) bit is provided in the Status Regis- BP1, BP0) bits are non-volatile. They define the
ter so that the application program can monitor its size of the area to be software protected against
value, polling it to establish when the previous Program and Erase instructions.
Write cycle, Program cycle or Erase cycle is com- SRWD bit. The Status Register Write Disable
plete. (SRWD) bit is operated in conjunction with the
Active Power, Stand-by Power and Deep Write Protect (W) signal. The Status Register
Power-Down Modes Write Disable (SRWD) bit and Write Protect (W)
When Chip Select (S) is Low, the device is en- signal allow the device to be put in the Hardware
abled, and in the Active Power mode. Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP2, BP1, BP0)
When Chip Select (S) is High, the device is dis- become read-only bits.
abled, but could remain in the Active Power mode
until all internal cycles have completed (Program,

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 M25P16

Protection Modes – Write Status Register (WRSR) instruction

The environments where non-volatile memory de- completion
vices are used can be very noisy. No SPI device – Page Program (PP) instruction completion
can operate correctly in the presence of excessive – Sector Erase (SE) instruction completion
noise. To help combat this, the M25P16 boasts the
– Bulk Erase (BE) instruction completion
following data protection mechanisms:
■ The Block Protect (BP2, BP1, BP0) bits allow
■ Power-On Reset and an internal timer (tPUW)
can provide protection against inadvertant part of the memory to be configured as read-
only. This is the Software Protected Mode
changes while the power supply is outside the
(SPM).
operating specification.
■ The Write Protect (W) signal allows the Block
■ Program, Erase and Write Status Register
instructions are checked that they consist of a Protect (BP2, BP1, BP0) bits and Status
number of clock pulses that is a multiple of Register Write Disable (SRWD) bit to be
protected. This is the Hardware Protected
eight, before they are accepted for execution.
Mode (HPM).
■ All instructions that modify data must be
■ In addition to the low power consumption
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch feature, the Deep Power-down mode offers
extra software protection from inadvertant
(WEL) bit . This bit is returned to its reset state
Write, Program and Erase instructions, as all
by the following events:
instructions are ignored except one particular
– Power-up instruction (the Release from Deep Power-
– Write Disable (WRDI) instruction down instruction).
completion

Table 2. Protected Area Sizes

Status Register
Memory Content
Content
BP2 BP1 BP0
Protected Area Unprotected Area
Bit Bit Bit

0 0 0 none All sectors1 (32 sectors: 0 to 31)

0 0 1 Upper 32nd (Sector 31) Lower 31/32nds (31 sectors: 0 to 30)
0 1 0 Upper sixteenth (two sectors: 30 and 31) Lower 15/16ths (30 sectors: 0 to 29)
0 1 1 Upper eighth (four sectors: 28 to 31) Lower seven-eighths (28 sectors: 0 to 27)
1 0 0 Upper quarter (eight sectors: 24 to 31) Lower three-quarters (24 sectors: 0 to 23)
1 0 1 Upper half (sixteen sectors: 16 to 31) Lower half (16 sectors: 0 to 15)
1 1 0 All sectors (32 sectors: 0 to 31) none
1 1 1 All sectors (32 sectors: 0 to 31) none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.

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M25P16

Hold Condition rising edge does not coincide with Serial Clock (C)
The Hold (HOLD) signal is used to pause any se- being Low, the Hold condition ends after Serial
rial communications with the device without reset- Clock (C) next goes Low. (This is shown in Figure
ting the clocking sequence. However, taking this 7.).
signal Low does not terminate any Write Status During the Hold condition, the Serial Data Output
Register, Program or Erase cycle that is currently (Q) is high impedance, and Serial Data Input (D)
in progress. and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be Normally, the device is kept selected, with Chip
selected, with Chip Select (S) Low. Select (S) driven Low, for the whole duration of the
The Hold condition starts on the falling edge of the Hold condition. This is to ensure that the state of
Hold (HOLD) signal, provided that this coincides the internal logic remains unchanged from the mo-
with Serial Clock (C) being Low (as shown in Fig- ment of entering the Hold condition.
ure 7.). If Chip Select (S) goes High while the device is in
The Hold condition ends on the rising edge of the the Hold condition, this has the effect of resetting
Hold (HOLD) signal, provided that this coincides the internal logic of the device. To restart commu-
with Serial Clock (C) being Low. nication with the device, it is necessary to drive
Hold (HOLD) High, and then to drive Chip Select
If the falling edge does not coincide with Serial
(S) Low. This prevents the device from going back
Clock (C) being Low, the Hold condition starts af-
to the Hold condition.
ter Serial Clock (C) next goes Low. Similarly, if the

Figure 7. Hold Condition Activation

HOLD

Hold Hold
Condition Condition
(standard use) (non-standard use)
AI02029D

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 M25P16

MEMORY ORGANIZATION
The memory is organized as: Each page can be individually programmed (bits
■ 2,097,152 bytes (8 bits each) are programmed from 1 to 0). The device is Sector
or Bulk Erasable (bits are erased from 0 to 1) but
■ 32 sectors (512 Kbits, 65536 bytes each) not Page Erasable.
■ 8192 pages (256 bytes each).

Figure 8. Block Diagram

HOLD
High Voltage
W Control Logic Generator
S

D
I/O Shift Register
Q

Address Register 256 Byte Status

and Counter Data Buffer Register

1FFFFFh

Size of the
Y Decoder

read-only
memory area

00000h 000FFh
256 Bytes (Page Size)

X Decoder

AI04987

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M25P16

Table 3. Memory Organization

Sector Address Range
31 1F0000h 1FFFFFh
30 1E0000h 1EFFFFh
29 1D0000h 1DFFFFh
28 1C0000h 1CFFFFh
27 1B0000h 1BFFFFh
26 1A0000h 1AFFFFh
25 190000h 19FFFFh
24 180000h 18FFFFh
23 170000h 17FFFFh
22 160000h 16FFFFh
21 150000h 15FFFFh
20 140000h 14FFFFh
19 130000h 13FFFFh
18 120000h 12FFFFh
17 110000h 11FFFFh
16 100000h 10FFFFh
15 0F0000h 0FFFFFh
14 0E0000h 0EFFFFh
13 0D0000h 0DFFFFh
12 0C0000h 0CFFFFh
11 0B0000h 0BFFFFh
10 0A0000h 0AFFFFh
9 090000h 09FFFFh
8 080000h 08FFFFh
7 070000h 07FFFFh
6 060000h 06FFFFh
5 050000h 05FFFFh
4 040000h 04FFFFh
3 030000h 03FFFFh
2 020000h 02FFFFh
1 010000h 01FFFFh
0 000000h 00FFFFh

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 M25P16

INSTRUCTIONS
All instructions, addresses and data are shifted in data-out sequence. Chip Select (S) can be driven
and out of the device, most significant bit first. High after any bit of the data-out sequence is be-
Serial Data Input (D) is sampled on the first rising ing shifted out.
edge of Serial Clock (C) after Chip Select (S) is In the case of a Page Program (PP), Sector Erase
driven Low. Then, the one-byte instruction code (SE), Bulk Erase (BE), Write Status Register
must be shifted in to the device, most significant bit (WRSR), Write Enable (WREN), Write Disable
first, on Serial Data Input (D), each bit being (WRDI) or Deep Power-down (DP) instruction,
latched on the rising edges of Serial Clock (C). Chip Select (S) must be driven High exactly at a
The instruction set is listed in Table 4.. byte boundary, otherwise the instruction is reject-
ed, and is not executed. That is, Chip Select (S)
Every instruction sequence starts with a one-byte must driven High when the number of clock pulses
instruction code. Depending on the instruction, after Chip Select (S) being driven Low is an exact
this might be followed by address bytes, or by data
multiple of eight.
bytes, or by both or none.
All attempts to access the memory array during a
In the case of a Read Data Bytes (READ), Read
Write Status Register cycle, Program cycle or
Data Bytes at Higher Speed (Fast_Read), Read Erase cycle are ignored, and the internal Write
Status Register (RDSR), Read Identification
Status Register cycle, Program cycle or Erase cy-
(RDID) or Release from Deep Power-down, and
cle continues unaffected.
Read Electronic Signature (RES) instruction, the
shifted-in instruction sequence is followed by a

Table 4. Instruction Set

Address Dummy Data
Instruction Description One-byte Instruction Code
Bytes Bytes Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
WRSR Write Status Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
Release from Deep Power-down,
0 3 1 to ∞
RES and Read Electronic Signature 1010 1011 ABh
Release from Deep Power-down 0 0 0

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M25P16

Write Enable (WREN) (SE), Bulk Erase (BE) and Write Status Register
The Write Enable (WREN) instruction (Figure 9.) (WRSR) instruction.
sets the Write Enable Latch (WEL) bit. The Write Enable (WREN) instruction is entered
The Write Enable Latch (WEL) bit must be set pri- by driving Chip Select (S) Low, sending the in-
or to every Page Program (PP), Sector Erase struction code, and then driving Chip Select (S)
High.

Figure 9. Write Enable (WREN) Instruction Sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI02281E

Write Disable (WRDI) – Power-up

The Write Disable (WRDI) instruction (Figure 10.) – Write Disable (WRDI) instruction completion
resets the Write Enable Latch (WEL) bit. – Write Status Register (WRSR) instruction
The Write Disable (WRDI) instruction is entered by completion
driving Chip Select (S) Low, sending the instruc- – Page Program (PP) instruction completion
tion code, and then driving Chip Select (S) High.
– Sector Erase (SE) instruction completion
The Write Enable Latch (WEL) bit is reset under
– Bulk Erase (BE) instruction completion
the following conditions:

Figure 10. Write Disable (WRDI) Instruction Sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI03750D

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 M25P16

Read Identification (RDID) struction is shifted in. This is followed by the 24-bit
The Read Identification (RDID) instruction allows device identification, stored in the memory, being
the 8-bit manufacturer identification to be read, fol- shifted out on Serial Data Output (Q), each bit be-
lowed by two bytes of device identification. The ing shifted out during the falling edge of Serial
manufacturer identification is assigned by JEDEC, Clock (C).
and has the value 20h for STMicroelectronics. The The instruction sequence is shown in Figure 11..
device identification is assigned by the device The Read Identification (RDID) instruction is termi-
manufacturer, and indicates the memory type in nated by driving Chip Select (S) High at any time
the first byte (20h), and the memory capacity of the during data output.
device in the second byte (15h).
When Chip Select (S) is driven High, the device is
Any Read Identification (RDID) instruction while put in the Stand-by Power mode. Once in the
an Erase or Program cycle is in progress, is not Stand-by Power mode, the device waits to be se-
decoded, and has no effect on the cycle that is in lected, so that it can receive, decode and execute
progress. instructions.
The device is first selected by driving Chip Select
(S) Low. Then, the 8-bit instruction code for the in-

Table 5. Read Identification (RDID) Data-Out Sequence

Device Identification
Manufacturer Identification
Memory Type Memory Capacity

20h 20h 15h

Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 18 28 29 30 31

Instruction

Manufacturer Identification Device Identification

High Impedance
Q 15 14 13 3 2 1 0

MSB MSB

AI06809

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M25P16

Read Status Register (RDSR) WEL bit. The Write Enable Latch (WEL) bit indi-
The Read Status Register (RDSR) instruction al- cates the status of the internal Write Enable Latch.
lows the Status Register to be read. The Status When set to 1 the internal Write Enable Latch is
Register may be read at any time, even while a set, when set to 0 the internal Write Enable Latch
Program, Erase or Write Status Register cycle is in is reset and no Write Status Register, Program or
progress. When one of these cycles is in progress, Erase instruction is accepted.
it is recommended to check the Write In Progress BP2, BP1, BP0 bits. The Block Protect (BP2,
(WIP) bit before sending a new instruction to the BP1, BP0) bits are non-volatile. They define the
device. It is also possible to read the Status Reg- size of the area to be software protected against
ister continuously, as shown in Figure 12.. Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) in-
Table 6. Status Register Format struction. When one or both of the Block Protect
(BP2, BP1, BP0) bits is set to 1, the relevant mem-
b7 b0 ory area (as defined in Table 2.) becomes protect-
SRWD 0 0 BP2 BP1 BP0 WEL WIP
ed against Page Program (PP) and Sector Erase
(SE) instructions. The Block Protect (BP2, BP1,
BP0) bits can be written provided that the Hard-
ware Protected mode has not been set. The Bulk
Status Register Erase (BE) instruction is executed if, and only if,
Write Protect
both Block Protect (BP2, BP1, BP0) bits are 0.
Block Protect Bits SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Enable Latch Bit
Write Protect (W) signal. The Status Register
Write In Progress Bit Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
The status and control bits of the Status Register Protected mode (when the Status Register Write
are as follows: Disable (SRWD) bit is set to 1, and Write Protect
WIP bit. The Write In Progress (WIP) bit indicates (W) is driven Low). In this mode, the non-volatile
whether the memory is busy with a Write Status bits of the Status Register (SRWD, BP2, BP1,
Register, Program or Erase cycle. When set to 1, BP0) become read-only bits and the Write Status
such a cycle is in progress, when reset to 0 no Register (WRSR) instruction is no longer accepted
such cycle is in progress. for execution.

Figure 12. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

Status Register Out Status Register Out

High Impedance
Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

AI02031E

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 M25P16

Write Status Register (WRSR) (whose duration is tW) is initiated. While the Write
The Write Status Register (WRSR) instruction al- Status Register cycle is in progress, the Status
lows new values to be written to the Status Regis- Register may still be read to check the value of the
ter. Before it can be accepted, a Write Enable Write In Progress (WIP) bit. The Write In Progress
(WREN) instruction must previously have been ex- (WIP) bit is 1 during the self-timed Write Status
ecuted. After the Write Enable (WREN) instruction Register cycle, and is 0 when it is completed.
has been decoded and executed, the device sets When the cycle is completed, the Write Enable
the Write Enable Latch (WEL). Latch (WEL) is reset.
The Write Status Register (WRSR) instruction is The Write Status Register (WRSR) instruction al-
entered by driving Chip Select (S) Low, followed lows the user to change the values of the Block
by the instruction code and the data byte on Serial Protect (BP2, BP1, BP0) bits, to define the size of
Data Input (D). the area that is to be treated as read-only, as de-
fined in Table 2.. The Write Status Register
The instruction sequence is shown in Figure 13..
(WRSR) instruction also allows the user to set or
The Write Status Register (WRSR) instruction has reset the Status Register Write Disable (SRWD)
no effect on b6, b5, b1 and b0 of the Status Reg- bit in accordance with the Write Protect (W) signal.
ister. b6 and b5 are always read as 0. The Status Register Write Disable (SRWD) bit and
Chip Select (S) must be driven High after the Write Protect (W) signal allow the device to be put
eighth bit of the data byte has been latched in. If in the Hardware Protected Mode (HPM). The Write
not, the Write Status Register (WRSR) instruction Status Register (WRSR) instruction is not execut-
is not executed. As soon as Chip Select (S) is driv- ed once the Hardware Protected Mode (HPM) is
en High, the self-timed Write Status Register cycle entered.

Figure 13. Write Status Register (WRSR) Instruction Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction Status
Register In

D 7 6 5 4 3 2 1 0

High Impedance MSB

Q
AI02282D

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M25P16

Table 7. Protection Modes

Memory Content
W SRWD Write Protection of the
Mode
Signal Bit Status Register
Protected Area1 Unprotected Area1
1 0 Status Register is Writable
(if the WREN instruction
0 0 Software Protected against Page Ready to accept Page
has set the WEL bit)
Protected Program, Sector Erase Program and Sector Erase
The values in the SRWD,
(SPM) and Bulk Erase instructions
1 1 BP2, BP1 and BP0 bits
can be changed
Status Register is
Hardware Hardware write protected Protected against Page Ready to accept Page
0 1 Protected The values in the SRWD, Program, Sector Erase Program and Sector Erase
(HPM) BP2, BP1 and BP0 bits and Bulk Erase instructions
cannot be changed
Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2..
The protection features of the device are summa- Status Register are rejected, and are not
rized in Table 7.. accepted for execution). As a consequence,
When the Status Register Write Disable (SRWD) all the data bytes in the memory area that are
bit of the Status Register is 0 (its initial delivery software protected (SPM) by the Block Protect
state), it is possible to write to the Status Register (BP2, BP1, BP0) bits of the Status Register,
provided that the Write Enable Latch (WEL) bit has are also hardware protected against data
previously been set by a Write Enable (WREN) in- modification.
struction, regardless of the whether Write Protect Regardless of the order of the two events, the
(W) is driven High or Low. Hardware Protected Mode (HPM) can be entered:
When the Status Register Write Disable (SRWD) – by setting the Status Register Write Disable
bit of the Status Register is set to 1, two cases (SRWD) bit after driving Write Protect (W) Low
need to be considered, depending on the state of – or by driving Write Protect (W) Low after
Write Protect (W): setting the Status Register Write Disable
– If Write Protect (W) is driven High, it is (SRWD) bit.
possible to write to the Status Register The only way to exit the Hardware Protected Mode
provided that the Write Enable Latch (WEL) bit (HPM) once entered is to pull Write Protect (W)
has previously been set by a Write Enable High.
(WREN) instruction.
If Write Protect (W) is permanently tied High, the
– If Write Protect (W) is driven Low, it is not Hardware Protected Mode (HPM) can never be
possible to write to the Status Register even if activated, and only the Software Protected Mode
the Write Enable Latch (WEL) bit has (SPM), using the Block Protect (BP2, BP1, BP0)
previously been set by a Write Enable bits of the Status Register, can be used.
(WREN) instruction. (Attempts to write to the

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 M25P16

Read Data Bytes (READ) next higher address after each byte of data is shift-
The device is first selected by driving Chip Select ed out. The whole memory can, therefore, be read
(S) Low. The instruction code for the Read Data with a single Read Data Bytes (READ) instruction.
Bytes (READ) instruction is followed by a 3-byte When the highest address is reached, the address
address (A23-A0), each bit being latched-in during counter rolls over to 000000h, allowing the read
the rising edge of Serial Clock (C). Then the mem- sequence to be continued indefinitely.
ory contents, at that address, is shifted out on Se- The Read Data Bytes (READ) instruction is termi-
rial Data Output (Q), each bit being shifted out, at nated by driving Chip Select (S) High. Chip Select
a maximum frequency fR, during the falling edge of (S) can be driven High at any time during data out-
Serial Clock (C). put. Any Read Data Bytes (READ) instruction,
The instruction sequence is shown in Figure 14.. while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
The first byte addressed can be at any location.
the cycle that is in progress.
The address is automatically incremented to the

Figure 14. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

Instruction 24-Bit Address

D 23 22 21 3 2 1 0
MSB
Data Out 1 Data Out 2
High Impedance
Q 7 6 5 4 3 2 1 0 7
MSB

AI03748D

Note: Address bits A23 to A21 are Don’t Care.

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M25P16

Read Data Bytes at Higher Speed next higher address after each byte of data is shift-
(FAST_READ) ed out. The whole memory can, therefore, be read
The device is first selected by driving Chip Select with a single Read Data Bytes at Higher Speed
(S) Low. The instruction code for the Read Data (FAST_READ) instruction. When the highest ad-
Bytes at Higher Speed (FAST_READ) instruction dress is reached, the address counter rolls over to
is followed by a 3-byte address (A23-A0) and a 000000h, allowing the read sequence to be contin-
dummy byte, each bit being latched-in during the ued indefinitely.
rising edge of Serial Clock (C). Then the memory The Read Data Bytes at Higher Speed
contents, at that address, is shifted out on Serial (FAST_READ) instruction is terminated by driving
Data Output (Q), each bit being shifted out, at a Chip Select (S) High. Chip Select (S) can be driv-
maximum frequency fC, during the falling edge of en High at any time during data output. Any Read
Serial Clock (C). Data Bytes at Higher Speed (FAST_READ) in-
The instruction sequence is shown in Figure 15.. struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
The first byte addressed can be at any location. fects on the cycle that is in progress.
The address is automatically incremented to the

Figure 15. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out
Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

Instruction 24 BIT ADDRESS

D 23 22 21 3 2 1 0

High Impedance
Q

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Dummy Byte

D 7 6 5 4 3 2 1 0

DATA OUT 1 DATA OUT 2

Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB MSB

AI04006

Note: 1. Address bits A23 to A21 are Don’t Care.

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 M25P16

Page Program (PP) rectly within the same page. If less than 256 Data
The Page Program (PP) instruction allows bytes to bytes are sent to device, they are correctly pro-
be programmed in the memory (changing bits from grammed at the requested addresses without hav-
1 to 0). Before it can be accepted, a Write Enable ing any effects on the other bytes of the same
(WREN) instruction must previously have been ex- page.
ecuted. After the Write Enable (WREN) instruction Chip Select (S) must be driven High after the
has been decoded, the device sets the Write En- eighth bit of the last data byte has been latched in,
able Latch (WEL). otherwise the Page Program (PP) instruction is not
The Page Program (PP) instruction is entered by executed.
driving Chip Select (S) Low, followed by the in- As soon as Chip Select (S) is driven High, the self-
struction code, three address bytes and at least timed Page Program cycle (whose duration is tPP)
one data byte on Serial Data Input (D). If the 8 is initiated. While the Page Program cycle is in
least significant address bits (A7-A0) are not all progress, the Status Register may be read to
zero, all transmitted data that goes beyond the end check the value of the Write In Progress (WIP) bit.
of the current page are programmed from the start The Write In Progress (WIP) bit is 1 during the self-
address of the same page (from the address timed Page Program cycle, and is 0 when it is
whose 8 least significant bits (A7-A0) are all zero). completed. At some unspecified time before the
Chip Select (S) must be driven Low for the entire cycle is completed, the Write Enable Latch (WEL)
duration of the sequence. bit is reset.
The instruction sequence is shown in Figure 16.. A Page Program (PP) instruction applied to a page
If more than 256 bytes are sent to the device, pre- which is protected by the Block Protect (BP2, BP1,
viously latched data are discarded and the last 256 BP0) bits (see Table 2. and Table 3.) is not execut-
data bytes are guaranteed to be programmed cor- ed.

Figure 16. Page Program (PP) Instruction Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

Instruction 24-Bit Address Data Byte 1

D 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB

S
2072
2073
2074
2075
2076
2077
2078
2079

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Data Byte 2 Data Byte 3 Data Byte 256

D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB MSB

AI04082B

Note: Address bits A23 to A21 are Don’t Care.

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M25P16

Sector Erase (SE) Chip Select (S) must be driven High after the
The Sector Erase (SE) instruction sets to 1 (FFh) eighth bit of the last address byte has been latched
all bits inside the chosen sector. Before it can be in, otherwise the Sector Erase (SE) instruction is
accepted, a Write Enable (WREN) instruction not executed. As soon as Chip Select (S) is driven
must previously have been executed. After the High, the self-timed Sector Erase cycle (whose du-
Write Enable (WREN) instruction has been decod- ration is tSE) is initiated. While the Sector Erase cy-
ed, the device sets the Write Enable Latch (WEL). cle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP)
The Sector Erase (SE) instruction is entered by
bit. The Write In Progress (WIP) bit is 1 during the
driving Chip Select (S) Low, followed by the in- self-timed Sector Erase cycle, and is 0 when it is
struction code, and three address bytes on Serial completed. At some unspecified time before the
Data Input (D). Any address inside the Sector (see
cycle is completed, the Write Enable Latch (WEL)
Table 3.) is a valid address for the Sector Erase
bit is reset.
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence. A Sector Erase (SE) instruction applied to a page
which is protected by the Block Protect (BP2, BP1,
The instruction sequence is shown in Figure 17..
BP0) bits (see Table 2. and Table 3.) is not execut-
ed.

Figure 17. Sector Erase (SE) Instruction Sequence

0 1 2 3 4 5 6 7 8 9 29 30 31

Instruction 24 Bit Address

D 23 22 2 1 0
MSB

AI03751D

Note: Address bits A23 to A21 are Don’t Care.

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 M25P16

Bulk Erase (BE) in, otherwise the Bulk Erase instruction is not exe-
The Bulk Erase (BE) instruction sets all bits to 1 cuted. As soon as Chip Select (S) is driven High,
(FFh). Before it can be accepted, a Write Enable the self-timed Bulk Erase cycle (whose duration is
(WREN) instruction must previously have been ex- tBE) is initiated. While the Bulk Erase cycle is in
ecuted. After the Write Enable (WREN) instruction progress, the Status Register may be read to
has been decoded, the device sets the Write En- check the value of the Write In Progress (WIP) bit.
able Latch (WEL). The Write In Progress (WIP) bit is 1 during the self-
timed Bulk Erase cycle, and is 0 when it is com-
The Bulk Erase (BE) instruction is entered by driv-
pleted. At some unspecified time before the cycle
ing Chip Select (S) Low, followed by the instruction is completed, the Write Enable Latch (WEL) bit is
code on Serial Data Input (D). Chip Select (S) reset.
must be driven Low for the entire duration of the
sequence. The Bulk Erase (BE) instruction is executed only if
all Block Protect (BP2, BP1, BP0) bits are 0. The
The instruction sequence is shown in Figure 18..
Bulk Erase (BE) instruction is ignored if one, or
Chip Select (S) must be driven High after the more, sectors are protected.
eighth bit of the instruction code has been latched

Figure 18. Bulk Erase (BE) Instruction Sequence

0 1 2 3 4 5 6 7

Instruction

AI03752D

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M25P16

Deep Power-down (DP) ture of the device to be output on Serial Data Out-
Executing the Deep Power-down (DP) instruction put (Q).
is the only way to put the device in the lowest con- The Deep Power-down mode automatically stops
sumption mode (the Deep Power-down mode). It at Power-down, and the device always Powers-up
can also be used as an extra software protection in the Standby mode.
mechanism, while the device is not in active use, The Deep Power-down (DP) instruction is entered
since in this mode, the device ignores all Write, by driving Chip Select (S) Low, followed by the in-
Program and Erase instructions. struction code on Serial Data Input (D). Chip Se-
Driving Chip Select (S) High deselects the device, lect (S) must be driven Low for the entire duration
and puts the device in the Standby mode (if there of the sequence.
is no internal cycle currently in progress). But this The instruction sequence is shown in Figure 19..
mode is not the Deep Power-down mode. The
Chip Select (S) must be driven High after the
Deep Power-down mode can only be entered by
eighth bit of the instruction code has been latched
executing the Deep Power-down (DP) instruction,
to reduce the standby current (from I CC1 to I CC2, in, otherwise the Deep Power-down (DP) instruc-
as specified in Table 13.). tion is not executed. As soon as Chip Select (S) is
driven High, it requires a delay of tDP before the
Once the device has entered the Deep Power- supply current is reduced to ICC2 and the Deep
down mode, all instructions are ignored except the Power-down mode is entered.
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. This releases Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
the device from this mode. The Release from
jected without having any effects on the cycle that
Deep Power-down and Read Electronic Signature
is in progress.
(RES) instruction also allows the Electronic Signa-

Figure 19. Deep Power-down (DP) Instruction Sequence

0 1 2 3 4 5 6 7 tDP

Instruction

Stand-by Mode Deep Power-down Mode

AI03753D

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 M25P16

Release from Deep Power-down and Read progress, is not decoded, and has no effect on the
Electronic Signature (RES) cycle that is in progress.
Once the device has entered the Deep Power- The device is first selected by driving Chip Select
down mode, all instructions are ignored except the (S) Low. The instruction code is followed by 3
Release from Deep Power-down and Read Elec- dummy bytes, each bit being latched-in on Serial
tronic Signature (RES) instruction. Executing this Data Input (D) during the rising edge of Serial
instruction takes the device out of the Deep Pow- Clock (C). Then, the old-style 8-bit Electronic Sig-
er-down mode. nature, stored in the memory, is shifted out on Se-
The instruction can also be used to read, on Serial rial Data Output (Q), each bit being shifted out
Data Output (Q), the old-style 8-bit Electronic Sig- during the falling edge of Serial Clock (C).
nature, whose value for the M25P16 is 14h. The instruction sequence is shown in Figure 20..
Please note that this is not the same as, or even a The Release from Deep Power-down and Read
subset of, the JEDEC 16-bit Electronic Signature Electronic Signature (RES) instruction is terminat-
that is read by the Read Identifier (RDID) instruc- ed by driving Chip Select (S) High after the Elec-
tion. The old-style Electronic Signature is support- tronic Signature has been read at least once.
ed for reasons of backward compatibility, only, and Sending additional clock cycles on Serial Clock
should not be used for new designs. New designs (C), while Chip Select (S) is driven Low, cause the
should, instead, make use of the JEDEC 16-bit Electronic Signature to be output repeatedly.
Electronic Signature, and the Read Identifier When Chip Select (S) is driven High, the device is
(RDID) instruction. put in the Stand-by Power mode. If the device was
Except while an Erase, Program or Write Status not previously in the Deep Power-down mode, the
Register cycle is in progress, the Release from transition to the Stand-by Power mode is immedi-
Deep Power-down and Read Electronic Signature ate. If the device was previously in the Deep Pow-
(RES) instruction always provides access to the er-down mode, though, the transition to the Stand-
old-style 8-bit Electronic Signature of the device, by Power mode is delayed by tRES2, and Chip Se-
and can be applied even if the Deep Power-down lect (S) must remain High for at least tRES2(max),
mode has not been entered. as specified in Table 14.. Once in the Stand-by
Any Release from Deep Power-down and Read Power mode, the device waits to be selected, so
Electronic Signature (RES) instruction while an that it can receive, decode and execute instruc-
Erase, Program or Write Status Register cycle is in tions.

Figure 20. Release from Deep Power-down and Read Electronic Signature (RES) Instruction
Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38

Instruction 3 Dummy Bytes tRES2

D 23 22 21 3 2 1 0

MSB
Electronic Signature Out
High Impedance
Q 7 6 5 4 3 2 1 0
MSB

Deep Power-down Mode Stand-by Mode

AI04047C

Note: The value of the 8-bit Electronic Signature, for the M25P16, is 14h.

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M25P16

Figure 21. Release from Deep Power-down (RES) Instruction Sequence

0 1 2 3 4 5 6 7 tRES1

Instruction

High Impedance
Q

Deep Power-down Mode Stand-by Mode

AI04078B

Driving Chip Select (S) High after the 8-bit instruc- the device was previously in the Deep Power-
tion byte has been received by the device, but be- down mode, though, the transition to the Stand-by
fore the whole of the 8-bit Electronic Signature has Power mode is delayed by t RES1, and Chip Select
been transmitted for the first time (as shown in Fig- (S) must remain High for at least tRES1(max), as
ure 21.), still insures that the device is put into specified in Table 14.. Once in the Stand-by Power
Stand-by Power mode. If the device was not pre- mode, the device waits to be selected, so that it
viously in the Deep Power-down mode, the transi- can receive, decode and execute instructions.
tion to the Stand-by Power mode is immediate. If

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 M25P16

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must Program or Erase instructions should be sent until
not be selected (that is Chip Select (S) must follow the later of:
the voltage applied on VCC) until V CC reaches the – tPUW after V CC passed the VWI threshold
correct value:
– tVSL afterVCC passed the VCC(min) level
– VCC(min) at Power-up, and then for a further
These values are specified in Table 8..
delay of tVSL
If the delay, tVSL, has elapsed, after VCC has risen
– VSS at Power-down
above VCC(min), the device can be selected for
Usually a simple pull-up resistor on Chip Select (S) READ instructions even if the tPUW delay is not yet
can be used to insure safe and proper Power-up fully elapsed.
and Power-down.
At Power-up, the device is in the following state:
To avoid data corruption and inadvertent write op-
– The device is in the Standby mode (not the
erations during power up, a Power On Reset
Deep Power-down mode).
(POR) circuit is included. The logic inside the de-
vice is held reset while VCC is less than the POR – The Write Enable Latch (WEL) bit is reset.
threshold value, V WI – all operations are disabled, Normal precautions must be taken for supply rail
and the device does not respond to any instruc- decoupling, to stabilize the VCC feed. Each device
tion. in a system should have the VCC rail decoupled by
Moreover, the device ignores all Write Enable a suitable capacitor close to the package pins.
(WREN), Page Program (PP), Sector Erase (SE), (Generally, this capacitor is of the order of 0.1µF).
Bulk Erase (BE) and Write Status Register At Power-down, when VCC drops from the operat-
(WRSR) instructions until a time delay of tPUW has ing voltage, to below the POR threshold value,
elapsed after the moment that V CC rises above the VWI, all operations are disabled and the device
VWI threshold. However, the correct operation of does not respond to any instruction. (The designer
the device is not guaranteed if, by this time, VCC is needs to be aware that if a Power-down occurs
still below VCC(min). No Write Status Register, while a Write, Program or Erase cycle is in
progress, some data corruption can result.)

Figure 22. Power-up Timing

VCC
VCC(max)
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed

VCC(min)

Reset State tVSL Read Access allowed Device fully

of the accessible
Device
VWI

tPUW

time AI04009C

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M25P16

Table 8. Power-Up Timing and VWI Threshold

Symbol Parameter Min. Max. Unit

tVSL 1 VCC(min) to S Low 30 µs

tPUW1 Time delay to Write instruction 1 10 ms

VWI1 Write Inhibit Voltage 1.5 2.5 V

Note: 1. These parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array FFh). The Status Register contains 00h (all Status
erased: all bits are set to 1 (each byte contains Register bits are 0).

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 M25P16

MAXIMUM RATING
Stressing the device above the rating listed in the plied. Exposure to Absolute Maximum Rating con-
Absolute Maximum Ratings" table may cause per- ditions for extended periods may affect device
manent damage to the device. These are stress reliability. Refer also to the STMicroelectronics
ratings only and operation of the device at these or SURE Program and other relevant quality docu-
any other conditions above those indicated in the ments.
Operating sections of this specification is not im-

Table 9. Absolute Maximum Ratings

Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering See note 1 °C

VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V
VCC Supply Voltage –0.6 4.0 V

VESD Electrostatic Discharge Voltage (Human Body model) 2 –2000 2000 V

Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

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M25P16

DC AND AC PARAMETERS
This section summarizes the operating and mea- ment Conditions summarized in the relevant
surement conditions, and the DC and AC charac- tables. Designers should check that the operating
teristics of the device. The parameters in the DC conditions in their circuit match the measurement
and AC Characteristic tables that follow are de- conditions when relying on the quoted parame-
rived from tests performed under the Measure- ters.

Table 10. Operating Conditions.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TA Ambient Operating Temperature –40 85 °C

Table 11. AC Measurement Conditions

Symbol Parameter Min. Max. Unit

CL Load Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input Timing Reference Voltages 0.3VCC to 0.7VCC V

Output Timing Reference Voltages VCC / 2 V

Note: Output Hi-Z is defined as the point where data out is no longer driven.

Figure 23. AC Measurement I/O Waveform

Input Levels Input and Output

Timing Reference Levels
0.8VCC
0.7VCC
0.5VCC
0.3VCC
0.2VCC
AI07455

Table 12. Capacitance

Symbol Parameter Test Condition Min. Max. Unit
COUT Output Capacitance (Q) VOUT = 0V 8 pF
CIN Input Capacitance (other pins) VIN = 0V 6 pF
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 20 MHz.

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 M25P16

Table 13. DC Characteristics

Test Condition
Symbol Parameter Min. Max. Unit
(in addition to those in Table 10.)
ILI Input Leakage Current ±2 µA
ILO Output Leakage Current ±2 µA
ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 µA
ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 10 µA
C = 0.1VCC / 0.9.VCC at 50MHz,
8 mA
Q = open
ICC3 Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 20MHz,
4 mA
Q = open
ICC4 Operating Current (PP) S = VCC 15 mA
ICC5 Operating Current (WRSR) S = VCC 15 mA
ICC6 Operating Current (SE) S = VCC 15 mA
ICC7 Operating Current (BE) S = VCC 15 mA
VIL Input Low Voltage – 0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6mA 0.4 V
VOH Output High Voltage IOH = –100µA VCC–0.2 V

Table 14. AC Characteristics

Test conditions specified in Table 10. and Table 11.
Symbol Alt. Parameter Min. Typ. Max. Unit

Clock Frequency1 for the following instructions:

fC fC FAST_READ, PP, SE, BE, DP, RES, D.C. 50 MHz
WREN, WRDI, RDID, RDSR, WRSR
fR Clock Frequency for READ instructions D.C. 20 MHz

tCH 1 tCLH Clock High Time 9 ns

tCL 1 tCLL Clock Low Time 9 ns

tCLCH 2 Clock Rise Time3 (peak to peak) 0.1 V/ns

tCHCL 2 Clock Fall Time3 (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 5 ns

tCHSL S Not Active Hold Time (relative to C) 5 ns

tDVCH tDSU Data In Setup Time 2 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 5 ns

tSHCH S Not Active Setup Time (relative to C) 5 ns

tSHSL tCSH S Deselect Time 100 ns

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M25P16

Test conditions specified in Table 10. and Table 11.

Symbol Alt. Parameter Min. Typ. Max. Unit

tSHQZ 2 tDIS Output Disable Time 8 ns

tCLQV tV Clock Low to Output Valid 8 ns

tCLQX tHO Output Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 5 ns

tCHHH HOLD Hold Time (relative to C) 5 ns

tHHCH HOLD Setup Time (relative to C) 5 ns

tCHHL HOLD Hold Time (relative to C) 5 ns

tHHQX 2 tLZ HOLD to Output Low-Z 8 ns

tHLQZ 2 tHZ HOLD to Output High-Z 8 ns

tWHSL 4 Write Protect Setup Time 20 ns

tSHWL 4 Write Protect Hold Time 100 ns

tDP 2 S High to Deep Power-down Mode 3 µs

S High to Standby Mode without Electronic

tRES1 2 30 µs
Signature Read
S High to Standby Mode with Electronic
tRES2 2 30 µs
Signature Read
tW Write Status Register Cycle Time 5 15 ms

tPP Page Program Cycle Time 1.4 5 ms

tSE Sector Erase Cycle Time 1 3 s

tBE Bulk Erase Cycle Time 17 40 s

Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

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 M25P16

Figure 24. Serial Input Timing

tSHSL

tCHSL tSLCH tCHSH tSHCH

tDVCH tCHCL

tCHDX tCLCH

D MSB IN LSB IN

High Impedance
Q

AI01447C

Figure 25. Write Protect Setup and Hold Timing during WRSR when SRWD=1

W
tSHWL
tWHSL

High Impedance
Q

AI07439

33/39
M25P16

Figure 26. Hold Timing

tHLCH

tCHHL tHHCH

tCHHH

tHLQZ tHHQX

HOLD

AI02032

Figure 27. Output Timing

tCH

tCLQV tCLQV tCL tSHQZ

tCLQX tCLQX

Q LSB OUT

tQLQH
tQHQL

D ADDR.LSB IN

AI01449D

34/39
 M25P16

PACKAGE MECHANICAL

Figure 28. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline

E E2 e

A D2

L L1
ddd
A1
VDFPN-02

Note: Drawing is not to scale.

Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Mechanical Data
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 0.85 1.00 0.0335 0.0394
A1 0.00 0.05 0.0000 0.0020
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 8.00 0.3150
D2 6.40 0.2520
ddd 0.05 0.0020
E 6.00 0.2362
E2 4.80 0.1890
e 1.27 – – 0.0500 – –
K 0.20 0.0079
L 0.50 0.45 0.60 0.0197 0.0177 0.0236
L1 0.15 0.0059
N 8 8

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M25P16

Figure 29. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Package Outline

D h x 45˚
16 9

E H

1 8
θ

A2 A A1 L

ddd
B e
SO-H

Note: Drawing is not to scale.

Table 16. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Mechanical Data
mm inches
Symb.
Typ. Min. Max. Typ. Min. Max.
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 10.10 10.50 0.398 0.413
E 7.40 7.60 0.291 0.299
e 1.27 – – 0.050 – –
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.40 1.27 0.016 0.050
q 0 8 0 8
ddd 0.10 0.004

36/39
 M25P16

PART NUMBERING

Table 17. Ordering Information Scheme

Example: M25P16 – V ME 6 T P

Device Type
M25P = Serial Flash Memory for Code Storage

Device Function
16 = 16Mbit (2M x 8)

Operating Voltage
V = VCC = 2.7 to 3.6V

Package
MF = SO16 (300 mil width)
ME = VDFPN8 8x6mm (MLP8)

Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow

Option
blank = Standard Packing
T = Tape and Reel Packing

Plating Technology
blank = Standard SnPb plating
P1 = Lead-Free and RoHS compliant
G2 = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free

Note: 1. Available for SO16 package only

2. Available for MLP package only
For a list of available options (speed, package, device, please contact your nearest ST Sales Of-
etc.) or for further information on any aspect of this fice.

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M25P16

REVISION HISTORY

Table 18. Document Revision History

Date Rev. Description of Revision
16-Jan-2002 0.1 Target Specification Document written
Clarification of descriptions of entering Stand-by Power mode from Deep Power-down mode,
23-Apr-2002 0.4 and of terminating an instruction sequence or data-out sequence.
ICC2(max) value changed to 10µA
Typical Page Program time improved. Write Protect setup and hold times specified, for
13-Dec-2002 0.5 applications that switch Write Protect to exit the Hardware Protection mode immediately before
a WRSR, and to enter the Hardware Protection mode again immediately after
0.6 MLP8 package added
15-May-2003
0.7 50MHz operation, and RDID instruction added. Published internally, only
20-Jun-2003 0.8 8x6 MLP8 and SO16(300 mil) packages added
tPP, tSE and tBE revised. SO16 package code changed. Output Timing Reference Voltage
24-Sep-2003 1.0
changed. Document promoted to Preliminary Data.
Table of contents, warning about exposed paddle on MLP8, and Pb-free options added.
24-Nov-2003 2.0 Value of tVSL(min) and tBE(typ) changed. Change of naming for VDFPN8 packages. Document
promoted to full Datasheet.
MLP8(5x6) package removed. Soldering temperature information clarified for RoHS compliant
17-May-2004 3.0
devices. Device Grade clarified

38/39
 M25P16

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

© 2004 STMicroelectronics - All rights reserved

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