1914 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO.

9, SEPTEMBER 2015

A 350-MS/s Continuous-Time Delta–Sigma

Modulator With a Digitally Assisted
Binary-DAC and a 5-Bits Two-Step-ADC
Quantizer in 130-nm CMOS
Mohammad Taherzadeh-Sani and Frederic Nabki, Member, IEEE

Abstract— Two techniques to improve the performance of A drawback of DEM is that the required shuffling of all
continuous-time delta–sigma (CTDS) modulators are presented. DAC elements dramatically increases the circuit complexity
A digital calibration technique is introduced to enable the as a function of the number of involved current cells [5].
use of binary current digital-to-analog converters (DACs) with-
out dynamic element matching. Furthermore, a high-speed This results in an excess loop delay (ELD) in the modulator’s
two-step analog-to-digital data converter quantizer is introduced feedback path which can cause the DAC pulse to be shifted
to efficiently increase the resolution of the quantizer in CTDS into the next clock cycle. This effectively increases the order
modulators with high-sampling rates. A proof-of-concept proto- of the loop filter, potentially destabilizing the modulator,
type implemented in 130-nm CMOS shows that the proposed cal- and degrading its noise-shaping performance, particularly in
ibration technique can compensate for up to 5% of mismatch in
the DAC elements. The modulator has a measured SNDR/SFDR high-speed CTDS modulators [6], [7].
of 60.3/74 dB for a sampling rate of 350 MS/s and oversampling A promising technique to substitute the DEM block is DAC
ratio of 20, translating to an 8.75-MHz bandwidth. The total calibration. There are limited reported works on DAC cali-
power consumption is 5.5 mW from a 1.6 V supply. bration in CTDS modulators [2], [8]–[11]. These techniques
Index Terms— Continuous-time, delta–sigma modulator, are reported for unary DAC structures. Thus, the complexity
self-calibration, two-step analog-to-digital data converter (ADC). of these techniques (e.g., the number of switches and their
I. I NTRODUCTION control signals, the number of unit element in the layout, etc.)
can significantly increase when applying the technique in a
C ONTINUOUS-TIME delta–sigma (CTDS) modulators
are an efficient option to realize medium-to-high-
resolution/low-to-medium-bandwidth analog-to-digital data
higher resolution DAC.
This paper proposes a digital DAC self-calibration technique
converters (ADCs). Current-mode digital-to-analog convert- that can be used in binary current-mode DACs. The proposed
ers (DACs) are widely used as one of the building blocks calibration technique is a foreground method and requires no
in CTDS modulators. These DACs must be extremely linear significant additional analog circuitry. The digital correction
to attain sufficient linearity for the modulator. Conventionally, block used to implement the calibration is also very simple
single-bit DACs that are inherently linear are utilized in due to the limited number of correction coefficients necessary
delta–sigma modulators. However, they are sensitive to clock for the binary output of the modulator.
jitter [1]. Furthermore, in single-loop delta–sigma modulators Traditionally, delta–sigma modulators utilize a unary DAC
with high integrator gain to maximize the signal-to-noise architecture, where the complexity is dramatically increased
ratio (SNR), they can result in an unstable output [2]–[4]. by the DAC resolution. However, the proposed DAC cali-
Accordingly, multibit DACs are required to attain less sensi- bration allows the proposed CTDS modulator to employ a
tivity to clock jitter [1] and stable operation with a good SNR binary DAC architecture without DEM. Thus, due to the
in high-order modulators. simplicity of the binary DAC cell, increasing DAC resolu-
The inherent current-cell mismatches in the current-mode tion becomes practical, and the resolution of the modulator’s
DACs of a multibit structure limit the linearity performance quantizer is also increased. Although flash ADCs are the
of the CTDS modulator. To mitigate this problem, dynamic common architecture to realize the quantizer, they require
element matching (DEM) techniques are usually utilized to many comparators and a relatively large encoder, complicating
shape the DAC element mismatch errors to high frequencies. the design of the quantizer. Alternatively, a two-step ADC
quantizer is a good candidate to increase the quantizer’s
Manuscript received February 28, 2014; revised July 10, 2014; accepted resolution without requiring many comparators and a large
August 25, 2014. Date of publication September 15, 2014; date of current digital encoder (see [12], [13] in discrete-time modulators).
version August 21, 2015.
M. Taherzadeh-Sani is with the Department of Electrical Engineering, Thus, in this paper, a multibit two-step-ADC quantizer, along
Ferdowsi University of Mashhad, Mashhad 91779-48974, Iran (e-mail: with a foreground digital binary-DAC calibration technique,
[email protected]). is introduced within the CTDS modulator.
F. Nabki is with the CoFaMic Research Centre, Université du Québec à
Montréal, Montréal, QC H2L 2C4, Canada (e-mail: [email protected]). As a proof-of-concept, a second-order CTDS modula-
Digital Object Identifier 10.1109/TVLSI.2014.2352463 tor that utilizes the proposed techniques was implemented
1063-8210 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

Authorized licensed use limited to: J.R.D. Tata Memorial Library Indian Institute of Science Bengaluru. Downloaded on March 20,2024 at 21:03:07 UTC from IEEE Xplore. Restrictions apply.
 TAHERZADEH-SANI AND NABKI: 350-MS/s CTDS MODULATOR 1915

Fig. 3. Five-bit two-step-ADC quantizer with 1-bit redundancy. The addition

of the modulator’s input to the loop filter output is also shown. Note that a
single-ended architecture is shown for simplicity.

Fig. 1. Architecture of the presented 350-MS/s CTDS modulator with

digitally assisted binary-DAC calibration and a 5-bits two-step-ADC quantizer. noise-shaping performance [6], [7]. Here, the ELD can be
compensated for by modifying the feedforward coefficients
and introducing an additional feedback path through DAC2
from the modulator output to the input of the quantizer, as
shown in Fig. 1 [7]. DAC2 is also a binary current NRZ DAC,
but it requires no calibration, as its errors are shaped by the
loop filter in a similar fashion to the well-known shaping of
quantization noise in the modulator.
In the primary design of the modulator, the equiva-
lent discrete-time noise transfer function (NTF) of this
Fig. 2. Circuit details of the utilized conventional second-order continuous-
time loop filter consisting of two integrators and a resistive adder. second-order CTDS modulator is considered to be
NTF(z) = (1 − z −1 )2 . (1)
in 130-nm CMOS technology. Section II presents the delta– The impulse-invariant transform is used to synthesize the
sigma modulator architecture, while Section III details the two- equivalent continuous-time transfer function of this NTF [6].
step-ADC quantizer. In Section IV, the binary-DAC calibration A methodology for determining the feedforward coefficients
technique is proposed and detailed. Finally, Section V presents and the additional feedback coefficient through DAC2 is
the measurement results of the implemented CTDS modulator. presented in [6].

II. D ELTA –S IGMA M ODULATOR A RCHITECTURE III. T WO -S TEP ADC Q UANTIZER

The key contributions of this paper are: 1) the DAC cali- Flash ADCs are widely utilized to realize the quantizer in
bration technique that mitigates the need for DEM; and 2) the delta–sigma modulators. However, in high-resolution imple-
two-step ADC that allows for increased quantizer resolution. mentations, the complexity of this ADC is exponentially
As such, a conventional second-order feedforward continuous- increased. Every extra bit in such a quantizer doubles its com-
time loop filter is employed in the CTDS modulator, as shown plexity and power consumption, as well as the capacitive load
in Fig. 1. of the analog circuit that drives the quantizer [1]. Accordingly,
In the loop-filter of the modulator, the integrators are a two-step ADC quantizer is a good candidate to increase
realized using opamp-based RC integrators. The adder in the quantizer’s resolution without requiring many comparators
front of the quantizer is an opamp-based resistive adder. All (less loading effect) and a complex digital encoder. Such an
opamps have a telescopic structure to minimize their power ADC has previously been utilized in discrete-time modulators
and enhance their speed. The input is also directly added to at lower sampling frequencies [7], [8]. In this paper, a high-
the quantizer input in order to minimize the swing requirement speed two-step ADC is employed to realize the quantizer of
of the adder’s opamp. Note that this addition is performed the continuous-time modulator. Fig. 3 shows the two-step ADC
directly at the quantizer after the adder, as seen in Fig. 1. which consists of two stages each having a 3-bit resolution.
Fig. 2 shows the circuit details of the loop filter. The two-step One redundant bit is present to relax the offset requirement of
ADC quantizer has a 5-bit resolution with one redundant bit, the comparators in the first stage. Thus, the total resolution
as described in Section III. The conventional feedback path is of the quantizer is of 5 bits. The first stage is a standard
closed through DAC1, which is a binary current nonreturn-to- switched-capacitor pipeline stage with six comparators and a
zero (NRZ) DAC that is calibrated as detailed in Section IV. capacitor-based residue stage. The addition of the modulator’s
The ELD which is a timing delay in the feedback DAC input signal at the quantizer’s input seen in Fig. 1 is performed
pulse results from the finite time required for the two-step- on the input capacitors of this residue stage, as shown in
ADC quantizer to resolve its input and for the DAC1 to Fig. 3. In the residue stage, an open-loop gain stage is utilized
respond to the ADC output. This timing delay can cause the to enhance the speed [14]. To reduce power consumption,
DAC pulse to be shifted into the next clock cycle which no explicit sample and hold circuit is used. Note that the
can potentially destabilize the modulator and degrade its 1-bit redundancy also allows for the proposed low-complexity

Authorized licensed use limited to: J.R.D. Tata Memorial Library Indian Institute of Science Bengaluru. Downloaded on March 20,2024 at 21:03:07 UTC from IEEE Xplore. Restrictions apply.
 1916 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 9, SEPTEMBER 2015

stage of the two-step-ADC quantizer (i.e., B1 –B3 ), while

switch phases ϕ4 −ϕ6 of binary-weighted current sources I4 –I6
are controlled by the output bits of the second stage of the
quantizer (i.e., B4 –B6 ). Here, the current of source I3 is equal
to that of source I4 because of the 1-bit redundancy in the
two-step-ADC quantizer.
The proposed foreground calibration technique estimates the
Fig. 4. (a) Utilized binary current DAC with I1 = IREF , I2 = IREF /2, relative values of current sources I2 –I6 with respect to that
I3 = I4 = IREF /4, I5 = IREF /8, and I6 = IREF /16. During the normal oper- of I1 such that, in the digital domain, the relative bits of each
ation of the modulator, phases ϕ1 −ϕ6 are connected to B1 − B6 , respectively.
During the DAC calibration, these phases are connected as detailed in Table I. current source is corrected using the estimated values.
(b) Transition behavior of all switches phases, ϕi. In the calibration phase of the DAC, the input to the
modulator is set to zero. Then, the values of switch phases
ϕ2 − ϕ6 of the DAC current sources are set to constant
calibration technique, as described in Section IV. Note that as binary values. Only ϕ1 is connected to the output of the
shown in Fig. 1, in order to synchronize the output bits of the quantizer (i.e., B1 ). This is analogous to having a single output
two-step ADC, the output bits of its first stage (i.e., B1 –B3 ) modulator (i.e., B1 ), where ϕ2 − ϕ6 control a current offset
are delayed by a half clock cycle until the output bits of its value, IOS , at the output of the DAC. This current can also
second stage (i.e., B4 –B6 ) are ready. be converted to a voltage offset at the input of the modulator.
One of the merits of utilizing a two-step architecture is that Since the input of the modulator is zero, the average of the
the total quantizer delay is only slightly more than half a clock modulator’s output (i.e., B1 ) is relative to the offset value set
cycle. Accordingly, the instability effects resulting from this by ϕ2 − ϕ6 .
relatively short ELD can be readily compensated using direct A typical calibration sequence for source I2 is described
feedback through DAC2 in front of the quantizer [6], [7]. in order to illustrate the method. First, B2 is set to −1 and
Usually, an ELD that is larger than one clock cycle is avoided the mean value of B1 (MB0) is saved.1 Then, B2 is set to
since its compensation requires more complex techniques [15]. +1, and the mean value of B1 (MB1) is saved again. The
difference between these two values (i.e., MB0–MB1) is equal
IV. D IGITAL C ALIBRATION OF B INARY-DAC E RRORS to I2 /I1 . This is explained by the fact that when B2 goes from
Traditionally, DAC nonlinearity error correction techniques −1 to +1, the offset current IOS increases by I2 , and this
in delta–sigma modulators are mostly based on error shaping offset is canceled at the DAC output by the resulting increase
(i.e., DEM techniques) [16]. Although these techniques are in the ON-time of current source I1 (i.e., the code density of
very reliable, they do not shape the DAC errors efficiently at B1 = 1 is increased in relation to I2 /I1 ). For added detail,
low oversampling ratios (OSRs) [2], and they result in an extra the mathematical calculations of this calibration method are
delay in the modulator’s feedback path, degrading modulator presented in the Appendix. Using the same procedure, the
stability. Another technique to mitigate the DAC nonlinearity relative values of the other current sources with respect to
is calibration. Recently, different DAC calibrations in CTDS that of I1 can be estimated. Note that the offset value of the
sigma modulators have been proposed particularly in low OSR ADC does not affect this estimation since its value affects
modulators [2], [8]–[11]. These techniques are reported for both MB0 and MB1, and hence it is canceled when calculating
unary DAC structures, and as such their complexity (e.g., the MB0–MB1.
number of switches and their control signals, the number of During the calibration phase, the modulator effectively
unit element in the layout, etc.) can noticeably increase by the utilizes a 1-bit quantizer, which limits its output linear range.
DAC resolution. If the current source switches are not set properly such that
Alternatively, the digital calibration technique proposed here MB0 and MB1 are symmetric (i.e., MB1 ≈ − MB0), the value
applies to binary current DACs and requires almost no extra of either MB0 or MB1 can more likely become sufficiently
analog circuitry. Note that the proposed calibration is a self- large to come close to the output linear range of the modulator
calibration technique, since it utilizes the modulator itself to such that the value of MB0–MB1 will include some error.
estimate the coefficient errors, which can lead to reduced area Accordingly, when a current source is under calibration, the
and power consumption. The digital correction block of this other current source switches are set such that the values of
technique is also very simple due to the limited number of MB0 and MB1 are symmetric to help estimate the values of
correction coefficients needed. MB1 and MB0 more accurately. This can be done by setting
Fig. 4(a) shows the utilized binary current DAC compris- the current source switches as shown in Table I. Interestingly,
ing of six switched current sources labeled from I1 to I6 . this symmetry is made possible by the use of redundant bits
Fig. 4(b) shows the transition behavior of all switch phases, ϕi. B3 and B4 in the quantizer, and it could not be realized with
Here, all switch phases and their inverts are overlapped by a standard binary output.
utilizing reduced-swing high-crossing current switch drivers As can be seen, this calibration technique does not add any
to minimize clock feedthrough effect and transient glitch extra analog circuitry to the ADC as only a few switches are
energy [3], [17]. During the normal operation phase of the added to the DAC, and do not affect its behavior during its
modulator, switch phases ϕ1 –ϕ3 of binary-weighted current
sources I1 –I3 are controlled by the output bits of the first 1 Here, it is assumed that output bits B have binary values −1 and +1.
i

Authorized licensed use limited to: J.R.D. Tata Memorial Library Indian Institute of Science Bengaluru. Downloaded on March 20,2024 at 21:03:07 UTC from IEEE Xplore. Restrictions apply.
 TAHERZADEH-SANI AND NABKI: 350-MS/s CTDS MODULATOR 1917

TABLE I
S TATES OF A LL P HASES ϕi D URING THE DAC C ALIBRATION

Fig. 6. Output spectrum of the presented CTDS modulator. (a) Before

Fig. 5. Chip micrograph of the fabricated die in 130-nm CMOS with an calibration. (b) After calibration.
active area of 260 μm × 300 μm.

TABLE II
E STIMATED VALUES OF THE DAC E LEMENTS D URING M EASUREMENTS
OF A T YPICAL D IE U SING THE P ROPOSED C ALIBRATION T ECHNIQUE

Fig. 7. Measured output SNDR versus the input amplitude of the modulator.
normal operation. Note that a calibration technique based on
similar toggling of the DAC unit elements is also presented
in [18] for a discrete-time delta–sigma modulator. However, 40.4, and 40.9 dB, respectively, at an 8.75-MHz bandwidth
it utilizes extra DAC elements to estimate the coefficient (sampling rate of 350 MS/s and OSR of 20). As shown in
errors, and not the modulator DAC itself. As demonstrated Fig. 6(b), with the same bandwidth, the proposed calibration
in Section V, the proposed calibration technique can estimate technique improves the SNDR, SNR, and SFDR values to
a relatively large current-mismatch value of 5%. 60.3, 62, and 74 dB, respectively. In addition, the modulator’s
dynamic range is 65 dB after calibration, as can be seen
V. M EASUREMENT R ESULTS in Fig. 7. The total power consumption of the circuit is 5.5 mW
from a 1.6-V supply voltage.
The second-order CTDS modulator that utilizes the pro-
Table III lists the performance summary of the presented
posed techniques was implemented in a 130-nm CMOS tech-
CTDS modulator, outlining its main conversion characteristics
nology. A chip micrograph is shown in Fig. 5. The circuitry
and its performance before and after calibration. Fig. 8 shows
occupies an active area of 260 μm × 300 μm. Measure-
a comparison of the presented CTDS modulator to state-of-
ments of this proof-of-concept prototype demonstrated that
the-art CTDS modulators in 130-nm CMOS. The following
the proposed calibration technique can calibrate up to 5% of
figure of merit (FOM) is used here:
mismatch in the DAC elements. Note that, in this design, the
DAC elements were sized intentionally small to be relatively Power
FOM = (2)
highly mismatched. Table II shows the DAC mismatch values 2 × BW × 2ENOB
that were estimated using the proposed calibration technique. where BW represents the modulator bandwidth, and ENOB is
As shown in Fig. 6(a) before calibration, the measurements the effective number of bits. Although the goal of this paper
of the modulator show an SNDR, SNR, and SFDR of 35.5, is to provide a proof-of-concept design for the two presented

Authorized licensed use limited to: J.R.D. Tata Memorial Library Indian Institute of Science Bengaluru. Downloaded on March 20,2024 at 21:03:07 UTC from IEEE Xplore. Restrictions apply.
 1918 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 9, SEPTEMBER 2015

TABLE III modulators. A low-complexity calibration technique is intro-

P ERFORMANCE S UMMARY OF THE P RESENTED CTDS M ODULATOR duced to digitally estimate and correct the errors in a binary
current DAC. Thus, no relatively complex DEM technique
is required, and the related delay and power consumption
increase are avoided. The proposed calibration technique can
calibrate up to a 5% of mismatch in the DAC elements
with very little added circuitry and additional active area.
Furthermore, for CTDS modulators with high-sampling rates,
a high-speed two-step-ADC quantizer is introduced to effi-
ciently increase the modulator’s resolution. The modulator has
a measured SNDR of 60.3 dB and an SFDR of 74 dB for a
sampling rate of 350 MS/s and OSR of 20, translating to a
8.75-MHz bandwidth.
Ultimately, the CTDS modulator introduced in this paper
enables the use of a low-complexity quantizer with increased
resolution and of a DAC with increased resolution that is
calibrated for high mismatch values in its elements.

A PPENDIX
In summary, in the proposed DAC calibration technique,
by two consecutive measurements in which the code of B2 is
toggled, the ratio of I2 /I1 is extracted. This Appendix aims
at briefly presenting the mathematical details of the proposed
calibration technique.
Toggling code B2 from −1 to +1, is equivalent to adding
an error signal to the DAC output with a normalized value of
2I2
E DAC = (A.1)
IREF
Fig. 8. Comparison of this work to state-of-the-art delta–sigma where IREF is the differential reference current of the DAC.
modulators implemented in 130-nm CMOS that are reported in the
International Solid-State Circuits Conference (ISSCC) or the Symposium on Since the DAC is a single-bit DAC with IREF = 2I1
VLSI Circuits (VLSI) [19].
I2
E DAC = . (A.2)
I1
techniques, its FOM remains comparable with the state-of- This error signal goes to the modulator’s output through the
the-art CTDS modulators in 130-nm CMOS, while providing DAC error transfer function of
advantages with regards to design simplicity in the increased-
H (z)
resolution quantizer and increased-resolution DAC, and with ETF(z) = (A.3)
regards to robustness against high mismatch values in the DAC 1 + H (z)
elements. where H (z) is the equivalent loop-filter transfer function (in
It should be noted that the modulator exhibits higher band- discrete-time domain) of the modulator. Since during the
width and resolution in simulations. However, due to some calibration phase, VIN = 0, the modulator’s output is given
unforeseen issues in its digital block, the sampling frequency by
had to be reduced. This reduction resulted in a lower modulator
bandwidth, and also affected the noise shaping behavior of OUT(z) = NTF(z) × Q N (z) + ETF(z) × E DAC
the modulator, which reduced the effective measured reso- 1 H (z) I2
= Q N (z) + (A.4)
lution. Furthermore, a few missing codes in the output of 1 + H (z) 1 + H (z) I1
the two-step ADC were observed during measurements. This
where Q N is the quantization noise of the quantizer. Consid-
slight reduction in the quantizer’s resolution, attributed to
ering a high low-frequency gain for H , the dc value of the
process variations, can lead to a reduced performance of the
modulator’s output is equal to I2 /I1 . Similar technique can be
modulator. However, this is mitigated by the shaping of the
used to measure other current source values.
quantizer’s error by the loop filter, and its effect is accounted
for in the measurement results.
ACKNOWLEDGMENT
VI. C ONCLUSION The authors would like to thank Prof. A. Hamoui (deceased)
This paper presented a proof-of-concept prototype in from McGill University, Montréal, QC, Canada, for the fruitful
130-nm CMOS to introduce two techniques to improve CTDS discussions.

Authorized licensed use limited to: J.R.D. Tata Memorial Library Indian Institute of Science Bengaluru. Downloaded on March 20,2024 at 21:03:07 UTC from IEEE Xplore. Restrictions apply.
 TAHERZADEH-SANI AND NABKI: 350-MS/s CTDS MODULATOR 1919

R EFERENCES [18] M. Sarhang-Nejad and G. C. Temes, “A high-resolution multibit 

ADC with digital correction and relaxed amplifier requirements,” IEEE
[1] J. De Maeyer, P. Rombouts, and L. Weyten, “Efficient multibit quantiza- J. Solid-State Circuits, vol. 28, no. 6, pp. 648–660, Jun. 1993.
tion in continuous-time  modulators,” IEEE Trans. Circuits Syst. I, [19] B. Murmann. (2013). ADC Performance Survey 1997–2013. [Online].
Reg. Papers, vol. 54, no. 4, pp. 757–767, Apr. 2007. Available: http://www.stanford.edu/~murmann/adcsurvey.html
[2] J. G. Kauffman, P. Witte, J. Becker, and M. Ortmanns, “An 8.5 mW
continuous-time  modulator with 25 MHz bandwidth using digital
background DAC linearization to achieve 63.5 dB SNDR and 81 dB
SFDR,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2869–2881,
Dec. 2011. Mohammad Taherzadeh-Sani received the B.Sc.
[3] S. Yan and E. Sánchez-Sinencio, “A continuous-time  modulator degree from the Ferdowsi University of Mashhad,
with 88-dB dynamic range and 1.1-MHz signal bandwidth,” IEEE J. Mashhad, Iran, in 2001, the M.Sc. degree from the
Solid-State Circuits, vol. 39, no. 1, pp. 75–86, Jan. 2004. University of Tehran, Tehran, Iran, in 2004, and the
[4] A. A. Hamoui and K. W. Martin, “High-order multibit modulators and Ph.D. degree from McGill University, Montréal, QC,
pseudo data-weighted-averaging in low-oversampling  ADCs for Canada, in 2011.
broad-band applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, He joined the Ferdowsi University of Mashhad,
vol. 51, no. 1, pp. 72–85, Jan. 2004. in 2012, as an Assistant Professor. He fabricated
[5] S.-C. Lee and Y. Chiu, “Digital calibration of capacitor mismatch in several integrated circuits in various technologies
sigma-delta modulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, from 65 to 180-nm CMOS. His current research
vol. 58, no. 4, pp. 690–698, Apr. 2011. interests include biomedical circuits and systems,
[6] M. Ortmanns and F. Gerfers, Continuous-Time Sigma-Delta A/D Conver- high-quality and high-speed data converters, and radio frequency integrated
sion: Fundamentals, Performance Limits and Robust Implementations. circuits.
Berlin, Germany: Springer-Verlag, 2006. Dr. Taherzadeh-Sani has authored several journal publications in distin-
[7] F. Ali and A. A. Hamoui, “Continuous-time  modulators with guished journals, e.g., IEEE J OURNAL OF S OLID -S TATE C IRCUITS , the IEEE
noise-transfer-function enhancement,” in Proc. IEEE Int. Symp. Circuits T RANSACTIONS ON C IRCUITS AND S YSTEMS I, the IEEE T RANSACTIONS
Syst. (ISCAS), May 2008, pp. 1428–1431. ON C IRCUITS AND S YSTEMS II, and the IEEE T RANSACTIONS ON V ERY
[8] C.-L. Lo, C.-Y. Ho, H.-C. Tsai, and Y.-H. Lin, “A 75.1 dB SNDR L ARGE S CALE I NTEGRATION S YSTEMS , and many conference papers in
840 MS/s CT  modulator with 30 MHz bandwidth and 46.4 fJ/conv well-known conferences, e.g., the European Solid-State Circuits Conference,
FOM in 55 nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2013, the IEEE Asian Solid-State Circuits Conference, the International Conference
pp. C60–C61. on Computer-Aided Design, and the IEEE International Symposium on
[9] X. Xing, M. De Bock, P. Rombouts, and G. Gielen, “A 40 MHz Circuits and Systems. He was a recipient of the J. W. McConnell Memorial
12 bit 84.2 dB-SFDR continuous-time delta-sigma modulator in 90 nm Fellowship from McGill University for his doctoral research in 2007 and
CMOS,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2011, 2008, and the Post-doctoral Fellowship from the Le Fonds Québécois de la
pp. 249–252. Recherche sur la Nature et les Technologies in 2012 and 2013.
[10] M. De Bock, X. Xing, L. Weyten, G. Gielen, and P. Rombouts,
“Calibration of DAC mismatch errors in  ADCs based on a sine-
wave measurement,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60,
no. 9, pp. 567–571, Sep. 2013. Frederic Nabki (S’99–M’10) received the B.Eng.
[11] Z. Li and T. S. Fiez, “A 14 bit continuous-time delta-sigma A/D (Hons.) and Ph.D. degrees in electrical engineering
modulator with 2.5 MHz signal bandwidth,” IEEE J. Solid-State Circuits, from McGill University, Montréal, QC, Canada, in
vol. 42, no. 9, pp. 1873–1883, Sep. 2007. 2003 and 2010, respectively.
[12] O. Rajaee, S. Takeuchi, M. Aniya, K. Hamashita, and U.-K. Moon, He joined the Université du Québec à Mon-
“Low-OSR over-ranging hybrid ADC incorporating noise-shaped two- tréal, Montréal, (UQAM) where he is currently an
step quantizer,” IEEE J. Solid-State Circuits, vol. 46, no. 11, Associate Professor of Microelectronics Engineer-
pp. 2458–2468, Nov. 2011. ing. Some of his research projects include the design
[13] O. Rajaee et al., “Design of a 79 dB 80 MHz 8X-OSR hybrid of novel low-power and high-speed analog-to-digital
delta-sigma/pipelined ADC,” IEEE J. Solid-State Circuits, vol. 45, no. 4, converters, CMOS phase-locked loops, ultrawide-
pp. 719–730, Apr. 2010. band transceivers, and wired communication chan-
[14] B. Murmann and B. E. Boser, “A 12-bit 75-MS/s pipelined ADC using nels. He is active in research projects involving the creation of next-
open-loop residue amplification,” IEEE J. Solid-State Circuits, vol. 38, generation microelectromechanical systems (MEMS) fabrication processes
no. 12, pp. 2040–2050, Dec. 2003. using advanced materials, the integration of MEMS devices with CMOS
[15] V. Singh, N. Krishnapura, S. Pavan, B. Vigraham, D. Behera, and systems, and the modeling of MEMS devices. His current research interests
N. Nigania, “A 16 MHz BW 75 dB DR CT  ADC compensated for include mixed-signal and radio frequency integrated circuits, and MEMS for
more than one cycle excess loop delay,” IEEE J. Solid-State Circuits, various applications, such as sensing and communications.
vol. 47, no. 8, pp. 1884–1895, Aug. 2012. Dr. Nabki is a member of the Quebec Order of Engineers. He has held
[16] L. R. Carley, “A noise-shaping coder topology for 15+ bit converters,” support from the Microsystems Strategic Alliance of Quebec, the Quebec
IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 267–273, Apr. 1989. Fund for Research in Nature and Technology, the Natural Sciences and
[17] K. Falakshahi, C.-K. K. Yang, and B. A. Wooley, “A 14-bit, Engineering Research Council of Canada, and the Canada Foundation for
10-Msamples/s D/A converter using multibit  modulation,” IEEE Innovation. He was a recipient of the Governor General of Canada’s Academic
J. Solid-State Circuits, vol. 34, no. 5, pp. 607–615, May 1999. Bronze Medal.

Authorized licensed use limited to: J.R.D. Tata Memorial Library Indian Institute of Science Bengaluru. Downloaded on March 20,2024 at 21:03:07 UTC from IEEE Xplore. Restrictions apply.