TLV 1117 LV

TLV1117LV
SBVS160C – MAY 2011 – REVISED JANUARY 2023
TLV1117LV 1-A, Positive Fixed-Voltage, Low-Dropout Regulator
1 Features 3 Description
• Typical accuracy: 1.5% The TLV1117LV low-dropout (LDO) linear regulator is
• Low IQ: 100 μA (maximum) a low input voltage version of the popular TLV1117
– 500 times lower than standard 1117 devices voltage regulator.
• VIN: 2 V to 5.5 V The TLV1117LV is an extremely low-power device
– Absolute maximum VIN: 6 V that consumes 500 times lower quiescent current
• Stable With 0-mA output current than traditional 1117 voltage regulators, making the
• Low dropout: 455 mV at 1 A for VOUT = 3.3 V device designed for applications that mandate very
• High PSRR: 65 dB at 1 kHz low standby current. The TLV1117LV LDO is also
• Minimum specified current limit: 1.1 A stable with 0 mA of load current; there is no
• Stable with cost-effective ceramic capacitors: minimum load requirement, making the device a
– With 0-Ω ESR good choice for applications where the regulator must
• Temperature range: –40°C to +125°C power very small loads during standby in addition
• Thermal shutdown and overcurrent protection to large currents on the order of 1 A during normal
• For drop-in replacement with upgraded operation. The TLV1117LV offers excellent line and
functionality, see the TLV761 load transient performance, resulting in very small
• Available in a SOT-223 package magnitude undershoots and overshoots of output
– See the Mechanical, Packaging, and Orderable voltage when the load current requirement changes
Information section at the end of this document from less than 1 mA to more than 500 mA.
for a complete list of available voltage options.
A precision band-gap and error amplifier provides
2 Applications 1.5% accuracy. A very high power-supply rejection
ratio (PSRR) enables use of the device for post-
• Set-top boxes
regulation after a switching regulator. Other valuable
• TVs and monitors
features include low output noise and low-dropout
• PC peripherals, notebooks, motherboards
voltage.
• Modems and other communication products
• Switching power supply post-regulation The device is internally compensated to be stable with
0-Ω equivalent series resistance (ESR) capacitors.
These key advantages enable the use of cost-
effective, small-size ceramic capacitors. Cost-effective
capacitors that have higher bias voltages and
temperature derating can also be used if desired.
The TLV1117LV is available in a SOT-223 package.
Package Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
TLV1117LV DCY (SOT-223, 4) 6.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
INPUT OUTPUT
CIN COUT
1 µF Device 1 µF
GND
Typical Application Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV1117LV
SBVS160C – MAY 2011 – REVISED JANUARY 2023 www.ti.com
Table of Contents
1 Features............................................................................1 8 Application and Implementation.................................. 13
2 Applications..................................................................... 1 8.1 Application Information............................................. 13
3 Description.......................................................................1 8.2 Typical Application.................................................... 13
4 Revision History.............................................................. 2 8.3 Best Design Practices...............................................14
5 Pin Configuration and Functions...................................3 8.4 Power Supply Recommendations.............................14
6 Specifications.................................................................. 4 8.5 Layout....................................................................... 14
6.1 Absolute Maximum Ratings........................................ 4 9 Device and Documentation Support............................16
6.2 ESD Ratings............................................................... 4 9.1 Device Support......................................................... 16
6.3 Recommended Operating Conditions.........................4 9.2 Documentation Support............................................ 16
6.4 Thermal Information....................................................4 9.3 Receiving Notification of Documentation Updates....16
6.5 Electrical Characteristics.............................................5 9.4 Support Resources................................................... 16
6.6 Typical Characteristics................................................ 6 9.5 Trademarks............................................................... 16
7 Detailed Description...................................................... 11 9.6 Electrostatic Discharge Caution................................16
7.1 Overview................................................................... 11 9.7 Glossary....................................................................16
7.2 Functional Block Diagram......................................... 11 10 Mechanical, Packaging, and Orderable
7.3 Feature Description...................................................11 Information.................................................................... 17
7.4 Device Functional Modes..........................................12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2015) to Revision C (January 2023) Page

• Added drop-in replacement bullet to Features section....................................................................................... 1
Changes from Revision A (September 2011) to Revision B (January 2015) Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
• Replaced front-page figure ................................................................................................................................ 1
• Deleted Dissipation Ratings table.......................................................................................................................4
2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: TLV1117LV

TLV1117LV
www.ti.com SBVS160C – MAY 2011 – REVISED JANUARY 2023
5 Pin Configuration and Functions
3 INPUT
OUTPUT
2 OUTPUT
1 GND
Figure 5-1. DCY Package, 4 Pins (SOT-223) (Top View)
Table 5-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
IN 3 I Input pin. See the Input and Output Capacitor Requirements section for more details.
Regulated output voltage pin. See the Input and Output Capacitor Requirements section for more
OUT 2, Tab O
details.
GND 1 — Ground pin.
Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

TLV1117LV
6 Specifications
6.1 Absolute Maximum Ratings
at TJ = 25°C (unless otherwise noted); all voltages are with respect to GND(1)
MIN MAX UNIT
VIN –0.3 6 V
Voltage
VOUT –0.3 6 V
Current IOUT Internally limited
Output short-circuit duration Indefinite
Continuous total power
PDISS See Thermal Information
dissipation
Operating junction, TJ –55 150 °C
Temperature
Storage, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
±2000
all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification
±500
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 2 5.5 V
VOUT Output voltage 0 5.5 V
IOUT Output current 0 1 A
6.4 Thermal Information

TLV1117LV
THERMAL METRIC(1) DCY (SOT-223) UNIT
4 PINS
RθJA Junction-to-ambient thermal resistance 62.9 °C/W
θJCtop Junction-to-case (top) thermal resistance 47.2 °C/W
RθJC(top) Junction-to-board thermal resistance 12 °C/W
ψJT Junction-to-top characterization parameter 6.1 °C/W
ψJB Junction-to-board characterization parameter 11.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.

TLV1117LV
6.5 Electrical Characteristics

at VIN = VOUT(nom) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 2 5.5 V
VOUT > 2 V –1.5% 1.5%
DC output
VOUT 1.5 V ≤ VOUT < 2 V –2% 2%
accuracy
1.2 V ≤ VOUT < 1.5 V –40 40 mV
ΔVOUT(ΔVIN) Line regulation VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA 1 5 mV
ΔVOUT(ΔIOUT) Load regulation 0 mA ≤ IOUT ≤ 1 A 1 35 mV
IOUT = 200 mA 115
IOUT = 500 mA 285
VOUT < 3.3 V
IOUT = 800 mA 455
VIN = 0.98 × IOUT = 1 A 570 800

VDO Dropout voltage(1) mV
VOUT(nom) IOUT = 200 mA 90
IOUT = 500 mA 230
VOUT ≥ 3.3 V
IOUT = 800 mA 365
IOUT = 1 A 455 700
ICL Output current limit VOUT = 0.9 × VOUT(nom) 1.1 A
IQ Quiescent current IOUT = 0 mA 50 100 μA
Power-supply VIN = 3.3 V, VOUT = 1.8 V,
PSRR 65 dB
rejection ratio IOUT = 500 mA, f = 100 Hz
Output noise BW = 10 Hz to 100 kHz, VIN = 2.8 V, VOUT = 1.8 V,
Vn 60 µVRMS
voltage IOUT = 500 mA
tSTR Start-up time(2) COUT = 1.0 µF, IOUT = 1 A 100 µs
Undervoltage
UVLO VIN rising 1.95 V
lockout
Thermal shutdown Shutdown, temperature increasing 165

TSD °C
temperature Reset, temperature decreasing 145
Operating junction
TJ –40 125 °C
temperature
(1) VDO is measured for devices with VOUT(nom) = 2.5 V so that VIN = 2.45 V.
(2) Start-up time = time from when VIN asserts to when output is sustained at a value greater than or equal to 0.98 × VOUT(nom).

TLV1117LV
6.6 Typical Characteristics

at VIN = VOUT(nom) + 1.5 V, IOUT = 10 mA, COUT = 1.0 μF, and TA = 25°C (unless otherwise noted)
1.9 1.9
VOUT = 1.8 V VOUT = 1.8 V
IOUT = 10 mA IOUT = 1 A
1.85 1.85
Output Voltage (V)
Output Voltage (V)

1.8 1.8
1.75 +125°C 1.75

+85°C +85°C
+25°C +25°C
-40°C -40°C
1.7 1.7
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
Input Voltage (V) Input Voltage (V)
Figure 6-1. Line Regulation Figure 6-2. Line Regulation

1.9 1200
VOUT = 1.8 V +85°C
+25°C
1000
-40°C
1.85
Dropout Voltage (mV)
Output Voltage (V)
800
1.8 600
400
1.75 +125°C
+85°C
200
+25°C
-40°C
1.7 0
0 100 200 300 400 500 600 700 800 900 1000 2 2.5 3 3.5 4 4.5
Output Current (mA) Input Voltage (V)
Figure 6-3. Load Regulation Figure 6-4. Dropout Voltage vs Input Voltage
600 1.9
VOUT = 1.8 V
500
1.85
Dropout Voltage (mV)
Output Voltage (V)
400
300 1.8
200
+125°C 1.75
+85°C
100
+25°C 10 mA
-40°C 500 mA
0 1.7
0 100 200 300 400 500 600 700 800 900 1000 -40 -25 -10 5 20 35 50 65 80 95 110 125
Output Current (mA) Temperature (°C)
Figure 6-5. Dropout Voltage vs Output Current Figure 6-6. Output Voltage vs Temperature

TLV1117LV
6.6 Typical Characteristics (continued)

600 1.8
1.78
500
1.76
Quiescent Current (mA)
Current Limit (mA)

1.74
400
1.72
300 1.7
1.68
200
1.66
+125°C
+85°C 1.64 +85°C
100
+25°C +25°C
1.62
-40°C -40°C
0 1.6
0 100 200 300 400 500 600 700 800 900 1000 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
Output Current (mA) Input Voltage (V)
Figure 6-7. Quiescent Current vs Load Figure 6-8. Current Limit vs Input Voltage
90 90
IOUT = 500 mA IOUT = 500 mA
Power-Supply Rejection Ratio (dB)
80 Power-Supply Rejection Ratio (dB) 80

IOUT = 150 mA IOUT = 150 mA
70 IOUT = 30 mA 70 IOUT = 30 mA
60 60
50 50
40 40
30 30
20 20
10 10
VIN - VOUT = 3 V VIN - VOUT = 1.5 V
0 0
10 100 1k 10 k 100 k 1M 10 M 10 100 1k 10 k 100 k 1M 10 M
Frequency (Hz) Frequency (Hz)
Figure 6-9. Power-Supply Rejection Ratio vs Frequency Figure 6-10. Power-Supply Rejection Ratio vs Frequency
90 10
f = 50 Hz f = 120 Hz
Power-Supply Rejection Ratio (dB)
80
Noise Spectral Density (mV/?Hz)
f = 10 kHz
70 1
60
f = 1 kHz f = 100 kHz
50
0.1
f = 1 MHz
40
30 f = 10 MHz
0.01
20
10
VIN - VOUT = 1.5 V
0.001
0
10 100 1k 10 k 100 k 1M 10 M
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Output Current (mA)
Figure 6-12. Spectral Noise Density vs Frequency

Figure 6-11. Power-Supply Rejection Ratio vs Output Current

TLV1117LV

500 mA VIN = 2.8 V 500 mA VIN = 2.8 V

200 mA/div
200 mA/div
200 mA IOUT 200 mA IOUT
VOUT VOUT
50 mV/div
50 mV/div
50 ms/div 50 ms/div
COUT = 1 μF COUT = 10 μF
Figure 6-13. Load Transient Response 200 mA to 500 mA Figure 6-14. Load Transient Response 200 mA to 500 mA
VIN = 2.8 V
500 mA/div
500 mA/div
500 mA 500 mA
1 mA IOUT 1 mA IOUT
50 mV/div
50 mV/div
VOUT VOUT
50 ms/div 50 ms/div
Figure 6-15. Load Transient Response 1 mA to 500 mA Figure 6-16. Load Transient Response 1 mA to 500 mA
1A 1A
500 mA/div
500 mA/div
200 mA IOUT 200 mA IOUT

100 mV/div
100 mV/div
VOUT VOUT
50 ms/div 50 ms/div
Figure 6-17. Load Transient Response 200 mA to 1 A Figure 6-18. Load Transient Response 200 mA to 1 A

TLV1117LV

1A 1A
500 mA/div
500 mA/div
1 mA IOUT 1 mA IOUT
100 mV/div
100 mV/div
VOUT VOUT
50 ms/div 50 ms/div
Figure 6-19. Load Transient Response 1 mA to 1 A Figure 6-20. Load Transient Response 1 mA to 1 A
4.3 V 4.3 V
1 V/div
3.3 V VIN 1 V/div 3.3 V VIN

5 mV/div
5 mV/div
VOUT VOUT
200 ms/div 200 ms/div
VOUT = 1.8 V, IOUT = 10 mA VOUT = 1.8 V, IOUT = 500 mA

Figure 6-21. Line Transient Response Figure 6-22. Line Transient Response
4.3 V 5.5 V
1 V/div
1 V/div
3.3 V VIN 3.3 V VIN

10 mV/div
10 mV/div
VOUT VOUT
VOUT = 1.8 V, IOUT = 1 A VOUT = 1.8 V, IOUT = 10 mA


TLV1117LV

5.5 V 5.5 V
1 V/div
1 V/div
3.3 V VIN 3.3 V VIN
10 mV/div
10 mV/div
VOUT VOUT
VOUT = 1.8 V, IOUT = 500 mA VOUT = 1.8 V, IOUT = 1 A


TLV1117LV
7 Detailed Description
7.1 Overview
The TLV1117LV is a low quiescent current, high PSRR LDO capable of handling up to 1 A of load current. This
device features an integrated current limit, thermal shutdown, band-gap reference, and undervoltage lockout
(UVLO) circuit blocks.
7.2 Functional Block Diagram
IN OUT
Current
Limit
Thermal
Shutdown
UVLO
Bandgap
LOGIC
TLV1117LV Series
GND
7.3 Feature Description

7.3.1 Internal Current Limit
The TLV1117LV internal current limit helps protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the
output voltage is not regulated, and can be calculated by the formula: VOUT = ILIMIT × RLOAD. The PMOS pass
transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device turns off. When
the device cools down, the internal thermal shutdown circuit turns the device back on. If the fault condition
continues, the device cycles between current limit and thermal shutdown. See the Thermal Protection section for
more details.
The PMOS pass transistor in the TLV1117LV has a built-in body diode that conducts current when the voltage at
OUT exceeds the voltage at IN. This current is not limited; if extended reverse voltage operation is anticipated,
external limiting to 5% of the rated output current is recommended.
7.3.2 Dropout Voltage
The TLV1117LV uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass transistor is in the linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass transistor. VDO scales approximately with output current because the
PMOS transistor behaves like a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded when (VIN – VOUT) approaches dropout.

TLV1117LV
7.3.3 Undervoltage Lockout

The TLV1117LV uses an undervoltage lockout (UVLO) circuit to keep the output shut off until internal circuitry is
operating properly.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is greater than the nominal output voltage added to the dropout voltage
• The output current is less than the current limit
• The device die temperature is lower than the thermal shutdown temperature
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass transistor is in a triode state and no longer controls the current through
the LDO. Line or load transients in dropout can result in large output voltage deviations.
Table 7-1 shows the conditions that lead to the different modes of operation.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN IOUT
Normal mode VIN > VOUT (nom) + VDO IOUT < ICL
Dropout mode VIN < VOUT (nom) + VDO IOUT < ICL

TLV1117LV
8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information

The TLV1117LV is a low quiescent current linear regulator designed for high current applications. Unlike typical
high current linear regulators, the TLV1117LV consumes significantly less quiescent current. This device delivers
excellent line and load transient performance. The device is low noise, and exhibits a very good PSRR. As a
result, this device is designed for high current applications that require very sensitive power-supply rails.
This regulators offer both current limit and thermal protection. The operating junction temperature range of the
device is –40°C to +125°C.
8.2 Typical Application
Figure 8-1 shows a typical application circuit.
INPUT OUTPUT
CIN COUT
1 µF Device 1 µF
GND
Figure 8-1. Typical Application Circuit
8.2.1 Design Requirements

For this design example, use the parameters listed in Table 8-1 as the input parameters.
Table 8-1. Design Parameters
PARAMETER DESIGN REQUIREMENT
Input voltage 2.5 V to 3.3 V
Output voltage 1.8 V
Output current 500 mA
8.2.2 Detailed Design Procedure

8.2.2.1 Input and Output Capacitor Requirements
For stability, 1.0-μF ceramic capacitors are required at the output. Higher-valued capacitors improve transient
performance. Use X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in
value and equivalent series resistance (ESR) over temperature. Unlike traditional linear regulators that need
a minimum ESR for stability, the TLV1117LV is specified to be stable with no ESR. Therefore, cost-effective
ceramic capacitors can be used with this device. Effective output capacitance that takes bias, temperature, and
aging effects into consideration must be greater than 0.5 μF to ensure stability of the device.
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF to
1.0-μF, low-ESR capacitor across the IN pin and GND pin of the regulator. This capacitor counteracts reactive
input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor
can be necessary if large, fast rise-time load transients are anticipated, or if the device is not located physically

TLV1117LV
close to the power source. If source impedance is greater than 2 Ω, a 0.1-μF input capacitor can also be
necessary to ensure stability.
8.2.2.2 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude.
8.2.3 Application Curves
500 mA VIN = 2.8 V

200 mA/div
4.3 V
1 V/div
200 mA IOUT 3.3 V VIN
VOUT
50 mV/div
5 mV/div
VOUT
Figure 8-2. Load Transient Response 200 mA to Figure 8-3. Line Transient Response VOUT = 1.8 V,
500 mA, COUT = 1 μF IOUT = 500 mA
8.3 Best Design Practices

Place input and output capacitors as close to the device as possible.
Use a ceramic output capacitor.
Do not use an electrolytic output capacitor.
Do not exceed the device absolute maximum ratings.
8.4 Power Supply Recommendations
Connect a low output impedance power supply directly to the INPUT pin of the TLV1117LV. Inductive
impedances between the input supply and the INPUT pin can create significant voltage excursions at the INPUT
pin during start-up or load transient events.
8.5 Layout
8.5.1 Layout Guidelines
Place input and output capacitors as close to the device pins as possible. To improve characteristic AC
performance (such as PSRR, output noise, and transient response), design the board with separate ground
planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the
ground connection for the output capacitor must be connected directly to the GND pin of the device. Higher
value ESR capacitors can degrade PSRR performance.
8.5.1.1 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing
the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting the regulator from
damage as a result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety
in a complete design (including heat sink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions.

TLV1117LV
The internal protection circuitry of the TLV1117LV is designed to protect against overload conditions. This
circuitry is not intended to replace proper heat sinking. Continuously running the TLV1117LV into thermal
shutdown degrades device reliability.
8.5.1.2 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given in the
Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device.
The addition of plated through-holes to heat-dissipating layers also improves heat-sink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product
of the output current and the voltage drop across the output pass element, as shown in Equation 1:
PD = (VIN - VOUT) IOUT (1)
8.5.2 Layout Example
OUTPUT
Tab
GND
COUT
CIN
1 2 3
GND INPUT
Figure 8-4. Layout Example

TLV1117LV
9 Device and Documentation Support

9.1 Device Support
9.1.1 Development Support
9.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TLV1117LV. The TLV1117LV33EVM-714 evaluation module (and related user's guide) can be requested at the TI
website through the product folders or purchased directly from the TI eStore.
9.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TLV1117LV is available through the product folders under
Tools & Software.
9.1.2 Device Nomenclature
Table 9-1. Available Options(1)
PRODUCT VOUT
xx is the nominal output voltage (for example 33 = 3.3 V).
TLV1117LVxxyyyz yyy is the package designator.
z is the package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
9.2 Documentation Support

9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TLV1117LVxxEVM-714 Evaluation Module user's guide
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

TLV1117LV
10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 17-Jul-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TLV1117LV12DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SI Samples
TLV1117LV12DCYT LIFEBUY SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SI
TLV1117LV15DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VR Samples
TLV1117LV15DCYT LIFEBUY SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VR
TLV1117LV18DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SH Samples
TLV1117LV18DCYT ACTIVE SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SH Samples
TLV1117LV25DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VS Samples
TLV1117LV25DCYT ACTIVE SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VS Samples
TLV1117LV28DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VT Samples
TLV1117LV30DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VU Samples
TLV1117LV30DCYT LIFEBUY SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VU
TLV1117LV33DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 TJ Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jul-2024
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Apr-2024
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV1117LV12DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV12DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
Pack Materials-Page 1
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV1117LV12DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0
TLV1117LV12DCYT SOT-223 DCY 4 250 340.0 340.0 38.0
MECHANICAL DATA
MPDS094A – APRIL 2001 – REVISED JUNE 2002
DCY (R-PDSO-G4) PLASTIC SMALL-OUTLINE
6,70 (0.264)
6,30 (0.248)
3,10 (0.122)
2,90 (0.114)
4
0,10 (0.004) M
7,30 (0.287) 3,70 (0.146)

6,70 (0.264) 3,30 (0.130)
Gauge Plane
1 2 3
0,25 (0.010)
0,84 (0.033) 0°–10°
2,30 (0.091)
0,66 (0.026)
0,10 (0.004) M
4,60 (0.181) 0,75 (0.030) MIN
1,70 (0.067)
1,80 (0.071) MAX 1,50 (0.059)
0,35 (0.014)
0,23 (0.009)
Seating Plane
0,10 (0.0040) 0,08 (0.003)

0,02 (0.0008)
4202506/B 06/2002
NOTES: A. All linear dimensions are in millimeters (inches).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC TO-261 Variation AA.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated

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TLV1117LV

SBVS160C – MAY 2011 – REVISED JANUARY 2023

TLV1117LV 1-A, Positive Fixed-Voltage, Low-Dropout Regulator

(1) For all available packages, see the orderable addendum at

Typical Application Circuit

Changes from Revision B (January 2015) to Revision C (January 2023) Page

Changes from Revision A (September 2011) to Revision B (January 2015) Page

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TLV1117LV

5 Pin Configuration and Functions

Figure 5-1. DCY Package, 4 Pins (SOT-223) (Top View)

Table 5-1. Pin Functions

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

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6.5 Electrical Characteristics

VIN = 0.98 × IOUT = 1 A 570 800

Thermal shutdown Shutdown, temperature increasing 165

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5

6.6 Typical Characteristics

Output Voltage (V)

1.75 +125°C 1.75

Figure 6-1. Line Regulation Figure 6-2. Line Regulation

Output Voltage (V)

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Product Folder Links: TLV1117LV

6.6 Typical Characteristics (continued)

Current Limit (mA)

80 Power-Supply Rejection Ratio (dB) 80

Figure 6-12. Spectral Noise Density vs Frequency

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7

6.6 Typical Characteristics (continued)

500 mA VIN = 2.8 V 500 mA VIN = 2.8 V

200 mA IOUT 200 mA IOUT

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Product Folder Links: TLV1117LV

6.6 Typical Characteristics (continued)

3.3 V VIN 1 V/div 3.3 V VIN

200 ms/div 200 ms/div

VOUT = 1.8 V, IOUT = 10 mA VOUT = 1.8 V, IOUT = 500 mA

3.3 V VIN 3.3 V VIN

200 ms/div 200 ms/div

VOUT = 1.8 V, IOUT = 1 A VOUT = 1.8 V, IOUT = 10 mA

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9

6.6 Typical Characteristics (continued)

200 ms/div 200 ms/div

VOUT = 1.8 V, IOUT = 500 mA VOUT = 1.8 V, IOUT = 1 A

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7.3 Feature Description

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11

7.3.3 Undervoltage Lockout

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Product Folder Links: TLV1117LV

8 Application and Implementation

8.1 Application Information