Meerut institute of Technology, Meerut

Department – CSE
Subject – computer organization and architecture
Question bank

Course- B.Tech(Second year)

1 Draw the block diagram for𝑦𝑇2: 𝑅1 ← 𝑅2, 𝑅2 ← 𝑅1. CO1, K1

2 Represent the following conditional control statement by two CO1, K1

register transfer statements with control functions.

If (P = 1) then (R1 ← R2) else if (Q = 1) then (R1 ← R3)

3. The following transfer statements specify a memory. Explain the CO1, K1

memory operation in each case.

a. R2 ← M[AR]
b. M[AR] ← R3
c. R5 ← M[R5]
4 Explain with neat and clean diagram the basic functional units of a CO1, K1
computer
5. Why bus arbitration is required in computer? CO1, K1

6 Explain The Role of IR (Instruction Register) and AC CO1, K1

(Accumulator Register) in computer System.

What is difference between a direct and an indirect address CO1, K1

7.
instruction? How many references to memory are needed for each
type of instruction to bring an operand into a processor register?
Design the block hardware diagram for the following Register CO1, K1
8
Transfer Language; assume that registers are of 8 bit.
X+ Y T0 + ZT1 : R1 R3
Design a 4-Bit Carry-Look ahead adder and explain its operation CO2, K3
9
with an example.
How Independent Request Method of Bus Arbitration is more CO1, K2
efficient than Daisy Chaining Method and Polling method?
Explain with neat and clean diagrams.
Represent the following decimal numbers in IEEE standard CO2, K4
10 format in a single and double precision method

i. (65.175)10
ii. (-307.1875)10
11 What are the IEEE 754 formats for floating point representation? CO2, K1

12 Perform the following operation with 8 bit register and using 2’s CO2, K2
complement method: (56)10 + (-27)10.
13 Represent (.75)10 in binary floating point representation (IEEE CO2, K2
754) single precision
14 Design a circuit for four bit arithmetic unit and describe its CO1, K2
function table in detail.

15 Draw and explain the common bus system using multiplexers. CO1, K2

16 Why the bus has very important role in computer system? A CO1, K2
digital computer has a common bus system for 16 registers of 32
bits each. The bus is constructed with multiplexers.

a. How many selection inputs are there in each

multiplexer?
b. What sizes of multiplexers are needed?
c. How many multiplexers are there in the bus?
17 Evaluate the arithmetic statement X = (A+B)*(C+D) using CO1, K2
general register computer with Zero Address ,One Address, Two
Address and Three Address instruction formats.

18 Explain in detail the different kinds of addressing modes with an CO1, K1

example.
19 What is General Register Organization? Explain with neat and CO1, K1
clean diagram.
Design a general register of processor organization. What are CO1, K1
20
different type instruction types, explain with a suitable example of
each?
21 Show the multiplication process using Booth’s Algorithm when CO2, K2
the following numbers are multiplied:
(-13) by (+8)
22 Explain the Booth’s multiplication algorithm in detail. Give an CO2, K2
example for multiplication using Booth’s algorithm.
What are different addressing modes? An Instruction is Stored at CO2, K2
23
location 200 with its address field at location 201. The address
field has the value 400. A processor register R1 contain the value
200. Find out the effective address if the addressing mode of the
instruction is : -
1) Immediate 2) Direct 3) Register indirect 4) Relative 5) Index
with R1 as the Index Register
 24 Multiply (+13) and (-12) using Booth Multiplication Algorithm. CO2, K2

25 Perform the division process of 00001111 by 0011(use a dividend CO2, K3

of 8 bits).

26 Perform the division process of the following numbers. Dividend CO2, K3

=17 and Divisor = 3.

27 Convert the following arithmetic expressions from infix to reverse CO1, K2

polish notations.
i. A*B+C*C
ii. (3*4)+(5*6)
iii. A*B+C*D+E*F
iv. A*[B+C*CD+E]/F*(G+H)
28 How D-flip flop play very important role in Shift (Left & Right CO1, K1
Shift) and Load micro operations in Registers? Explain with neat
and clean diagram.

29 Differentiate between Floating point number and Fixed Point CO1, K1

Number with an example

30 Discuss Stack Organization: CO1, K1

i. Register Stack ii. Memory Stack

31 Design a Full Adder by using 2 Half Adder. CO1, K1

UNIT -3: CONTROL UNIT

S.N. Problem CO, KL Mapping
What is difference between a direct and an indirect address instruction? How
32 CO3, K2
many references to memory are needed for each type of instruction to bring an
operand into a processor register?
33 How the instructions are executed in CPU? Describe various phases of the CO3, K2
instruction cycle with suitable register transfer statements.

A computer uses a memory unit with 256K words of 32 bits each. A binary
34 CO3, K3
instruction code is stored in one word of memory. The instruction has four parts:
an indirect bit, an operation code, a register code part to specify one of 64
registers, and an address part.
a. How many bits are there in the operation code, the register code part,
and the address part?
b. Draw the instruction word format and indicate the number of bits in each
part.
c. How many bits are there in the data and address inputs of the memory?
35 The content of AC in the basic computer is hexadecimal A937 and the initial CO3, K3
value of E is 1. Determine the contents of AC, E, PC, AR, and IR in hexadecimal
after the execution of the CLA instruction. Repeat 11 more times, starting from
each one of the register-reference instructions. The initial value of PC is
 hexadecimal 021.
36 What is RISC and how it differs with CISC? CO3, K1
37 What are differences between hardwired and microprogrammed control unit? CO3, K1
38 Differentiate between Horizontal & Vertical microprogramming CO3, K1
What is micro programmed control unit? Give the basic structure of micro
39 CO3, K2
programmed control unit. Also discuss the microinstruction format and the
control unit organization for a typical micro programmed controllers using
suitable diagram.
40 Explain the pipelining in detail with neat and clean diagram. CO3, K1
41 A non-pipelined system takes 50 ns to process a task. The same task can be CO3, K3
processed in a six-segment pipeline with a clock cycle of 10 ns. Determine the
speedup ratio of the pipeline for 100 tasks. What is the maximum speedup that
can be achieved?
42 Explain the following term. CO3, K1
i)Microoperation ii) Microinstruction iii) Microprogram iv) Micro Code
UNIT-4: MEMORY ORGANIZATION
S.N. Problem CO, KL Mapping

43. Answer the following questions in short: CO4, K2

a. What is the difference between RAM and ROM?
b. What is difference between Page and Page Frame (Block)?
c. What do you mean by locality of reference?
d. What is hit rate?

44. Explain the concept of cache memory in detail. CO4, K2

45. Describe the concept of virtual memory with suitable diagram. CO4, K2

46. The access time of a cache memory is 100 ns and that of main memory 1000 ns. It CO4, K2
is estimated that 80 percent of memory requests are for read and remaining 20
percent for write. The hit ratio for read access only is 0.9. A write through
procedure is used.
I. What is average access time of the system considering only memory read
cycle?
II. What is the average access time of the system for both read and write
requests?
III. What is the hit ratio taking into consideration the write cycle?

47. A virtual memory system has an address space of 8K words, a memory space of CO4, K2
4K words and page and block sizes of 1K words. The following page reference
changes occur during given time interval (only page changes are listed. If the
same page is referenced again it is not listed twice.)
4 2 0 1 2 6 1 4 0 1 0 2 3 5 7
Determine the four pages that are resident in main memory after each page
reference change if the replacement algorithm used is (a) FIFO (b) LRU.

48. A two-way set associative cache memory uses blocks of four words. The cache CO4, K2
can accommodate a total of 2048 words from main memory. The main memory
size is 128K X 32.
a. Formulate all pertinent information required to construct the cache
memory.
b. What is the size of cache memory?
49. Answer the following questions: CO4, K2
a. How many 128X8 RAM chips are needed to provide a memory capacity
of 2048 bytes?
b. How many lines of the address bus must be used to access 2048 bytes of
memory? How many of these lines will be common to all chips?
How many lines to be decoded for chip select? Specify the size of decoders.

50. An address space is specified by 24 bits and corresponding memory space by 16 CO4, K2
bits.
a. How many words are there in the address space?
b. How many words are there in the memory space?
If a page consists of 2K words, how many pages and blocks are there in the
system?

UNIT-5: INPUT-OUTPUT

S.N. Problem CO, KL Mapping

51. What do you mean by asynchronous data transfer? Explain strobe control and CO5, K1
Handshaking mechanism with neat and clean diagram
Why input output interface is required? Describe in detail.
52. CO5, K1
Write down the difference between Isolated I/O and Memory mapped I/O. Also
53 CO5, K1
discuss the advantages and disadvantages of Isolated I/O and memory mapped
I/O.

Differentiate between:
54. CO5, K1
a. Processor and Input output processor with neat and clean
diagram.
b. Synchronous and Asynchronous data transfer.
c. RISC and CISC based microprocessor.
d. Serial and parallel communication.
e. What is Cycle Stealing and Burst Transfer (Block Transfer)
Find the average time to read or write a 512B sector for a disk rotating at 15,000
55. CO5, K3
RPM with average seek time of 4 ms, a 100MB/sec transfer rate, and a 0.2 ms
controller overhead.

56. Explain various modes of data transfer in detail. CO5, K1

57. Explain the concept and working of DMA in detail with suitable diagram. CO5, K2

58. A DMA controller transfers 16-bit words to memory using cycle stealing. The CO5, K3
words are assembled from a device that transmits characters at a rate of 2400
characters per second. The CPU is fetching and executing instructions at an
average rate of 1 milling instructions per second. By how much will the CPU be
slowed down because of DMA transfer?

59. Explain the input output processor with suitable diagram along with CPU-IOP CO5, K2
communication.

60 Differentiate between isolated and memory mapped input output. CO5, K1