Dr.

T G Manjunath, Professor and HOD, Department of CSE(AI & ML),SVIT

MODULE-2
Combinational Logic and Sequential Logic

Syllabus:
Combinational Logic: Introduction, Combinational Circuits, Design Procedure, Binary Adder-
Subtractor, Decoders, Encoders, Multiplexers.

HDL Models of Combinational Circuits – Adder, Multiplexer, Encoder.

Sequential Logic: Introduction, Sequential Circuits, Storage Elements: Latches, Flip-Flops

Introduction: A combinational circuit consists of logic gates whose outputs

at any time are determined from only the present combination of inputs.
Combinational logic gates react to the values of the signals at their inputs and
produce the value of the output signal, transforming binary information from
the given input data to a required output data.

Following are the characteristics of the combinational logic circuit:

 At any instant of time, the output of the combinational circuits depends

only on the present input.
 The combinational circuit doesn't have any backup or previous
memory.
 The n number of inputs and m number of outputs are possible in
combinational logic circuits.

The n input binary variables come from an external source; the m output
variables are produced by the internal combinational logic circuit and go to
an external destination. Some of the Examples are, Adders, Subtractors,
Decoders, Encoders, Multiplexers etc

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Design Procedure of Combinational Logic Circuits:

The design of combinational circuits starts from the Design specification of
the circuit. Procedure involves the following steps:
Step1: From the specifications of the circuit, determine the required number
of inputs and outputs and assign a symbol to each.
Step 2: Create the truth table that defines the required relationship between
inputs and outputs.
Step 3: Obtain the simplified Boolean functions for each output as a function
of the input variables.
Step 4: Draw the logic diagram and verify the correctness of the design
(manually or by simulation).

A truth table for a combinational circuit consists of input columns and output
columns. The input columns are obtained from the 2n binary numbers for
the n input variables. The binary values for the outputs are determined from
the stated specifications. The output functions specified in the truth table give
the exact definition of the combinational circuit.

Code Conversion Example:

BCD to excess-3 code Converter:

BCD stands for Binary Coded Decimal. BCD is a coding scheme used to
represent decimal numbers in the binary format. In BCD coding scheme, each
decimal digit, from 0 to 9, is encoded as a group of 4-bits.
The process of converting BCD to Excess-3 is quite simple . The Excess-3 code
can be calculated by adding 3, i.e., 0011 to each four -digit BCD code. Below
is the truth table for the conversion of BCD to Excess-3 code.

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Design of BCD to excess-3 code Converter

Step 1: Decide the number of inputs and outputs:

Since each code uses four bits to represent a decimal digit, there must be four
input variables and four output variables. We designate the four input binary
variables by the symbols A, B, C, and D, and the four output variables by w,
x, y , and z .
Step 2: Create the truth table that defines the required relationship
between inputs and outputs.
Note that four binary input variables may have 16 bit combinations, but only
10 (0 to 9)are listed in the truth table with Excess-3 output and the remaining
six input combinations of variables are don’t-care conditions. These values
have no meaning in BCD and we assume that they will never occur in actual
operation of the circuit.

Decimal BCD Code EXCESS -3 CODE

Number A B C D W X Y Z
0 0 0 0 0 0 0 1 1

1 0 0 0 1 0 1 0 0

2 0 0 1 0 0 1 0 1

3 0 0 1 1 0 1 1 0

4 0 1 0 0 0 1 1 1

5 0 1 0 1 1 0 0 0

6 0 1 1 0 1 0 0 1

7 0 1 1 1 1 0 1 0

8 1 0 0 0 1 0 1 1

9 1 0 0 1 1 1 0 0

10 1 0 1 0 X X X X

11 1 0 1 1 X X X X

12 1 1 0 0 X X X X

13 1 1 0 1 X X X X

14 1 1 1 0 X X X X

15 1 1 1 1 X X X X

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Step 3: Obtain the simplified Boolean functions for each output as a function
of the input variables. (From K map)

The final expressions can be written as

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Step-4: Draw the Logic Diagram for the above Boolean expressions.

Fig: Logic Diagram for BCD-to-excess-3 code converter

BINARY ADDER AND SUBTRACTOR:
A binary Adder and Subtractor is a combinational circuit that performs the
arithmetic operations of addition and subtraction with binary numbers
respectively..

Design of Half Adder: A combinational circuit that performs the addition of

two bits and generates SUM and Carry is called Half Adder.
Step 1: Decide the number of inputs and outputs:
It has two inputs, x and y, and two outputs, SUM(S) and Carry-out(C)

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Step 2: Create the truth table that defines the required relationship
between inputs and outputs.
Truth Table
Input Output

x y Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Step 3: Obtain the simplified Boolean functions for each output as a

function of the input variables.
The simplified Boolean functions for the two outputs can be obtained directly
from the truth table. The simplified sum-of-products expressions are
S = x’_y + x y’
C=x y
Step-4: Draw the Logic Diagram for the above Boolean expressions.
(a) Implementation of Half Adder using Basic gates

(b) Implementation of Half Adder using minimum number of gates

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Full Adder

A combinational circuit that performs the Arithmetic Sum of three bits and
generates Sum and Carry is called Full Adder. It performs the addition of three
bits (two significant bits and a previous carry).
Design of Full Adder:
Step 1: Decide the number of inputs and outputs
It has three Inputs and two outputs, Let the inputs be x,y,z and outputs be Sum(S) and
Carry(C)

Step 2: Create the truth table that defines the required relationship
between inputs and outputs.
Truth table:
Decimal Input Output
x y z Sum (S) Carry(C)
0 0 0 0 0 0
1 0 0 1 1 0
2 0 1 0 1 0
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 1
6 1 1 0 0 1
7 1 1 1 1 1

Step 3: Obtain the simplified Boolean functions for each output as a

function of the input variables. (from K map)

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Step-4: Draw the Logic Diagram for the above Boolean expressions.
Implementation of Sum and Carry of Full Adder using Basic Gates

Implementation of Full Adder using minimum number of gates. From the

truth table of Sum column, we can write

From truth table of Carry column

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Binary Adder:
A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adders connected in cascade,
with the carry output from each full adder connected to the carry input of the
next full adder in the chain. Addition of n-bit numbers requires a chain of n
Full Adders.
4-bit Binary Adder:
Let’s consider two 4-bit binary numbers A and B as inputs to the Digital
Circuit. Binary number A being A0 A1 A2 A3 and B being B0 B1 B2 B3.
The circuit consists of 4 full adders since we are performing operations on
4-bit numbers.

The carries are connected in a chain through the full adders. The input carry
to the adder is C0, and it ripples through the full adders to the output carry
C4. The Sum outputs generate the required sum bits S3,S2,S1,S0. An n -bit
adder requires n full adders, with each output carry connected to the input
carry of the next higher order full adder.

4 Bit Binary Subtractor:

The subtraction of unsigned binary numbers can be done most conveniently

by means of complements. Remember that the subtraction A - B can be done
by taking the 2’s complement of B and adding it to A . The 2’s complement
can be obtained by taking the 1’s complement and adding 1 to the least
significant pair of bits. The 1’s complement can be implemented with
inverters, and a 1 can be added to the sum through the input carry. Fig below
shows 4 bit subtractor.

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The circuit for subtracting A - B consists of an adder with inverters placed

between each data input B and the corresponding input of the full adder. The
input carry C0 must be equal to 1 when subtraction is performed. The
operation thus performed becomes A , plus the 1’s complement of B , plus 1.
This is equal to A plus the 2’s complement of B .

The addition and subtraction operations can be combined into one circuit
with one common binary adder by including an exclusive -OR gate with each
full adder. A four-bit adder–subtractor circuit is shown in above Fig.. The
mode input M controls the operation. W hen M = 0, the circuit is an adder,
and when M = 1, the circuit becomes a subtractor.

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DECODERS:
Discrete quantities of information are represented in digital systems by binary
codes. The name “Decoder” means to translate or decode the coded
information from one format into another.
A binary code of n bits is capable of representing up to 2 n distinct
elements of coded information. A decoder is a combinational circuit that
converts binary information from n input lines to a maximum of 2n unique
output lines. The decoders presented here are called n -to- m -line decoders,
where m <= 2n. Their purpose is to generate the 2n minterms from n input
variables. Each combination of inputs will assert a unique output.
2 to 4 Line Decoder:
It has Two inputs and Four outputs. Also an Enable input is considered. An
Enable Input is used to Enable or disable the Decoder. At any point of time
only one output is HIGH and remaining outputs are LOW.

Enable input(E)

From the truth table we can write the boolean function for each output

Fig: Logic Diagram

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3 to 8 Line Decoder:
It has three inputs and Eight outputs. Enable Input is used just to Enable or
disable the circuit. A decoder provides the 2n minterms for n input variables.
Each asserted output of the decoder is associated with a unique pattern of
input bits. Hence in 3 to 8 line decoder provides 8 minterms of input variables
and decoded into 8 bit binary form for each input combination. At any point
of time only one output is 1 and others outputs are 0.

From the truth table, we can write Boolean function for each output
variable in terms of input variable by observing each output column.

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Logic Diagram :

Implementation of higher order Decoders using Lower order Decoders.

Decoders with enable inputs can be connected together to form a larger
decoder circuit. Figure below shows two 3-to-8-line decoders with enable
inputs connected to form a 4-to-16-line decoder.

4-to-16-line decoder using two 3 to 8-line Decoder:

A 4 to 16 Line Decoder has Four inputs(w,x,y,z) and 16 outputs (D0 to D15)

Enable input is suitably used to obtain the required output function.
An inverter (NOT Gate ) is used between the Enable inputs of both 3 to 8 line
Decoder as shown below.

When w= 0, then E =1 for the top decoder and hence it is enabled and the
corresponding Enable input for the lower Decoder E=0 and hence it is
disabled. The bottom decoder outputs are all 0’s, and the top eight outputs
generate minterms 0000 to 0111(D0 to D7).

When w = 1, the enable conditions are reversed: The bottom decoder is

Enabled and outputs generate minterms 1000 to 1111(D8 to D15), while upper
Decoder is disabled, hence the outputs of the top decoder are all 0’s.
Thus both decoders together working as 4 to 16 decoder.

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Truth Table:

Inputs Outputs

E x y z D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Implementation of Boolean function using Decoder:

Decoder provides the 2n minterms for n input variables. Each asserted output
of the decoder is associated with a unique pattern of input bits. Since any
Boolean function can be expressed in sum-of-minterms form, a decoder can
be used for implementing any Boolean function.

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EX: Implementation of Full Adder using 3 to 8-line Decoder:

We know that Full Adder adds three binary bits and generates Sum and
Carry. Truth table of Full Adder is as shown.

From the truth table of the full adder (observe 1 in Sum and carry column),
we obtain the functions for the combinational circuit in sum-of-minterms
form:
Sum = S(x, y, z) = ∑m(1, 2, 4, 7)
Carry = C(x, y, z) = ∑m(3, 5, 6, 7)
Since there are three inputs and a total of eight minterms, we need a three-
to-eight-line decoder. The implementation is shown in Fig. The decoder
generates the eight minterms for x , y , and z . The OR gate for output S forms
the logical sum of minterms 1, 2, 4, and 7. The OR gate for output C forms
the logical sum of minte rms 3, 5, 6, and 7.

Fig .Implementation of a full adder with a decoder

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ENCODERS:
An Encoder is a digital circuit that performs the inverse operation of a
decoder. An encoder is a digital circuit that converts a set of binary inputs
into a unique binary code. It has maximum 2n input lines and n output lines.

Hence it Encodes the information from 2n inputs into an n-bit code. It will
produce a binary code equivalent to the input, which is active High.

Octal to Binary Encoder:

It has eight inputs (one for each of the octal digits) and three outputs that
generate the corresponding binary number. It is assumed that only one input .

The encoder can be implemented with OR gates whose inputs are determined.

directly from the truth table. Output z is equal to 1 when the input octal digit is 1,
3, 5, 7. Output y is 1 for octal digits 2, 3, 6, 7, and output x is 1 for digits 4, 5, 6, 7.
These conditions can be expressed by the following Boolean output functions:

The above equations can be implemented by using three OR gates.

Note: Draw the Logic diagram for the above Boolean equations to obtain

octal to binary Encoder.

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Priority Encoder:

Why Priority Encoder?

In case of an ordinary encoder, one and only one input can be activated at
any given time. But in the case of some practical digital systems, two or more
decimal inputs can unintentionally become active at the same ti me that might
cause a confusion to generate the encoded output. In such cases, the primary
function of the encoder is to select the input with the highest priority and this
is done using Priority Encoder.

A priority encoder is an encoder circuit that includes the priority function.

The operation of the priority encoder is such that if two or more inputs are
equal to 1 at the same time, the input having the highest priority will take
precedence. The truth table of a four-input priority encoder is given in Table .

In addition to the two outputs x and y, the circuit has a third output
designated by V; this is a valid bit indicator that is set to 1 when one or more
inputs are equal to 1. If all inputs are 0, there is no valid input and V is equal
to 0

Note that X ’s in output columns represent don’t-care conditions, the X ’s in

the input columns are useful for representing a truth table i n condensed form.
Instead of listing all 16 minterms of four variables, the truth table uses an X
to represent either 1 or 0. For example, X 100 represents the two minterms
0100 and 1100. and so on.

Truth Table:

INPUTS OUTPUTS

D3 D2 D1 D0 x y v
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1

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To obtain the Boolean expressions for each output variable, we need to check
for all 16 combinations and the corresponding minterms need to be entered
in K map.

Note: Refer the class Notes for K- Map

The simplified Boolean expressions for the priority encoder are obtained from
the K maps. The priority encoder is implemented according to the following
Boolean functions:

x = D 2 + D3

y = D3 + D1 D’2

V = D 0 + D 1 + D 2 + D3

Fig: Four Input Priority Encoder

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Multiplexers:
A Multiplexer is a data selector. A multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a
single output line. The selection of a particular input line is controlled by a
set of selection lines. Normally, there are 2 n input lines and n selection lines.
The bit combinations of select lines determine which input is to be selected.

2 to 1-line Multiplexer (2:1 MUX):

It has two inputs and only one output and one select line.
When S=0, Multiplexer selects data available at I 0 input
When S=1, Multiplexer selects data available at I 1 input
Block diagram Truth table

Logic Diagram :

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4 to 1-line Multiplexer (4:1 Multiplexer)

4x1 Multiplexer has four data inputs I 3, I2, I1 & I0, two selection lines S1 & S0
and one output line Y. The block diagram of 4x1 Multiplexer is shown in the
following figure.
Truth table

From the above truth ,if select lines value S 1S0 = 00, Input I0 is selected and
the data available at Io is routed to output Y, Therefore, we have Y=I0 when
S1S0 = 00
Similarly, if select lines value S 1S0 = 01, Input I1 is selected and it routed to
output, Therefore, we have Y=I1 when S1S0= 01

Similarly, if select lines value S 1S0= 10, Input I2 is selected and it is routed to
output, Therefore, we have Y=I2 when S1S0 = 10

Similarly, if select lines value S 1S0 = 11, Input I3 is selected and it routed to
output, Therefore, we have Y=I3 when S1S0= 11

From truth we get the logical expression for output Y in the SOP
form will be as under

Y= S’0 S’1 I0 + S’0 S1 I1 + S0 S’1 I2 +S0 S1 I3

Fig.Logic diagram

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8:1 Multiplexer

8 X 1 Multiplexer has 8 data inputs D0, D1, D2, D3, D4, D5, D6 & D7, with
3 select lines S0, S1, & S2 and one output line Y. One of these data inputs
will be connected to the output Y based on the values of selection lines.

Truth table

Select input lines Output

S2 S1 S0 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

From the truth table, We can write the Boolean expression representing the
output Y. In the logic circuit diagram shown below, 8-to-1 multiplexer can be
implemented by using 8 AND gates, 1 OR gate and 3 NOT gates. The output
gets connected to only one of the n data inputs at a gi ven instant of time. The
output is selected based on the truth table of this integrated circuit.

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8:1 Multiplexer Logic diagram :

Implementation of Boolean Function using Multiplexer:

The minterms of a function are generated in a multiplexer by the circuit
associated with the selection inputs. The individual minterms can be selected
by the data inputs, thereby providing a method of implementing a Boolean
function of n variables with a multiplexer that has n selection inputs and 2n
data inputs, one for each minterm.

Procedure:

1. To begin with, Boolean function is listed in a truth table.

2. Then first n - 1 variables in the table are applied to the sele ction inputs
of the multiplexer, where n = number of input variables.
3. For each combination of the selection variables, we evaluate the output
as a function of the last variable. This function can be 0, 1, any variable,
or its complement. These values are then applied to the data inputs in
the proper order.

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EX:1 To demonstrate this procedure, consider the Boolean function

F (x, y, z) = ∑m(1, 2, 6, 7) Refer the class notes
This function of three variables can be implemented with a four -to-one-line
multiplexer as shown in Fig.below. The two variables x and y are applied to
the selection lines in that order; x is connected to the S1 input and y to the
S0 input.
The values for the data input lines are determined from the truth table of the
function. When xy = 00, output F is equal to z because F = 0 whe n z = 0 and
F = 1 when z = 1. This requires that variable z be applied to data input 0. The
operation of the multiplexer is such that when xy = 00, data input 0 has a
path to the output, and that makes F equal to z .
In a similar fashion, we can determine the required input to data lines 1, 2,
and 3 from the value of F when xy = 01, 10, and 11, respectively. This
particular example shows all four possibilities that can be obtained for the
data inputs.

EX:2 Consider the implementation of the Boolean function

F (A, B, C, D) = ∑m(1, 3, 4, 11, 12, 13, 14, 15) Refer the Class notes
Solution: This function is implemented with a multiplexer with three
selection inputs as shown in Fig.below. Note that the first variable A must be
connected to selection input S2 so that A , B, and C correspond to selection
inputs S2, S1, and S0, respectively. The values for the data inputs are
determined from the truth table listed in the figure. The corresponding data
line number is determined from the binary combination of ABC.

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EX 3: Implementation of Full Adder using Multiplexer

Solution: (For detailed solution refer class notes)
Multiplexer and Full Adder are two different Digital Logic circuits. The
Multiplexer is a data selector, It allows digital information from several
sources to be routed onto a single output line. On the other hand, the Full
adder circuit performs the addition of three bits and produces the Sum and
Carry as an output. Our aim is to build the Full Adder circuit using
Multiplexers rather than the usual basic logic gates.

EX4: Implement the following Boolean function with a multiplexer

F (A, B, C, D) = ∑m (0, 2, 5, 8, 10, 14)
Solution: (refer class notes)

EX:5: Construct a 16: 1 multiplexer with two 8 : 1 and one 2 : 1 multiplexers

Solution: (refer class notes)

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Three State Gates:

A multiplexer can be constructed with three -state gates—digital circuits that

exhibit three states. The first two of the states are signals equivalent to logic
1 and logic 0 as in a conventional gate. The third state is a high-impedance
state in which it behaves like an open circuit. This means that the output
appears to be disconnected and the circuit has no logic significance.
The graphic symbol for a three-state buffer gate is shown in Fig.
When the control input is equal to 1, the output is enabled and the gate behaves like
a conventional buffer, with the output equal to the normal input.
 When the control input is 0, the output is disabled and the gate goes to a high-
impedance state, regardless of the value in the normal input.

Fig(a) .Graphic symbol for a three -state buffer

4:1 Multiplexer using three state buffer
The construction of a four-to-one-line multiplexer is shown in Fig. The
outputs of 4 three-state buffers are connected together to form a single output
line. The control inputs to the buffers determine which one of the four normal
inputs I0 through I3 will be connected to the output line. No more than one
buffer may be in the active state at any given time. The connected buffers
must be controlled so that only 1 three state buffer has access to the output
while all other buffers are maintained in a high impedance state.
Truth table of 4:1 Multiplexer and Logic diagram using three state gates

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Part (b) Sequential circuits

A sequential circuit is a logical circuit, where the output depends on the
present value of the input signal as well as the sequence of past inputs .

A block diagram of a sequential circuit is shown in F ig. It consists of a

combinational circuit to which storage elements are connected to form a
feedback path. The storage elements are devices capable of storing binary
information. The binary information stored in these elements at any given
time defines the state of the sequential circuit at that time.

STORAGE ELEMENTS:
LATCHES and FLIP FLOPS:
A storage element in a digital circuit can maintain a binary state indefinitely
until directed by an input signal to switch states.

Storage elements that operate with signal levels are referred to as latches and
if storage elements controlled by a clock transition are referred as flip-flops.
Latches are said to be level sensitive devices; on the other hand, flip-flops are
edge-sensitive devices. Each Latch or a flip flop can store one bit of binary
information.

S R Latch:(Set-Reset) Latches:

The SR latch has two stable states and can store a single bit of information;
the two stable states are known as Set(S) and Reset(R), hence the name SR.
The latch also provides two outputs, namely Q and Q-bar (the inverse of Q).

The S input sets the output to 1, while the R input resets the output to 0.
When both S and R are at 1, the latch is said to be in an “undefined” state.

DEPARTMENT OF CSE (AI & ML), SAI VIDYA INSTITUTE OF TECHNOLOGY.

Dr.T G Manjunath, Professor and HOD, Department of CSE(AI & ML),SVIT

The SR latch with two cross-coupled NAND gates is shown in Fig.

Case(1):When inputs S=0,R=0

The NAND gates provide an output of 1 whenever one of the input of NAND
gate is 0. In the case of S = 0 and R = 0, the output of both NAND gates goes
to 1 then Q and Q’ both comes 1 violating the basic definition of Latch. Hence
it is said tobe invalid state.

Case(2):When inputs S=0,R=1

When S=0, the upper NAND gate provides an output of 1, so output Q=1(SET
State) and Q’=0 .

Case(3):When inputs S=1,R=0

When R=0, the lower NAND gate provides an output of 1, so output Q’=1 but
Q=0(RE SET State)

Case(4):When inputs S=1,R=1

When S=1, R=1, both NAND gate output depends on previous state of the
output. ie Present state is same as previous state (no change in the output
state)

SR Latch with control input:

The operation of the basic SR latch can be modified by providing an additional

input signal that determines (controls) when the state of the latch can be
changed by determining whether S and R can affect the circuit. An SR latch
with a control input is shown in Fig.below.

DEPARTMENT OF CSE (AI & ML), SAI VIDYA INSTITUTE OF TECHNOLOGY.

Dr.T G Manjunath, Professor and HOD, Department of CSE(AI & ML),SVIT

It consists of the basic SR latch and two additional NAND gates. The control
input En acts as an enable signal for the other two inputs. The outputs of
the NAND gates stay at the logic-1 level as long as the enable signal
remains at 0.

This is the quiescent condition for the SR latch. When the enable input goes
to 1, information from the S or R input is allowed to affect the latch. The set
state is reached with S = 1, R = 0, and En = 1.To change to the reset state,
the inputs must be S = 0, R = 1, and En = 1.

In either case, when En returns to 0, the circuit remains in its current state.
The control input disables the circuit by applying 0 to En, so that the state of
the output does not change regardless of the values of S and R . Moreover,
when En = 1 and both the S and R inputs are equal to 0, the state of the
circuit does not change. These conditions are listed in the function table
accompanying the diagram.

An indeterminate condition occurs when all three inputs are equal to 1. This
condition places 0’s on both inputs of the basic SR latch, which puts it in the
undefined state. When the enable input goes back to 0, one cannot
conclusively determine the next state, because it depends on whether the S
or R input goes to 0 first. This indeterminate condition makes this circuit
difficult to manage .

DEPARTMENT OF CSE (AI & ML), SAI VIDYA INSTITUTE OF TECHNOLOGY.

Dr.T G Manjunath, Professor and HOD, Department of CSE(AI & ML),SVIT

D Latch (Transparent Latch):

One way to eliminate the undesirable condition of the indeterminate state in

the SR latch is to ensure that inputs S and R are never equal to 1 at the same
time. This is done in the D latch, shown in Fig. This latch has only two inputs:
D (data) and En (enable).

The D input goes directly to the S input, and its complement is applied to the
R input. As long as the enable input is at 0, the cross-coupled SR latch has
both inputs at the 1 level and the circuit cannot change state regardless of
the value of D .

The D input is sampled when En = 1. If D = 1, the Q output goes to 1, placing

the circuit in the set state. If D = 0, output Q goes to 0, placing the circ uit in
the reset state. Output depends on D input. Hence the named Data Latch.

FLIP-FLOPS:

Edge-Triggered Flip Flops

Edge triggered flip flop operates only on the rising or falling edge of the clock
pulse. There are two types

1.Positive Edge-Triggered Flip-Flop and 2. Negative Edge-Triggered Flip-Flop

Positive Edge-Triggered Flip-Flop

The type of edge-triggered flip-flop whose output changes its state only on the
rising edge (edge that goes from low to high) of the clock pulse is called a
positive edge-triggered flip-flop. The positive edge triggered flip flop is also
called a rising edge-triggered flip-flop.

DEPARTMENT OF CSE (AI & ML), SAI VIDYA INSTITUTE OF TECHNOLOGY.

Dr.T G Manjunath, Professor and HOD, Department of CSE(AI & ML),SVIT

Negative Edge-Triggered Flip-Flop

The type of edge-triggered flip flop whose output changes its state only on the
falling edge (edge that goes from high to low) of the clock pulse is called a
negative edge-triggered flip-flop. The negative edge triggered flip flop is also
known as a falling edge -triggered flip-flop.

Master Slave D Flip Flop:

The construction of a D flip-flop with two D latches and an inverter is shown

in Fig. The first latch is called the master and the second the slave. The circuit
samples the D input and changes its output Q only at the negative edge of the
clock (designated as Clk ).

When the clock is 0, the output of the inverter is 1. The slave latch is enabled,
and its output Q is equal to the master output Y . The master latch is disabled
because Clk = 0.

When the input pulse changes to the logic-1 level, the data from the external
D input are transferred to the master. The slave, however, is disabled as long
as the clock remains at the 1 level, because its enable input is equal to 0.

Any change in the input changes the master output at Y, but cannot affect
the slave output. When the clock pulse returns to 0, the master is disabled
and is isolated from the D input. At the same time, the slave is enabled and
the value of Y is transferred to the output of the flip-flop at Q . Thus, a change
in the output of the flip-flop can be triggered only by and during the transition
of the clock from 1 to 0.

DEPARTMENT OF CSE (AI & ML), SAI VIDYA INSTITUTE OF TECHNOLOGY.