What is Combinational Circuit?

A combinational circuit is a kind of digital electronic circuit of which outputs depend on the
present inputs and have no connections to the past inputs. These circuits do such tasks as
additions, subtractions and logically AND, OR and NOR circuits. The key characteristics of
combinational circuits include:
 No Memory Elements: The output is dependent solely on the current policy inputs.
 Immediate Response: Good input differs from its output and bad input differs from its
output.
 Examples: The most commonly encountered examples are adders, multiplexers and
encoders.

Combinational Circuit
Advantages of Combinational Circuits
 Simplicity: It is easier to design and implement more so because it lacks memory
elements mainly.
 Speed: Operational at a faster rate as the output automatically adjusts with the
changes in inputs.
 Resource Efficiency: Generally it needs far fewer components as compared to its
equivalent sequential circuits.
Disadvantages of Combinational Circuits
 Limited Functionality: Is not able to perform operations that need historical
information or sequence details.
 Complexity with Increased Inputs: It becomes difficult to design combinational
circuits when there are many inputs.

BCD Adder in Digital Logic

BCD stands for binary coded decimal. It is used to perform the addition of BCD numbers. A
BCD digit can have any of ten possible four-bit representations. Suppose, we have two 4-bit
numbers A and B. The value of A and B can vary from 0(0000 in binary) to 9(1001 in binary)
because we are considering decimal numbers.

The output will vary from 0 to 18 if we are not considering the carry from the previous sum.
But if we are considering the carry, then the maximum value of output will be 19 (i.e. 9+9+1
= 19). When we are simply adding A and B, then we get the binary sum. Here, to get the
output in BCD form, we will use BCD Adder.
What is BCD Adder?
A BCD adder is a circuit for the addition of two binary-coded decimal numbers. BCD is
another format used in representing numbers where each digit will be represented using a 4-
bit binary code. In BCD, it is obvious that the most significant bit (leftmost) is always 0, and
therefore each digit will be confined to the range 0-9.
A BCD adder contains four full-adder circuits in cascade. Each full-adder is contrived to
consider both the two BCD digits being added and a carry-in from the previous stage. The
output of each full-adder produces a sum bit and a carry-out bit, which becomes the input to
the following stage.
When adding BCD numbers, if the sum of two BCD digits is greater than 9, the result is
greater than 1001 in binary and hence is not valid in BCD. A correction needs to be
performed by adding 0110 (6 in BCD) to the sum to get the correct BCD result.
A BCD adder is, overall, a design capable of correctly adding two BCD numbers and making
all necessary corrections so that the answer is also a valid BCD number.
Steps to Design a BCD Adder
 Find Number of Digits : Find out how many Extended digits of BCD the adder should
support. A BCD digit requires 4 bits.
  Adder Structure : The full adder connected in series could be selected as the general
adder structure. Any extra full-adder shall be incremented by one BCD digit addition
plus a carry from the previous stage.
 Full-Adder Circuit Implementation : Implement a full-adder circuit capable of adding
two 4-bit BCD digits with a carry-in. The full adder shall output a sum bit and a carry-
out bit
 Interconnect the Full-Adders : Now, full-adders are connected in series with each
other; at this point, carry-out from each stage will be given to carry-in of the next
higher order stage.
 Provide BCD Correction : The logic is implemented detecting whether the sum of two
BCD digits is greater than 9. In the case of such, 0110 is added to the sum, and carry
propagates to the next higher order stage.
 Test the BCD Adder : The BCD adder functionality needs to be checked with the
application of different BCD numbers to its input for the correctness of addition and
correction handling.
Example 1:
Input :
A = 0111
B = 1000
Output :
Y = 1 0101
Explanation: We are adding A(=7) and B(=8).
The value of binary sum will be 1111(=15).
But, the BCD sum will be 1 0101,
where 1 is 0001 in binary and 5 is 0101 in binary.
Example 2:
Input :
A = 0101 B = 1001
Output :
Y = 1 0100
Explanation: We are adding A(=5) and B(=9).
The value of binary sum will be 1110(=14).
But, the BCD sum will be 1 0100,
where 1 is 0001 in binary and 4 is 0100 in binary.
Note: If the sum of two numbers is less than or equal to 9, then the value of BCD sum and
binary sum will be same otherwise they will differ by 6(0110 in binary). Now, lets move to the
table and find out the logic when we are going to add “0110”.
We are adding “0110” (=6) only to the second half of the table. The conditions are:
1. If C’ = 1 (Satisfies 16-19)
2. If S3′.S2′ = 1 (Satisfies 12-15)
3. If S3′.S1′ = 1 (Satisfies 10 and 11)
So, our logic is
C’ + S3′.S2′ + S3′.S1′ = 1
Advantages of BCD Adder
There are various reasons why a BCD adder is beneficial in digital logic.
 Decimal Precision : BCD adders guarantee that when adding decimal numbers, they
do not make mistakes since the process is conducted on digits that are Binary-Coded
Decimal direct (0-9) this rules out any error related to switching from base 10 to base
2 or vice versa.
 Simplified Decimal Arithmetic : When it comes to decimal arithmetic operations,
BCD adders offer computerized systems with an easier way out making them fit for
fields where calculations are predominantly in decimals such as, anywhere money is
involved – shopping stores or market areas; calculators; and even real-time clocks.
 Common Display Compatibility : The common display technologies such as 7-
segment displays are directly compatible with BCD numbers thus making BCD
adders suitable for applications where output should be displayed directly in decimal
format.
 Mistake Recognition : Just a simple addition is all that is required by such devices so
as to find out the parity of invalid BCDs (for instance those larger than digit 9),
making it easier for FEC systems. In this manner it forms part of an error detection
system and correction scheme that ensure precision results.
 High-Efficiency Circuit Design : BCD adders facilitate the creation of efficient,
optimized circuits specifically designed for decimal arithmetic, which results in
speedier processing times and less complicated digital circuits.
These benefits show how critical BCD adders are in processing decimal arithmetic using
digital logic well and correctly.
Disadvantages of BCD Adder
 Memory Misallocation : In comparison to binary digits, the BCD figures take up more
memory to portray comparable values, hence generating greater memory use within
BCD operational systems.
 Restricted Set of Values : BCD adders are constrained to only decimal digits (0-9)
hence cannot carry out direct arithmetic on values that are beyond this range without
extra conversion circuitry thus restricting their versatility in some applications.
 Lower Speed of Arithmetic Operations : Since they require BCD correction and
manage decimal numbers, BCD adders may have lower operational speeds than
binary ones affecting the overall performance of digital systems.
 Compatibility concerns : BCD arithmetic could be at odds with some techniques or
algorithms especially those that are improved to perform better in binary arithmetic;
hence you get such compatibility problems when using both types of arithmetics
within a system.
 High Circuit Complexity : BCD adders are more complicated than binary adders
owing to BCD correction logic requirements that make sure valid BCD outputs are
produced. This increased complexity can also lead to bigger circuit sizes as well as
more difficult designs.
Conclusion
To sum up, an accurate BCD adder circuit design in digital logic contains the assemblage of
full adders that connect to multiple BCD digits for addition process, the addition and testing
of such a circuit for BCD correction logic implementation will guarantee the correct
functioning of this BCD adder. This design is important as it allows an efficient addition of
binary-coded decimal numbers in computer systems.
Half Adder in Digital Logic

A half adder is a digital logic circuit that performs binary addition of two single-bit binary
numbers. It has two inputs, A and B, and two outputs, SUM and CARRY. The SUM output is
the least significant bit (LSB) of the result, while the CARRY output is the most significant
bit (MSB) of the result, indicating whether there was a carry-over from the addition of the
two inputs. The half adder can be implemented using basic gates such as XOR and AND
gates.
What is Half Adder?
The half adder is a basic building block for more complex adder circuits such as full adders
and multiple-bit adders. It performs binary addition of two single-bit inputs, A and B, and
provides two outputs, SUM and CARRY.
The SUM output is the least significant bit (LSB) of the result, which is the XOR of the two
inputs A and B. The XOR gate implements the addition operation for binary digits, where a
“1” is generated in the SUM output only when one of the inputs is “1”.
The CARRY output is the most significant bit (MSB) of the result, indicating whether there
was a carry-over from the addition of the two inputs. The CARRY output is the AND of the
two inputs A and B. The AND gate generates a “1” in the CARRY output only when both
inputs are “1”.
Half adder is the simplest of all adder circuits. Half adder is a combinational arithmetic
circuit that adds two numbers and produces a sum bit (s) and carry bit (c) both as output. The
addition of 2 bits is done using a combination circuit called a Half adder. The input variables
are augend and addend bits and output variables are sum & carry bits. A and B are the two
input bits.
let us consider two input bits A and B, then sum bit (s) is the X-OR of A and B. it is evident
from the function of a half adder that it requires one X-OR gate and one AND gate for its
construction.
Truth Table
Here we perform two operations Sum and Carry, thus we need two K-maps one for each to
derive the expression.
Logical Expression
For Sum

Sum = A XOR B
For Carry

Carry = A AND B
Implementation

Note: Half adder has only two inputs and there is no provision to add a carry coming from the
lower order bits when multi addition is performed.
Advantages of Half Adder in Digital Logic
  Simplicity: A half adder is a straightforward circuit that requires a couple of
fundamental parts like XOR AND entryways. It is not difficult to carry out and can be
utilized in numerous advanced frameworks.
 Speed: The half adder works at an extremely rapid, making it reasonable for use in
fast computerized circuits.
Disadvantages of Half Adder in Digital Logic
 Limited Usefulness: The half adder can add two single-piece numbers and produce a
total and a convey bit. It can’t perform expansion of multi-bit numbers, which
requires the utilization of additional intricate circuits like full adders.
 Lack of Convey Info: The half adder doesn’t have a convey input, which restricts its
value in more mind boggling expansion tasks. A convey input is important to perform
expansion of multi-bit numbers and to chain numerous adders together.
 Propagation Deferral: The half adder circuit has a proliferation delay, which is the
time it takes for the result to change in light of an adjustment of the info. This can
cause timing issues in computerized circuits, particularly in fast frameworks.
 Application of Half Adder in Digital Logic
 Arithmetic circuits: Half adders are utilized in number-crunching circuits to add
double numbers. At the point when different half adders are associated in a chain, they
can add multi-bit double numbers.
 Data handling: Half adders are utilized in information handling applications like
computerized signal handling, information encryption, and blunder adjustment.
 Address unraveling: In memory tending to, half adders are utilized in address
deciphering circuits to produce the location of a particular memory area.
 Encoder and decoder circuits: Half adders are utilized in encoder and decoder circuits
for computerized correspondence frameworks.
 Multiplexers and demultiplexers: Half adders are utilized
in multiplexers and demultiplexers to choose and course information.
 Counters: Half adders are utilized in counters to augment the count by one.

Full Adder in Digital Logic

Full Adder is the adder that adds three inputs and produces two outputs. The first two
inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM. The C-
OUT is also known as the majority 1’s detector, whose output goes high when more
than one input is high. A full adder logic is designed in such a manner that can take
eight inputs together to create a byte-wide adder and cascade the carry bit from one
adder to another. we use a full adder because when a carry-in bit is available, another
1-bit adder must be used since a 1-bit half-adder does not take a carry-in bit. A 1-bit
full adder adds three operands and generates 2-bit results.

Full Adder Truth Table:

Logical Expression for SUM: = A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN =

C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’) = C-IN XOR (A XOR B) = (1,2,4,7)
Logical Expression for C-OUT: = A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN =
A B + B C-IN + A C-IN = (3,5,6,7)
Another form in which C-OUT can be implemented: = A B + A C-IN + B C-IN (A +
A’) = A B C-IN + A B + A C-IN + A’ B C-IN = A B (1 +C-IN) + A C-IN + A’ B C-IN
= A B + A C-IN + A’ B C-IN = A B + A C-IN (B + B’) + A’ B C-IN = A B C-IN + A B
+ A B’ C-IN + A’ B C-IN = A B (C-IN + 1) + A B’ C-IN + A’ B C-IN = A B + A B’ C-
IN + A’ B C-IN = AB + C-IN (A’ B + A B’)
Therefore COUT = AB + C-IN (A EX – OR B)
Full Adder logic circuit.
Implementation of Full Adder using Half Adders:
2 Half Adders and an OR gate is required to implement a Full Adder.

With this logic circuit, two bits can be added together, taking a carry from the next
lower order of magnitude, and sending a carry to the next higher order of magnitude.
Implementation of Full Adder using NAND gates:

Implementation of Full Adder using NOR gates:

Total 9 NOR gates are required to implement a Full Adder.
Total 9 NOR gates are required to implement a Full Adder.

In the logic expression above, one would recognize the logic expressions of a 1-bit
half-adder. A 1-bit full adder can be accomplished by cascading two 1-bit half adders.
Advantages and Disadvantages of Full Adder in Digital Logic
Advantages of Full Adder in Digital Logic:
1.Flexibility: A full snake can add three information bits, making it more flexible than
a half viper. It can likewise be utilized to add multi-bit numbers by binding different
full adders together.
2.Carry Info: The full viper has a convey input, which permits it to perform expansion
of multi-bit numbers and to chain different adders together.
3.Speed: The full snake works at an extremely fast, making it reasonable for use in
rapid computerized circuits.
Disadvantages of Full Adder in Digital Logic:
1.Complexity: The full snake is more mind boggling than a half viper and requires
more parts like XOR, AND, or potentially entryways. It is likewise more challenging
to execute and plan.
2.Propagation Deferral: The full viper circuit has a proliferation delay, which is the
time it takes for the result to change in light of an adjustment of the info. This can
cause timing issues in computerized circuits, particularly in fast frameworks.
Application of Full Adder in Digital Logic:
1.Arithmetic circuits: Full adders are utilized in math circuits to add twofold numbers.
At the point when different full adders are associated in a chain, they can add multi-
bit paired numbers.
2.Data handling: Full adders are utilized in information handling applications like
advanced signal handling, information encryption, and mistake rectification.
3.Counters: Full adders are utilized in counters to addition or decrement the count by
one.
4.Multiplexers and demultiplexers: Full adders are utilized in multiplexers and
demultiplexers to choose and course information.
5.Memory tending to: Full adders are utilized in memory addressing circuits to
produce the location of a particular memory area.
6.ALUs: Full adders are a fundamental part of Number juggling Rationale Units
(ALUs) utilized in chip and computerized signal processors.
Multiplexer
A multiplexer is a combinational circuit that has 2 n input lines and a single output line.
Simply, the multiplexer is a multi-input and single-output combinational circuit. The binary
information is received from the input lines and directed to the output line. On the basis of the
values of the selection lines, one of these data inputs will be connected to the output.
Unlike encoder and decoder, there are n selection lines and 2 n input lines. So, there is a total
of 2N possible combinations of inputs. A multiplexer is also treated as Mux.
There are various types of the multiplexer which are as follows:
2×1 Multiplexer:
In 2×1 multiplexer, there are only two inputs, i.e., A 0 and A1, 1 selection line, i.e., S 0 and
single outputs, i.e., Y. On the basis of the combination of inputs which are present at the
selection line S0, one of these 2 inputs will be connected to the output. The block diagram and
the truth table of the 2×1 multiplexer are given below.
Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1
Logical circuit of the above expression is given below:
4×1 Multiplexer:
In the 4×1 multiplexer, there is a total of four inputs, i.e., A 0, A1, A2, and A3, 2 selection lines,
i.e., S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are
present at the selection lines S 0 and S1, one of these 4 inputs are connected to the output. The
block diagram and the truth table of the 4×1 multiplexer are given below.
Block Diagram:

Truth Table:
The logical expression of the term Y is as follows:
Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3
Logical circuit of the above expression is given below:

8 to 1 Multiplexer
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A 0, A1, A2, A3, A4, A5, A6, and A7, 3
selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination of
inputs that are present at the selection lines S 0, S1, and S2, one of these 8 inputs are connected
to the output. The block diagram and the truth table of the 8×1 multiplexer are given below.
Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6
+S0.S1.S3.A7
Logical circuit of the above expression is given below:

8 ×1 multiplexer using 4×1 and 2×1 multiplexer

We can implement the 8×1 multiplexer using a lower order multiplexer. To implement the
8×1 multiplexer, we need two 4×1 multiplexers and one 2×1 multiplexer. The 4×1
multiplexer has 2 selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1
selection line.
For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1 multiplexer produces one
output. So, in order to get the final output, we need a 2×1 multiplexer. The block diagram of
8×1 multiplexer using 4×1 and 2×1 multiplexer is given below.
16 to 1 Multiplexer
In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A 0, A1, …, A16, 4 selection lines,
i.e., S0, S1, S2, and S3 and single output, i.e., Y. On the basis of the combination of inputs that
are present at the selection lines S 0, S1, and S2, one of these 16 inputs will be connected to the
output. The block diagram and the truth table of the 16×1
Block Diagram:
Truth Table:
The logical expression of the term Y is as follows:
Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3+A4.S0'.S1.S2'.S3'+A5.S0 '.
S1.S2'.S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+Y10.S0.S1'.S2.S3 '+A11.
S0.S1'.S2.S3+A12 S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3
Logical circuit of the above expression is given below:
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16×1 multiplexer using 8×1 and 2×1 multiplexer
We can implement the 16×1 multiplexer using a lower order multiplexer. To implement the
8×1 multiplexer, we need two 8×1 multiplexers and one 2×1 multiplexer. The 8×1
multiplexer has 3 selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1
selection line.
For getting 16 data inputs, we need two 8 ×1 multiplexers. The 8×1 multiplexer produces one
output. So, in order to get the final output, we need a 2×1 multiplexer. The block diagram of
16×1 multiplexer using 8×1 and 2×1 multiplexer is given below.
De-multiplexer
A De-multiplexer is a combinational circuit that has only 1 input line and 2 N output lines.
Simply, the multiplexer is a single-input and multi-output combinational circuit. The
information is received from the single input lines and directed to the output line. On the
basis of the values of the selection lines, the input will be connected to one of these outputs.
De-multiplexer is opposite to the multiplexer.
Unlike encoder and decoder, there are n selection lines and 2 n outputs. So, there is a total of
2n possible combinations of inputs. De-multiplexer is also treated as De-mux.
There are various types of De-multiplexer which are as follows:
1×2 De-multiplexer:
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y 0, and Y1, 1 selection lines, i.e.,
S0, and single input, i.e., A. On the basis of the selection value, the input will be connected to
one of the outputs. The block diagram and the truth table of the 1×2 multiplexer are given
below.
Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A
Logical circuit of the above expressions is given below:

1×4 De-multiplexer:
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2 selection
lines, i.e., S0 and S1 and single input, i.e., A. On the basis of the combination of inputs which
are present at the selection lines S 0 and S1, the input be connected to one of the outputs. The
block diagram and the truth table of the 1×4 multiplexer are given below.
Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y0=S1'S0'A
y1=S1'S0 A
y2=S1 S0'A
y3=S1 S0 A
Logical circuit of the above expressions is given below:
1×8 De-multiplexer
In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and
Y7, 3 selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the
combination of inputs which are present at the selection lines S 0, S1 and S2, the input will be
connected to one of these outputs. The block diagram and the truth table of the 1×8 de-
multiplexer are given below.
Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A
Logical circuit of the above expressions is given below:

1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer

We can implement the 1×8 de-multiplexer using a lower order de-multiplexer. To implement
the 1×8 de-multiplexer, we need two 1×4 de-multiplexer and one 1×2 de-multiplexer. The
1×4 multiplexer has 2 selection lines, 4 outputs, and 1 input. The 1×2 de-multiplexer has only
1 selection line.
For getting 8 data outputs, we need two 1×4 de-multiplexer. The 1×2 de-multiplexer produces
two outputs. So, in order to get the final output, we have to pass the outputs of 1×2 de-
multiplexer as an input of both the 1×4 de-multiplexer. The block diagram of 1×8 de-
multiplexer using 1×4 and 1×2 de-multiplexer is given below.
1 x 16 De-multiplexer
In 1×16 de-multiplexer, there are total of 16 outputs, i.e., Y 0, Y1, …, Y16, 4 selection lines,
i.e., S0, S1, S2, and S3 and single input, i.e., A. On the basis of the combination of inputs which
are present at the selection lines S 0, S1, and S2, the input will be connected to one of these
outputs. The block diagram and the truth table of the 1×16 de-multiplexer are given below.
Block Diagram:
Truth Table:
The logical expression of the term Y is as follows:
Y0=A.S0'.S1'.S2'.S3'
Y1=A.S0'.S1'.S2'.S3
Y2=A.S0'.S1'.S2.S3'
Y3=A.S0'.S1'.S2.S3
Y4=A.S0'.S1.S2'.S3'
Y5=A.S0'.S1.S2'.S3
Y6=A.S0'.S1.S2.S3'
Y7=A.S0'.S1.S2.S3
Y8=A.S0.S1'.S2'.S3'
Y9=A.S0.S1'.S2'.S3
Y10=A.S0.S1'.S2.S3'
Y11=A.S0.S1'.S2.S3
Y12=A.S0.S1.S2'.S3'
Y13=A.S0.S1.S2'.S3
Y14=A.S0.S1.S2.S3'
Y15=A.S0.S1.S2'.S3
Logical circuit of the above expressions is given below:

1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer

We can implement the 1×16 de-multiplexer using a lower order de-multiplexer. To implement
the 1×16 de-multiplexer, we need two 1×8 de-multiplexer and one 1×2 de-multiplexer. The
1×8 multiplexer has 3 selection lines, 1 input, and 8 outputs. The 1×2 de-multiplexer has only
1 selection line.
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For getting 16 data outputs, we need two 1×8 de-multiplexer. The 1×8 de-multiplexer
produces eight outputs. So, in order to get the final output, we need a 1×2 de-multiplexer to
produce two outputs from a single input. Then we pass these outputs into both the de-
multiplexer as an input. The block diagram of 1×16 de-multiplexer using 1×8 and 1×2 de-
multiplexer is given below.
Magnitude Comparator in Digital Logic
A magnitude digital Comparator is a combinational circuit that compares two digital or
binary numbers in order to find out whether one binary number is equal, less than, or greater
than the other binary number. We logically design a circuit for which we will have two inputs
one for A and the other for B and have three output terminals, one for A > B condition, one
for A = B condition, and one for A < B condition.
What is Magnitude Comparator?
Magnitude comparator is a type of Combinational circuit, It Basically compares two binary
numbers and determines their relative magnitude. It gives output whether one number is
greater than the other, or less than or equal. These comparators are used in digital systems,
such as for sorting networks, and decision-making circuits to handle numerical comparisons
perfectly without any error.

N – bit Comparator
The circuit works by comparing the bits of the two numbers starting from the most significant
bit (MSB) and moving toward the least significant bit (LSB). At each bit position, the two
corresponding bits of the numbers are compared. If the bit in the first number is greater than
the corresponding bit in the second number, the A>B output is set to 1,and the circuit
immediately determines that the first number is greater than the second. Similarly, if the bit in
the second number is greater than the corresponding bit in the first number, the A<B output is
set to 1, and the circuit immediately determines that the first number is less than the second.
If the two corresponding bits are equal, the circuit moves to the next bit position and
compares the next pair of bits. This process continues until all the bits have been compared. If
at any point in the comparison, the circuit determines that the first number is greater or less
than the second number, the comparison is terminated, and the appropriate output is
generated.
If all the bits are equal, the circuit generates an A=B output, indicating that the two numbers
are equal.
There are different ways to implement a magnitude comparator, such as using a combination
of XOR, AND, and OR gates, or by using a cascaded arrangement of full adders. The choice
of implementation depends on factors such as speed, complexity, and power consumption.
On Simple terms, Magnitude comparators compare binary numbers to determine the greater,
lesser, or equal value. If you’re preparing for GATE, the GATE CS Self-Paced Course is an
excellent resource.
1-Bit Magnitude Comparator
A comparator used to compare two bits is called a single-bit comparator. It consists of two
inputs each for two single-bit numbers and three outputs to generate less than, equal to, and
greater than between two binary numbers.
The truth table for a 1-bit comparator is given below.

1-Bit Magnitude Comparator

From the above truth table logical expressions for each output can be expressed as follows.
A>B: AB’ A<B: A’B A=B: A’B’ + AB