Questions from model paper and previous year question papers

Module 1.

1. Demonstrate the non-associativity of the NOR gate

2. Design a car safety alarm circuit diagram. The system considers four inputs: door (D), key (K),
seat pressure (P) and seat belt (B). The input is considered HIGH (1) if the door is closed, the
key is in, the driver is on the seat, or the seat belt is fastened. The alarm (A) should sound
with two conditions as stated below: The door is not closed, and the key is in. The door is
closed, the key is in the driver's seat, and the seat belt is not closed.
(a) Construct a truth table for the system based on input arrangement D, K, P, B with A as an
output
(b)Design a Karnaugh map to verify the simplified expression
(c) Draw the simplified circuit using NOR gates only L3 8 c With an example explain the
working of Test Bench in V.
3. Demonstrate the positive and negative logic signal.
4. A digital system is to be designed in which the month of the year is given as I/P in four-bit
form. The month of January is represented as '0000', February as "0001" and so on. The
output of the system should correspond to the input of the month containing 31 days, or
otherwise, it is '0'. Consider the excess number in the I/P beyond 1011' as don't care
condition:
(i) Write truth table, SOP Em and POSIIM form
(ii) Simplify for SOP using K-map
(iii) Realize using basic gates
5. What is User-Defined Primitives in Verilog? What are the general rules for UDP? Explain with
an example HDL for user defined primitive. Draw the Schematic for the Circuit with
UDP_02467.
6. Find the POS expression for F(a,b,c,d) = Π(2,3,5,8,10,13,14) + d(1,6,7,11) and realize it using
NOR gates.
7. Simplify the Boolean function, F(w,x,y,z) = ∑(0,1,2,4,6,7,9,12,14) using k map and Write the
Verilog Program for realizing the minimized expression.
8. What is Binary logic? List out any 4 Laws of Logic
9. Simplify the following Boolean function and find its SOP:
i) F(x,y,z) = ∑(0,1,4,5,6) + d(2,3,7)\
ii) F (w,x,y,z) = ∑(5,6,7,12,14,15) + d(13,9,11)
10. Demonstrate the working of NAND & XOR gate.
11. Explain the working of Test Bench in Verilog.
12. Simplify the following Boolean function into (i) sum-of-products form and (ii) product-of-
sums form:

13. Write a program in Verilog to demonstrate the working of User-Defined primitive table.
14. Realize F = AB + CD using NAND gate only.
15. Simplify the following Boolean Expression using kmap:
 16. Realize the XOR gate using (i) NAND gate (ii) NOR gate.
17. Define canonical Minterm form and canonical Maxterm form.
18. Express the function F=x+yz as the sum of its minterms and product of maxterms.
19. With an example explain duality?
20. List all Postulates and Theorems available in Boolean algebra?
21. State and Prove Absorption Theorem.
22. Find the complement and simplify the Boolean function and also write logic circuit F = A ′ B
′C ′ + A ′ B C .
23. Draw a two-level logic diagram to implement the Boolean function F = BC ′ + A B + A C D.
24. Demonstrating the non-associativity of the below operator: ( x ↓y ) ↓ z ≠ x ↓ ( y ↓ z )
25. Define negative logic and Write the equivalent negative logic for positive NAND gate.
26. Implement the Boolean function F = yz + z ′ y ′ + x ′ z With NAND and inverter gates.

Module 2.

1. Differentiate Latches and Flip-Flops.

2. Explain the working of Four-bit adders using 4-full Adders.
3. Implement Y (A, B, C, D) = ∑m (0, 1, 6, 7, 8, 9, 10, 11, 12, 14) using 16- to-1 multiplexer and 8-
to-1 multiplexer.
4. Explain different modelling styles used to write the code in VERILOG with an example.
5. Design a BCD-to-excess-3 code converter.
6. Define decoder. Describe the working principle of a 3:8 decoder. Draw the logic diagram of
the 3:8 decoder with enabled input. Realize the following Boolean expressions using a 3:8
decoder and multi-input OR gates: F1(A, B, C) = ∑ m(1, 3, 7) F2(A, B, C) = ∑m(2, 3, 5).
7. Explain the differences between Combinational and Sequential Circuits with their block
diagrams and examples.
8. What are decoders? Implement the following Boolean functions with a decoder:
F1(A,B,C) = ∑m(1, 3,4,7),
F2(A,B,C) = ∑m(0,2,3,6)
and F3(A,B,C) = ∑m(2,3,6,7)
9. What are Multiplexers? Implement the Boolean function
F(A,B,C,D)=∑m(1,3,4,11,12,13,14,15) with a 8:1 MUX.
10. Define Encoder. Design a Four-input Priority Encoder.
11. Write the Verilog program to Implement Full Adder and Subtractor Circuits.
12. Write the Characteristic Table and Equations of SR, JK, D and T Flip Flops
13. Explain Dataflow Modelling in Verilog with an example program.
14. Design a Full Adder and Subtractor Circuit.
15. Design an Octal-to-Binary Encoder.
16. Explain the working of Four-bit adders using 4-Full Adders.
17. Design a BCD-to-excess-3 code converter.
18. Demonstrate the working of SR Latch and Edge-Triggered D Flip-Flop.

19. What is a multiplexer? Design a 4 to 1 multiplexer using logic gates. Write the truth table and
explain its working principle.

20. Construct 4:1 multiplexer using only 2:1 multiplexer and also write Verilog program.

21. Construct 8:1 multiplexer using only 2:1 multiplexer.

 22. Design 32 to 1 multiplexer using 16 to 1 multiplexer and one 2 to 1 multiplexer.

23 Mention the differences between decoder and demultiplexer.

24.. (a) Realize Y = AB + BC + ABC using an 8 to 1 Multiplexer.

(b) Can it be realized with a 4 to 1 multiplxer?

25. Design a priority encoder for a system with a 3 inputs, the middle bit with highest priority
encoding to 10, the MSB with the next priority encoding to 11, while the LSB with least priority
encoding to 01.

25. Give state transition diagram of SR, D, JK and T flip flops.

27 Obtain the characteristic equation of SR, JK, D and T flip flops.

28. Explain the operation of edge triggered ‘SR’ flip flop with the help of a logic diagram and
truth table. Also draw the relevant waveforms.

29. Explain the working of Master Slave J K flip flops with logic diagram.

30. Derive the Excitation table for equation for D, T,SR, and JK Flip flops.

31. with a example explain the syntax of conditional signal assignment statement in VHDL and
Verilog.

32. Differentiate between Latch and flip flop.

Module 3.

1. Write one address, two address, and three address instructions to carry out C← [A] + [B].
2. Explain the basic operation concepts of the computer with a neat diagram.
3. Explain a) Processor Clock, b) Basic performance equation, c) Clock rate d) Performance
measurement
4. Write ALP of adding a list of n numbers using indirect addressing mode.
5. What is an addressing mode? Explain the different addressing modes. With an example for
each.
6. Explain the following: (i) Byte addressability (ii) Big-endian assignment (i) Little-endian
assignment.
7. What do you mean by an Addressing Mode? Explain any 5 Addressing Modes.
8. Describe the functionality of the following: MAR, PC, IR, MDR and ALU.
9. Explain Basic Performance Equation and SPEC rating.
10. Demonstrate the Branching operations using a loop to add n numbers with block diagram.
11. The Registers R1 and R2 has decimal values 1200 and 4600. Calculate the effective address of
the memory operand in each of the following instructions when they are executed in
sequence
i) Load 20(R1), R5
ii) ii) Move #3000, R5
iii) iii) Store R5, 30(R1,R2)
iv) iv) Add –(R2), R5
v) v) Subtract (R1)+, R5
12. Explain Single Bus Structure.
13. Describe the Big-endian and little-endian address assignment
14. Demonstrate the Instruction Execution and Sequencing for C ← [A] + [B] with block diagram.
 15. With a block diagram, explain the basic functional units of a computer.
16. With relevant example, Explain the following modes of Addressing:
i) Direct
ii) Register
iii) Index
iv) Base with index and offset
v) Autoincrement
17. A program with 7000 machine instructions needs an average of 3 basic steps to execute one
instruction. Find the performance of the computer having a clock speed of 700 KHz.
18. What are Condition Code Flags? Mention the significance of the flags N, Z, V and C.
19. With a neat diagram explain the different processor registers.
20. What are the factors that affect the performance?Explain any 4.
21. What is performance measurement? Explain the overall SPEC rating for a computer in a
program suite.
22. Write the difference b/w RISC and CISC processors.
23. A program contains 1000 instructions. Out of that 25% instructions requires 4 clock cycles,
40% instructions requires 5 clock cycles and remaining requires 3 clock cycles for execution.
Find the total time required to execute the program running in a 1GHz machine.
24. Write a note on byte addressability, big-endian and little-endian assignment.
25. Explain the basic operational concepts b/w the processor and the memory.
26. Derive the basic performance equation? Discuss the measures to improve the performance.
27. Explain processor clock and clock rate.
28. What is an addressing mode? Explain any four addressing modes.
29. Write ALP program to copy ‘N’ numbers from array ‘A’ to array ‘B’ using indirect
addresses.(Assume A and B are the starting memory location of a array).
30. With a neat block diagram, describe the I/O operation.
31. Explain functional units of computer.
32. Discuss connection between processor and memory .
33. Mention four types of operations to be performed by instructions in a computer. Explain with
basic types of instructions formats to carry out C<-[A]+[B].
34. How input and output operation performed by Processor?

Module 4.

1. Draw a neat block diagram of memory hierarchy in a computer system. Discuss the variation
of size, speed and cost per bit in the hierarchy.
2. What is DMA Bus arbitration? Explain different bus arbitration techniques.
3. With neat sketches, explain various methods for handling multiple interrupt requests raised
by multiple devices.
4. What is cache memory? Explain the different mapping functions used in cache memory.
5. Explain Memory mapped I/O and I/O interface for an input device with a 10 L2 CO4 diagram.
6. Explain I/O operations involving a keyboard and display device with a program that reads one
line from keyboard, stores it in buffer and echoes it back to display.
7. Explain how to handle interrupt from multiple devices using daisy chain and priority scheme
8. Explain Centralized and Distributed Bus Arbitration approaches.
9. Describe DMA with its registers and controllers.
10. Explain the effect of size, cost and speed in Memory Hierarchy.
11. Explain Hardware Interrupt, enabling/disabling of Interrupts and sequence of events in
handling interrupt request from a single device.
 12. Describe the different memory mapping functions.
13. Define bus arbitration.Explain in detail both approach of bus arbitration.
14. What is an interrupt? With example illustrate the concept of interrupts.
15. Explain in detail the situation where a number of devices capable of initiating interrupts are
connected to the processor? How to resolve the problems?
16. Explain the following terms a) interrupt service routine b) interrupt latency c) interrupt
disabling.
17. Draw the arrangement of a single bus structure and brief about memory mapped I/O.
18. Explain interrupt enabling,interrupt disabling,edge triggering with respect to interrupts
19. Draw the arrangement for bus arbitrations using a daisychain and explain in brief.
20. With neat sketches explain various methods for handling multiple interrupt requests.
21. Define memory mapped I/0 and I/0 mapped I/0 with examples
22. Explain how interrupt request from several I/0 devices can be communicated to a processor
through a single INTR line.
23. What are the different methods of DMA. Explain in brief.
24. Show with diagram the memory hierarchy with respect to speed , size and cost
25. What is DMA? Explain the hardware registers that are required in a DMA controller chip.
Explain the use of DMA controller in a computer system with a neat diagram
26. Explain with a block diagram a general 8 bit parallel interface.
27. Explain different mapping functions used in cache memory.

Module 5.

1. Explain the single-bus organization of computers and fundamental concepts with a neat
diagram.
2. Write and explain the control sequence for execution of the instruction Add(R3), R1
3. Explain with an example the different types of hazards that occur during pipelining.
4. Write and explain the control sequence for the execution of an unconditional branch
instruction.
5. With a diagram, explain the single bus organization of the data path inside a processor.
6. Describe the Basic idea of Instruction Pipeline.
7. Explain the process of Fetching Word from Memory in processor.
8. Explain the Pipeline Performance of a Processor and pipeline stalls.
9. Describe how an ALU performs an Arithmetic and Logic Operations along with input gating
diagrams.
10. Explain 4-stage pipeline with diagrams.
11. Explain the complete set of operations involved in executing the instruction Add (R3), R1
along with control sequence.
12. What are Hazards? Explain Data Hazard, Control Hazard and Structural Hazard.
13. Discuss Connection of the memory to the processor with diagram,
14. Explain with need diagram a single-bus structure.
15. Discuss synchronous Bus operation with neat diagram.
16. Discuss asynchronous Bus operation with neat diagram.
17. Explain multiple bus organization and its advantages.
18. Explain the role of cache memory in pipelining.
19. Explain pipelining performance.
20. Explain the processing and control capabilities of Microwave oven and Digital camera.
21. Explain the structure of General-Purpose Multiprocessors.
22. Describe the classifications of Parallel Structures.
23. Describe the three-bus organization of the data path and describe in detail.
24. Write control sequence for the instruction Add R1, R2, R3. 13.Explain a complete processor
with a neat diagram
25. Write and explain the control sequences for the execution of the following instruction:
Add(R3),R1.
26. Explain Field coded micro-Instructions with a neat diagram.
27. Discuss with neat diagram I/O interface for an input device.