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    Assignment_3, Solutions

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    Ali Abrar

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    © All Rights Reserved
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    Assignment_3, Solutions

    Uploaded by

    Ali Abrar
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    Assignment_3, Solutions

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    Ali Abrar

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    Memorial University of Newfoundland

    Faculty of Engineering and Applied Science

    ENGI 9819: Computer Hardware Foundations

    ASSIGNMENT 3, Solutions

    P.1. Design a new type of positive-edge-triggered flip-flop called the LH flip-flop. It has a clock
    C, a data input D, and a load input L. If, at the positive edge of C, L equals 1, then the data on D
    is stored in the flip-flop. If, at the positive edge of C, L equals 0, then the current stored value in
    the flip-flop is held. Design the flip-flop using only latches, NAND gates, and inverters (20
    marks).

    Answer:

    P.2. Find a state-machine diagram that is equivalent to the state diagram in Fig. 1. Reduce the
    complexity of the transition conditions as much as possible. Attempt to make outputs
    unconditional by changing Mealy outputs to Moore outputs. Make a state assignment to your
    state-machine diagram and find an implementation for the corresponding sequential circuit using
    D flop-flops, AND gates, OR gates, and inverters (20 marks).

    Fig. 1. State diagram for P. 2.

    1
    Answer:

    P.3. The circuit given in Fig. 2 is to be redesigned to cut its cost (20 marks: 5 marks for each
    part).
    (a) Find the state table for the circuit and replace the state codes with single letter identifiers.
    States 100 and 111 were unused in the original design.
    (b) Check for and combine equivalent states.
    (c) Make a state assignment such that the output is one of the state variables.
    (d) Find the gate-input costs of the original circuit and your circuit, assuming that the gate-input
    cost of a D flip-flop is 14. Is the cost of the new circuit reduced?

    2
    Fig. 2. State diagram for P. 3.

    3
    Answer:

    P.4. Given a 256 × 8 ROM chip with an enable input, show the external connections necessary to
    construct a 1K × 16 ROM with eight chips and a decoder (10 marks).

    Answer:

    4
    P.5. Specify the size of a ROM (number of words and number of bits per word) that will
    accommodate the truth table for the following combinational circuit components (15 marks: 5
    marks for each correct answer):
    (a) A 16-bit ripple carry adder with Cin and Cout.
    Answer: 16 + 16 + 1 = 33 address bits and 16 + 1 = 17 output bits, 8G × 17

    (b) An 8-bit adder–subtractor with Cin and Cout.


    Answer: 8 + 8 + 1 + 1 = 18 address bits and 8 + 1 = 9 output bits, 256K×9

    (c) A code converter from a 4-digit BCD number to a binary number.


    Answer: 4 × 4 = 16 address bits and 14 output bits are needed, 64K × 14

    5
    P.6. The rear lights of a car are to be controlled by digital logic. There is a single lamp in each of
    the rear lights. The inputs are (15 marks):
    LT left turn switch—causes blinking of left side lamp
    RT right turn switch—causes blinking of right side lamp
    EM emergency flasher switch—causes blinking of both lamps
    BR brake applied switch—causes both lamps to be on
    BL blinking signal with 1 Hz frequency
    The outputs are:
    LR power control for left rear lamp
    RR power control for right rear lamp
    (a) Write the equations for LR and RR. Assume that BR overrides EM and that LT and RT
    override BR (4 marks).
    (b) Implement each function LR (BL, BR, EM, LT) and RR (BL, BR, EM, RT) with a 4-to-16-
    line decoder and external OR gates (9 marks).

    Answer:

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