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    Mid 2 DLD

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    nskprasad89
    The document contains 20 questions related to digital logic design topics such as multiplexer design, comparator design, flip-flop design, counter design, conversion between number systems, and sequential circuit design. It involves designing combinational and sequential circuits using basic gates, multiplexers, flip-flops, counters, and other digital components. The questions cover both combinational and sequential logic design principles.

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    Mid 2 DLD

    Uploaded by

    nskprasad89
    74 views2 pages
    The document contains 20 questions related to digital logic design topics such as multiplexer design, comparator design, flip-flop design, counter design, conversion between number systems, and sequential circuit design. It involves designing combinational and sequential circuits using basic gates, multiplexers, flip-flops, counters, and other digital components. The questions cover both combinational and sequential logic design principles.

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    The document contains 20 questions related to digital logic design topics such as multiplexer design, comparator design, flip-flop design, counter design, conversion between number systems, and sequential circuit design. It involves designing combinational and sequential circuits using basic gates, multiplexers, flip-flops, counters, and other digital components. The questions cover both combinational and sequential logic design principles.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    74 views2 pages

    Mid 2 DLD

    Uploaded by

    nskprasad89
    The document contains 20 questions related to digital logic design topics such as multiplexer design, comparator design, flip-flop design, counter design, conversion between number systems, and sequential circuit design. It involves designing combinational and sequential circuits using basic gates, multiplexers, flip-flops, counters, and other digital components. The questions cover both combinational and sequential logic design principles.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    1. Design of a BCD to Gray code converter.

    2. Implement the following logic function using an 8 x 1 MUX (, , , ) =


    (1,3,4,11,12,13,14,15)
    3. Design of a 2 bit comparator using two 1 bit comparator modules.
    4. Show how a full-adder can be converted to a full-subtractor with the addition of an inverter circuit.
    5. Convert SR flip flop to T flip flop.
    6. Design of a synchronous 3 bit up-down counter using JK FFs.
    7. Design of synchronous modulo-8 gray code counter using D FFs.
    8. A digital computer has a common bus system for 16 registers of 32 bits each. The bus is
    constructed with multiplexers.
    a. How many selection inputs are there in each multiplexer?
    b. What sizes of multiplexers are needed?
    c. How many multiplexers are there in the bus?
    9. Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and B. The
    circuit generates the following four arithmetic operations in conjunction with the input carry Cin.
    Draw the logic diagram for the first two stahes.

    10. Draw the block diagram for the hardware that implements the following statements:
    + : +
    where AR and BR are two n-bit registers and x,y, and z are control variables. Include the logic
    gates for the control function.
    11. Tabulate the PLA programming table for the four Boolr=ean functions listed below. Minimize the
    numbers of product terms.
    (, , ) = (1,3,5,6) B(, , ) = (0,1,6,7)
    C(, , ) = (3,5) (, , ) = (1,2,4,5,7)
    12. Tabulate the truth table for an 8 X 4 ROM that implements the Boolean functions
    (, , ) = (0,3,4,6) B(, , ) = (0,1,4,7)
    C(, , ) = (1,5) (, , ) = (0,1,3,5,7)
    Considering now the ROM as a memory. Specify the memory contents at addresses 1 and 4.
    13. Derive the PLA programming table for the combinational circuit that squares a three-bit
    number.Minimize the number of product terms.
    14. Derive the ROM programming table for the combinational circuit that squares a four-bit
    number.Minimize the number of product terms.
    15. List the PLA programming that for the BCD-to-excess-3-code converter.
    16. Design a four-bit binary synchronous counter with D flip-flops.
    17. What is the difference between serial and parallel transfer? Explain how to convert serial data to
    parallel and parallel data to serial.What type of register is needed?
    18. Te contents of a four-bit register is initially 0110. The register is shifted six times to the right with
    serial input being 1011100. What is the content of the register after each shift?
    19. A sequential circuit has two JK flip-flops A and B and one input x. Yhe circuit is described by the
    following flip-flop inpot equations:
    = = = =
    a. Derive the state equations A(t+1) and B(t+1) by substituting the input equations for the J and K
    variables.
    b. Draw the state diagram of the circuit.
    20. A sequential circuit has three flip-flops A,B,C; one input x_in;and one output y_out. The state
    diagram is shown in fig. The circuit is to be design by treating the unused states as dont-care
    conditions. Analyze the circuit obtained from the design to determine the effect of the unsuded
    states. Use D flip-flops in the design.

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