design

Edited by Bill Travis

ideas

The best of
! Check it out at: www.edn.com

design ideas

Positive feedback yields fast amplifier with precision dc offset

Steve Woodward, Chapel Hill, NC
ome signal-processing applications require a high-speed, lownoise, dc-coupled amplifier that incorporates a precision dc-offset adjustment. Examples include oscilloscopes, in which the offset adjustment typically acts as a position control), ADC-input gain blocks, and scanningion-beam-microscopy deflection circuitry. Figure 1 illustrates the circuit concepts. Op amp IC2A is a 70-MHz, high-slew-rate device configured with a fixed gain of 3 (9.5 dB) and a 10V precision offset adjustment. Op amp IC1A buffers and thereby linearizes the offset potentiometer. IC1A is a low-cost, low-fre-

quency device that befits the dc circuit it occupies. But the mismatch between the frequency responses of IC2 and IC1A creates the need for the novel topology of Figure 1. An obvious way to couple IC1A and IC2A, which might seem to allow the addition of dc offset, would be to omit R1, R2, R5, and C1 and simply connect IC1A as a unity-gain buffer providing the termination for the gain-set resistor, R3. Unfortunately, this scheme wouldnt work, because the output impedance of the pokey IC1A starts rising at frequencies far below the capabilities of the speedy IC2. This drawback would ruin the highfrequency performance of the composite
R4* 2k 20 X OUT 10V

Positive feedback yields fast amplifier with precision dc offset..................................91 Buck regulator forms high-power, inverting 5V supply ..................................92 Low-loss circuit powers solar lantern ........94 RC network quashes auxiliary winding in quasiresonant converter..........................98 Low-power CMOS oscillator has push-pull output ..........................................100
Publish your Design Idea in EDN. See the Whats Up section at www.edn.com.

12V

X GAIN CCW 2.5k CW R7 V2 R10* 402 R11* 200 X.5 ADJ

2 3 IC2B 4

0.1 6 IN X V1 R8* 825 R9* 500 X10 ADJ 5 8 IC2A 7

R3* 1k 12V

0.1 R1* 4990

R5* 150k 12V

3600 R2* 100 1 IC1A 3 2 V3 CCW X AND Y 5V OFFSET R6 20k CCW 20k CW VR2 5V LED 12V 12V R5* 150k 100 F 16V 20 Y OUT 10V 12V 7824 OFF 0 1 0 2N4401 20k 10k 0.01 F 4 NOTES: IC1=LM324. IC2, IC3=LT1364. FOR 0.1- F BYPASSES ON LT1364 SUPPLIES, USE SEVERAL IN PARALLEL. *=1% TOLERANCE. 6 5 100 F 16V 12V 20k IC1C 100 F 35V 7 11 2N4403 62 1W + DC INPUT 24V 0.4A 3600 VR1 VR1=VR2= LM4040 5 12V

C1 1 F

470k

2k 100* 1 F 1k* 14 IC1B 12 13 CW

Figure 1
12V

Y GAIN CCW 2.5k CW R10* 402 0.1 8 6 F R11* 200

4990*
1

2 3 IC3B 4 0.1 12V 2k* F

ON

IN Y 825*

IC3A

470k

500

In this circuit, positive feedback makes it possible to obtain wide-range dc offset without compromising bandwidth. www.edn.com April 1, 2004 | edn 91

design

ideas
components than for ac. The circuit avoids this effect by using positive feedback that R1 and R5 provide. The dc gain that R1 and R5 provide generates a compensation-voltage component that nulls the voltage drop across R2. This action cancels the tendency of the R3C1 node to track IC2As input and makes IC2s output accurately equal to VOUT V2(1 R4/R3) V3(R4/R3) 3V2 2 V3. The rest of the schematic illustrates the use of the offset circuit in a dual-channel amplifier. In this amplifier, the variablegain front ends incorporate a pseudologarithmic gain adjustment spanning gains of 0.5 to 10 ( 6 to 20 dB). To achieve this wide gain-control range with a single-turn potentiometer and maintain reasonable adjustment resolution without compromising the LT1364s 20-MHz capability, the control potentiometer, R7, is connected such that its resistance element serves two circuit functions. The left half forms a variable-gain (1 to 3.33 0 to 10.5 dB) feedback network around IC2A. The right half forms a variable-loss (1 to 0.167 0 to 15.5 dB) circuit. The net result, when you combine it with the fixed 9.5-dB gain of IC2A, is an overall gain variable from (0 15.5 9.5) 6 dB when you adjust R7 to one extreme to (10.5 0 9.5) 20 dB when you adjust R7 to the other extreme. IC1C finishes the gain-block subsystem by generating tracking 12V rails, by splitting the ground of the 7824 24V regulator. This regulator uses as its source an inexpensive, unregulated wall-socket power supply.

amplifier. You could (partially) avoid this problem by using another LM1364 in place of the LM324, but the result would be a significantly noisier circuit because of the summation of IC1As output noise with the signal at point V2. This Design Idea offers a different approach, in which C1 provides a robust, low-impedance termination for R3, and the R2C2 time constant isolates the signal path from noise originating in either IC1A or the VR1 and VR2 voltage references. Unfortunately, this approach creates a problem arising from R2s dc resistance. C1 holds down the bottom end of R3 for ac-signal frequencies higher than 1 kHz or so. But near dc, R2 and R3 tend to sum, and the summing action would make the closed-loop gain of IC2 approximately 10% less for dc-signal

Buck regulator forms high-power, inverting

5V supply

Bruce Denmark, Maxim Integrated Products, Sunnyvale, CA

onfiguring a step-down switch12V ing-converter IC as an inverter yields an efficient, high-power, 4.7 F 10 5V supply that can of deliver currents 20 as high as 4.5A at the 12V input or 3.2A 5V 10 F 10 F 10 F 10 F 13 14 at the 5V input (Figure 1). ConventionCENTRAL 4.7 F V+ VL SEMICONDUCTOR VCC 12 al inverting power supplies do their LOW ESR CMPSH-3 SHDN* 4 20 switching using a p-channel MOSFET SKIP* SYNC 8 (Figure 2). That configuration works FDS9412 BST 17 well at lower currents, but has limited use FAIRCHILD DH 18 above approximately 2A, depending on 2 H IC1 0.1 F 0.008 PANASONIC MAX1663 the input and output voltage levels and 1W 2 1 LX 19 the MOSFET you use. If you compare a ETQP6F2R0 N2 standard buck circuit with the circuit in FDS6680 15 FAIRCHILD Figure 1, you can see that the converters STPS2L250 DL 3 RESET* ST MICROELECTRONIC output in Figure 1 connects to ground, R1 CSH 1 10k 1 F and what used to be ground becomes the CSL 2 7 FB 3 REF 5V output (Figure 3). Because the on6 resistance of an n-channel MOSFET is CC R2 1500 pF 2.80k lower than that of a comparably sized p5 channel device, a power supply with nOVP GND PGND GND channel MOSFETs usually provides 9 16 10 more current at higher efficiency. To turn on, however, an n-channel device re5V, 4.5A 470 F 470 F 470 F 470 F quires a gate voltage approximately LOW ESR Figure 1 4V higher than the source voltage, which is usually the supply voltage. The circuit in Figure 1 achieves high By configuring this high-power dc/dc step-down converter as an inverter, you can obtain 4.5A at output current and high efficiency by re5V from a 12V input or 3.2A at 5V from a 5V input.
www.edn.com

92 edn | April 1, 2004

design

ideas
POSITIVE VIN
VIN V+ SHDN OVP VL

Figure 2
NEGATIVE VOUT EXT MAX1846 MAX1847

VCC

VL

IN

Figure 3
CC DH BST

COMP

CS
MAX1636

LX

DL

FREQ

PGND

SKIP PGND SYNC CSH GND CSL

REF GND

FB

REF

FB RESET TO MICROPROCESSOR

GND

This conventional inverting power supply uses a relatively inefficient p-channel MOSFET.

IC1 in Figure 1 normally operates as a high-power buck converter.

configuring a high-power buck converter, IC1, as an inverter, thus exploiting an all-n-channel design. Efficiency is 90% with a 12.35V input, 5.02V output, and 4.7A load. The efficiency is 84% with a 4.56V input, 5.02V output, and 3.3A load.You can easily accommodate 5.2V applications by changing the values of R1 and R2. (Operation at 5.2V incurs a

small penalty on maximum output current.) Input and output ripple voltages directly relate to the input and output capacitors ESR (equivalent series resistance), so you should carefully select these capacitors. Circuit layout is also extremely important, as for all dc/dc converters. You may want to consider the MAX1636 evaluation kit from Maxim

(www.maxim-ic.com). The kit includes a small pc board with optimized layout and all components necessary for operating the MAX1636. Because the boards layout is similar to the one required in Figure 1, the kit can serve as a rough layout guide for this Design Idea.

Low-loss circuit powers solar lantern

Ramsesh Kumar, Bangalore, India

he solar-lantern circuit in Figure 1 is a low-loss configuration that uses a 7W, four-pin CFL (compact fluorescent lamp) and a 12V, 7-Ahr, sealed, maintenance-free battery. The inverter features greater-than-85% efficiency, less-than-2mA quiescent current, and a shunt-charge controller with deep-discharge and overcharge protection for the battery. The low quiescent current and the deep-discharge and overcharge protection ensure long life for the battery. The preheating feature in the inverter avoids the blackening of the end of the CFL, thereby ensuring long life. The circuit finds application in rural areas

as a reliable, compact, portable light load condition, the discharged battery source and in urban areas as an emer- voltage is approximately 12.2V. Hence, the gency-lighting system. The shunt charge- circuit provides a deep-discharge reset controller circuit comprises IC1, a low- level of 12.3V to avoid oscillations. Red current, voltage-reference 2.5V LM385, LED1 indicates a low-battery condition. and IC2, an LM324 comparator. IC2A, with IC2B with resistors R9 through R14 and resistors R1 through R8 and transistor Q1, transistor Q2 provides protection against provides protection against deep discharge overcharging the battery. Q2 switches on of the battery. The circuit switches off the TABLE 1WINDING DETAILS FOR TRANSFORMER load, including the inverter Start pin End pin Wire gauge Turns Inductance and the lamp, when the battery 2 1 26 21 28 mH 3 4 26 21 28 mH voltage falls below 10.8V and 6 10 38 380 17 mH thus protects the battery from Core: EE25/13/7 deep discharge. Under a nowww.edn.com

94 edn | April 1, 2004

design

ideas

and shunts the solar array when the battery voltage exceeds 14.8V and thus protects the battery from overcharging. Q2 turns off when the battery voltage drops below 12.5V and thus enables battery charging. D2 is a reverse-blocking diode. It prevents the discharge of the battery through the solar cells when the cells are not generating electricity. Amber LED2 indicates that the battery is in full-charge

condition. Green LED3, along TABLE 3WINDING DETAILS FOR INDUCTOR L1 with IC2C and resistors R15 Wire gauge Turns through R20, provides an indi26 100 cation of charging. Core: Ferrite rod, 5-mm diameter, 25 mm long. Tables 1, 2, and 3 give core and winding details for the magnetic kHz. Q6, along with resistors R29, R30, and components in the circuit. The inverter R31 and capacitor C10, forms the preuses a Class D, push-pull, force-driven heating circuit. In addition to the 12V, 7topology with MOSFETs as switching Ahr sealed, maintenance-free battery, the devices. IC3, an SG3524, drives the in- circuit uses a 10W, 12V single-crysverter. The force-driven top- talline-silicon solar-cell panel. The TABLE 2WINDING DETAILS FOR INDUCTOR L2 ology ensures trouble-free recorded backup time is approximately Start pin End pin Wire gauge Turns Inductance start-up in all environmental eight to 10 hours for a fully charged bat1 2 27 215 8.2 mH conditions. The switching fre- tery with a light output of 370 lumens Core: EE25/13/7 quency is approximately 26 using a 7W, four-pin CFL.
SOLAR BATTERY D1 IN4007 R6 1k R8 3.3k LED1 RED 2 _ R4 10k
IC1

R12 470k R9 100k R10 2.2k Q1 BC557 VREF X V1 S1B L1 2 + C2 1000 F 25V 3 R11 10k

R14 5 5W

IN5408 D2
+ + BATTERY _

R1 100k VREG

R2 100k 4 IC2A 3 +

R7 1 S1A 3.3k

6 _

IC2B

7 R13 1k Q2 MJE 3055

C1 10 F 25V

LM385 2.5V

R3 26k

11 A R5 470k

LED2 AMBER

SOLAR PANEL 12V 10W

12V 7 AHR

T1 6

L2 1 2

SOLAR BATTERY R15 180k R18 180k 12

LM324
IC2

BATTERY FUSE 1A
+

D3 IN4007

1 4 Q3 IRFZ44 C4 0.47 F LAMP CFL 7W/ FOUR PIN

C5 C6 10 F 6.8 F 2kV 2kV

R16 100 R17 180k R19 180k

13 _

IC2C

R20 14 1k LED3 GREEN

C3 0.47 F R21 10 R22 100k D21 D22 E 12V 500 mW C

R23 10 Q4 D23 IRFZ44 D24

C7 1 nF 1 kV RELAY CONTACTS V1

V1 A R28 1k + C8 100 F 25V 10 R26 1k D4 IN4007 15 13 12 B

R32

R24 100k

Figure 1
C9 10 nF

R25 6.7k B C

11 7 6 4 16 5 3 1 2 89

IC3 13 SG3524

D5 IN4007 D R33 330 E R29 820 R27 1k

D6 IN6007 C10 1000 F 25V

RELAY 12V

R30 33k

R31 1k

Q5 BC547

C11 1 F NC

This solar-powered lantern driver can serve as an emergency lighting system.

96 edn | April 1, 2004

www.edn.com

design

ideas

RC network quashes auxiliary winding in quasiresonant converter

Nicolas Cyr, On Semiconductor, Toulouse, France
VOUT uasi-square-wave-resonant converters, also known as QR (quasiresonant) converters, allow the de+ R1 sign of flyback-type SMPSs (switch+ mode power supplies) with a reduced GROUND EMI (electromagnetic-interference) sigNCP1207 nature and improved efficiency. You can DMG 1 8 achieve so-called QR operation by au2 7 thorizing the turn-on of the switching MAINS 3 6 MOSFET when the drain voltage reachDRV C2 4 5 es its minimumhence, the name valley switching operation. The circuit usually externally detects the minimum Figure 1 drain voltage of an auxiliary winding, which delivers a voltage image + of the cores internal flux activity. The circuit in Figure 1 offers a solution that incorporates core-reset detection with the aid of an auxiliary winding. As you can see, the auxiliary winding solely performs the function of core-reset detection. To In this configuration, an auxiliary winding performs the function of core-reset detection. further simplify this schematic, you can remove the auxiliary winding and use the with the internal resistor on the best valley detection possible. Because R1 drain signal itself to generate the demag- NCP1207 demagnetization pin (Pin 1), has a relatively high value, it is essential netization signal that Pin 1 of the creates a resistor divider. The divider that the component resides close to the NCP1207 requires. Figure 2 shows this safely limits the voltage you apply on the controllers Pin 1. The Figure 3 wavearrangement. Thanks to its use of high- controller when the drain swings high. forms show the final application results. voltage technology, On Semiconductors C2 delays the signal to detect exactly the The waveforms are captured on a single(www.onsemi.com) NCP1207 QR con- drain signal valley. Compared with Fig- output, 30W SMPS delivering 16V. In troller can derive its power directly from ure 1, where R1 and C2 were present, the this application, C1 220 pF/1 kV, the rectified mains via its dynamic-self- only addition is C1 (in replacement of R1 1.5 M , and C2 100 pF. By propthe auxiliary winding. Because capacitor erly adjusting the time constants, you supply feature. Capacitor C1 removes the dc compo- C1 touches the MOSFET drain, it must can obtain perfect valley switching. nent of the drain signal. R1, together sustain at least the same maximum voltage: A 220-pF, 1-kV or 1-nF, 1kV ceramic capacitor perfectly fills the bill. The internal resistLPRI ance of NCP1207s demagnetization pin is 28 k . The value of C1 R1 DMG R1 ranges from 1 to 2 M if you want to create a 5V signal with a maximum drain voltage of 600 and 900V. The value of capacitor C2 DRV C2 depends on the frequency of the resonating network comprising the primary inductance, Figure 2 LPRI, and the total capaciFigure 3 tance of the drain node. You In this circuit, the MOSFETs drain waveadjust the values of R1 and C2 diThese waveforms illustrate the operation of form generates the demagnetization sigrectly on the board to reach the Figure 1s circuit without the auxiliary winding. nal for the controller IC.

98 edn | April 1, 2004

www.edn.com

design

ideas
3 74HC14 4

Low-power CMOS oscillator has push-pull output

Shyam Sunder Tiwari, Sensors Technology Private Ltd, Gwalior, India
igital oscillators often generate TTL- or CMOS-level outputs, referred to ground. Generating a symmetric bipolar output with respect to ground presents a challenge. In this design, four 1.5V flashlight 3V DC Figure 1 cells create 3V voltage sources, and the midpoint of cells acts 14 as the ground reference (Figure 1). The 1 74HC14 oscillator at the input, based on the R1C1 time constant, generates a 2.8V bipolar output. The symmetrical outR1 put waveform requires no dc-blocking C1 capability to drive a piezoelectric 3V DC buzzer or loudspeaker. The circuit works well with 1 to 3V sources and delivers a symmetrical output over the This oscillator uses multiple logic gates to deliver a full range of source voltages.

2.8V 5 6 0V

74HC14

2.8V 2 9 74HC14 8 OUTPUT GROUND

11

74HC14

10

13

74HC14 7 3V DC

symmetrical bipolar output.

100 edn | April 1, 2004

www.edn.com