Module 5

Applications of Digital Circuits:

• A sequence detector is a sequential state machine that takes an input string of bits and generates an output 1
whenever the target sequence has been detected.
• In a Mealy machine, output depends on the present state and the external input (x). Hence, in the diagram,
the output is written outside the states, along with inputs
• The circuit will examine a string of 0’s and 1’s applied to the X input
and generate an output Z = 1, only when a prescribed input sequence
occurs. It will be assumed that the input X can only change between
clock pulses. Specifically, we will design the circuit so that any input
sequence ending in 101 will produce an output Z = 1,coincident with
the last 1.The circuit does not reset when a 1 output occurs . A typical
input sequence and the corresponding output sequence are:
• The flip-flop inputs are then derived from the next-state maps using the same
method that was used for counters. If D flip-flops are used, DA =A+ = X’B and DB
= B+ = X, which leads to the circuit shown in Figure 14-5.
• Initially, we will reset both flip-flops to the 0 state. By tracing signals through
the circuit, you can verify that an output Z = 1 will occur when an input
sequence ending in 101 occurs. To avoid reading false outputs, always read the
value of Z after the input has changed and before the next active clock edge.
• The procedure for finding the state graph for a Moore machine is similar to that
used for a Mealy machine, except that the output is written with the state
instead of with the transition between states .
• We will rework the previous example as a Moore machine to illustrate this
procedure . The circuit should produce an output of 1 only if an input sequence
ending in 101 has occurred .
• The design is similar to that for the Mealy machine up until the input sequence
10 has occurred, except that 0 output is associated with states S0, S1, and S2:
• Because there are four states, two flip-flops are required to realize the circuit.
Using the state assignment AB = 00 for S0; AB = 01 for S1; AB = 11 for S2 and
AB = 10 for S3, the following transition table for the flip-flops results (Table
14-4):

• The output function is Z = AB’. Note that Z depends only on the flip-flop states
and is independent of X, while for the corresponding Mealy machine, Z was a
function of X.
Guidelines for Construction of State Graphs:
1. First, construct some sample input and output sequences to make sure that you
understand the problem statement.
2. Determine under what conditions, if any, the circuit should reset to its initial
state.
3. If only one or two sequences lead to a nonzero output, a good way to start is to
construct a partial state graph for those sequences.
4. Another way to get started is to determine what sequences or groups of
sequences must be remembered by the circuit and set up states accordingly.
5. Each time you add an arrow to the state graph, determine whether it can go to
one of the previously defined states or whether a new state must be added.
6. Check your graph to make sure there is one and only one path leaving each state
for each combination of values of the input variables.
7. When your graph is complete, test it by applying the input sequences formulated
in part 1 and making sure the output sequences are correct.
• A sequential circuit has one input (X) and one output (Z).The circuit examines
groups of four consecutive inputs and produces an output Z=1 if the input
sequence 0101 or 1001 occurs . The circuit resets after every four inputs.
Find the Mealy state graph.
• A sequential circuit has one input ( X) and two outputs ( Z1 and Z2). An
output Z1 = 1 occurs every time the input sequence 100 is completed,
provided that the sequence 010 has never occurred. An output Z2 = 1 occurs
every time the input sequence 010 is completed. Note that once a Z2 = 1
output has occurred, Z1 =1 can never occur but not vice versa. Find a Mealy
state graph and table.
 Design Example–Code Converter:
• We will design a sequential circuit to convert BCD to excess-3 code. This circuit
adds three to a binary-coded-decimal digit in the range 0 to 9.The input and
output will be serial with the least significant bit first. A list of allowed input
and output sequences is shown in Table 16-1.
• Next, we will reduce the table using row matching. When matching rows which contain
dashes (don’t-cares), a dash will match with any state or with any output value.
• By matching rows in this manner, we have H ≡ I ≡ J ≡ K ≡ L andM ≡ N ≡ P. After
eliminating I, J, K, L, N, and P, we find E ≡ F ≡ G and the table reduces to seven rows
(Table 16-3).
Using the guidelines given inSection 15.8, states B and C, D and E, and H andMshould
be given adjacent assignments in order to simplify the next-state functions. To simplify
the output function, states (A, B, E, and M) and (C, D, and H) should be given adjacent
assignments
Design of Iterative Circuits:

Design of a Comparator:
• As an example, we will design a circuit which compares two n-bit
binary numbers and determines if they are equal or which one is
larger if they are not equal.
• Direct design as a 2n-input combinational circuit is not practical for n
larger than 4 or 5, so we will try the iterative approach. Designate the
two binary numbers to be compared as
• If the numbers are equal to the left of cell i and xi = yi, the numbers are still equal including
cell i so: S i+1 = S0.
• However, if Si = S0 and xi yi = 10, then (x1x2 . . . xi )>( y1y2 . . . yi )and S i+1 = S1.
• If X > Y to the left of cell i, then regardless of the values of, xi and yi (x1x2 . . . Xi) > (y1y2 . . .
Yi) and S i+1 = S1.
• Similarly, if X < Y to the left of cell i, then X < Y including the inputs to cell i, and S i+1 = S2.
 Design of Sequential Circuits Using
ROMs and PLAs:
• A sequential circuit can easily be designed using a ROM (read-only memory) and
flipflops.The combinational part of the sequential circuit can be realized using a ROM.
• The ROM can be used to realize the output functions (Z1, Z2, . . . , Zn) and the next-
state functions (Q1 ,Q2 , . . . ,Qk ).
• The state of the circuit can then be stored in a register of D flip-flops and fed back to
the input of the ROM.
• Thus, a Mealy sequential circuit with m inputs, n outputs, and k state variables can be
realized using k - D flip-flops and a ROM with m +k inputs (2 m+k words) and n + k
outputs.
• The Moore sequential circuit can be realized in a similar manner . The next-state and
output combinational subcircuits of the Moore circuit can be realized using two ROMs
or alternatively, a single ROM can be used to realize both the next-state and output
functions and flip flops are used for remembering the previous state.
• Use of D flip-flops is preferable to J-K flip-flops because use of two-
input flipflops would require increasing the number of outputs from
the ROM.
• The fact that the D flip-flop input equations would generally require
more gates than the J-K equations is of no consequence because the
size of the ROM depends only on the number of inputs and outputs
and not on the complexity of the equations being realized.
• For this reason, the state assignment which is used is also of little
importance, and, generally, a state assignment in straight binary order
is as good as any.
Example:Realize the converter using a ROM and D
flip-flops:
Sequential Circuit Design Using CPLDs:
• A typical CPLD contains a number of macrocells that are grouped into function blocks.
• Connections between the function blocks are made through an interconnection array.
• Each macrocell contains a flip-flop and an OR gate, which has its inputs connected to an AND gate array.
• Some CPLDs are based on PALs, in which case each OR gate has a fixed set of AND gates associated with it.
• Other CPLDs are based on PLAs, in which case any AND gate output within a function block can be
connected to any OR gate input in that block.
• Figure shows the structure of a Xilinx CoolRunner II CPLD, which uses a PLA in each function block.
• This CPLD family is available in sizes from two to 32 function blocks (32 to 512 macrocells).
• Each function block has 16 inputs from the AIM (advanced interconnection matrix) and up to 40 outputs to
the AIM.
• Each function block PLA contains the equivalent of 56 AND gates.
Sequential Circuit Design Using FPGA’s:
• FPGA usually consists of an array of configurable logic blocks (CLBs)
surrounded by a ring of I/O blocks.
• The FPGA may also contain other components such as memory
blocks, clock generators, tri-state buffers, etc.
• A typical CLB contains two or more function generators, often
referred to as look-up tables or LUTs, programmable multiplexers, and
D-CE flip-flops (see Figure 9-33).
• The I/O blocks usually contain additional flip-flops for storing inputs
or outputs and tri-state buffers for driving the I/O pins.
• This CLB is divided into two nearly identical slices. Each slice contains two 4-variable function
generators (LUTs), two D-CE flip-flops, and additional logic for carry and control.
• This additional logic includes MUXes for selecting the flip-flop inputs and for multiplexing the LUT
outputs to form functions of five or more variables.
Implementation using FPGA:
• Mealy sequential machine with two inputs,
two outputs, and two flip-flops can be
implemented by a FPGA.
• Four LUTs (FGs or function generators) are
required, two to generate the D inputs to
the flip-flops and two to generate the Z
outputs.
• The flip-flop outputs are fed back to the
CLB inputs via interconnections external to
the CLB.
• The entire circuit fits into one Virtex CLB.
• This implementation works because each D
and Z is a function of only four variables
(X1,X2,Q1, and Q2).
• If more flip-flops or inputs are needed, the
D or Z functions may have to be
decomposed to use additional function
generators
 Implementation of Loadable shift register:

• Figure shows how the 4-bit loadable right-shift register. Four LUTs are used to generate the D inputs to the flip-flops, and a fifth LUT
generates the CE input.
• If we had implemented Equations directly without using the CE input, we would need to implement four 5-variable functions.
• This would require eight LUTs because each 5-variable function requires two 4-variable function generators .
• However, if we set CE = Ld + Sh, then CE = 0 when Ld = Sh = 0 and the flip-flops hold their current values.
• Therefore, we do not need the first term in each of Equations12-1), and the flip-flop D input equations fit into 4-variable function
generators.
• We can rewrite Equation (12-1(a)) in terms of CE as follows
Implementation of adder with accumulator:
Serial Adder with Accumulator:
• In this section we will design a control circuit for a serial adder with
an accumulator. Figure 18-1 shows a block diagram for the adder.
• Two shift registers are used to hold the 4-bit numbers to be added, X and Y.
• The X register serves as an accumulator and the Y register serves as an addend
register.
• When the addition is completed, the contents of the X register are replaced with
the sum of X and Y.
• The addend register is connected as a cyclic shift register so that after shifting
four times it is back in its original state, and the number Y is not lost.
• The box at the left end of each shift register shows the inputs: Sh (shift signal), SI
(serial input), and Clock.
• When Sh = 1 and an active clock edge occurs, SI is entered into x3 (or y3) at the
same time as the contents of the register are shifted one place to the right.
• The additional connections required for initially loading the X and Y registers and
clearing the carry flip-flop are not shown in the block diagram.
Design of a Parallel Multiplier:
Design of a Binary Divider: