Design of a Moore Sequential Circuit

• Outputs depend only on the present state.

• Easier to design and debug than Mealy
machines, but often contain more states than
equivalent Mealy machines.
• No outputs occur during the transition.
• Cannot respond to an input until the active
edge of the clock occurs; this is in contrast to a
Mealy circuit.
1-1
Moore Sequential Circuit

Clock X A0 B0 Z0 A1 B1 Z1
T0 0 0 0 0 1 0 1
T1 1 1 0 1 0 1 1
T2 1 0 1 1 1 1 0
T3 0 1 1 0 0 1 1
T4 1 0 1 1 1 1 0
1 1 0
Note : For the Moore circuit, the output which results from application of a given
input does not appear until after the active clock edge; therefore, the output
sequence is displaced in time with respect to the input sequence.
 Mealy Sequential Circuit Design
Mealy: the outputs depend on both the present state and the
present inputs.
• Consists of: combinational circuit, which generates the outputs and the
next state, and a state register, which holds the present state. State
register is usually comprised of D flip-flops.

1-4
 Mealy Sequential Circuit Design
(continued)
 Steps required to design a sequential circuit:
 1. Determine the required relationship between the input
and output sequences. Find a state graph and state table.
 2. Reduce the table to a minimum number of states.
 3. If the reduced table has m states (2n 1  m  2n ) ,n flip-flops
are needed. Use either the encoded state assignment
technique or the one-hot assignment technique.
 4. Form the transition table.
 5. Plot next-state maps and input maps for each flip-flop
and derive the flip-flop input equations. Derive the output
functions.
 6. Realize the flip-flop input equations and the output
equations using the available logic gates.
 7. Check design.

1-5
Mealy Sequential Circuit

Clock X A0 B0 Z0 A1 B1 Z1
T0 1 0 0 1 0 1 1 (0)
T1 0 0 1 1 (0) 0 1 1
T2 1 0 1 1 1 1 0 (1)
T3 0 1 1 0 (1) 1 1 0
T4 1 1 1 0 0 0 1
0 0 1
• After the circuit has changed state and before the input is changed, the output
may temporarily assume an incorrect value, which we call a false output. As
indicated on the timing chart, this false value arises when the circuit has assumed
a new state but the old input associated with the previous state is still present.

• For the Mealy circuit, the output which corresponds to a given input appears
shortly after the application of that input. Because the correct output
appears before the active clock edge, the output sequence is not displaced in
time with respect to the input sequence as was the case for the Moore
circuit.
 State Graphs

• The state table specifies the next state and output of a sequential circuit in terms of
its present state and input. The following method can be used to construct the state
table:
1. Determine the flip-flop input equations and the output equations from the
circuit.
2. Derive the next-state equation for each flip-flop from its input equations, using
one of the following relations:
• D flip-flop Q+ = D
• T flip-flop Q+ = T ⊕ Q
• S-R flip-flop Q+ = S + R’ Q
• J-K flip-flop Q+ = JQ’+ K’ Q

3. Plot a next-state map for each flip-flop.

4. Combine these maps to form the state table. Such a state table, which gives the
next state of the flip-flops as a function of their present state and the circuit
inputs, is frequently referred to as a transition table.
1. The flip-flop input equations and output
equation are
DA = X ⊕ B’ DB= X + A Z= A ⊕ B
2. The next-state equations for the flip-flops
are
A+ = X ⊕ B’ B+ = X+ A
3. The corresponding maps are
4. Combining these maps yields the transition table in Table which gives the
next state of both flip-flops (A+, B+) as a function of the present state and
input.
5. The output function Z is then added to the table. In this example, the
output depends only on the present state of the flip-flops and not on the
input, so only a single output column is required.

Moore State Tables

6. Using Table we can construct the timing chart

Construct the state table and graph for the Mealy machine of
 Mealy State Tables

Mealy State Graph

 Tristate Logic and Busses
• Tristate buffers: gates with a high-impedance
state (hi-Z) in addition to high and low logic
states. The high-impedance state is equivalent
to an open circuit.
• Use tristate buffers when connecting multiple
gate outputs to the same wire or channel.
• Can be used to aid in data transfers between
registers.
• Tristate buffers are either inverting or non-
inverting.
 Tristate Logic and Busses
(continued)
• 4 kinds of Tristate buffers:
 Sequential Circuit Timing
• The correct functioning of sequential circuits
involves several timing issues:
– Propagation Delay or Clock-to-Q delay: small
amount of time that elapses from the time the
clock changes to the time the Q output changes.
– Setup Time (tsu): amount of time the D input is
stable before the active edge of the clock.
– Hold time (th): amount of time the D input is stable
after the active edge of the clock.
 Sequential Circuit Timing
(continued)
• Timing Conditions: Maximum clock frequency
for a sequential circuit depends on several
factors:
– Clock period must be long enough.
– Propagation delays and setup and hold times create
complications in timing.
• Static timing analysis (STA) is a method of
validating the timing performance of a design
by checking all possible paths for timing
violations under worst-case conditions.
Setup and Hold Times for an Edge-Triggered D Flip-Flop
 Sequential Circuit Timing
(continued)
Timing paths in a synchronous digital system can be
classified into 4 types:
I. Register to register paths (i.e., flip-flop to flip-flop).
II. Primary input to register paths (i.e., input to flip-flop).
III. Register to primary output paths (i.e., flip-flop to
output).
IV. Input to output paths (i.e., no flip-flop).
 Sequential Circuit Timing (continued)
Question: Identify the static timing paths in the following
circuit:

1-21
 Sequential Circuit Timing
(continued)
• Answer: there are six static timing paths in this
circuit:
– I. From A to D1 (primary input to flip-flop)
– II. From D1 to D2 including the XOR (flip-flop to
flip-flop)
– III. From D2 via XOR to D2 (flip-flop to flip-flop)
– IV. From D2 to D1 via AND (flip-flop to flip-flop) V.
From D2 to Z via the OR gate (flip-flop to output)
– VI. From A to Z via the OR gate (input to output)
 Sequential Circuit Timing
(continued)
• Timing Rules for Flip-Flop to Flip-Flop Paths:
– 1. Setup time rule for flip-flop to flip-flop path: Clock period should be
long enough to satisfy flip-flop setup time.
– 2. Hold-time rule for flip-flop to flip-flop path: Minimum circuit delays
should be long enough to satisfy flip-flop hold time.
– 3. Setup time rule for input to flip-flop path: External input changes to
the circuit should satisfy flip-flop setup time.
– 4 Hold-time rule for input to flip-flop path: External input changes to
the circuit should satisfy flip-flop hold times.

1-23
 Sequential Circuit Timing
(continued)
• Synchronous design vs. asynchronous
design:
– Synchronous circuits are more reliable than asynchronous circuits.
– Synchronous design philosophy makes design and debugging easier as
compared with asynchronous.
– Synchronous designs consume more power than asynchronous designs
because of the power consumed in the clock distribution network.
– Asynchronous designs can reduce power consumption, but it is very
difficult to get timing issues under control.
• Hence, despite their high power consumption, designers favor
synchronous designs.
1-24
 Sequential Circuit Timing
(continued)
• Timing Rules (continued)for Circuits with Skew:
– 5. For a positive skew: tck  t p max  tc max  tskew  tsu
– 6. t p min  tc min  th  t skew
• Clock skew: total time difference in clock signal arrival
between 2 points in the clock network.
• Positive skew: the capturing flip-flop gets the clock delayed
with reference to the launching flip-flop. Positive skew is
good for setup time, but it is bad for hold time.
• Negative skew: the launching flip-flop gets the clock
delayed with reference to the capturing flip-flop. Negative
skew is good for hold time, but it is bad for setup time.

1-25
Suppose the inverter has a propagation delay of 2 ns, and suppose the flip-flop has
a propagation delay of 5 ns and a setup time of 3 ns. (The hold time does not affect
this calculation.) Suppose, that the clock period is 9 ns, i.e., 9 ns is the time
between successive active edges
Suppose instead that the clock period were 15 ns. Again, the input to the flip-flop
will change 7 ns after the rising edge. However, because the clock is slower, this is 8
ns before the next rising edge. Therefore, the flip-flop will work properly.
 Design of a Sequence Detector

To illustrate the design of a clocked Mealy sequential circuit, we will design a sequence
detector.

Sequence Detector to be Designed

The circuit will examine a string of 0’s and 1’s applied to the X input and generate an
output Z 1 only when a prescribed input sequence occurs. It will be assumed that the
input X can only change between clock pulses. Specifically, we will design the circuit
so that any input sequence ending in 101 will produce an output Z 1 coincident with
the last 1. The circuit does not reset when a 1 output occurs. A typical input sequence and
the corresponding output sequence are

X 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0
Z 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
we do not know how many flip-flops will be required, so we will designate the
circuit states as S0, S1. The labels on the graph are of the form X/Z.

state table
One flip-flop can have only two states, two flip-flops are needed to represent the three
states. Designate the two flip-flops as A and B.
Let flip-flop states A=0 and B=0 correspond to circuit state S0;
A=0 and B=1 correspond to S1;
and A=1 and B=0 correspond to circuit state S2.
DA=A+ = X’ B , DB=B+= X, Z=AX
Moore machine is similar to that used for a Mealy machine, except that the output is
written with the state instead of with the transition between states.

Z AB’ .
Practice for:

1. Design of Mealy and Moore Sq. Ckt.

2. Analysis of Mealy and Moore Sq. Ckt to get the state graph.