Received 4 May 2023, accepted 5 June 2023, date of publication 9 June 2023, date of current version 15 June 2023.

Digital Object Identifier 10.1109/ACCESS.2023.3284459

A New Topology of Single-Phase Common

Ground Buck-Boost Inverter With Component
Voltage Rating Reduction
VINH-THANH TRAN 1 , KHAI M. NGUYEN 1 , (Senior Member, IEEE),
DUC-TRI DO 1 , (Member, IEEE), AND YOUN-OK CHOI 2 , (Member, IEEE)
1 Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology and Education, Ho Chi Minh City 700000, Vietnam
2 Department of Electrical Engineering, Chosun University, Gwangju 61452, South Korea
Corresponding author: Youn-Ok Choi ([email protected])
This work was supported by the National Research Foundation of Korea (NRF) funded by the Korean Government (MSIT) under Grant
NRF-2019R1F1A1059763.

ABSTRACT The combination of conventional front-end DC-DC converter and H-bridge inverter has been
proposed with common-ground (CG) characteristic and voltage booting capability. However, it has drawback
of low modulation index utilization which causes high component voltage rating and small conversion
efficiency. In this paper, a new topology of a single-phase common-ground buck-boost inverter (1P-CG-
BBI) is presented to overcome existing drawbacks of conventional CG inverters. The proposed 1P-CG-BBI
uses one more active-switch and one more diode than traditional CG inverter. Note that the proposed inverter
still shares the same ground for DC input source and AC output voltage, which completely eliminates the
leakage current. A hybrid pulse width modulation (PWM) technique is introduced to control the buck-boost
stage. Accordingly, the buck-boost stage of the 1P-CG-BBI operates similar to a conventional DC-DC boost
converter in the positive half cycle. In the negative half cycle, this stage behaves as a traditional inverting
DC-DC buck-boost converter. Accordingly, the DC-DC operation and DC-AC operation can be controlled,
independently. Consequently, the modulation index can be significantly improved compared to previous CG
inverters. High modulation index tends to reduce component voltage rating and increase system efficiency.
A comparison study has been discussed to highlight these advantages. Simulation results conducted using
PSIM software are considered to verify the operation of the proposed inverter. A laboratory prototype is
also developed to further demonstrated the accuracy of theory. Accordingly, the proposed inverter obtains
93.12% and 91.83% efficiency at 550-W for buck and boost operating, respectively.

INDEX TERMS Buck-boost inverter, common-ground inverter, leakage current elimination, single-phase
inverter, two-stage inverter.

I. INTRODUCTION high DC input voltage feed to a voltage source inverter (VSI).

Currently, renewable energies, such as photovoltaic (PV) Typically, a low-frequency transformer is installed between
arrays and fuel cells, have attracted the attention of many the output of the inverter and AC grid to isolate grid to power
researchers worldwide because of the increasing global circuit [4]. The use of a line transformer increases system size
warming problem. Accordingly, the development of inverter- and cost, and reduces conversion efficiency. Moreover, the
based PV/fuel cell grid connection has played an integral role conventional VSI only behaves like a buck DC-AC converter,
in civil/industrial applications [1], [2], [3]. Generally, a string where the peak-value of the output voltage is smaller than
of PV panels or fuel cells are connected in series to supply a the DC input source [4], [5]. In some operation conditions,
such as cloudy days or when some PV panels/fuel cells are
The associate editor coordinating the review of this manuscript and faulty, the DC input source is significantly reduced, and it is
approving it for publication was Vitor Monteiro . insufficient to ensure grid-connected operation [6], [7], [8].
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.
VOLUME 11, 2023 For more information, see https://creativecommons.org/licenses/by-nc-nd/4.0/ 58333
 V.-T. Tran et al.: New Topology of 1P-CG-BBI With Component Voltage Rating Reduction

In this case, the system is forced to stop. To deal with these increase DC-link voltage utilization and the number of out-
problems, a front-end DC-DC boost converter is typically put voltage levels [23], [24], [25]. The work in [26] has
installed before the VSI to boost the DC input source [9], [10]. presented a three-level triple boost SC-based CG inverter
It makes the system flexible to be controlled with wide range where the DC-link voltage is boost to three times larger than
of input DC voltage. Moreover, a high-frequency transformer input voltage. Accordingly, the voltage gain of the inverter
is integrated into the DC-DC converter to achieve the isola- is significantly improved which makes it suitable for low
tion characteristic. However, the DC-DC converter with the input voltage applications. However, the common drawback
isolated transformer is complicated to control. Furthermore, of SC-based configurations is high inrush current through
the system efficiency decreases when using a high-frequency capacitors and semiconductor devices when capacitors are
transformer [11]. connected in parallel. As a result, the switching devices of
Transformer-less based grid-connection inverter topolo- these inverters must be designed with a very high current
gies present an efficient alternative solution for reducing the rating compared to output load current. A semi-Z-source
system size, price, and control complexity, while improv- inverter (semi-ZSI), which is explored in [27], is consid-
ing the system efficiency compared to the aforementioned ered as a low-cost buck-type CG inverter. In this topology,
low/high frequency transformer-based solutions [12], [13]. two active switches are used besides one inductor and one
The conventional single-phase H-bridge inverter is com- non-electrolytic capacitor to obtain DC-AC operating. How-
monly utilized as a solution for PV/fuel cells applications. ever, the component voltage rating of semi-ZSI is very high
Indeed, the topology has good DC input voltage utilization which leads to decrease the system efficiency. Furthermore,
and good output voltage/current quality. However, single- the semi-ZSI has a two-output-voltage-levels which increases
phase H-bridge inverters generate a common-mode voltage the total harmonic distortion (THD) of output load current
(CMV) with high slew-rate, dv/dt. Consequently, it generates and the size of output filter.
a leakage current that flows through parasitic capacitors of Although, these above CG inverters can handle with leak-
PV/fuel cells and the ground of the utility grid [14], [15]. age current problem, they only behave as a buck-type con-
In short, the CMV/leakage current can generate an electro- verter which is not suitable for PV applications where DC
magnetic interference (EMI) problem, output-current distor- input source is varied in a wide range. The semi-ZSI is
tion and safety trouble. combined with a conventional DC-DC boost converter to
Many topologies have been explored to reduce the ampli- provide the step up/down output voltage capability [28].
tude of the leakage current [16], [17], [18], [19]. In [16] and A combination of a conventional DC-DC boost converter
[17], a H5 inverter is presented with a single active switch and H-bridge inverter was introduced in [11] and [29] to
added between the input DC source and H-bridge inverter to realize buck-boost operation and CG feature. The pulse-width
reduce the leakage current. In the H5 configuration, the extra modulation (PWM) method discussed in [29] provides a con-
switch is turned off during the freewheeling mode, which tinuous inductor current feature which reduces current stress
generates zero at the output voltage. Specifically, it results in on semiconductor devices compared to [11]. In this work, the
galvanic isolation between DC input source and utility grid, duty ratio D of DC-DC stage is always larger than modulation
which significantly reduces the leakage current. Moreover, index M of DC-AC stage. As a result, the DC-link voltage of
a H6 inverter was introduced by adding two switches into the the inverter is boosted to a very high value in low voltage gain
H-bridge circuit in [18] to reduce the leakage current. How- applications. Hence, it can be concluded that the work in [29]
ever, the H5 and H6 inverters introduce more loss when extra has bad capacitor voltage utilization. The same drawback of
switches are introduced, which reduces inverter efficiency. the limited modulation index is also reported in [30] and [31].
In [19], a HERIC inverter is explored to perform the same References [30] and [32] present topologies of a five-level
task compared to H5 and H6 inverters without increasing the CG inverter to increase the number of output voltage levels.
loss. Although, the leakage current is reduced in H5, H6, and The above discussion of buck-boost type CG inverters has
HERIC configurations compared to conventional H-bridge limitation of modulation index and boost duty ratio coupling.
inverter, it is still high because the leakage current in other To solve with this problem, this paper presents a new topology
active operating states is not eliminated. involving a single-phase common-ground buck-boost inverter
Common-ground (CG) inverters are considered as (1P-CG-BBI) for realizing: 1) step up/down output voltage
zero-leakage current topologies. These configurations gener- and 2) eliminate leakage current by sharing the same ground
ate a constant CMV to completely eliminate leakage current. between input and output voltage. In the proposed topology,
Half-bridge inverter is one of the most commonly used DC-DC and DC-AC operations are independently controlled.
topologies for this task [20], [21], [22]. In this topology, Therefore, the modulation index and component voltage rat-
the CMV is kept as the half of DC-link voltage. However, ing are significantly improved. The operating principle and
this type of CG inverters has bad capacitor voltage utiliza- steady state analysis will be detailed in the remainder of
tion where the maximum voltage gain of the inverter is this paper. A comparative study, simulation, and experimental
not greater than value 0.5. Switched-capacitor (SC) con- results are presented to highlight the advantages of the intro-
figurations are other solution for CG inverters which can duced topology.

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FIGURE 1. Topology of the proposed 1P-CG-BBI.

The rest of this paper includes eight sections. Section II

presents the proposed 1P-CG-BBI topology and PWM con-
trol strategy. The component selection is presented in sec-
tion III. Small-signal analysis and closed-loop controller are
expressed in sections IV and V, respectively. The power
loss analysis is attached in section VI. Comparison study is
presented in section VII. The simulation and experimental
results are included in section VIII to verify the proposed
inverter. The summary of this paper is attached in section IX.

II. PROPOSED 1P-CG-BBI TOPOLOGY

The proposed 1P-CG-BBI is depicted in Fig. 1, which com-
bines a buck-boost DC-DC circuit and an inverter circuit.
The buck-boost operation is ensured by switches S1 – S4 ,
diode D1 , inductor LB , and capacitor CB . Meanwhile, the
DC-AC operation is adopted by using switches S2 – S6 .
In the proposed topology, three active switches S2 – S4 are
shared for DC-DC and DC-AC operations. However, with
FIGURE 2. Operating modes of the proposed inverter under (a)-(d)
the corresponding control scheme, both DC-DC and DC-AC positive half cycle, and (e)-(h) negative half cycle.
operations are independently controlled. The output filter (Lf
and Cf ) and resistor load are adopted to verify the operation
TABLE 1. On/Off states of switching devices.
of the proposed inverter. It is evident that the input DC source,
Vdc , and output load voltage VR share the same ground. There-
fore, there is no leakage current in this proposed topology.
The operating modes of the proposed inverter contains eight
modes, four modes (I – IV) are adopted in the positive half
cycle, and four modes (V – VIII) are adopted in the negative
half cycle, as depicted in Fig. 2. The switching states of
the semiconductor devices are presented in Table 1. It can
be observed that the proposed inverter uses two additional
semiconductor devices, switch S1 and diode D1 , to achieve
two-stage power conversion compared to the topology in
literatures [11], [29].
DC-AC side. In positive half cycle of output voltage VAB ,
A. OPERATING MODES the switches S1 and S4 are always gated on, as shown in
The operating of the proposed inverter is divided into DC-DC Figs. 2(a) – 2(d). It results in reverse biased diode D1 . The
operating and DC-AC operating. These two stages are con- DC-DC side of the proposed 1P-CG-BBI operates like a
trolled independently, which is detailed as follow. conventional DC-DC boost converter, which is detailed as
Firstly, the DC-DC operating is considered to be analyzed. follow.
The key waveforms of the DC-DC operating are depicted in When switch S3 is gated on and switch S2 is turned off, the
Fig. 3. The IPN mentioned in Fig. 3 is equivalent current of inductor LB is stored energy from the DC input source Vdc ,

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of inductor LB is connected to the negative point of capacitor

CB . The inductor LB , now, charges for capacitor CB and
transfers energy to the load. The inductor current and capac-
itor voltage are decreased and increased, respectively. The
following equation are obtained to present these operating
modes.

diLB
 vLB = LB = −VCB


dt
(3)
dv
 iCB = CB CB = ILB − IPN ,


dt
By combining these operating modes, the DC-link voltage
VCB of the proposed 1P-CG-BBI can enhance from input
voltage like any conventional two-stage inverters.
Secondly, the DC-AC operating is ensured by using
FIGURE 3. Key waveforms of the proposed inverter under (a) positive half switches S2 – S6 . The summary of DC-AC operating is listed
cycle, and (b) negative half cycle. in Table 1. In positive half cycle of VAB , the inverter is able
to generate two values 0-V and +VCB at output voltage. The
as shown in Figs. 2(a) and 2(b). The current of the inductor value 0-V is obtained at VAB by triggering on switches S4 and
is increased linearly, as presented in Fig. 3(a). Now, the S6 , as shown in Figs. 2(b) and 2(d). When switches S4 and
capacitor CB transfers energy to the inverter side. As a result, S5 are gated on, as shown in Figs. 2(a) and 2(c), the output
the voltage across capacitor CB is decreased, as shown in voltage VAB obtains +VCB .
Fig. 3(a). The voltage across inductor LB and current through In negative half cycle of VAB , the output voltage varies
capacitor CB are expressed as follow: from -VCB to 0-V. Unlike positive half cycle, the value

di 0-V is obtained by triggering on switches S2 , S3 and S5 ,
 vLB = LB LB = Vdc

dt (1) as illustrated in Figs. 2(e) and 2(g). While the value -VCB is
dv
 iCB = CB CB = −IPN ,
 obtained by turning on switches S2 , S3 and S6 , as shown in
dt Figs. 2(f) and 2(h).
In operating modes III and IV, as shown in
Figs. 2(c) and 2(d), the switch S2 is triggered on while switch B. PWM CONTROL STRATEGY
S3 is triggered off. The inductor LB releases energy to the As discussed above, terminal B of the output voltage is always
capacitor CB and inverter side. As a result, the inductor clamped to the negative point of CB during the positive
LB current is decreased whereas capacitor CB voltage is half cycle, and the positive point of capacitor CB during the
increased, as illustrated in Fig. 3(a). The following equation negative half cycle. The output voltage VAB is controlled by
is obtained. switching S5 and S6 of leg A. The control signals of these
switches are depicted in Fig. 4. The logic implementation

di
 vLB = LB LB = Vdc − VCB

dt for the proposed scheme is drawn in Fig. 5. The reference
dv (2)
 iCB = CB CB = ILB − IPN ,
 signal Vref is compared to the high-frequency carrier Vtri to
dt generate the on/off signal for switch S5 . Switch S5 is gated
In negative half cycle of output voltage VAB , the inverter on when Vref is larger than carrier Vtri , and vice versa. The
operates under four modes (V – VIII), as shown in control signal of switch S6 is the inverted from control signal
Figs. 2(e) –2(h). In these modes, switches S2 and S3 are of switch S5 .
always gated on which directly connects the negative point The reference signal Vref is defined as follows:
of inductor LB to the positive point of the capacitor CB . The 
M × sin(θ) when 0 ≤ θ < π
DC-DC side of the proposed inverter, now, operates like a Vref = (4)
1 + M × sin(θ) when π ≤ θ < 2π,
conventional inverting buck-boost DC-DC converter, which
is detailed as follow. where M indicates the modulation index (0 ≤ M ≤ 1), and ∅
When switch S1 is gated on, diode D1 is reverse biased, represents the phase angle of the output voltage.
as illustrated in Figs. 2(e) and 2(f). The inductor LB is stored The control signals of switches S5 and S6 are expressed as:
energy from DC input source while capacitor CB transfers 0, vref < Vtri

S5 = S = S̄5 , (5)
energy to the load. The inductor current and capacitor volt- 1, vref ≥ Vtri , 6
age are respectively increased and decreased, as shown in
Fig. 3(b). The inductor voltage and capacitor current are Under this approach, the switch S4 is obtained by compar-
presented in (1). ing modulation signal M.sin∅ to value 0 as follow.
0, M sin θ < 0

When switch S1 is triggered off, diode D1 is forward
S4 = (6)
biased, as presented in Figs. 2(g) and 2(h), the positive point 1, M sin θ ≥ 0,

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C. STEADY-STATE ANALYSIS
In the positive half cycle, the total time intervals in each
switching period, TS , of modes I and mode II is equal to
DP ×TS . The rest time of TS is the total time intervals of
mode III and mode IV, which is equal to (1 - DP )×TS . Based
on the volt-second balance principle for inductor LB , the
voltage across capacitor CB is calculated as
1
VCB = Vdc , (9)
1 − DP
In the negative half cycle, the total time intervals of modes
V and VI is DN ×TS . Meanwhile, the total time interval of
modes VII and VIII is (1 – DN )×TS . In steady-state, the aver-
age value of inductor LB voltage is zero, thus the capacitor CB
voltage can be expressed as
DN
FIGURE 4. PWM control strategy for the proposed 1P-CGBBI.
VCB = Vdc , (10)
1 − DN
The boost factor, B, is defined as:
B = VCB /Vdc , (11)
To achieve the same boost factor for both positive and
negative half cycles, the duty ratio DP and DN are defined
as:
(
DP = 1 − 1/B
(12)
DN = B/(1 + B),
The peak-value of fundamental harmonic of output voltage
VAB is calculated as:
M · Vdc M · Vdc · DN
V̂AB = M · VCB = = , (13)
1 − DP 1 − DN
where V̂AB represents the fundamental-harmonic of the output
voltage.
FIGURE 5. PWM logic implementation for the proposed method. The voltage gain G of the inverter is defined as
V̂AB M M × DN
G= =M ×B= = , (14)
Switch S1 is always gated on during the positive half cycle. Vdc 1 − DP 1 − DN
While, it is controlled by using control signal DN and carrier where G represents the voltage gain of the inverter.
Vtri during the negative half cycle, as depicted in Fig. 4. In this
time interval, switch S1 is triggered on when DN is larger than III. COMPONENT SELECTION
Vtri , and vice versa. The duty ratio of switch S1 equals to DN , A. INDUCTOR AND CAPACITOR SELECTIONS
where DN < 1. As shown in Fig. 5, the control signal of switch In the positive half cycle, the inductor LB is always connected
S1 is described as follow. in series with the input voltage source Vdc . Therefore, the
0, DN < Vtri inductor current is equal to input current Idc . While in the

S1 = u1 + S4 , where u1 = (7) negative half cycle, the inductor LB is connected to the input
1, DN ≥ Vtri ,
source in DN TO /2 when switch S1 is turned on, where TO is
Furthermore, switches S2 and S3 are gated on during the the output period. Therefore, the input current Idc is calculated
negative half cycle. In the positive half cycle, switch S3 is as follows:
turned on when control signal DP is larger than the carrier
1
Vtri , and vice versa. The control signal of switch S2 is inverted Idc = ILB (1 + DN ), (15)
from S3 . The duty ratios of S2 and S3 are (1 – DP ) and DP , 2
respectively, where DP < 1. So, the control signals of these Assume that the power loss of the inverter is exceedingly
switches are expressed as follow. small and can be ignored, then the average value of inductor
( LB current can be calculated as
0, DP < Vtri

S2 = ū2 + S̄4 2PO
where u2 = (8) ILB = , (16)
S3 = u2 + S̄4 , 1, DP ≥ Vtri Vdc (1 + DN )
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FIGURE 7. AC small signal model of (a) inductor loop, and (b) capacitor
node for positive half cycle.

half cycle, the equivalent circuits of the proposed inverter

are drawn in Figs. 6(a) and 6(b). The state equations for
Figs. 6(a) and 6(b) are expressed as (1) and (2), respectively.
In positive half cycle, the average model the proposed inverter
FIGURE 6. Equivalent circuit of the proposed 1P-CG-BBI under (a), is obtained by averaging (1), and (2). The following equations
(b) positive half cycle, and (c), (d) negative half cycle. are achieved.
d īLB
= v̄dc − v̄CB 1 − d̄P − rLB ĪLB ,


LB (20)
where PO represents the output power. dt
d v̄CB
According to (12), it is evident that the duty ratio DN is = īLB 1 − d̄P − īPN ,


CB (21)
consistently larger than duty ratio DP . It results in a higher dt
inductor LB current ripple for the negative half cycle. Based where x̄ denotes average model of signal x.
on (1), the inductor current ripple of the inductor LB can be Assume that any average signal consists of an DC signal X
calculated as and an AC small signal x̃, and x̄ = X + x̃, x̃ ≪ X . Now, the
1 equations (20) and (21) are rewritten as follow.
1ILB = Vdc DN TS , (17)  
LB LB s ILB + ĩLB
where 1ILB is the current ripple of inductor LB .  
Inductor LB is selected in terms of 1ILB ≤ x%ILB , where = Vdc + ṽdc − (VCB + ṽCB ) 1 − DP − d̃P
x% indicates the maximum percentage of the inductor current  
ripple. As a result, the inductor LB is selected as − rL ILB + ĩLB , (22)
2 D (1 + D )T
Vdc N N S CB s (VCB + ṽCB )
LB ≥ , (18)   
2x%PO = ILB + ĩLB 1 − DP − d̃P − IPN − ĩPN , (23)
Similar to [11], the capacitor CB selection is based on the
output power PO , output voltage V̂AB , maximum acceptable The AC equations of (22) and (23) can be expressed as
capacitor voltage ripple 1VCB , and switching period, TS . The follow.
estimated capacitance of CB can be expressed as ṽdc (s) + VCB d̃P (s) − (1 − DP ) ṽCB (s)
ĩLB (s) = , (24)
PO TS LB s + rLB
CB ≥ , (19)
1VCB V̂AB (1 − DP ) ĩLB (s) − ILB d̃P (s) − ĩPN (s)
ṽCB (s) = , (25)
CB s
B. SEMICONDUCTOR DEVICE SELECTION
In positive half cycle, the equivalent circuits of AC
Switches S1 and diode D1 block (Vdc + VCB ) voltage in
small-signals of the proposed inverter for inductor loop and
modes VII, VIII and modes V, VI, respectively, as presented
capacitor node are presented in Fig. 7.
in Figs. 2(e) – 2(h). The currents through switch S1 and diode
Based on (24) and (25), the transfer functions GL1 (s),
D1 are equal to inductor current ILB .
GL2 (s), GC1 (s), and GC2 (s) are achieved as follow.
The voltage ratings of switches S2 – S6 are the capacitor
voltage VCB . Switches S2 – S4 are designed to carry inductor ĩLB ĩPN = 0 CB s
GL1 (s) = = ,
the current ILB . While switches S5 and S6 are transferred ṽdc d̃P = 0 LB CB s + rLB CB s + (1 − DP )2
2
output current IO = PO / VO . (26)
ĩLB ĩPN = 0 VCB CB s + (1 − DP ) ILB
IV. SMALL SIGNAL ANALYSIS GL2 (s) = = ,
The small signal analysis of the proposed 1P-CG-BBI is con- ṽ
d̃P dc = 0 LB CB s2 + rLB CB s + (1 − DP )2
ducted for both positive and negative half cycles. In positive (27)

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ṽCB ĩPN = 0 1 − DP
GC1 (s) = = ,
ṽdc d̃P = 0 LB CB s + rLB CB s + (1 − DP )2
2

(28)
ṽCB ĩPN = 0
GC2 (s) =
d̃P ṽdc = 0
−ILB LB s − rLB ILB + (1 − DP ) VCB
= , (29)
LB CB s2 + rLB CB s + (1 − DP )2
The equivalent circuits of the proposed inverter under neg-
ative half cycle are depicted in Figs. 6(c) and 6(d). The state
equations of these modes are presented in (1) and (3). The
average value of inductor voltage and capacitor current in any FIGURE 8. AC small signal model of (a) inductor loop, and (b) capacitor
node for negative half cycle.
switching period are presented as follow.
d īLB
= v̄dc d̄N − v̄CB 1 − d̄N − rL ĪLB ,


LB (30)
dt
d v̄CB
= īLB 1 − d̄N − īPN ,


CB (31)
dt
Substitute x̄ = X + x̃, the equations (30) and (31) are
expressed as follow.
 
d ILB + ĩLB FIGURE 9. Control block diagram of the proposed 1P-CG-BBI.
LB
dt (1 − DN ) DN
= , (38)
 
= (Vdc + ṽdc ) DN + d̃N LB CB s2 + rLB CB s + (1 − DN )2
ṽCB ĩPN = 0
   
− (VCB + ṽCB ) 1 − DN − d̃N − rL ILB + ĩLB , GC4 (s) =
d̃N ṽdc = 0
(32)
−ILB LB s − rLB ILB + (1 − DN ) (Vdc + VCB )
CB s (VCB + ṽCB ) = ,
   LB CB s2 + rLB CB s + (1 − DN )2
= ILB + ĩLB 1 − DN − d̃N − IPN − ĩPN , (33) (39)

Based on (32) and (33), the AC small signals of inductor V. CLOSED-LOOP CONTROLLER FOR 1P-CG-BBI
current and capacitor voltage are expressed as follow. In this section, the simple controller for the proposed inverter
is presented to control the capacitor CB voltage and output
DN ṽdc (s)−(1 − DN ) ṽCB (s) + (Vdc + VCB ) d̃N (s) load voltage. The proposed control block diagram of 1P-CG-
ĩLB (s) = ,
LB s + rLB BBI is depicted in Fig. 9. Firstly, the capacitor voltage VCB
(34) is controlled by using proportional-integral-derivative (PID)
(1 − DN ) ĩLB (s) − ILB d̃N (s) − ĩPN (s) controller, as shown in Fig. 9. The output of PID controller is
ṽCB (s) = , (35) defined as follow.
CB s  
ki
The equivalent circuits of inductor loop and capacitor node y(s) = kp + + kd s e (s) (40)
of AC small signals of the proposed inverter in negative half s
cycle are shown in Fig. 8. where y(s) and e(s) are respectively output of PID controller
Based on (34) and (35), transfer functions GL3 (s), GL4 (s), and different between desired capacitor voltage VCB,ref and
GC3 (s), and GC4 (s) are obtained as follow. actual capacitor voltage VCB ; kp , ki , kd are proportional,
integral and derivative coefficients of PID controller.
ĩLB ĩPN = 0 DN CB s
GL3 (s) = = , Three coefficients kp , ki , kd are selected with the help of
ṽdc d̃N = 0 LB CB s + rLB CB s + (1 − DN )2
2
bode diagrams of GC2 (s) and GC4 (s) mentioned in (29) and
(36) (39). These bode diagrams are built for 600-W output power,
ĩLB ĩPN = 0 200-V DC input source. The capacitor voltage VCB is fixed at
GL4 (s) = 350-V. Based on (9), (10) and (16), the coefficients DP , DN ,
d̃N ṽdc = 0
and ILB are calculated as 0.43, 0.64, and 3.65-A. The series
(Vdc + VCB ) CB s + (1 − DN ) ILB
= , (37) resistor of inductor LB is set as 0.3-. As shown in Fig. 10,
LB CB s2 + rLB CB s + (1 − DP )2 before adding PID controller, the phase margin (Pm) and gain
ṽCB ĩPN = 0 margin (Gm) of the proposed inverter are -31.3 dB and -
GC3 (s) =
ṽdc d̃N = 0 24.70 , which are smaller than zero. As a result, the system

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where rLB and rESR are series resistors of inductor and capaci-
tor, respectively; ILB,rms and ICB,rms are RMS values of induc-
tor LB and capacitor CB currents.
The conduction losses of switches and diodes in the pro-
posed inverter are defined as follow.

Z2π
1




 PS,cond = VCE,sat IC dθ
2π



0 (42)
Z2π
1


VF ID dθ ,


 PD,cond =
2π



0
where PS,cond and PD,cond are the conduction losses of IGBT
and diode; VCE,sat and VF are collector-emitter voltage and
forward voltage of IGBT and diode, IC and ID are currents
through IGBT and diode.
In any switching period TS , the switch S1 has one switching
event in negative half cycle, while switch S3 has one switch-
ing event in positive half cycle. Switch S2 has no switching
loss, but it has a reverse recovery loss of body diode in any
switching period in positive half cycle. The switching voltage
of switch S1 is the sum of Vdc and VCB , while it is only VCB
for switches S3 and body diode of switch S2 . The switching
currents of these switches are inductor LB current. So, the
switching losses of these switches are calculated as:
Z2π


 1 Esw (Vdc + VCB , ILB )
PS1,sw = dθ


2π


 TS
π


Zπ


Esw (VCB , ILB )

 1
PS3,sw = dθ (43)

 2π TS
 0
Zπ



1 Qrr VCB


FIGURE 10. Bode diagrams of (a) GC 2 (s), PID(s)GC 2 (s), PID(s), and P = dθ ,


 D2,rr

(b) GC 4 (s), PID(s)GC 4 (s), PID(s).  2π TS
0
where PS1,sw , PS2,sw are switching losses of switches S1 and
is unstable. By selecting kp , ki and kd as 2 · 10−6 , 0.01, and 1, S2 ; Esw (VCE , IC ) is switching energy which is a function of
the Pm and Gm of the PID(s) · GCj (s) (j = 2, 4) are greater switching voltage and current; Qrr is reverse recovery charge
than zero. Now, the system is controllable. The output of PID of diode D2 .
controller is limited to generate coefficient DP , as shown in Switch S5 has one switching event per switching period
Fig. 9. In the experiment, the duty ratio DP is limited by 0.7. in positive half cycle of output load current, while its
The duty ratio DN are calculated by applying (12). anti-parallel diode has one reverse recovery loss per switching
Then the output load voltage is controlled. To be sim- period in negative half cycle. The switching voltage of switch
ple, when capacitor voltage is controllable, the output load S5 is capacitor CB voltage. This switch is switching at output
voltage can be controlled by calculating modulation signal load current Iload . Therefore, the switching loss and reverse
Vref , as shown in Fig. 9. The reference signal Vref and two recovery loss of switch S5 is calculated as follow. Note that
coefficients DP and DN are used to generate PWM control the switching loss of S6 is equal to switch S5 .
signals of inverter switches by employing PWM logic imple- 
Zπ
mentation shown in Fig. 5.

 1 Esw (VCB , Iload )

 PS5,sw = PS6,sw = dθ


 2π TS
0
VI. POWER LOSS INVESTIGATION (44)
Z2π
The power losses of inductor LB and capacitor CB (PLB and 1 Q V

rr CB


 P = PD6,rr = dθ
PCB ) are calculated as:  D5,rr

 2π TS
( π
2
PLB = rLB ILB,rms Diode D1 has one reverse recovery action per switching
(41)
2
PCB = rESR ICB,rms , period TS , in negative half cycle. Reverse biased voltage of

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TABLE 2. Components parameters.

FIGURE 11. Power loss contribution of the proposed inverter and inverter
in [29] with 1-kW output power. (1), (2) proposed inverter under 200-V
and 350-V of Vdc , (3), (4) Inverter in [29] under 200-V and 350-V of Vdc .
Based on Fig. 11, the total losses of the proposed inverter
and inverter in [29] are calculated as 52.3-W and 66.9-W
for 200-V input voltage, and 38.6-W and 61.7-W for 350-V
input voltage. It can be seen that the proposed inverter has
smaller power loss than the inverter in [29]. It is because
the proposed inverter is designed with smaller component
voltage rating. Furthermore, the most switching devices of the
proposed inverter are switching at smaller voltage than that
of inverter in [29]. Hence, the proposed inverter has smaller
switching loss than [29]. The efficiency comparison between
both inverters is shown in Fig. 12. When the input voltage
increases, the inverter efficiency are also increases because
the conduction losses of all devices are decreased. In both
cases of input voltages, the introduced 1P-CG-BBI has better
efficiency than conventional CG inverter [29].

VII. COMPARISON STUDY

The main contribution of the proposed inverter is the reduc-
FIGURE 12. Efficiency comparison between the proposed inverter and
convention inverter in [29]. tion of the component voltage rating. To highlight the advan-
tages of the proposed 1P-CGBBI, some topologies have
diode D1 is the sum of Vdc and VCB . So, the reverse recovery been employed to compare with the introduced inverter.
loss of diode D1 is expressed as follow. They include the conventional three-level active-neutral-
Z2π point clamped (3L-ANPC) inverter mentioned in [21], and
1 Qrr (Vdc + VCB ) CG inverters presented in [29], [30], and [31]. To ensure
PD1,rr = dθ (45)
2π TS fairness in comparisons, the conventional DC-DC boost con-
π verter mentioned in [11] has been installed before the 3L-
The deadtime loss of the proposed inverter is very small ANPC inverter to achieve buck/boost operation. The overall
and can be ignored. comparison between the proposed inverter and those of other
The power loss contribution of the proposed inverter studies is presented in Table 3. The component voltage rating
and the conventional common-ground inverter in [29] under investigation is presented in Fig. 13.
200-V and 350-V of input voltage are presented in Fig. 11.
Both inverters are operated at 220-VRMS output load volt- A. NUMBER OF COMPONENTS
age. The components used in this investigation are listed in As indicated in Table 3, all topologies use the same number
Table 2. Note that the proposed inverter is designed to operate of inductors which includes one boost inductor. However, the
with 350-V of DC-link voltage. As a result, the voltage 3L-ANPC inverter in [21] and inverter in [30] require two
rating of switch S1 and diode D1 is 750-V which obtained capacitors to generate AC output voltage, while the proposed
when the inverter operates under 350-V input voltage. The 1P-CG-BBI and other inverters in [29] and [31] use only
other switches of 1P-CG-BBI block 350-V. Thus, switch S1 one capacitor. In 3L-ANPC inverter in [21], the ground of
and diode D1 are selected as 1200-V IGBTs whereas other output terminal of AC output voltage is connected to the
switches are 650-V IGBTs. The maximum voltage rating of neutral point of DC-link voltage, which makes the CMV
switching devices of conventional inverter in [29] is 661-V of [21] constant during operation. As a result, the leakage
which is obtained at 350-V with minimum boost control. current is approximately eliminated. The same result for the
Thus, all semiconductor devices of [29] are 1200-V IGBTs. leakage current can be achieved for the topologies reported

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TABLE 3. Overall comparison study.

FIGURE 13. Component voltage rating comparison. (a) voltage gain vs capacitor voltage rating, (b) voltage gain vs switch voltage rating, and
(c) voltage gain vs diode voltage rating.

in [29], [30], and [31], and the introduced 1P-CG-BBI by B. COMPONENT VOLTAGE STRESS
sharing the same ground for DC input source and AC output The voltage stresses of capacitors and semiconductor devices
voltage. are investigated in this section. To ensure fairness in the
The proposed inverter has one active switch less than comparisons, the maximum value of the modulation index
3L-ANPC [21] following conventional DC-DC boost topol- M is applied for the works in the comparative study. For
ogy in [21] and inverter in [30]. Although the proposed the proposed inverter and boost + 3L-ANPC inverter [21],
inverter uses one more active switch than inverters in [29] the modulation index M and duty ratios of boost switches
and [31], however, it makes the proposed inverter have decou- are independently controlled; therefore, the value of M can
pled duty ratio D and modulation index M . In detail, the mod- be increased to 1 for any values of voltage gain G. For the
ulation index M of the inverters in [29] and [31] is not larger inverter in [30], the modulation index M is set to 1/2 (1 + D),
than D while it does not depend on D and can increase to 1 for while it is D for the topologies in [29] and [31]. The results of
the proposed inverter. As a result, the proposed inverter can the component voltage rating versus voltage gain are depicted
operate with higher modulation index M and lower DC-link in Fig. 13.
voltage and component voltage rating than others. The detail With these modulation index values, M , it is evident that
of component rating comparison is presented in Fig. 13 and the proposed 1P-CG-BBI and boost + 3L-ANPC inverter
explained as follow. use the largest value of M . As a result, the capacitor voltage

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FIGURE 14. Simulation results under 350 V input voltage.

stresses of the proposed inverter and boost + 3L-ANPC TABLE 4. Simulation and experimental parameters.
inverter are smallest, as shown in Fig. 13(a). Although it
has the same capacitor voltage rating, the 3L-ANPC con-
figuration uses two capacitors, which increases the DC-link
voltage to twice of that in the proposed topology. A higher
DC-link voltage increases the voltage stress of the boost
switch and diode compared to the proposed 1P-CGBBI,
as shown in Figs. 13(b) and 13(c). The voltage ratings of
the inverter switches of 3L-ANPC inverter are equal to the
proposed inverter. As listed in Table 3, the voltage stresses
of most switches of [30] are equal to the capacitor C1 volt-
age. Therefore, having a higher voltage rating of C1 results
in a larger switch voltage rating compared to the proposed as presented in Fig. 14(a). The RMS value of the output load
inverter, as shown in Fig. 13(b). The inverters in [29] and [31] voltage VR is 218 VRMS . For an 80  resistive output load, the
use the smallest modulation index; thus, the topologies have output load current is 2.73 ARMS . The output load voltage and
the largest voltage rating for switches. However, the diode current are sinusoidal waveforms after low pass filtering (Lf
voltage rating of [31] is equal to that of the proposed inverter. and Cf ). The inductor current ILB has no switching frequency
current ripple in the positive half-cycle, because DP is set
VIII. SIMULATION AND EXPERIMENTAL RESULTS to zero, which triggers on switch S2 and triggers off switch
A. SIMULATION RESULTS S3 , as depicted in Figs. 14(a) and 14(b). In the negative
The proposed 1P-CG-BBI has been verified by simulation half cycle, the inductor current ripple is 5.83 A, primarily
using PSIM software. The parameters used for simulation because the duty ratio DN is set to 0.5. In this time interval,
are presented in Table 4. Both buck and boost modes are switches S2 and S3 are consistently gated on, while switch
considered in this section. S1 is switched at 10 kHz, as illustrated in Fig. 14(c). When
In buck mode, a 350-V DC input source is adopted. In this switch S1 is turned on, inductor current ILB is increased, and
mode, the modulation index M is set to 0.89, while duty ratios ILB decreases when switch S1 is turned off. The average value
DP and DN are set to 0 and 0.5, respectively. With these duty of the inductor LB current is 2.58 A. The input current Idc
ratios, the capacitor CB voltage is equal to the input voltage, is continuous in the positive half cycle because it is directly
which are 350-V, as depicted in Fig. 14(a). The output voltage connected to inductor LB , while it is discontinuous in the
VAB contains three voltage levels: –350 V, 0 V, and + 350 V, negative half cycle, as shown in Fig. 14(a). The average value

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FIGURE 15. Simulation results under 200 V input voltage.

of the input current is 1.71 A. The voltage ratings of switch duty ratio DN . The voltage stress of switch S1 and diode D1
S1 and diode D1 are 700 V, while the other switch voltage are 550-V, which is the sum of the input voltage and capacitor
ratings are 350 V, as presented in Fig. 14(b). In the positive CB voltage. The voltage rating of switches S2 – S6 are equal to
half cycle, diode D1 is always reverse biased, which blocks the capacitor CB voltage, which is 350 V. Switch S4 switches
the input voltage Vdc , as shown in Fig. 14(b). Switches S2 and at line frequency 50 Hz, while other switches are switching
S3 are consistently switched on and off in buck mode. While at the switching frequency, 10 kHz.
switch S4 is switched at the line frequency, 50 Hz.
To test the proposed inverter in boost mode, the input B. EXPERIMENTAL RESULTS
DC voltage is set to 200 V. The simulation results for boost An experimental prototype was developed to verify the
mode are illustrated in Fig. 15. In this mode, the modulation operation of the proposed 1P-CGBBI, as depicted in
index M was selected as 0.89, while duty ratios DP and Fig. 16. The prototype is based on the microcontroller DSP
DN were set to 0.43 and 0.64, respectively. As a result, the TMS320 F28335. IGBT module SKM75GB12T4 and diode
capacitor CB was boosted to 350 V from the 200 V input UJ3D1250K2 were utilized for switches S1 – S6 , and diode
voltage, as presented in Fig. 15(a). The output voltage VAB D1 , respectively. The IGBTs are controlled by isolated IC
still has three voltage levels, which varies from –350 V to TLP250. The input voltage Vdc was set at 200-V and 350-V,
+350 V, as illustrated in Fig. 15(a). The RMS values of the respectively, to generate 220-VRMS at the output load voltage,
output load voltage and current are 216 VRMS and 2.7 ARMS , in theory. The capacitor voltage VCB was boosted to 350-V,
respectively. The average values of the inductor current ILB in theory. The modulation index M for both cases of input
and input current Idc are 3.69 A and 2.93 A, respectively. The voltages was set at 0.89. The summary of simulation and
magnified waveforms of the inductor current ILB and voltages experimental results are listed in Table 5.
of switches S1 – S3 in the positive and negative half cycles In case of the 350-V input DC source, the duty ratios DP
are illustrated in Figs. 15(c) and 15(d), respectively. In the and DN were still selected as 0 and 0.5, respectively. The
positive half cycle, the inductor LB current increases when experimental results for the 350-V of Vdc are presented in
switch S3 is on, and vice versa. When switch S1 is on, the Fig. 17. The capacitor CB voltage was measured as 347-V.
inductor LB stores energy in the negative half cycle, as shown With DP set to zero, 1ILB is zero in the positive half cycle,
in Fig. 15(d). The inductor current ripple 1ILB in the positive as depicted in Fig. 17(a). In the negative half cycle, 1ILB is
and negative half cycles are 2.89 A and 3.68 A, respectively. approximately measured as 5.1A, as shown in Fig. 17(e). The
The 1ILB in the positive half cycle is smaller than that in the average values of the inductor current ILB and input current
negative half cycle because the duty ratio DP is smaller than Idc were measured as 2.36-A and 1.7-A, respectively. The

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TABLE 5. Summary of simulation and experimental results.

FIGURE 16. Laboratory prototype.

output voltage VAB has three-voltage levels: +VCB , 0, and

-VCB , as presented in Fig. 17(b). The RMS values of the FIGURE 17. Experimental results under Vdc = 350 V.

output load voltage and current were measured as 212 VRMS

and 2.58 ARMS , respectively. The voltage ratings of switch
S1 and diode D1 were approximately measured as 700-V, current of experiment are higher than simulation because the
which is the sum of the input voltage and VCB , as depicted noise, stray inductor and capacitor of experimental prototype.
in Fig. 17(c). While the voltage rating of the other devices is The experimental efficiency of the proposed 1P-CG-BBI is
equal to capacitor voltage, as shown in Figs. 17(c) and 17(d). presented in Fig. 19 which is measured by using WT3000E
The THD of output voltage VAB and output load current IR power analyzer. It can be observed that the conversion effi-
are measured as 69.3% and 3.18%. ciency of the inverter increases when the input voltage and
In case of 200 V of Vdc , the duty ratios DP and DN were voltage gain are increased and decreased, respectively. Since
respectively set as 0.43 and 0.64. The capacitor voltage VCB the experimental prototype was only developed to verify the
was booted to 338 V from 200 V of Vdc . It results in 207 VRMS operation of the proposed inverter, a more optimal design
and 2.52 ARMS of output load voltage and current, respec- cannot be obtained. As a result, the system efficiency is low.
tively. The average values of the inductor and input currents
are 3.47 A and 2.89 A, respectively. The inductor current C. CAPACITOR AND OUTPUT LOAD VOLTAGE CONTROL
ripples in positive and negative half cycles are depicted in The experimental results for closed-loop controller have been
Figs. 18(e) and 18(f), which are measured as 2.5-A and 3.5-A, presented in Figs. 20 and 21. The parameter selections of PID
respectively. The voltage rating of switch S1 and diode D1 is controller have been detailed in section V. Firstly, the inverter
550-V. In particular, diode D1 only blocks 200-V DC input is tested under variation of DC input source. The input
voltage in the positive half cycle, as illustrated in Fig. 18(c). voltage, now, is varied from 350-V to 200-V, as shown in
Other semiconductor devices of the inverter block 350-V of Fig. 20(a), and from 200-V to 350-V, as shown in Fig. 20(b).
capacitor CB voltage, as presented in Figs. 18(c) and 18(d). It can be seen that the capacitor voltage is stable at 350-V
The THD of output voltage VAB and output load current without the variation of Vdc . As a result, the output load
IR are measured as 70.4% and 3.63%. The experimental voltage VR and current IR are maintained as 218-VRMS and
results of capacitor voltage and output voltage are smaller 2.71-ARMS , as shown in Fig. 20.
than simulation results. It is because the parasitic of devices Finally, the 1P-CG-BBI is tested under variation of output
is ignored in simulation. The THDs of output voltage and load current. In this case, the input voltage is set to 250-V,

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FIGURE 20. Experimental results when (a) Vdc varies from 350-V to 200-V,
and (b) Vdc varies from 200-V to 350-V.

FIGURE 18. Experimental results under Vdc = 200V.

FIGURE 21. Experimental results when (a) resistor load varies from 120-
to 80-, and (b) resistor load varies from 80- to 120-.

FIGURE 19. 1P-CG-BBI efficiency.

IX. CONCLUSION
This paper presented a new topology for 1P-CGBBI, which
the resistor load is changed from 120- to 80- and vice realizes step up/down output voltage operation in two-stage
versa. The experimental results for this case are shown in power conversion. With this characteristic, the proposed
Fig. 21. In case of 120- and 80- resistor loads, the output inverter can increase the modulation index to 1, in theory.
load currents are measured as 1.82-ARMS and 2.7-ARMS , As a result, the voltage rating of the capacitor and semicon-
respectively. In both cases of resistor loads, the capacitor ductor devices can be significantly improved. The compo-
voltage VCB , output load voltage VR are still fixed at 350-V, nent voltage stress of the introduced 1P-CG-BBI has been
and 218-VRMS , as presented in Fig. 21. These tests have compared to previous studies to highlight this benefit. With
verified the proposed controller presented in section V. a smaller component voltage rating, the proposed inverter

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common-ground three-switch single-phase inverter for photovoltaic sys- nam, in 1973. He received the B.S., M.S., and
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Ho Chi Minh City University of Technology and
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Education, Ho Chi Minh City, Vietnam, in 1999,
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pp. 6192–6196, Jun. 2021. energy systems.
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Syst. II, Exp. Briefs, vol. 70, no. 2, pp. 556–560, Feb. 2023.

YOUN-OK CHOI (Member, IEEE) received

the B.S., M.S., and Ph.D. degrees in electrical
VINH-THANH TRAN was born in Vietnam, engineering from Chosun University, Gwangju,
in 1995. He received the B.S. and M.S. degrees in South Korea, in 1995, 1997, and 2003, respec-
electronic engineering from the Ho Chi Minh City tively. From 2001 to 2015, he was a Lecturer,
University of Technology and Education, Viet- a Visiting Professor, and a Research Professor
nam, in 2018 and 2020, respectively, where he with the Department of Electrical Engineering,
is currently pursuing the Ph.D. degree in elec- Chosun University, where he has been an Assistant
tronic engineering. His current research interests Professor, since 2016. His current research inter-
include impedance source inverters and the control ests include photovoltaic systems, the analysis and
of multi-level inverters. control of motors, microgrid, and power converters.

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